Lab Manual 1-8

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Expt No: 1 CURRENT-SERIES FEEDBACK AMPLIFIER

Aim:

To design and test the current-series feedback amplifier and to calculate thefollowing parameters with and without feedback.

1. Mid band gain.2. Bandwidth and cut-off frequencies.3. Input and output impedance.

Components & Equipment required:

Sl. No. Components / EquipmentRange /

SpecificationsQuantity

1 Power supply (0-30)V 1

2 Function generator (0-20M)Hz 1

3 CRO 1

4 Transistor BC107 15 Resistors

6 Capacitors

7 Connecting wires Accordingly

Circuit diagram:

(i) Without feedback:

0

Cin

CERE

Cout

R1

R2

RC

RLBC107B

C

E

Vin=50mV

Vcc = +12V

CRO

f=(1-3M)Hz

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(ii) With feedback:

0

Cin

RE

Cout

R1

R2

RC

RLBC107B

C

E

Vin=50mV

Vcc = +12V

f=(1-3M)Hz

CRO

Theory:

The current series feedback amplifier is characterized by having shunt samplingand series mixing. In amplifiers, there is a sampling network, which samples the outputand gives to the feedback network. The feedback signal is mixed with input signal byeither shunt or series mixing technique. Due to shunt sampling the output resistanceincreases by a factor of D and the input resistance is also increased by the same factordue to series mixing. This is basically transconductance amplifier. Its input is voltagewhich is amplified as current.

Design:


VCC = 12V; IC = 1mA; fL = 50Hz; S = 2; RL = 4.7K; hfe =

re = 26mV / IC = 26;

hie = hfe re =

VCE= Vcc/2 (transistor Active) =

VE = IERE = Vcc/10

Applying KVL to output loop, we get

VCC = ICRC + VCE + IERE

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RC =

Since IB is very small when compare with IC,

IC IE

RE = VE / IE =

S = 1+ RB / RE = 2

RB =

VB = VCC R2/ (R1 + R2)

RB = R1 || R2

R1 = R2 =

XCi = Zi / 10 = (hie || RB) / 10 =

Ci = 1 / (2f XCi) =

Xco = (RC || RL)/10 =

Co = 1 / (2f XCo) =

XCE = RE/10 =

CE = 1 / (2f XCE) =

(ii) With feedback (Remove the Emitter Capacitor, CE):

Feedback factor, = -RE =

Gm = -hfe / (hie + RE) =

Desensitivity factor, D = 1 + Gm =

Transconductance with feedback, Gmf= Gm / D =

Input impedance with feedback, Zif= Zi D

Output impedance with feedback, Z0f= Z0 D

Procedure:

1. Connect the circuit as per the circuit diagram.

2. Keeping the input voltage constant, vary the frequency from 50Hz to 3MHz inregular steps and note down the corresponding output voltage.

3. Plot the graph: Gain (dB) Vs Frequency4. Calculate the bandwidth from the graph.5. Calculate the input and output impedance.6. Remove Emitter Capacitance, and follow the same procedures (1 to 5).

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Tabular column:


Vi =

Sl. NoFrequency

(Hz)

Output Voltage

(V0) (volts)

Gain = V0/ViGain = 20 log(V0/Vi)

(dB)

(ii) With feedback:Vi =

Sl. NoFrequency

(Hz)Output Voltage

(V0) (volts)Gain = V0/Vi

Gain = 20 log(V0/Vi)(dB)

Model graph: (frequency response)

Gain in dB

Without feedback

With feedback

Frequency in Hz

Result:

Thus the current series feedback amplifier is designed and constructed and thefollowing parameters are calculated.

With feedback Without feedback

Inputimpedance

Output

impedanceGain(midband)

Bandwidth

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Expt. No. 2 VOLTAGE SHUNT FEEDBACK AMPLIFIER

Aim:

To design and test the voltage-shunt feedback amplifier and to calculate thefollowing parameters with and without feedback.

1. Mid band gain.2. Bandwidth and cut-off frequencies.3. Input and output impedance.






3 CRO 1

4 Transistor BC107 15 Resistors

6 Capacitors

7 Connecting wires

Circuit Diagram:

(i) Without Feedback:

0

Cin

CERE

Cout

R1

R2

RC

BC107B

C

E

Vin=50mV

Vcc = +12V

f=(1-3M)Hz

CRO

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(ii) With Feedback:

0

CE

CoutRf

R2

RCR1

Vin=50mV

BC107B

C

E

Cin

Cf

RE

Vcc = +12V

CRO

f=(1-3M)Hz

Theory:

In voltage shunt feedback amplifier, the feedback signal voltage is given to

the base of the transistor in shunt through the base resistor RB. This shunt connectiontends to decrease the input resistance and the voltage feedback tends to decrease theoutput resistance. In the circuit RB appears directly across the input base terminal andoutput collector terminal. A part of output is feedback to input through RB and increase inIC decreases IB. Thus negative feedback exists in the circuit. So this circuit is also calledvoltage feedback bias circuit. This feedback amplifier is known an transresistanceamplifier. It amplifies the input current to required voltage levels. The feedback pathconsists of a resistor and a capacitor.

Design


VCC = 12V; IC = 1mA; AV = 30; Rf= 2.5K; S = 2; hfe = ; =1/ Rf= 0.0004

re = 26mV / IC = 26;

hie = hfe re =


VE = IERE = Vcc/10 =

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Applying KVL to output loop, we get VCC = ICRC + VCE + IERE

RC =

Since IB is very small when compare with IC, IC IE

RE = VE / IE =

S = 1+ RB / RE

RB =

VB = VCC R2/ (R1 + R2)

RB = R1 || R2

R1 = R2 =

(ii) With feedback:

RO = RC || Rf=

Ri = (RB || hie ) || Rf=

Rm = -(hfe (RB || Rf) (RC || Rf)) / ((RB || Rf) + hie) =

Desensitivity factor, D = 1 + Rm

Rif= Ri/ D =

Rof= Ro/ D =

Rmf= Rm/ D =

XCi = Rif/10 =

Ci = 1 / (2f XCi) =

Xco = Rof/10 =

Co = 1 / (2f XCo) =

RE = RE || ((RB + hie) / (1+hfe))

XCE = RE/10 =

CE = 1 / (2f XCE) =

XCf= Rf/10

Cf= 1 / (2f XCf) =

Procedure:

1. Connect the circuit as per the circuit diagram.2. Keeping the input voltage constant, vary the frequency from 50Hz to 3MHz in

regular steps and note down the corresponding output voltage.3. Plot the graph: Gain (dB) Vs Frequency

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4. Calculate the bandwidth from the graph.5. Calculate the input and output impedance.6. Remove Emitter Capacitance, and follow the same procedures (1 to 5).

Tabular Column:


Vi =

Frequency V0

(volts)

Gain = V0/Vi Gain (dB) = 20 log(V0/Vi)

(ii) With Feedback:

Vi =

Frequency V0

(volts)

Gain = V0/Vi Gain (dB) = 20 log(V0/Vi)

Model graph: (frequency response)

Gain in dB

Without feedback

With feedback

Frequency in Hz

Result:Thus the current series feedback amplifier is designed and constructed and the

following parameters are calculated.

With feedback Without feedback

Inputimpedance

Outputimpedance

Gain(midband)

Bandwidth

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Expt. No. 3 RC PHASE SHIFT OSCILLATOR

Aim:

To design and construct a RC phase shift oscillator for the given frequency (f0)




1 Power supply (0-30) V 1

2 CRO 1

3 Transistor BC107 1

4 Resistors

5 Capacitors


Circuit Diagram:

0

0

R2CE

C

BC107B

C

E

C C

Cin

Cout

RR

RE

R1

R

RC

Vcc = +12V

CRO

Theory:

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In the RC phase shift oscillator, the required phase shift of 180 in the feedback

loop from the output to input is obtained by using R and C components, instead of tankcircuit. Here a common emitter amplifier is used in forward path followed by threesections of RC phase network in the reverse path with the output of the last section being

returned to the input of the amplifier. The phase shift

is given by each RC section=tan1 (1/rc). In practice R-value is adjusted such that becomes 60. If the valueof R and C are chosen such that the given frequency for the phase shift of each RCsection is 60. Therefore at a specific frequency the total phase shift from base totransistors around circuit and back to base is exactly 360 or 0. Thus the Barkhausencriterion for oscillation is satisfied

Design:

VCC = 12V; IC = 1mA; C = 0.01F; fo = ; S = 2; hfe =

re = 26mV / IC = 26;

hie = hfe re =


VE = IERE = Vcc/10



RC =


IC IE

RE = VE / IE =

S = 1+ RB / RE = 2

RB =

VB = VBE + VE =

VB = VCC R2/ (R1 + R2)

RB = R1 || R2

R1 = R2 =Gain formula is given by,

AV =ie

Lefffe

h

Rh(Av = -29, design given)

Effective load resistance is given by, Rleff = Rc || RL

RL =

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XCi = {[hie+(1+hfe)RE]|| RB}/10 =

Ci = 1 / (2f XCi) =

Xco = Rleff /10 =

Co = 1 / (2f XCo) =

XCE = RE/10 =

CE = 1 / (2f XCE) =

Feedback Network:

f0 = ; C = 0.01f;

fo =RC62

1

R =

Procedure:

1. Connections are made as per the circuit diagram.2. Switch on the power supply and observe the output on the CRO (sine wave).3. Note down the practical frequency and compare with its theoretical frequency.

Model Graph:

Vout (Voltage)

Time(ms)

Result:

Thus RC phase shift oscillator is designed and constructed and the output sinewave frequency is calculated as

Theoretical Practical

Frequency

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Expt. No. 4 WEIN BRIDGE OSCILLATOR

Aim:

To design and construct a Wein Bridge oscillator for the given frequency (f0)

Components & Equipment required:Sl. No. Components / Equipment

Range /


1 Power supply (0-30) V 1

2 CRO (0-20M0Hz 1

3 Transistor SL100 1

4 Resistors

5 Capacitors


Circuit Diagram:

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Theory:Wein bridge oscillator is one of the low frequency audio oscillators. The feedback

loop in this oscillator consists of a lead lag network, i.e., a series R and C cascaded with aparallel combination of R and C (frequency sensitive arms of the bridge). This networkdoes not introduce any phase shift and so the total phase shift in the feedback path is zero.

So we use a two stage CE amplifier in the forward path that also introduces zero phaseshifts. Hence the total phase shift around the loop is zero and the Barkhausen conditionfor sustained oscillation is satisfied. The feedback is taken from the collector of Q2 andgiven to the bridge using a coupling capacitor. The RE1 serves for dual purpose i.e., it actsas RE for Q1 and forms R4 for the wein bridge network. The last bridge arm is given by

R3.The oscillation frequency is given by f=1/2RC.

Design:VCC = ; IC = mA; fo = ; S = ; hfe =

re = 26mV / IC = 26;

hie = hfe re =VCE= Vcc/2 (transistor Active) =

VE = IERE = Vcc/10



RC1 = RC2 = (VCC -VCE - VE)/ IC


IC IE

RE = VE / IE =

S = 1+ RB / RE =

RB =

VB = VBE + VE =

VB = VCC R22/ (R11 + R22)=

R11= VCC RB/ VB

R11 = R33= R22 = R44=

Feedback Network:

f0 = ; C=C1=C2= 0.1f;

For Wein Bridge Oscillator,RC

f2

10 =

R =R1=R2=

43 2 RR = = 1k Let R4=500

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Procedure:1. Connections are made as per the circuit diagram.2. Switch on the power supply and observe the output on the CRO (sine wave).3. Note down the practical frequency and compare with its theoretical frequency.

Model Graph:

Vout (Voltage)

Time (ms)

Result:

Thus the Wein Bridge oscillator is designed and constructed and the output sinewave frequency is calculated .


Frequency

Amplitude

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Expt. No.5 HARTELY OSCILLATOR

Aim:To design and construct the given oscillator for the given frequency (fO).

Components & Equipment required:Sl. No. Components / Equipment

Range /



2 CRO 1


4 Resistors

5 Capacitors

6 DIB

7 DCB


Circuit Diagram:

0

0

Cin

CERE

Cout

R1

C

R2

RC

RL

BC107

B

C

E

L1 L2

Vcc = +12V

CRO

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Theory:

Hartley oscillator is a type of sine wave generator. The oscillator derives itsinitial output from the noise signals present in the circuit. After considerable time, itgains strength and thereby producing sustained oscillations. Hartley Oscillator have two

major parts namely amplifier part and feedback part. The amplifier part has a typicallyCE amplifier with voltage divider bias. In the feedback path, there is a LCL network.The feedback network generally provides a fraction of output as feedback.

Design:

VCC = 12V; IC = 1mA; fo = ; S = 2; hfe =

re = 26mV / IC = 26;

hie = hfe re =


VE = IERE = Vcc/10



RC =


RE = VE / IE =

S = 1+ RB / RE = 2

RB =

VB = VBE + VE =

VB = VCC R2/ (R1 + R2)

RB = R1 || R2

R1 = R2 =

Gain formula is given by,

AV =ie

Lefffe

h



RL =

XCi = {[hie+(1+hfe)RE]|| RB}/10 =

Ci = 1 / (2f XCi) =

Xco = Rleff /10 =

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Co = 1 / (2f XCo) =

XCE = RE/10 =

CE = 1 / (2f XCE) =

Feedback Network:

f0 = ; L1 = 1mH; L2 = 10mH

A =

1=

2

1

L

L

f =( )CLL2

1

21 +

C =

Procedure:

1. Connections are made as per the circuit diagram.2. Switch on the power supply and observe the output on the CRO (sine wave).3. Note down the practical frequency and compare with its theoretical frequency.

Model Graph:

Vout (Voltage)

Time(ms)

Result:Thus Hartley oscillator is designed and constructed and the output sine wavefrequency is calculated as


Frequency

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Expt. No.6 COLPITTS OSCILLATOR

Aim: To design and construct the given oscillator at the given operating frequency.

Equipments required:





3 CRO 1


5 Resistors

6 Capacitors

7 DIB

8 DCB

9 Connecting wires

Circuit Diagram:

0

0

Cin

CERE

Cout

R1

R2

RC

RL

BC107B

C

E

C1 C2

Vcc =

L

CRO

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Theory:

A Colpitts oscillator is the electrical dual of a Hartley oscillator. In the Colpittscircuit, two capacitors and one inductor determine the frequency of oscillation. Theoscillator derives its initial output from the noise signals present in the circuit. After

considerable time, it gains strength and thereby producing sustained oscillations. It hastwo major parts namely amplifier part and feedback part. The amplifier part has atypically CE amplifier with voltage divider bias. In the feedback path, there is a CLCnetwork. The feedback network generally provides a fraction of output as feedback.

Design:

VCC = 12V; IC = 1mA; fo = ; S = 2; hfe =

re = 26mV / IC = 26;

hie = hfe re =


VE = IERE = Vcc/10



RC =


RE = VE / IE =

S = 1+ RB / RE = 2RB =

VB = VBE + VE =

VB = VCC R2/ (R1 + R2)

RB = R1 || R2

R1 = R2 =

Gain formula is given by,

AV =ie

Lefffe

h



RL =

XCi = {[hie+(1+hfe) RE]|| RB}/10 =

Ci = 1 / (2f XCi) =

Xco = Rleff /10 =

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Co = 1 / (2f XCo) =

XCE = RE/10 =

CE = 1 / (2f XCE) =

Feedback Network:

f0 = ; C1 = ; C2 =

A =

1=

1

2

C

C

f =2

1

21

21

CLC

CC +

L =

Procedure:1. Rig up the circuit as per the circuit diagrams (both oscillators).2. Switches on the power supply and observe the output on the CRO (sine wave).3. Note down the practical frequency and compare with its theoretical frequency.

Model Graph:

Vout (Voltage)

Time(ms)

Result:Thus Colpitts oscillator is designed and constructed and the output sine wave

frequency is calculated as


Frequency

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Expt. No. 7(a) CMOS Inverter, NAND and NOR using PSPICE

Aim:

To plot the transient characteristics of output voltage for the given CMOS inverter,

NAND and NOR from 0 to 80s in steps of 1s. To calculate the voltage gain, input

impedance and output impedance for the input voltage of 5V.

Parameter Table:

Parameters PMOS NMOS

L 1 1W 20 5VTO -2 2

KP 4.5E-4 2

CBD 5p 5p

CBS 2p 2p

RD 5 5

RS 2 2

RB 0 0

RG 0 0

RDS 1Meg 1Meg

CGSO 1p 1p

CGDO 1p 1p

CGBO 1p 1p

Circuit Diagram:

(i) Inverter:

Vin

VDD = +5V

Vout

Q2

G

D

S

RL = 100K

Q1G

D

S

2

3

1

0

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(ii) NAND

Vout

Vin1

Q1

G

D

S

Q2G

D

S

Vin2

VDD = +5V

RL = 100K

Q4G

D

S

Q3G

D

S1

3

2

4

(iii) NOR

VDD = +5V

Q2G

D

S

RL = 100K

Vin2

Q1

G

D

S

Vout

Vin1

Q3G

D

S

Q4G

D

S

4

3

2

1

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Theory:

(i) Inverter

CMOS is widely used in digital ICs because of their high speed, low powerdissipation and it can be operated at high voltages resulting in improved noise immunity.

The inverter consists of two MOSFETs. The source of p-channel device is connected to+VDD and that of n-channel device is connected to ground. The gates of two devices areconnected as common input.

(ii) NANDIt consists of two p-channel MOSFETs connected in parallel and two n-channel

MOSFETs connected in series. P-channel MOSFET is ON when gate is negative and N-channel MOSFET is ON when gate is positive. Thus when both input is low and wheneither of input is low, the output is high.

(iii) NOR

It consists of two p-channel MOSFETs connected in series and two n-channelMOSFETs connected in parallel. P-channel MOSFET is ON when gate is negative and

N-channel MOSFET is ON when gate is positive. Thus when both inputs are high andwhen either of input is high, the output is low. When both the inputs are low, the outputis high.

Procedure:1. Draw the circuit diagram and mark the nodes.2. Go to start program Orcas release9.1-pspiceA/D and open the new text file.3. Type the PSPICE program on the text window4. Save the program in any location with CIR extension5. Go to file open simulation and create a new simulation file6. Go to simulation run. Now the result can be viewed either in the output file or in

graphical simulation file.

Truth Table:

(i) InverterInput Output

0 1

1 0

(ii) NANDV1 V2 Output

0 0 1

0 1 1

1 0 11 1 0

(iii) NORV1 V2 Output

0 0 1

0 1 0

1 0 0

1 1 0

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Model Graph:

(i) Inverter

Voltage

Input Waveform5V

time (s)0 10 20 30 40 50 60 70 80

Output Waveform5V

time (s)0 10 20 30 40 50 60 70 80

(ii) NANDVoltage

Input Waveform

time (s)

0 10 20 30 40 50 60 70 80

Output Waveform

time (s)0 10 20 30 40 50 60 70 80

time (s)0 10 20 30 40 50 60 70 80

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(iii) NOR

Voltage

Input Waveform

time (s)0 10 20 30 40 50 60 70 80

Output Waveform

0 10 20 30 40 50 60 70 80 time (s)

time (s)0 10 20 30 40 50 60 70 80

Output:

(i) Inverter

Gain = V (2)/Vin =Input Resistance at Vin =

Output Resistance at V (2) =

(ii) NANDGain = V (4)/Vin1 = V(4)/Vin2 =Input Resistance at Vin1 =Input Resistance at Vin2 =Output Resistance at V (4) =

(iii) NORGain = V (4)/Vin1 = V (4)/Vin2 =Input Resistance at Vin1 =

Input Resistance at Vin2 =Output Resistance at V (4) =

Result:

Thus the transient characteristics of output voltage for the given CMOS inverter,NAND and NOR is plotted and the voltage gain, input impedance and output impedanceare calculated.

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Expt. No.7 (b) SECOND ORDER BUTTERWORTH - LOW PASS FILTER

Aim:

To design and implement the second order butterworth Low pass filter usingPSpice.

Circuit Diagram:

-

+LM741

23

4

6

7

1V

RL

10KVIN

(100 - 10K)Hz

V+

RIN 1K RF 586 ohm

R2

1.59K

C2 0.1u

R1

1.59K

V-

C1 0.1u

1

0

35

0

2

6 VOUT

Theory:

A Low pass filter has a constant gain from 0 to fH. Hence the bandwidth of thefilter is fH. The range of frequency from 0 to fH is called pass band. The range offrequencies beyond fH is completely attenuated and it is called as stop band.

Procedure:

1. Draw the circuit diagram and mark the nodes.2. Go to start program orcad release9.1-pspiceA/D and open the new text file.3. Type the PSPICE program on the text window4. Save the program in any location with CIR extension5. Go to file open simulation and create a new simulation file6. Go to simulation run. Now the result can be viewed either in the output file or in

graphical simulation file

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Design:

fH = 1000HZ C1= C2 =0.1F RIN=1000

fH = 1 / 2RC

R = 1 / 2CfH

R = R1 = R2 = 1592

Gain = 1.5861.586 = 1 + (RF / RIN)

RF = 586

Model Graph:Gain (dB)

3dB

Frequency (HZ)fH

Result:

Thus Low pass filter is designed and implemented using PSpice.

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Expt. No.8 (a) DIFFERENTIAL AMPLIFIER

Aim:

To implement the differential amplifier using PSpice.

Circuit Diagram:

V+

R2 10K

VIN

-

+LM741

2

3

4

6

7

V-

VIN

RIN 10K

RF 10K

RCOMP10K

Vout

61 2

35

Theory:

A differential amplifier amplifies the difference between two voltages V1 and V2.The output of the differential amplifier is dependent on the difference between twosignals and the common mode signal since it finds the difference between two inputs itcan be used as a subtractor. The output of differential amplifier is

RFVO = (V2 V1)

R1

Procedure:

1. Draw the circuit diagram and mark the nodes.2. Go to start program Orcad release9.1-pspiceA/D and open the new text file.3. Type the PSPICE program on the text window4. Save the program in any location with CIR extension5. Go to file open simulation and create a new simulation file6. Go to simulation run. Now the result can be viewed either in the output file or in

graphical simulation file

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Model Graph:Voltage

V1 time

V2

time

V3

time

Calculation:

V1 = 5V V2 = 10VRF 10K

VO = (V2 V1) = (10 5)R1 10K

VO = 5V

Output: VO

= 5V

Result:

Thus a differential amplifier using op-amp is implemented in PSpice.

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Expt. No.8 (b) SECOND ORDER BUTTERWORTH - HIGH PASS FILTER

Aim:

To design and implement the second order butterworth High pass filter usingPSpice.

Circuit Diagram:

Theory:

A high pass filter passes "high frequencies" and attenuates low frequencies.Ideally, any frequencies above a specified "cutoff frequency" are passed. The cutoff isdetermined by circuit components and can vary greatly. A high-pass filter, roughly, ischaracterized by two things: its cutoff frequency, and its order. The cutoff frequency of

the above high-pass filter is fc = 1/(2RC). The order of the filter determines howsteeply the filter cuts off high frequencies; a first-order filter reduces signal power by 20dB per decade once the frequencies are below the cutoff frequency; that is, if the inputsignal frequency goes down by a factor of 10, the input will be attenuated roughly byfactor of 8 more than before. A second-order filter will attenuate at 40 dB per decade, andso on.

Procedure:

1. Draw the circuit diagram and mark the nodes.2. Go to start program Orcad release9.1-PspiceA/D and open the new text file.3. Type the PSPICE program on the text window4. Save the program in any location with .CIR extension5. Go to file open simulation and create a new simulation file

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6. Go to Simulation Run. Now the result can be viewed either in the output file orin graphical simulation file

Design:

FL = 1000HZ C1= C2 =0.1F RIN=1000

FL = 1 / 2RC

R = 1 / 2CfL

R = R1 = R2 = 1592Gain = 1.5861.586 = 1 + (RF / RIN)

RF = 586

Result:

Thus the second order high pass filter is designed and implemented using PSpice.

Documents

Lab Manual 1-8