Lab Practicing in Studying the Assembly Languages and Computer Architecture

Lab Practicing in Studying the Lab Practicing in Studying the Assembly Languages and Assembly Languages and

Computer ArchitectureComputer Architecturebbyy

Mile K. StojMile K. Stojčevčev11, Tatjana R. Stanković, Tatjana R. Stanković11 and Predrag V. Krtolicaand Predrag V. Krtolica22

11Faculty of Electronic Engineering in NiFaculty of Electronic Engineering in Niš,š, University of Ni University of Nišš 22Faculty of Science and Mathematics in NiFaculty of Science and Mathematics in Nišš, University of Ni, University of Nišš

OutlinesOutlines

I.I. IntroductionIntroduction

II.II. Review of the exercisesReview of the exercises

III.III. Structure of cycle oneStructure of cycle one

IV.IV. Structure of cycle twoStructure of cycle two

V.V. Structure of cycle threeStructure of cycle three

VI.VI. Structure of cycle fourStructure of cycle four

VII.VII. ConclusionConclusion

I. IntroductionI. Introduction

Lab exercisesLab exercises

Programming orientedProgramming oriented Logic design orientedLogic design oriented

DOS (4 exercises)DOS (4 exercises)

Intel 80x86 (15 exercises)Intel 80x86 (15 exercises)

MIPS (5 exercises)MIPS (5 exercises)

VHDL description of three VHDL description of three stage pipelined systemstage pipelined system

Six more exercises about Six more exercises about VHDL design, in perspectiveVHDL design, in perspective

Two very popular paradigms of the processor architecture in Two very popular paradigms of the processor architecture in computer science curricula are:computer science curricula are:

• MIPS processor,MIPS processor,

• Intel 80x86 microprocessor family.Intel 80x86 microprocessor family.

For writing and running programs in assembly language of For writing and running programs in assembly language of Intel microprocessor family we use MASM 6.11.Intel microprocessor family we use MASM 6.11.

But, MIPS workstations are expensive, so we use a PCSpim But, MIPS workstations are expensive, so we use a PCSpim simulator, created by J. R. Larus [6].simulator, created by J. R. Larus [6].

Programming oriented lab exercisesProgramming oriented lab exercises

The best way to learn programming is programming it self!The best way to learn programming is programming it self!








OutlinesOutlines

II. Review of the exercisesII. Review of the exercises

We have 28 exercises developed. We have 28 exercises developed.

Exercises 1-4 are devoted to DOS and related topics. Exercises 1-4 are devoted to DOS and related topics.

Exercises 5-19 are devoted to Intel 80x86 family and PWB editor. Exercises 5-19 are devoted to Intel 80x86 family and PWB editor.

Exercises 20-24 are devoted to MIPS programming and Exercises 20-24 are devoted to MIPS programming and corresponding simulator. corresponding simulator.

Exercises 25-28 are devoted to VHDL. Exercises 25-28 are devoted to VHDL.

The exercise material contains brief guidelines for the exercise, The exercise material contains brief guidelines for the exercise, followed by one or more practical tasks.followed by one or more practical tasks.

At the end of every exercise there is a set of questions, covering At the end of every exercise there is a set of questions, covering the underlying topic, which students should answerthe underlying topic, which students should answer..

The described exercises are part of subjects The described exercises are part of subjects Microprocessor Microprocessor systemssystems (2075) and (2075) and Microcomputer systemsMicrocomputer systems (6107) at Faculty of (6107) at Faculty of Electronic Engineering in NiElectronic Engineering in Nišš, University of Ni, University of Nišš..

These exercises are going to be introduced as a part of These exercises are going to be introduced as a part of Computer Computer systemssystems (1231) subject in III and IV semester of informatics (1231) subject in III and IV semester of informatics course, at Department of Mathematics and Informatics, Faculty course, at Department of Mathematics and Informatics, Faculty of Science and Mathematics in Niof Science and Mathematics in Nišš, University of Ni, University of Nišš..

General structure and usage of lab exercisesGeneral structure and usage of lab exercises








OutlinesOutlines

No.No. ExerciseExercise 20752075 61076107 12311231

1.1. DOS user manualDOS user manual

2.2. Autoexec.bat and config.sys filesAutoexec.bat and config.sys files

3.3. Batch filesBatch files

4.4. Using DEBUG programUsing DEBUG program

- prerequisite

- part of the subject

- not included in the subject

III. Structure of cycle oneIII. Structure of cycle one

- Microprocessor systems (2+2+1, semesters VII & VIII at FENN)

- Microcomputer systems (2+2+1, VII semester at FENN)

- Computer systems (2+2+1, semesters III & IV at FSMN)

Let us suppose that a small program is displaying a message Let us suppose that a small program is displaying a message “Hi, colleagues”. To display a character string, DOS function call 9 “Hi, colleagues”. To display a character string, DOS function call 9 is used. This function requires that register pairis used. This function requires that register pair DS:DX DS:DX points to points to stringstring and and AH registAH registeer r containscontains 09H, 09H, before before INT 21HINT 21H instruction instruction is is executed. This instruction allows access to DOS functions. Note executed. This instruction allows access to DOS functions. Note that character string must be ended with $. In the following that character string must be ended with $. In the following example the character string is stored from address example the character string is stored from address 1000:01000:01100, 00, andand program program is stored from addressis stored from address 1000:0000: 1000:0000:

Problem definition from a part of Exercise 4Problem definition from a part of Exercise 4

-A1000:0100-A1000:01001000:01001000:0100 DBDB ’’Hi, colleaguesHi, colleagues$’$’1000:010E1000:010E-A1000:0000-A1000:00001000:00001000:0000 MOVMOV AX,1000AX,10001000:00031000:0003 MOVMOV DS, AXDS, AX1000:00051000:0005 MOVMOV AH, 9AH, 91000:00071000:0007 MOVMOV DX, 100DX, 1001000:000A1000:000A INTINT 21211000:000C1000:000C INTINT 33--

Example program from a part of Exercise 4Example program from a part of Exercise 4

StepStep 5: 5: Using the commandUsing the command U ( U (UnassembleUnassemble) ) check if the program check if the program is stored in memory, i.e. display it using DEBUG command:is stored in memory, i.e. display it using DEBUG command:

U1000:0000U1000:0000

If the program is correctly stored, its execution is possible.If the program is correctly stored, its execution is possible.

Task from a part of Exercise 4Task from a part of Exercise 4

These four exercises should make the students totally These four exercises should make the students totally independent for work in DOS environment. independent for work in DOS environment.

Students were taught about the most frequent DOS Students were taught about the most frequent DOS commands, including batch files commands, and about commands, including batch files commands, and about setting a computer defining contents of setting a computer defining contents of autoexec.batautoexec.bat and and config.sysconfig.sys. .

Students are introduced in editor EDIT and DEBUG Students are introduced in editor EDIT and DEBUG program. program.

Their knowledge about DOS and related topics can be Their knowledge about DOS and related topics can be estimated from medium to advanced. estimated from medium to advanced.

What we get?What we get?

I. Introduction

II. Review of the exercises

III. Structure of cycle one

IV. Structure of cycle two

V. Structure of cycle three

VI. Structure of cycle four

VII. Conclusion

Outlines

No. Exercise 20752075 61076107 12311231

5. PWB & CodeView programs

6. Introducing 80x86 assembly language

7. Models & full segment definition

8. Additional DOS INT 21H instructions

9. Macros

10. Data conversions

11. Lookup tables

12. Using disk files

13. Video memory access –VGA controller

IV. Structure of cycle twoIV. Structure of cycle two

No. Exercise 20752075 61076107 12311231

14. Using the mouse

15. Interrupt processing

16. TSR programs

17. Arithmetic coprocessor programming

18. 80386 – Pentium instructions usage

19. Project tasks

(continued)(continued)

CODECODE SEGMENT ‘code’ SEGMENT ‘code’ASSUME CS: CODEASSUME CS: CODEMAINMAIN PROC PROC FARFAR

MOV MOV AH,02HAH,02HMOV MOV DL,’A’DL,’A’ ;; display A display AINT INT 21H21HMOVMOV DL,’B’DL,’B’ ;; display display B BINTINT 21H 21H MOVMOV DL,’C’DL,’C’ ;; display display C CINT INT 21H21HMOVMOV AX,4C00H AX,4C00H ;; return to return to DOS DOSINT INT 21H21H

MAINMAIN ENDPENDP ;; end of MAIN end of MAINCODECODE ENDSENDS ;; end of end of program segmentprogram segmentEND END MAINMAIN

Example program from a part of Exercise 6Example program from a part of Exercise 6

Note thatNote that that the value 02H is stored in AH register only that the value 02H is stored in AH register only once, in the begining of the program. Further calls for once, in the begining of the program. Further calls for displying an ASCII character need not tdisplying an ASCII character need not too lo loaad 02H in AH. d 02H in AH. Only contents of AL is changed.Only contents of AL is changed.

Note for example from a part of Exercise 6Note for example from a part of Exercise 6

StepStep 1: 1: Using Using PWB, PWB, type thetype the program program from Examplefrom Example 6-1 6-1 and check if it runs correctly. Now, rewrite the program to and check if it runs correctly. Now, rewrite the program to display word ELEFdisplay word ELEF. . Do not forget that contents of DL Do not forget that contents of DL register is reserved by DOS INTregister is reserved by DOS INT 21H 21H function call (in DL function call (in DL the current character to display must be stored)the current character to display must be stored)..

Task from a part of Exercise 6Task from a part of Exercise 6


By completing these exercises, the students become capable By completing these exercises, the students become capable of writing and running programs for Intel microprocessor of writing and running programs for Intel microprocessor family. family.

Their knowledge in assembly programming is medium Their knowledge in assembly programming is medium graded, and allows them to be independent in future graded, and allows them to be independent in future programming tasks. programming tasks.

Students should understand better the architecture of Students should understand better the architecture of computers based on Intel microprocessor family, and they computers based on Intel microprocessor family, and they should know more about overall computer operation. should know more about overall computer operation.

I. Introduction






VII. Conclusion

Outlines

No. Exercise 20752075 61076107 12311231

20. PCSpim user manual

21. MIPS instruction set

22. Translation of HLL statements, …

23. Data dependencies, loops

24. Recursive procedures, functions …

V. Structure of cycle threeV. Structure of cycle three

PCSpim layoutPCSpim layout

Settings dialog boxSettings dialog box

In the following we will present the complete In the following we will present the complete layout of exercise 21 named layout of exercise 21 named MIPS instruction set, MIPS instruction set, pseudoinstructions.pseudoinstructions.

Student: _____________________ Date: ______________

Lab exercise 21Lab exercise 21

MIPS instruction set, pseudoinstructionsMIPS instruction set, pseudoinstructions

For this lab exercise, the experience in PCSpim simulator usage from the For this lab exercise, the experience in PCSpim simulator usage from the previous exercise is needed. Also, knowledge about basic instruction set for previous exercise is needed. Also, knowledge about basic instruction set for microprocessor MIPS, available in [1] and [2] (chapters 4 and 5), is necessary. microprocessor MIPS, available in [1] and [2] (chapters 4 and 5), is necessary. Inputting and running the shorter sequences in MIPS assembly language, a student Inputting and running the shorter sequences in MIPS assembly language, a student should confirm his/hers knowledge about the instruction execution mechanism should confirm his/hers knowledge about the instruction execution mechanism through the effects of this execution. Also, the notion of through the effects of this execution. Also, the notion of pseudoinstructionspseudoinstructions is is introduced, and their importance, as well. By the example of two vectors introduced, and their importance, as well. By the example of two vectors comparison, the student is introduced to the fundamental conventions of assembly comparison, the student is introduced to the fundamental conventions of assembly programs writing.programs writing.

IntroductionIntroduction

Introduce yourself to basic instruction and functional instruction sequences Introduce yourself to basic instruction and functional instruction sequences which correspond to HLL statements. Make an overview of complete program, which correspond to HLL statements. Make an overview of complete program, that is, the ways of data declaration (that is, the ways of data declaration (data segmentdata segment) and program declaration () and program declaration (text text segmentsegment).).

TaskTask

Working procedureWorking procedure

Step 1Step 1: Let : Let A A be a 100 elements vector, and be a 100 elements vector, and g g = 1500 and = 1500 and h h = 1900 are variables. = 1900 are variables. The variables The variables gg and and hh should be stored in registers $s1 and $s2, respectively, the should be stored in registers $s1 and $s2, respectively, the vector A base address in $s3, while the result should be stored at location of vector A base address in $s3, while the result should be stored at location of variable variable gg. Firstly, in . Firstly, in Notepad Notepad editor type data declaration as the following:editor type data declaration as the following:

.data.dataa:a: .word 0x00001234 0x00005678 0x00009abc 0x0000def0 0x12340000 .word 0x00001234 0x00005678 0x00009abc 0x0000def0 0x12340000

.word 0x56780000 0x9abc0000 0xdef00000 0x00123400 0x00567800 .word 0x56780000 0x9abc0000 0xdef00000 0x00123400 0x00567800

.word 0x009abc00.word 0x009abc00g: g: .word 1500.word 1500h: h: .word 1900.word 1900

The following C statementThe following C statement

g = h + A[8];g = h + A[8];

translated to MIPS assembly language has a form:translated to MIPS assembly language has a form:

main:main:llaa $s3,$s3,aa # # address of address of aa[0[0]]$s3$s3lwlw $s2,h($zero)$s2,h($zero) # h# h$s2$s2lwlw $t0,$t0,3232($s3)($s3) # a8# a8$t0$t0addadd $s1,$s2,$t0$s1,$s2,$t0 # g = $s1 = h + a[8]# g = $s1 = h + a[8]swsw $s1,g($zero)$s1,g($zero) # g# gGGjj $ra$ra

In the same file, after the data, enter directive In the same file, after the data, enter directive .globl main.globl main, and, after that, the , and, after that, the sequence beginning at label sequence beginning at label mainmain. Save the program as pr_1.asm in PCSpim . Save the program as pr_1.asm in PCSpim directory. Run this program step by step (using F10 key). Note the effects of every directory. Run this program step by step (using F10 key). Note the effects of every instruction execution, and write them in source file as a comment. Which of the instruction execution, and write them in source file as a comment. Which of the instructions are the pseudoinstructions? Which is the hexadecimal value of the instructions are the pseudoinstructions? Which is the hexadecimal value of the result?result?

Step 2Step 2: Using the same text editor as in Step 1, type the following MIPS : Using the same text editor as in Step 1, type the following MIPS assembly code for comparisons of two integer vectors. How many values should assembly code for comparisons of two integer vectors. How many values should be tested in each vector? What is the form of the result and where comparison be tested in each vector? What is the form of the result and where comparison result is stored? Run the program and write, as the comments, the effects of every result is stored? Run the program and write, as the comments, the effects of every instruction in the source file.instruction in the source file.

.text.text

.globl main.globl mainmain:main:subu $sp, $sp, 32subu $sp, $sp, 32sw $ra, 20($sp)sw $ra, 20($sp)sw $fp, 16($sp)sw $fp, 16($sp)addu $fp, $sp, 32addu $fp, $sp, 32lw $a0, sizelw $a0, sizela $a1, array1la $a1, array1la $a2, array2la $a2, array2jal comparejal comparelw $ra, 20($sp)lw $ra, 20($sp)lw $fp, 16($sp)lw $fp, 16($sp)addu $sp, $sp, 32addu $sp, $sp, 32j $raj $ra# a0 = vector length# a0 = vector length# a1 = base address of vector 1# a1 = base address of vector 1# a2 = base address of vector 2# a2 = base address of vector 2compare:compare:subu $sp, $sp, 32subu $sp, $sp, 32sw $ra, 20($sp)sw $ra, 20($sp)sw $fp, 16($sp)sw $fp, 16($sp)addiu $fp, $sp, 32addiu $fp, $sp, 32

loop:loop:beq $a0, $0, donebeq $a0, $0, donelw $t0, 0($a1)lw $t0, 0($a1)lw $t1, 0($a2)lw $t1, 0($a2)bne $t0, $t1, nobne $t0, $t1, noaddiu $a1, $a1, 4addiu $a1, $a1, 4addiu $a2, $a2, 4addiu $a2, $a2, 4addi $a0, $a0, -1addi $a0, $a0, -1b loopb loopno:no:ori $v0, $0, 1ori $v0, $0, 1b returnb returndone:done:ori $v0, $0, 0ori $v0, $0, 0return:return:lw $31, 20($sp)lw $31, 20($sp)lw $fp, 16($sp)lw $fp, 16($sp)addu $sp, $sp, 32addu $sp, $sp, 32j $31j $31.data.datasize: size: .word 5.word 5array1: .word 1 2 3 4 5array1: .word 1 2 3 4 5array2: .word 1 2 3 4 5array2: .word 1 2 3 4 5

Step 3: Step 3: As we noted in Step 1, there are some assembly instructions called As we noted in Step 1, there are some assembly instructions called pseudoinstructionspseudoinstructions. The assembler translates them in the form of the shorter . The assembler translates them in the form of the shorter sequences of instructions from basic set (sequences of instructions from basic set (bar-codebar-code). After that, they are translated ). After that, they are translated in machine code. Using the descriptions of basic assembly instructions, find out in machine code. Using the descriptions of basic assembly instructions, find out the bar-code sequences which should replace the following instructions:the bar-code sequences which should replace the following instructions:

a) a) abs, babs, b) ) mul, mul, c) c) neg, neg, d) d) rem, rem, e) e) rol, rol, f) f) seq, seq, g) g) bgeu, bgeu, h) h) bgt, bgt, and i) and i) ldld..

Check if PCSpim supports these pseudoinstructions. For supported ones, compare Check if PCSpim supports these pseudoinstructions. For supported ones, compare them with your solution.them with your solution.

QuestionsQuestions

1.1. Explain the notion of bar-code machine.Explain the notion of bar-code machine.

2.2. By which directive data segment starts, and by which program By which directive data segment starts, and by which program segment starts?segment starts?

3.3. Find the key instruction in pr_1.asm that fetches the target Find the key instruction in pr_1.asm that fetches the target vector element. What is the index of this element?vector element. What is the index of this element?

4.4. Draw a flowchart for two vector comparison example. Mark Draw a flowchart for two vector comparison example. Mark the program labels on the flowchart.the program labels on the flowchart.

5.5. Observe and point every pseudoinstruction in the given Observe and point every pseudoinstruction in the given examples.examples.

Examined by: ____________________ Grade: __________


Using PCSpim simulator and MIPS assembly language in Using PCSpim simulator and MIPS assembly language in these exercises get more skills in MIPS programming,these exercises get more skills in MIPS programming,

Also, they get better picture of RISC architecture and Also, they get better picture of RISC architecture and parallelism on machine and instruction level. parallelism on machine and instruction level.

I. Introduction






VII. Conclusion

Outlines

No. Exercise 20752075 61076107 12311231

25. Pipelined microcontroller

26. Predecode i Decode blocks

27. Register file and Execute blocks

28. Microcontroller

VI. Structure of cycle fourVI. Structure of cycle four

decode

d_data

d_command

execution

d_src2

d_src1

d_dst

predecode

register file

d_src1_data

d_src2_data

ext_data

ext_store

ext_dst

pd_read

pd_dst

pd_data

command

pd_src1

pd_src2

flush

jump

output

data

dst

src2

src1

inst

Microarchitectural definition of microcontrollerMicroarchitectural definition of microcontroller

Microcontroller instruction setMicrocontroller instruction set

Instruction setInstruction set DescriptionDescription

MOVE <src1>,<dst>MOVE <src1>,<dst> Copy contents of Copy contents of <src1> in <dst><src1> in <dst>

ADD <src1>,<src2>,<dst>ADD <src1>,<src2>,<dst> Add contents of <src1> with contents of <src2> and store Add contents of <src1> with contents of <src2> and store result in <dst>result in <dst>

SUB <src1>,<src2>,<dst>SUB <src1>,<src2>,<dst> Subtract contents of <src1> from contents of <src2> and Subtract contents of <src1> from contents of <src2> and store result in <dst>store result in <dst>

MUL <src1>,<src2>,<dst>MUL <src1>,<src2>,<dst> Multiply contents of <src1> and <src2> and store result in Multiply contents of <src1> and <src2> and store result in <dst><dst>

CJE CJE <src1>,<src2>,<CODE><src1>,<src2>,<CODE>

Compare contents of <src1> and <src2> and, if they equal, Compare contents of <src1> and <src2> and, if they equal, branch to instruction labeled with <CODE>branch to instruction labeled with <CODE>

LOAD <val>,<dst>LOAD <val>,<dst> Load contents of <val> in <dst>Load contents of <val> in <dst>

READ <dst>READ <dst> Read contents of <dst> and transfer data to the output pinsRead contents of <dst> and transfer data to the output pins

NOPNOP Operation without effectOperation without effect

ENTITY decode_ent ISENTITY decode_ent ISPORTPORT ((

clock : IN std_logic;clock : IN std_logic;command : IN command_type;command : IN command_type;pd_source1 : IN register_type;pd_source1 : IN register_type;pd_pd_source2 : IN register_type;source2 : IN register_type;pd_pd_destination : IN register_type;destination : IN register_type;pd_data : IN std_logic_vector (31 downto 0);pd_data : IN std_logic_vector (31 downto 0);flush : IN std_logic;flush : IN std_logic;d_command : OUT command_type;d_command : OUT command_type;

d_d_destination : OUT register_type;destination : OUT register_type;d_source1 : OUT register_type;d_source1 : OUT register_type;

d_d_source2 : OUT register_type;source2 : OUT register_type;d_data : OUT std_logic_vector (31 downto 0);d_data : OUT std_logic_vector (31 downto 0);

););END decode_ent;END decode_ent;

VHDL ENTITY description of DECODE blockVHDL ENTITY description of DECODE block

Load Load #10051, reg0#10051, reg0Load Load #1, reg1#1, reg1Add Add reg0, reg1, reg2reg0, reg1, reg2Sub Sub reg0, reg1, reg3reg0, reg1, reg3

Benchmark program from Exercise 26Benchmark program from Exercise 26

Modify testbench program code to stimulate predecode block by the following instructions:

Group 1: Group 2:Load #183FFA20, reg2 Load #183FFA20, reg5Load #0210AA18, reg4 Load #0210AA18, reg3Add reg2, reg4, reg8 Sub reg3, reg5, reg9Read reg8 Read reg9Nop Move reg3, reg5 Read reg5

One of the tasks from Exercise 26 for two One of the tasks from Exercise 26 for two groups of students (there are much more group groups of students (there are much more group

tasks)tasks)

LIBRARY IEEE;LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.std_logic_1164.ALL;USE WORK.pipeline_package.ALL;USE WORK.pipeline_package.ALL; ENTITY predecode_ent ISENTITY predecode_ent ISPORTPORT ((

clock : IN std_logic;clock : IN std_logic;inst : IN std_logic_vector (2 downto 0);inst : IN std_logic_vector (2 downto 0);source1 : IN std_logic_vector (3 downto 0);source1 : IN std_logic_vector (3 downto 0);source2 : IN std_logic_vector (3 downto 0);source2 : IN std_logic_vector (3 downto 0);destination : IN std_logic_vector (3 downto 0);destination : IN std_logic_vector (3 downto 0);data : IN std_logic_vector (31 downto 0);data : IN std_logic_vector (31 downto 0);flush : IN std_logic;flush : IN std_logic;command : OUT command_type;command : OUT command_type;pd_source1 : OUT register_type;pd_source1 : OUT register_type;pd_source2 : OUT register_type;pd_source2 : OUT register_type;pd_destination : OUT register_type;pd_destination : OUT register_type;pd_data : OUT std_logic_vector (31 downto 0);pd_data : OUT std_logic_vector (31 downto 0);pd_read : OUT std_logicpd_read : OUT std_logic););

END predecode_ent;END predecode_ent;

VHDL code for PREDECODE blockVHDL code for PREDECODE block

ARCHITECTURE predecode_arch OF predecode_ent ISBEGINPROCESS (clock, inst, source1, source2, destination, data, flush)

VARIABLE internal_command : command_type := NOP;VARIABLE internal_source1 : register_type := reg0;VARIABLE internal_source2 : register_type := reg0;VARIABLE internal_destination : register_type := reg0;

BEGINIF (clock = '1' AND clock'EVENT) THEN

IF (flush = '0') THENCASE inst IS

WHEN "000" =>pd_read <= '1';internal_command := MOVE;

WHEN "001" =>pd_read <= '1';internal_command := ADD;

WHEN "010" =>pd_read <= '1';internal_command := SUB;

continuedcontinued

WHEN "011" =>pd_read <= '1';internal_command := MUL;

WHEN "100" =>pd_read <= '1';internal_command := CJE;

WHEN "101" =>pd_read <= '0';internal_command := LOAD;

WHEN "110" =>pd_read <= '1';internal_command := READ;

WHEN "111" =>pd_read <= '0';internal_command := NOP;

WHEN OTHERS =>NULL;

END CASE;

continuedcontinued

CASE source1 ISWHEN "0000" =>

internal_source1 := reg0;WHEN "0001" =>









internal_source1 := reg9;

continuedcontinued

WHEN "1010" =>internal_source1 := reg10;






WHEN OTHERS =>NULL;

END CASE;

continuedcontinued

continuedcontinued

CASE source2 ISWHEN "0000" =>










internal_source2 := reg9;

continuedcontinued







WHEN OTHERS =>NULL;

END CASE;

continuedcontinued

CASE destination ISWHEN "0000" =>

internal_destination := reg0;WHEN "0001" =>









internal_destination := reg9;

continuedcontinued

WHEN "1010" =>internal_destination := reg10;






WHEN OTHERS =>NULL;

END CASE;

continuedcontinued

IF (internal_command = LOAD) THENpd_data <= data;

ELSEpd_data <=(others => '0');

END IF;ELSE

pd_data <= (others => '0');internal_command := NOP;pd_read <= '0';

END IF;command <= internal_command;pd_source1 <= internal_source1;pd_source2 <= internal_source2;pd_destination <= internal_destination;

END IF;END PROCESS;

END predecode_arch;

Using these exercises, students should get the basic Using these exercises, students should get the basic knowledge about logic design in VHDL and pipelined knowledge about logic design in VHDL and pipelined processor organization.processor organization.


I. Introduction






VII. Conclusion

Outlines

VII. ConclusionVII. Conclusion

Innovation of the lab exercises for subjects Innovation of the lab exercises for subjects Microprocessor Microprocessor systemssystems (2075) and (2075) and Microcomputer systemsMicrocomputer systems (6107) at Faculty of (6107) at Faculty of Electronic Engineering in NiElectronic Engineering in Nišš, , and and Computer systemsComputer systems (1231) at (1231) at Department of Mathematics and Informatics, Faculty of Science Department of Mathematics and Informatics, Faculty of Science and Mathematics in Niand Mathematics in Nišš..

We have 28 exercises developed divided in four groups: the We have 28 exercises developed divided in four groups: the exercises devoted to DOS, the exercises devoted to Intel 80x86 exercises devoted to DOS, the exercises devoted to Intel 80x86 microprocessor family programming, the exercises devoted to microprocessor family programming, the exercises devoted to MIPS programming, and the exercises devoted to logic design MIPS programming, and the exercises devoted to logic design using VHDL.using VHDL.

So far experience tells us that students are very interested in So far experience tells us that students are very interested in working on these lab exercises, which obviously means that we working on these lab exercises, which obviously means that we made a good choice of the exercises.made a good choice of the exercises.

References[1][1] M. K. StojM. K. Stojččev, S. S. Ristiev, S. S. Ristić, M. D. Krstić, ć, M. D. Krstić, “Problems in “Problems in

microprocessors and microcomputers”, microprocessors and microcomputers”, Faculty of Electronic Faculty of Electronic Engeneerinig, Niš, 1999 (in Serbian).Engeneerinig, Niš, 1999 (in Serbian).

[2][2] M. K. StojM. K. Stojččev, “RISC, CISC, and DSP Processors”, ev, “RISC, CISC, and DSP Processors”, Faculty of Faculty of Electronic Engeneerinig, Niš, 1997 (in Serbian).Electronic Engeneerinig, Niš, 1997 (in Serbian).

[3][3] M. K. StojM. K. Stojččev, B. D. Petroviev, B. D. Petrovićć, “Architecture and programming , “Architecture and programming of microcomputer systems based on 80x86 processor family”, of microcomputer systems based on 80x86 processor family”, Faculty of Electronic Engeneerinig, Niš, 1999 (in Serbian).Faculty of Electronic Engeneerinig, Niš, 1999 (in Serbian).

[4][4] M. K. StojM. K. Stojččev, R. S. Stankoviev, R. S. Stankovićć, P. V. Krtolica, “Microprocessors , P. V. Krtolica, “Microprocessors and Microcomputers: Lab Practicing Manual, and Microcomputers: Lab Practicing Manual, Faculty of Faculty of Electronic Engeneerinig & Faculty of Science and Mathematics, Electronic Engeneerinig & Faculty of Science and Mathematics, Niš, 2003 (in Serbian).Niš, 2003 (in Serbian).

[5][5] M. K. StojM. K. Stojččev, P. V. Krtolica, “Computer Systems: Digital ev, P. V. Krtolica, “Computer Systems: Digital Systems Principles, Systems Principles, Faculty of Science and Mathematics, Niš, Faculty of Science and Mathematics, Niš, 2003 (Web edition).2003 (Web edition).

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[8][8] J. Uffenbeck, “The 80x86 Family: Design, Programming, and J. Uffenbeck, “The 80x86 Family: Design, Programming, and Interfacing 2/e”, Prentice Hall, NJ, 1998.Interfacing 2/e”, Prentice Hall, NJ, 1998.

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Documents

Lab Practicing in Studying the Assembly Languages and Computer Architecture