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SECOND EDITION

First Printing, July 2003

Copyright July, 2003 Lab-Volt Systems, Inc.

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THIS

i

Table of Contents

Section 1 – Workstation Inventory and Installation............................................................... 1-1

Inventory of Workstation ........................................................................................................ 1-1

Minimum Computer Requirements.................................................................................... 1-1

Equipment and Supplies..................................................................................................... 1-1

Equipment Installation ............................................................................................................ 1-1

Software Installation ............................................................................................................... 1-1

Section 2 – Introduction to FACET Curriculum.................................................................... 2-1

Getting Started ........................................................................................................................ 2-2

Screen Buttons ........................................................................................................................ 2-3

FACET Help Screens and Resources...................................................................................... 2-4

Internet Access ........................................................................................................................ 2-5

Instructor Annotation Tool...................................................................................................... 2-5

Student Journal........................................................................................................................ 2-5

Assessing Progress .................................................................................................................. 2-6

Real-Number Questions and Answers .................................................................................... 2-8

Recall Values in Text ............................................................................................................ 2-10

Safety .................................................................................................................................... 2-10

Safety .................................................................................................................................... 2-11

Section 3 – Courseware ............................................................................................................. 3-1

Unit 1 – Trainer Familiarization .............................................................................................. 3-1

Exercise 1 – Introduction to the Trainer ................................................................................. 3-4

Exercise 2 – Operating the Trainer ....................................................................................... 3-12

Unit 2 – Bus Operations .......................................................................................................... 3-21

Exercise 1 – Bus States ......................................................................................................... 3-24

Exercise 2 – 32-Bit Bus Transfers ........................................................................................ 3-30

Exercise 3 – Read and Write Cycles ..................................................................................... 3-37

Exercise – CPU Initialization................................................................................................ 3-42

Unit 3 – Memory Interfacing .................................................................................................. 3-51

Exercise 1 – Memory Control Signals .................................................................................. 3-54

Exercise 2 – Memory Address Decoding.............................................................................. 3-64

Exercise 3 – Memory Data Transfers.................................................................................... 3-73

ii

Unit 4 – I/O Interfacing ........................................................................................................... 3-81

Exercise 1 – DAC and ADC Ports ........................................................................................ 3-82

Exercise 2 – PPI and Keypad Interface................................................................................. 3-88

Exercise 3 – Display and Serial Port..................................................................................... 3-95

Unit 5 – Interrupt Processing................................................................................................ 3-103

Exercise 1 – Non-Maskable Interrupts................................................................................ 3-107

Exercise 2 – Maskable Interrupts........................................................................................ 3-115

Exercise 3 – Exceptions ...................................................................................................... 3-124

Unit 6 – Programming: Addressing Modes ......................................................................... 3-135

Exercise 1 – Immediate and Register Addressing Modes................................................... 3-137

Exercise 2 – Memory Addressing Modes - I ...................................................................... 3-144

Exercise 3 – Memory Addressing Modes - II ..................................................................... 3-152

Unit 7 – Programming: 80386 CPU Instructions................................................................ 3-159

Exercise 1 – Instruction Formats - I .................................................................................... 3-160

Exercise 2 – Instruction Formats - II................................................................................... 3-169

Exercise 3 – Using the 80386 CPU Instructions - I ............................................................ 3-178

Exercise 4 – Using the 80386 CPU Instructions - II........................................................... 3-186

Unit 8 – Troubleshooting....................................................................................................... 3-195

Unit 9 – Microprocessor Applications (Optional)............................................................... 3-199

Exercise 1 – Application Board Familiarization................................................................. 3-201

Exercise 2 – DC Motor Control .......................................................................................... 3-206

Exercise 3 – Temperature Control ...................................................................................... 3-213

Appendix A – Pretest and Posttest Questions and Answers ................................................. A-1

Appendix B – Faults and Circuit Modifications (CMs) .........................................................B-1

Appendix C – Board and Courseware Troubleshooting....................................................... C-1

iii

Introduction

This Instructor Guide is divided into three sections and the appendices. It provides a unit-by-unit

outline of the Fault Assisted Circuits for Electronics Training (FACET) curriculum.

Section 1 – Workstation Inventory and Installation contains a list and description of

equipment and materials required for all units in this course of study as well as installation

instructions.

Section 2 – Introduction to FACET Curriculum provides a description of the courseware

structure, instructions on getting started with the multimedia presentation, and an explanation of

student-progress assessment methods.

Section 3 – Courseware includes information that enables the instructor to gain a general

understanding of the units within the course.

♦ The unit objective

♦ Unit Fundamentals questions and answers

♦ A list of new terms and words for the unit

♦ Equipment required for the unit

♦ The exercise objectives

♦ Exercise Discussion questions and answers

♦ Exercise Procedure questions and answers

♦ Review questions and answers

♦ CMs and Faults available

♦ Unit Test questions and answers

♦ Troubleshooting questions and answers (where applicable)

Appendices include the questions and answers to the Pretest and Posttest plus additional specific

information on faults and circuit modifications (CMs).

Please complete and return the OWNER REGISTRATION CARD included with the CD-

ROM. This will assist Lab-Volt in ensuring that our customers receive maximum support.

iv

THIS

SECTION 1 – WORKSTATION INVENTORY

AND INSTALLATION

THIS

32 Bit Microprocessor Section 1 – Workstation Inventory and Installation

1-1

SECTION 1 – WORKSTATION INVENTORY AND INSTALLATION

Inventory of Workstation

Use this section to identify and inventory the items needed.

Minimum Computer Requirements 100% compatible Windows

®PC with Windows98 second edition or newer, NT, 2000, Me or XP;

Pentium class CPU, (Pentium II or newer); 126 MB RAM; 10 GB HDD; CD-ROM drive; SVGA

monitor and video card capable of 32-bit color display at 1024 x 768 resolution and sound

capabilities.

Equipment and Supplies The following equipment and supplies are needed for 32 Bit Microprocessor:

Quantity Description

1 F.A.C.E.T. base unit

1 Multimeter

1 Oscilloscope, dual trace

1 32-BIT MICROPROCESSOR circuit board

1 Student Workbook

Instructor Guide

MICROPROCESSOR APPLICATION BOARD (optional)

Equipment Installation

To install the hardware, refer to the Tech-Lab (minimum version 6.x) Installation Guide..

Software Installation

Third Party Application Installation

All applications and files that the courseware launches, or that are required for the course should

be installed before the courseware. Load all third party software according to the manufacturers'

directions. Install this software to the default location and note that location. (Alternatively, you

can install this software to a different location that you designate.) Remember to register all

software as required.

No third-party software is required for this course.

Installation of Courseware and Resources

To install the courseware and resources, refer to the Tech-Lab (minimum version 6.x) and

Gradepoint 2020 (minimum version 6.x) Installation Guide.

32 Bit Microprocessor Section 1 – Workstation Inventory and Installation

1-2

SECTION 2 – INTRODUCTION TO FACET

CURRICULUM

THIS

32 Bit Microprocessor Section 2 – Introduction to FACET Curriculum

2-1

SECTION 2 – INTRODUCTION TO FACET CURRICULUM

Overview FACET curriculum is multimedia-based courseware. The curriculum gives students hands-on

experience using equipment and software closely associated with industry standards. It provides

students with opportunities for instruction in academic and technical skills.

All courses are activity-driven curricula. Each course consists of several units containing two or

more exercises. Each unit begins with a statement explaining the overall goal of the unit (Unit

Objective). This is followed by Unit Fundamentals. Next is a list of new terms and words then

the equipment required for the unit. The exercises follow the unit material. When students

complete all the exercises, they complete the Troubleshooting section and take the Unit Test.

The exercises consist of an exercise objective, exercise discussion, and exercise procedures. The

Exercise Conclusions section provides the students with a list of their achievements. Every

exercise concludes with Review Questions. Available circuit modifications (CMs) and faults are

listed after the review questions. Additional specific information on CMs and faults is available

in Appendix B.


2-2

Getting Started

Desktop

After the Tech-Lab System is installed, the TechLab icon appears on the desktop.

1. Click on the TechLab icon.

2. The student clicks on LOGON and selects his or her name.

3. The student enters his or her password and clicks on OK. (If he or she is creating a password,

four alphanumeric characters must be entered. The system will ask for the password to be

entered again for verification. Keep a record of the students' passwords.)

4. The previous two steps are repeated until all members of the student team have logged on.

Click on Complete and then Yes.

5. When the Available Courses menu appears, students click on the course name.

6. A window with the name of the course and a list of units for that course appears. Students

click on the unit name. The unit title page appears and the students are ready to begin.

Selecting Other Courses and Exiting the Courseware

1. Clicking on Exit when in a unit returns the student to the list of units for that course.

2. If students wish to select another unit, they click on it.

3. If students wish to exit FACET, they click on the X symbol in the upper right corner.

4. If students wish to exit another course, they click on the Course Menu button. The Available

Courses menu screen appears. They may also exit FACET from this screen by clicking on the

LOGOFF button.


2-3

Screen Buttons

If you click on the FACET logo on the top right of the unit title page the About screen appears. It

acknowledges the copyright holder(s) of video and/or screen-capture material used in the topic.

The Menu button calls these menus:

when on an exercise menu screen, it calls the Unit Menu.

when on an exercise screen, it calls the Exercise Menu.

when on a unit screen, it calls the Unit Menu.

The Bookmark button marks the current screen. A student can click on the button at any time in

the lesson. The second time the student clicks on the button, the page displayed when the button

was first clicked will return to the screen. Any bookmarks used during a lesson are not saved

when the student logs out of the lesson.

The Application Launch button opens third-party software.

Click on the Resources button to view a pop-up menu. The pop-up menu includes access to a

calculator, a student journal, new terms and words, a print current screen option, the Lab-Volt

authored Internet Website, and a variety of FACET help screens.

The Help button aids students with system information. On certain screens the Help button

appears to be depressed. On these screens, clicking on the Help button will access Screen Help

windows (context-sensitive help).

The Internet button opens an Internet browser. Students will have unrestricted access to all

search engines and web sites unless the school administration has restricted this usage.

Use the Exit button to exit the course.

The right arrow ⇒ button moves you forward to the next screen.

The left arrow ⇐ button moves you backward to the previous screen.


2-4

FACET Help Screens and Resources

There are three ways to access FACET help screens and other resources.

System Help Students access System Help by clicking on the Help button at the bottom of the screen when the

button does not appear to be depressed. The menu selections access a variety of system help,

navigation, and information windows.

Screen Help On certain screens, the Help button appears to be depressed. On these screens, clicking on the

Help button will access Screen Help windows. This is information specific to the content of that

particular screen.

Resources Students click on the Resources button to access the following windows.

Calculator

FACET 32-Bit Microprocessor Help

FACET Analog Communications Setup Procedure

FACET Digital Communications Help

FACET Electronics and Troubleshooting Help

FACET Fiber Optic Communications Help

FACET Math Help

Internet Link

New Terms and Words

Print Current Page

Student Journal


2-5

Internet Access

There are two ways for students to access the Internet:

The Internet button opens an Internet browser. Students have unrestricted access to all search

engines and websites unless the school administration has restricted this usage.

The Resources button pops up a menu that includes access to the Lab-Volt

authored Internet website. If students wish to access this site when they are not in

the lesson, then they must go to http://learning.labvolt.com.

NOTE: The Lab-Volt Internet site does not have content-filtering

software to block access to objectionable or inappropriate

websites.

Instructor Annotation Tool

The annotation tool gives the instructor the ability to add comments or additional information

onscreen. Refer to the Tech-Lab and GradePoint 2020 Installation Guide for detailed

information.

Student Journal

The student journal is an online notebook that each student can access while they are logged into

TechLab. The journal allows students to share notes with other students in their workgroups.

When used in conjunction with GradePoint 2020, the instructor may post messages, review, edit,

or delete any journal note.


2-6

Assessing Progress

Assessment Tools

Student assessment is achieved in several ways:

♦ Exercise questions

♦ Unit tests

♦ Pretest and Posttest

♦ Troubleshooting questions

Exercise and Troubleshooting Questions

Throughout the unit material, exercise discussion, exercise procedure, and troubleshooting

sections there are several types of questions with instant feedback. These questions occur in the

following formats:

♦ Multiple choice

♦ True-false

♦ Real-number entry

In most cases, when your students encounter a question set, they must answer these questions

before continuing. However, there are cases where students may progress to the next screen

without answering the questions. Lab-Volt recommends that you encourage your students to

complete all questions. In this way, students reinforce the material that's presented, verify that

they understand this material, and are empowered to decide if a review of this material is

required.

Review Questions

At the end of each exercise, there are review questions. The student receives feedback with each

entry. Feedback guides the student toward the correct answer.

Unit Tests

A unit test appears at the end of each unit. The test consists of 10 multiple-choice questions with

the option of having feedback. The Tech-Lab System defaults to no feedback, but the instructor

can configure the test so that students receive feedback after taking the test. You can randomize

questions in the unit test. Use the Tech-Lab Global Configurator to make feedback available,

randomize questions, and select other configuration options if desired. Refer to the Tech Lab

Quick-Start Guide for detailed information.


2-7

Pretest and Posttest

Every course includes a pretest and a posttest. These are multiple choice tests. Refer to the Tech

Lab Quick-Start Guide for detailed information on how to record student competency gains.

Grading

Student grades are based on exercise questions, troubleshooting questions, a unit test, and a

posttest. The default weighting value of the unit test and the threshold for passing the unit test

can be adjusted by using the Global Configurator of the Tech-Lab System. Refer to the Tech Lab

Quick-Start Guide for detailed information.

Student Progress and Instructor Feedback

Unit progress is available through the Unit menu. The Progress window allows the instructor and

student to view the percentage of the unit completed, number of sessions, and time spent on that

unit. The Progress window shows whether the Unit Test was completed. If the test was

completed, it indicates whether the student passed based on the scoring criteria.


2-8

Real-Number Questions and Answers

Throughout FACET courses students may encounter real-number questions such as the one

shown below. Answers to real-number questions are graded correct if they fall within an

acceptable tolerance range.

The answer to the question posed in the illustration above does not involve a recall value from a

previous question. It appears in the Instructor Guide (IG) as shown in the box below.

The information in the IG tells you where the question is located and the range of acceptable

answers. In this case, the acceptable answers fall within the range of the nominal answer plus or

minus 5 percent tolerance: (15 ± 5%).

Location: Exercise Procedure page:

se1p1, Question ID: e1p1a

VS = Vdc

Recall Label for this Question: V1

Nominal Answer: 15.0

Min/Max Value: (14.25) to (15.75)

Value Calculation: 15.000

Correct Tolerance Percent = true

Correct Minus Tolerance = 5

Correct Plus Tolerance = 5

This is the name the computer uses internally

to identify the input value. In this case, 14.5

will be stored under the name V1.

NOTE: The recall value V1 is not the same as

the voltage V1. The recall label does not

appear onscreen.

In this case, the answer to this question is not

based on a value recalled from a previous

question. Therefore, the Value Calculation is

equal to the Nominal Answer.

The word "true" tells you that the tolerance is

calculated as a percent.

e1p1 stands for

Exercise 1 Procedure screen 1

The computer

saves this input

value so that it can

be recalled for use

in later questions.


2-9

A second example (shown below) illustrates an answer that the computer grades using a value

recalled from a previous question.

When a real-number question is based on a recall value from a previous question, the Min/Max

Value shown in the Instructor Guide is based upon a calculation using the lowest and highest

possible recall value. It represents the theoretical range of answers that could be accepted by the

computer. (It is not the nominal answer plus or minus the tolerance.)

To find the actual range of answers that the computer will accept onscreen, you must use the

actual recall value (14.5 in this example) in your calculations; see below.

NOTE: After four incorrect answers, students will be prompted to press <Ins> to insert the

correct answer if this feature has been enabled in the configuration settings. When the question is

based on a value recalled from a previous question, answers obtained using the Insert key may

not match the nominal answers in this guide.

Location: Exercise Procedure page:

se1p5, Question ID: e1p5c

IT = mA

Recall Label for this Question: I1

Nominal Answer: 9.091 *Min/Max Value: (6.477) to (11.93)

Value Calculation: #V1#/1650*1000




Since the value for #V1# is 14.5, the

computer will accept answers in the

following range as correct:

14.5/1650*1000 ± 25% or

8.79 ± 25% or

6.59 to 10.99

This calculated range is different from the

Min/Max Value shown in the IG, which

was based upon a calculation using the

lowest and highest possible recall value.

Any letter enclosed in "#" signs refers to a

recall value from a previous question.


2-10

Recall Values in Text

Sometimes numbers displayed on screen are values recalled from input on previous screens.

Because these numbers are recall values, they will change for each student.

The Instructor Guide lists the recall label in place of a number in this question.

The value of 10

was recalled

from a previous

screen.

Location:Exercise Procedure page: se1p11, Question ID: e1p11c

IR2 = VR2/R2

= #V4#/3.3 kΩ

= mA

Recall Label for this Question: I1


Min/Max Value: (2.489) to (3.164)

Value Calculation: #V4#/3.3




This is a

recall label

for a value

recorded in a

previous

question.

The correct

answer will

depend on the

value the student

recorded in the

previous question.


2-11

Safety

Safety is everyone’s responsibility. All must cooperate to create the safest possible working

environment. Students must be reminded of the potential for harm, given common sense safety

rules, and instructed to follow the electrical safety rules.

Any environment can be hazardous when it is unfamiliar. The FACET computer-based

laboratory may be a new environment to some students. Instruct students in the proper use of the

FACET equipment and explain what behavior is expected of them in this laboratory. It is up to

the instructor to provide the necessary introduction to the learning environment and the

equipment. This task will prevent injury to both student and equipment.

The voltage and current used in the FACET Computer-Based Laboratory are, in themselves,

harmless to the normal, healthy person. However, an electrical shock coming as a surprise will

be uncomfortable and may cause a reaction that could create injury. The students should be made

aware of the following electrical safety rules.

1. Turn off the power before working on a circuit.

2. Always confirm that the circuit is wired correctly before turning on the power. If required,

have your instructor check your circuit wiring.

3. Perform the experiments as you are instructed: do not deviate from the documentation.

4. Never touch “live” wires with your bare hands or with tools.

5. Always hold test leads by their insulated areas.

6. Be aware that some components can become very hot during operation. (However, this is not

a normal condition for your F.A.C.E.T. course equipment.) Always allow time for the

components to cool before proceeding to touch or remove them from the circuit.

7. Do not work without supervision. Be sure someone is nearby to shut off the power and

provide first aid in case of an accident.

8. Remove power cords by the plug, not by pulling on the cord. Check for cracked or broken

insulation on the cord.


2-12

SECTION 3 – COURSEWARE

SECTION 3 – COURSEWARE

THIS

32 Bit Microprocessor Unit 1 – Trainer Familiarization

3-1

UNIT 1 – TRAINER FAMILIARIZATION

UNIT OBJECTIVE

Locate and describe the various components on your circuit board, and demonstrate basic trainer

functions.

UNIT FUNDAMENTALS

Location: Unit Fundamentals page: sf3, Question ID: f3a

What other system components can communicate with the CPU in your computer via I/O

devices?

a. printer

b. mouse

c. disk drive

d. all of the above.


maximum # =

Recall Label for this Question: None


Min/Max Value: (65536) to (65536)






Which of these is an input device?

a. keypad

b. LCD display

c. LEDs

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-2

NEW TERMS AND WORDS

data bus - a group of bidirectional lines used for transferring data between a microprocessor and

memory or I/O devices.

address bus - a group of output signals from a microprocessor used for specifying a location in

which data is to be read or written.

registers - a temporary storage area inside a microprocessor that holds system status information,

results of calculations, and other values.

monitor - a program that performs system initialization functions and allows interaction between

the CPU and the user.

Programmable Peripheral Interface (PPI) - a support IC that manages data transfers between

the CPU and several external devices.

interrupt - an operation in which the CPU stops what it is doing and saves its place in the

program to perform another task. When the task is completed, the CPU returns to its former

place in the program.

Programmable Interrupt Controller - a support IC that manages interrupt signals from several

external devices.

bus cycle - a complete data transfer cycle, including a bus request from the microprocessor and a

response from an external device.

physical address - the address that the CPU places on the address bus.

logical address - an eight-digit representation of the physical address, written in the

form AAAA:BBBB (segment:offset).

segment - a 64 Kbyte section of memory.

offset - the distance (in bytes) of a given location from the segment base.

segment base - the first address in a segment.

function mode - a keypad operating mode that exists when you reset the CPU.

memory mode - a keypad operating mode that allows you to view or change memory bytes.

Mnemonic - an abbreviated form of an instruction that is written in a way that makes it easy to

recall the function.

assembly language - a programming language that uses words, statements, and phrases to

produce CPU instructions.

loop - a series of instructions that repeats itself continuously or for a specific number of times.

microprocessor - a computer element that contains the control unit, central processing circuitry,

and arithmetic and logic functions; also called the Central Processing Unit (CPU).

logic probe - a device for digital troubleshooting and signal tracing that has LEDs to indicate

logic levels and pulse activity.

programs - a series of instructions stored in memory to be executed or carried

out by a microprocessor.

byte - a group of eight bits transferred or operated on as a unit.

register mode - a keypad operating mode that allows you to view or change the contents of the

CPU's internal registers.


3-3

EQUIPMENT REQUIRED

F.A.C.E.T. base unit

Multimeter

Oscilloscope, dual trace

32-BIT MICROPROCESSOR circuit board


3-4

Exercise 1 – Introduction to the Trainer

EXERCISE OBJECTIVE

Locate and describe the various components and circuit blocks on the 32-BIT

MICROPROCESSOR circuit board.

EXERCISE DISCUSSION

Location: Exercise Discussion page: se1d4, Question ID: e1d4a

There are three headers in the CPU block: JP1, JP2, and JP3. Which header has the fewest pins?

a. JP1

b. JP2

c. JP3

d. All have the same number of pins.


Although JP1 and JP2 both have 32 signal connections, there are 34 pins on each header. By

looking at the CPU circuit block, you can determine that two pins on each header are

a. ground connections.

b. VCC connections.

c. not used.


Memory/Input-Output# (M/IO#) distinguishes between memory and I/O operations. What logic

level indicates a memory operation?

a. 0

b. 1


Which memory block does not have headers?

a. MONITOR ROM

b. USER ROM

c. RAM


3-5


What other circuit block has a clock oscillator?

a. CPU

b. MONITOR ROM

c. BUS CONTROL


number of codes =



Min/Max Value: (16) to (16)






Which of these ports can be used as an output port?

a. Port B

b. Port C

c. Both of the above.


You can use a shunt on the 3-pin header to select an output voltage range of 0 - 10 Vdc or 0 -

2.56 Vdc. Which range is selected in the figure?

a. 0 - 10 Vdc

b. 0 - 2.56 Vdc


Both the ADC and DAC blocks have jacks for an external analog connection (ADC IN

and DAC OUT). In which other circuit block are these signals available?

a. SERIAL PORT

b. PARALLEL PORT

c. CPU


3-6


You can use a shunt to connect one of the top pins to the interrupt input directly below it to allow

the other circuit block(s) to interrupt the CPU. Which signal can be shunted to IR4?

a. INTRA

b. INTRB

c. RXC

d. DR#


Which circuit block loses power when the PWR switch is in its down position?

a. only the CPU block

b. only the POWER SUPPLY block

c. all circuit blocks


Which hexadecimal key can also be used for the READ function?

a. 1

b. 7

c. C

d. F


What binary number is shown on address LEDs A0-A7?

a. 1010 0110

b. 1110 0111

c. 0001 1000

Location: Exercise Discussion page: se1d28, Question ID: e1d28c

The LEDs are arranged in groups of four because

a. the CPU transfers four bits at a time.

b. four binary bits equal one hexadecimal digit.


3-7


How many digits of hexadecimal information can you view in each LED block?

a. 4

b. 8

c. 16


What is the complete hex value shown on the data LEDs?

a. E098 D26A

b. D26A E098

c. A62D 890E

EXERCISE PROCEDURE

Location: Exercise Procedure page: se1p4, Question ID: e1p4a

What message does the CPU display on the LCD to let you know it is ready for operation?

a. "Read Address?"

b. "Lab-Volt 32 bit µPROC. Trainer"


1. Aside from the PWR LED, what indication(s) tell you that power is applied to your circuit

board?

a. address and data LEDs on

b. logic probe LED on


Location: Exercise Procedure page: se1p9, Question ID: e1p9c

What message appears in the LCD display?

a. "Lab-Volt 32 bit µPROC. Trainer"

b. "Read Address?"

c. Neither of the above.

Location: Exercise Procedure page: se1p9, Question ID: e1p9e

Why hasn't the startup message "Lab-Volt 32 bit µPROC. Trainer" appeared?

a. The CPU is in single cycle mode.

b. The address and data selector switches are set to LOW.


3-8


In which circuit block is JP3 located?

a. PARALLEL PORT

b. CPU

c. IR CONTROLLER


Does the waveform on the scope match the top waveform (BS16#) shown in the figure?

a. yes

b. no


Which CH 2 connection results in the bottom waveform shown in the figure?

a. BE0#

b. BE1#

c. BE2#

d. BE3#


If a pulsing waveform is not symmetrical, the HIGH and LOW LED brightness levels are

different. For which type of waveform is the HIGH LED brighter than the LOW LED?

a. repeating high pulse

b. repeating low pulse


According to the logic probe, what type of signal is UROMS#?

a. high level

b. low level

c. square wave


Which signal is a repeating low pulse?

a. L0

b. L1

c. L2


3-9


What can you conclude from the waveform and the logic probe indications?

a. The LEDs indicate a different waveform type than the one shown on the scope.

b. The LEDs indicate the same waveform type as the one shown on the scope.


The logic probe indicates that ADS# is

a. at a high level.

b. at a low level.

c. pulsing.


23. Turn on the SINGLE CYCLE switch. What indications show that the CPU is now in the

single cycle mode?

a. ADS# has stopped pulsing.

b. The address and data LEDs have all assumed a steady on or off level.



24. Observe the logic probe LEDs as you press STEP several times. What happens as you press

STEP?

a. The ADS# level alternates between high and low with each step.

b. A short pulse appears on the PULSE LED with each step.



3-10

REVIEW QUESTIONS

Location: Review Questions page: se1r1, Question ID: e1r1

1. What step(s) must you perform to start up the 32-BIT MICROPROCESSOR circuit board?

a. Set the control switches to their correct initial conditions.

b. Make sure the CPU is in the run mode.

c. Set some of shunts to their correct initial conditions.

d. All of the above.


2. What type of waveform is indicated by the logic probe LEDs?

a. high level

b. low level

c. repeating high pulse

d. repeating low pulse


3. In which circuit block can you monitor the signal INTRA?

a. IR CONTROLLER

b. CPU

c. PARALLEL PORT

d. SERIAL PORT


4. When the CPU starts up in the run mode, you cannot read the address and data LEDs because

a. the wrong information is displayed.

b. the information is constantly changing.

c. the STEP switch has not been pressed.

d. the LEDs are turned off.


5. Which circuit block synchronizes control signals between the CPU and its support circuitry?

a. DAC

b. ADC

c. BUS CONTROL

d. PARALLEL PORT


3-11

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-12

Exercise 2 – Operating the Trainer

EXERCISE OBJECTIVE

Perform the basic keypad functions of the 32-BIT MICROPROCESSOR circuit board. Verify

results by reading the data and prompts on the LCD display.

EXERCISE DISCUSSION


How many hexadecimal digits correspond to 20 binary bits?

a. 4

b. 5

c. 8


What other logical address also equals the physical address 04050?

a. 0402:0030

b. 0403:0020

c. 0200:2050



Which hexadecimal keys correspond to these functions?

a. 1,2,3,4

b. C,D,E,F

c. 3,A,9,C


In which form should you enter the address?

a. physical

b. logical


3-13


What is the physical address of the byte AA?

a. FFC04

b. FFC05

c. FFC06

d. FFC07


How many registers can you select?

a. 8

b. 16


How many bits do the CS and IP registers contain?

a. 8

b. 16

c. 32


Which of these registers contains 32 bits of information?

a. SS

b. ESP


What other function is associated with this key?

a. auto

b. read

c. step


3-14

EXERCISE PROCEDURE


2. Press <READ>. What message appears in the LCD display?

a. Lab-Volt 32 bit µProc. Trainer

b. Read Address?

c. Goto Address?


The display shows the address as 04000 instead of 00004000 because you entered a

a. logical address and the display shows a physical address.

b. physical address and the display shows a logical address.


The 11 appears in the first byte position. The second byte did not change because

a. you can enter only one byte at a time by using the WRT key.

b. RESET must be pressed before another byte is entered.


What happens when you enter the last digit?

a. All the bytes you entered are shown in the display.

b. The display shows eight different bytes beginning at address 04008.


5. Which key is more efficient to use if you need to enter a long program?

a. AUTO

b. WRT


What instruction byte is located at address FFC14?

a. A3

b. 04

c. 50


3-15


What instruction code has the mnemonic, mov ebx ds:[5004H]

a. 66 8B 1E 00 50

b. 66 8B 1E 04 50

c. EB E9


What key can you press to view the next eight bytes?

a. FFWD

b. FWD

c. FBACK


You have stepped to address FFC0B in the single instruction mode. What address will be

displayed if you press the STEP key once?

a. FFC0C

b. FFC0F

c. FFC0E


The CS-IP register pair forms a logical address consisting of a segment base (CS) and an offset

(IP). What is the physical address for the register contents shown?

a. FFF00

b. FFFF0

c. FFFFF


What information is contained in the CS-IP register pair?

a. the logical address FFC0:000B

b. the address of the next instruction to be fetched



21. Press <EXIT> to cancel the register mode. What address now appears in the display?

a. FFC0B

b. FFC00


3-16


You can verify this by checking the register contents. Which register key should you use to view

the contents of EAX?

a. (BP-FL)

b. (CS-IP)

c. (A-B)


Which figure matches the contents of the LCD display?

a. A

b. B

c. C


Which mode can you use to verify that the CPU has copied the EAX register contents to the

memory location?

a. register mode

b. memory mode


31. Press <READ> and enter the memory address 0000:5000.

a. The contents of EAX have been copied to memory address 05000H.

b. The contents of EAX have not been copied to memory address 05000H.


3-17

REVIEW QUESTIONS


1. Which key(s) can you use to enter data into memory?

a. WRT

b. AUTO


d. None of the above.


2. Which register pair always contains the address of the next instruction that the CPU will

fetch?

a. A-B

b. C-D

c. SI-DI

d. CS-IP


3. Press <REG> and select <(A-B)>. What number does EAX contain?

a. 33333333H

b. CCCCCCCCH

c. 00000000H

d. FFFFFFFFH


4. Each time you press the FFWD key, the first byte in the display (after the address) represents

a. the first byte of the next instruction.

b. the contents of the CS-IP registers.

c. every eighth byte in the program listing.



5. Which key would not be used to change the contents of a CPU register?

a. REG

b. FWD

c. WRT

d. STEP


3-18

CMS AVAILABLE

CM 2

FAULTS AVAILABLE

FAULT 1


3-19

UNIT TEST

Location: Unit Test Question page: sut1, Question ID: ut1

Which of the following is not used to view memory addresses?

a. HIGH/LOW data LED switch

b. HIGH/LOW address LED switch

c. address LEDs

d. LCD display


Which circuit block accepts an analog input?

a. SERIAL PORT

b. PARALLEL PORT

c. ADC

d. DAC


The IR CONTROLLER circuit block manages the CPU's

a. internal registers.

b. internal ROM.

c. interrupt signals.

d. input rate.


Which circuit block(s) can contain memory devices?

a. RAM

b. USER ROM

c. MONITOR ROM



What indication would appear on the logic probe LEDs each time you press the STEP switch?

a. constant high level

b. constant low level

c. constant pulsing

d. single pulse


3-20


Which key can you use to execute a program stored in memory?

a. READ

b. GO

c. STEP

d. REG


When the CPU in the trainer operates in the real mode,

a. the addressable memory space is 1 Mbyte.

b. only 20 of the 32 address lines are used.

c. any memory location can be represented by its five-digit physical address.



Which of the following logical addresses has a physical address of 12345H?

a. 1234:0005

b. 1234:0050

c. 1234:0500

d. 1234:5000


Which of the following physical addresses has a logical address of 1122:3344?

a. 14564H

b. 11223H

c. 11224H

d. 44660H


Which key is used to leave the register mode?

a. GO

b. READ

c. EXIT

d. STEP

32 Bit Microprocessor Unit 2 – Bus Operations

3-21

UNIT 2 – BUS OPERATIONS

UNIT OBJECTIVE

Understand the basic data transfer operations of the 80386 microprocessor.

UNIT FUNDAMENTALS


Which bus is bidirectional?

a. data bus

b. address bus


First, the CPU activates the address bus. What information appears on the address lines?

a. data to be read

b. data to be written

c. the location for which data is to be written or read


The CPU then looks for a response from the external device. According to the flow diagram,

what does the CPU do if a response is not received?

a. proceeds to the next step

b. waits for a response

Location: Unit Fundamentals page: sf3, Question ID: f3c

What is the direction of data flow for a read cycle?

a. from the CPU to an external device.

b. from an external device to the CPU.


Instructions from memory are continuously transferred to the CPU. Each transfer requires a

a. read cycle.

b. write cycle.


3-22

Location: Unit Fundamentals page: sf5, Question ID: f3c

Instructions for the 80386 microprocessor may be up to 32 bits wide. How many hex digits are

needed to represent 32 binary bits?

a. 4.

b. 8.

c. 16.

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-23

NEW TERMS AND WORDS

microprocessor - a computer element that contains the control unit, central processing circuitry,

and arithmetic and logic functions; also called Central Processing Unit (CPU).

bus cycle - a complete data transfer cycle including a bus request from the micropocessor and a

response from an external device.

read cycle - a bus cycle during which a memory or I/O device transfers data to the

microprocessor.

data bus - a group of bidirectional lines used for transferring data between a microprocessor and

memory or I/O devices.

address bus - a group of output signals from a microprocessor used for specifying a device and

location where data is to be read or written.

write cycle - a bus cycle during which the microprocessor transfers data to a memory or

Input/Output (I/0) device.

programs - series of instructions stored in memory to be executed or carried out by the

microprocessor.

idle state - a period during which a microprocessor is not requesting a bus cycle.

byte - a group of eight bits transferred or operated on as a unit.

word - a group of bits transferred or operated on as a unit; often specifically refers to a group of

16 bits.

doubleword - a group of 32 bits transferred or operated on as a unit.

doubleword boundaries - the starting addresses of 32-bit memory locations. The starting address

must be an integral multiple of four.

aligned transfers - transfers involving data that does not overlap a doubleword boundry.

misaligned transfer - a 16-, 24-, or 32-bit transfer that overlaps a doubleword boundry.

wait state - a period during which a microprocessor is waiting for a response from a slower

device.

EQUIPMENT REQUIRED





3-24

Exercise 1 – Bus States

EXERCISE OBJECTIVE

Understand the bus states that allow the 80386 microprocessor to communicate with memory

and Input/Output (I/O) devices. Verify results by using an oscilloscope and by loading and

executing a simple program in the 32-BIT MICROPROCESSOR circuit board.

EXERCISE DISCUSSION


How many CLK2 cycles occur within one cycle of CLK?

a. 1

b. 2

c. 1/2


Which of these lines are inputs to the CPU?

a. status

b. control


When the microprocessor issues valid address information, it activates ADS#. The ADS# line is

active for the

a. entire bus cycle.

b. T1 state only.

c. T2 state only.


RDY# is shown as a don't care condition during T1 because

a. ADS# is inactive.

b. the CPU has not yet sampled RDY#.

c. READY# has not yet become active.


3-25


Compare the timing diagram to the flow diagram. Which path is taken out of the decision box?

a. NO path

b. YES path


The 80386 microprocessor's wait states allow it to interface with external devices that are

a. faster than the CPU.

b. slower than the CPU.

c. either faster or slower than the CPU.


Which path out of the decision box corresponds to a wait state?

a. YES path

b. NO path


What causes a wait state to terminate?

a. three consecutive T2 states

b. a RDY# input from memory or I/O

c. a RDY# output from the microprocessor


If RDY# is inactive during the T2 state, the CPU executes another T2. This condition is a(n)

a. idle state.

b. wait state.


What state occurs after T2 if RDY# is active and a bus request is not pending?

a. T1

b. T2

c. Ti


Which sequence is valid according to the state diagram?

a. T1-T2-T2-Ti

b. T1-T2-T1-Ti

c. T1-T1-T2-Ti



3-26

EXERCISE PROCEDURE


2. Does the message shown appear in the circuit board's Liquid Crystal Display (LCD)?

a. yes

b. no


8. Does the prompt shown appear in the LCD?

a. yes

b. no


11. Does the data shown appear in the LCD?

a. yes

b. no


15. Each transition of the ADS# waveform coincides with a clock transition because

a. CLK is synchronized to ADS#.

b. ADS# is synchronized to CLK.


The falling edge of ADS# was chosen to trigger the oscilloscope because it

a. occurs at the beginning of a bus cycle.

b. is synchronized to CLK.

c. represents the external device's response.


17. Which part of the waveforms indicates the beginning of a bus cycle?

a. a high pulse on ADS#

b. a low pulse on RDY#

c. a low pulse on ADS#


3-27


18. At which clock cycle does a bus cycle begin?

a. CLK cycle 1

b. CLK cycle 4

c. CLK cycle 7



19. The low ADS# pulses are identified here as T1 states. When does a bus cycle terminate?

a. immediately when RDY# goes low

b. when RDY# is sampled low at the end of T2


The CPU samples the RDY# line at the end of every T2. What is the state of RDY# during CLK

cycle 2?

a. active

b. inactive


20. Where is the wait state in bus cycle 2?

a. CLK cycle 4

b. CLK cycle 5

c. CLK cycle 6


21. Which CLK cycles in bus cycle 3 are wait states?

a. CLK cycle 9

b. CLK cycle 10



3-28

REVIEW QUESTIONS


1. What can you use to identify all the types of CPU bus states (T1, T2, Ti, or wait)?

a. address and data bus information

b. ADS# and RDY#

c. ADS# only

d. RDY# only


2. You can cause additional wait states to be added to each bus cycle by pressing <CM> to

toggle CM 12 on and off. How many total wait states are in the first bus cycle when CM 12 is

on?

a. 1

b. 2

c. 3

d. 4


3. Which area highlighted on the state diagram represents a CPU wait state?

a. A

b. B

c. C



4. Which step in the flow diagram corresponds to the activation of ADS#?

a. Send Address

b. Send Read Signal

c. Signal Address Valid

d. External Device Response


5. Every bus cycle begins when ADS# goes low and ends

a. when ADS# goes high.

b. when RDY# is low at the end of a T2 state.

c. after the next T2 state.

d. after the next wait state.


3-29

CMS AVAILABLE

CM 12 TOGGLE

FAULTS AVAILABLE

None


3-30

Exercise 2 – 32-Bit Bus Transfers

EXERCISE OBJECTIVE

Demonstrate data transfers on the 32-BIT MICROPROCESSOR circuit board. Verify results

with an oscilloscope.

EXERCISE DISCUSSION


How many bytes make up a doubleword?

a. 2

b. 4

c. 8


What logic levels would be present at the byte enable outputs (BE3# through BE0#) if the CPU

were to only output bytes 0 and 1?

a. 0011

b. 1100


Which data bits are transferred if only BE1# and BE2# are low?

a. D0 through D15

b. D8 through D23

c. D16 through D31


What is the byte address of byte 3 at doubleword address 0008H?

a. 0008H

b. 0011H

c. 000BH


3-31


Which combinations cannot be used for a 16-bit transfer?

a. 3-1

b. 3-0

c. 2-0



The CPU needs two bus cycles to complete a misaligned transfer. Why are two bus cycles

required?

a. Twice as much data is transferred.

b. One bus cycle is needed for each doubleword address.

c. The CPU must compensate for slower memory devices.


The D/C# (Data Control#) output is high for data transfers and low for instruction (control)

transfers. For what type(s) of transfers can D/C# be low?

a. read cycles

b. write cycles

c. read or write cycles


What size group of data bits cannot be transferred in one bus cycle in the 16-bit mode?

a. byte

b. word

c. doubleword


3-32

EXERCISE PROCEDURE


2. Does the prompt shown appear in the LCD?

a. yes

b. no


6. To verify your data, press RESET, and then press <READ>. Enter address "0000:5000", and

verify that the data is 66 C7 06 00 70 FF FF FF. Press <FFWD> to view the second field, and

verify that the first line reads FF EB F5. Is all the data correct?

a. yes

b. no


If the microprocessor were to transfer data from memory area 5000H to memory area 7000H,

which address bit would change?

a. A12

b. A13

c. A14

d. A15


What do the falling edges of ADS# represent?

a. the end of a bus cycle

b. the beginning of a bus cycle


What can you conclude from the waveforms?

a. Bus cycles occur only when A13 is low.

b. No data is transferred while A13 is high.

c. One bus cycle occurs while A13 is high.


3-33


Since the transferred data does not overlap doubleword boundaries, this is an aligned transfer.

This transfer requires

a. four bus cycles because there are four bytes.

b. two bus cycles because there are two words.

c. one bus cycle because only one doubleword location is addressed.


12. Move the channel 2 probe to each of the other outputs, BE1#, BE2#, and BE3#. Which of

these is high while A13 is high?

a. BE1#

b. BE2#

c. BE3#

d. None


All four byte enables are low during the high portion of A13 because

a. there is an aligned transfer.

b. there is a misaligned transfer.

c. the transfer involves all 32 data bits in one bus cycle.


Do the scope traces appear as shown?

a. yes

b. no


What kind of transfer does this indicate?

a. aligned

b. misaligned


Do the byte enables (BE0# and BE1#) appear as shown?

a. yes

b. no


3-34


Which byte enable is active for the first bus cycle?

a. BE0#

b. BE1#


A13 and ADS# are shown again for reference. Do the BE2# and BE3# signals appear as shown?

a. yes

b. no


You can see that the same signal appears at BE2# and BE3#. During which bus cycle are these

byte enables active?

a. first (A)

b. second (B)


Based on your results, are the bytes in the higher or lower doubleword address transferred first in

a misaligned transfer?

a. higher

b. lower


Do the waveforms shown here appear on your oscilloscope?

a. yes

b. no


The W/R# signal pulses high the same time A13 does because during the A13 pulse, a

a. read operation occurs.

b. write operation occurs.


3-35


You determined that while A13 is high, the data FF FF FF FF is being transferred. D/C# is high

during this time because

a. FF FF FF FF is data and not an instruction.

b. the transfer is misaligned.


The M/IO# output is high for the entire program loop because all transfers are between the CPU

and

a. memory.

b. I/O.


Output data is transferred at the highlighted time because of the

a. high level of W/R#.

b. low level of M/IO#.


REVIEW QUESTIONS


1. Which signal does not provide information about the type of bus cycle?

a. ADS#

b. M/IO#

c. W/R#

d. D/C#


2. Which scope pattern shown here represents the byte enable signals?

a. A

b. B

c. C



3-36


3. The CPU is to load three bytes in an aligned transfer. Which starting address can it use?

a. 7002H

b. 7003H

c. 7004H



4. A three-byte misaligned transfer begins at byte address 7002H. Which byte enable is not

active in either bus cycle?

a. BE0#

b. BE1#

c. BE2#

d. BE3#


5. Which signal must be low while the CPU sends data to an I/O device?

a. D/C#

b. M/IO#

c. W/R#


CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-37

Exercise 3 – Read and Write Cycles

EXERCISE OBJECTIVE

Understand the functions of CPU read cycles and write cycles. Verify results with an

oscilloscope.

EXERCISE DISCUSSION


Based on the level of the W/R# line in the timing diagram, what type of bus cycle is shown?

a. read cycle

b. write cycle

c. cannot be determined


This is a timing diagram for a typical write cycle. Which signal allows you to tell a write cycle

from a read cycle?

a. ADS#

b. RDY#

c. W/R#


According to the timing diagram, when is RDY# sampled?

a. before data becomes valid

b. after data is no longer valid

c. while data is valid


According to the table, what determines if a memory read cycle is a memory code read or a

memory data read?

a. the direction of data flow

b. the D/C# signal

c. whether an input or an output device is involved


3-38

EXERCISE PROCEDURE


Does the LCD appear as shown?

a. yes

b. no


Do your waveforms appear as shown here?

a. yes

b. no


The CPU is writing data for

a. one bus cycle.

b. five bus cycles.


The ADS# and W/R# signals are shown in a different color for timing reference only. Do the

M/IO# and D/C# waveforms appear on your scope as shown here?

a. yes

b. no


Which section consists of I/O data read cycles?

a. B

b. C


What cycle type is executed in section B?

a. memory code read

b. memory data read

c. memory data write


3-39


Are your waveforms similar to those shown here?

a. yes

b. no


The transitions on ADS# represent all the bus cycles in a program loop. Are most of the bus

cycles read or write cycles?

a. read

b. write


The ADS# and W/R# signals are shown in a different color for reference. Do the M/IO# and

D/C# waveforms on your scope appear as shown here?

a. yes

b. no


The steady high level on M/IO# means that all the bus cycles are

a. read cycles.

b. I/O cycles.

c. memory cycles.


According to the figure and the table shown in the help window (click on Help), section A is a

memory

a. code read.

b. data read.

c. data write.


3-40


In which remaining section does the CPU fetch instructions?

a. B

b. C


What type of cycle is executed in section C?

a. memory code read

b. memory data read


REVIEW QUESTIONS


1. What signal can you use to distinguish a read cycle from a write cycle?

a. M/IO#

b. D/C#

c. W/R#

d. Any of these


2. You can use this table to determine the nature of a bus cycle by reading the status signal levels

a. within that cycle.

b. only during T1 states.

c. only during T2 states.


Location: Review Questions page: se3r3, Question ID: e3r3a

Do the scope waveforms appear as shown here?

a. yes

b. no


3-41


3. What type of cycle occurs in the highlighted area?

a. I/O data read

b. memory data write

c. memory data read

d. cannot be determined

Location: Review Questions page: se3r4, Question ID: e3r4a

Do the W/R# and M/IO# waveforms appear as shown?

a. yes

b. no


4. What type of cycle occurs in the highlighted area?

a. I/O data read

b. memory code read

c. memory data read

d. memory data write


5. An I/O code read cycle does not appear in the table because

a. D/C# cannot be low in any write cycle.

b. instructions are fetched from memory, not from I/O.

c. instructions are fetched from I/O, not from memory.


CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-42

Exercise – CPU Initialization

EXERCISE OBJECTIVE

Describe the reset state and initialization procedure of the 80386 microprocessor.

EXERCISE DISCUSSION


When power is applied, the RES signal starts

a. high and switches low.

b. low and switches high.


What condition is necessary to reset the microprocessor?

a. either a power-up reset or a pushbutton reset

b. both a power-up reset and a pushbutton reset


During reset, what type of cycle do the status outputs D/C#, W/R#, and M/IO# indicate?

a. memory data read

b. memory data write

c. I/O data read

d. I/O data write


If the display message does not appear, the problem is caused by

a. improper status output levels at reset

b. a failure to execute the jump instruction at FFFF FFFOH

c. Either of the above.


3-43


A low pulse on the RDY# output results from a low pulse on which input?

a. EXTRDY#

b. PLDRDY#



When S7 is not pressed, the PLDRDY# output is inactive. The CPU does not receive a

RDY# signal and so it remains in a(n)

a. wait state.

b. idle state.


What number is shown on the data bus LEDs?

a. 1E46 925DH

b. D529 64E1H

c. 64E1 02EAH

EXERCISE PROCEDURE


Do the logic levels of these two signals agree with those in the table?

a. yes

b. no


Do these logic levels agree with the table?

a. yes

b. no


3-44


4. Press and hold the RESET switch as you read the address displayed on the LEDs. Does the

pattern on your circuit board match the one shown here?

a. yes

b. no


What is address FFFF FFFCH?

a. the address for the first instruction fetch

b. the address corresponding to the bit pattern in the table



When you release the RESET switch, the PULSE LED blinks and the logic level

a. remains high.

b. switches low.


What logic probe indication occurs when you release the RESET switch?

a. steady high

b. steady low

c. pulse


The M/IO# level is

a. high when you press RESET and low when you release RESET.

b. low when you press RESET and high when you release RESET.

c. always high.


The D/C# level is

a. high when you press RESET and low when you release RESET.

b. low when you press RESET and high when you release RESET.

c. always low.


3-45


What type of bus cycle do these levels indicate?

a. memory code read

b. memory data read

c. I/O data read


Do the LED patterns shown here agree with those on the circuit board?

a. yes

b. no


How can you view the remaining 16 address bits?

a. Press the STEP switch.

b. Press RESET.

c. Set the address selector switch to HIGH.


What hexadecimal address is displayed on the LEDs?

a. 0FFF FFFFH

b. FFFF FFF0H

c. 0000 000FH

d. 000F 0000H


What hexadecimal data is displayed?

a. AE02H

b. FD15H

c. 02EAH

d. 51DFH


3-46

REVIEW QUESTIONS


1. What is the first thing the 80386 microprocessor does after a reset?

a. writes to the display

b. writes an instruction to address FFFF FFF0H

c. fetches an instruction from address FFFF FFF0H

d. fetches an instruction from address 0000 0000H


2. In the PROCEDURE, you confirmed that the logic levels in the table exist during the CPU's

reset state. What type of bus cycle is defined by these levels?

a. memory code read

b. memory data read

c. I/O data read

d. I/O code read


3. What function is not performed by the circuit shown?

a. synchronizing a reset signal with the CPU CLK

b. power-up reset

c. pushbutton reset

d. external reset


4. During a power-up reset, the RES signal goes low

a. when C40 charges up to the inverter's input threshold voltage.

b. when C40 discharges completely.

c. immediately when power is applied.



5. When you close S5 and press S7, this circuit causes the CPU to execute single cycles by

a. disabling the PLDRDY# signal.

b. resetting the CPU.

c. generating one PLDRDY# pulse each time S7 is pressed.

d. generating one ADS# pulse each time S7 is pressed.


3-47

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-48

UNIT TEST


Where does the information that the CPU writes to or reads from an external device appear?

a. on the address bus

b. on the data bus

c. at the status outputs

d. at the control inputs


Which group of signals does the CPU use to select the location for data to be transferred?

a. address bus

b. data bus

c. status outputs

d. control inputs


Any cycle that begins with a low pulse on ADS# and ends with a low pulse on RDY# is a

a. clock cycle.

b. read cycle only.

c. write cycle only.

d. bus cycle.


What size group of bits can be involved in an aligned transfer?

a. byte

b. word

c. doubleword



An aligned transfer is faster than a misaligned transfer because an aligned transfer requires

a. two bus cycles.

b. one bus cycle.

c. more data.

d. less data.


3-49


Transferring a doubleword into the highlighted locations is an example of a

a. four-byte aligned transfer.

b. four-byte misaligned transfer.

c. two-byte aligned transfer.

d. two-byte misaligned transfer.


Which byte address cannot be the starting address for a three-byte aligned transfer?

a. 0005H

b. 0008H

c. 0009H

d. 000AH


Which signal(s) is (are) not required to determine the type of bus cycle?

a. BE0#–BE3#

b. M/IO#

c. W/R#

d. D/C#


You can determine from these waveforms that section A is a(n)

a. memory data read cycle.

b. memory data write cycle.

c. I/O data read cycle.

d. I/O data write cycle.


For any given bus cycle, you can use this table to determine whether

a. a transfer is aligned or misaligned.

b. one, two, three, or four bytes are being transferred.

c. the CPU is reading or writing data.



3-50

32 Bit Microprocessor Unit 3 – Memory Interfacing

3-51

UNIT 3 – MEMORY INTERFACING

UNIT OBJECTIVE

Demonstrate memory transfers and describe the functions of memory control signals.

UNIT FUNDAMENTALS


In which type of memory is it better to store the monitor program for the 32-BIT

MICROPROCESSOR circuit board?

a. RAM

b. ROM


The CPU enables a single chip or group of chips at a time so that

a. only one location in one chip or group is selected.

b. one location in every chip or group is selected.


When A13 is high,

a. RAM 1 is selected.

b. RAM 2 is selected.

c. both RAMs are selected.


How many RAMs could be selected if 3 address lines (A13, A14, and A15) were decoded?

a. 6.

b. 8.

c. 16.


What other signal is common to both the bus controller and the address decoder?

a. W/R#.

b. M/IO#.

c. D/C#.



3-52


Which area(s) of memory on your circuit board contain 16-bit devices?

a. RAM.

b. ROM

c. both RAM and ROM.

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-53

NEW TERMS AND WORDS

volatile - subject to the loss of stored data when power is removed.

bus controller - a circuit that manages the control signals needed to transfer information between

the CPU and memory or I/O.

bug - a hardware or software flaw that causes incorrect system operation.

debug - to locate and correct a flaw in hardware or software.

system address lines - the address lines that are common to the CPU and peripheral devices.

memory map - a listing or graphical representation describing how blocks of memory in a

system are assigned.

image - a memory location or block that is repeated one or more times due to partial address

decoding.

op code - the hexadecimal representation of a microprocessor instruction.

operand - a number that is affected, manipulated, or operated upon.

EQUIPMENT REQUIRED


Oscilloscope dual trace



3-54

Exercise 1 – Memory Control Signals

EXERCISE OBJECTIVE

Describe the data, address, and control signals of memory devices in a microprocessor circuit.

EXERCISE DISCUSSION


How many memory locations are specified by the number of address lines on this RAM chip?

(2n = XXXX locations)

a. 2048 (2K)

b. 4096 (4K)

c. 8192 (8K)


Tristate outputs are used on the data lines to

a. allow several devices to share the data bus.

b. adjust the outputs to the proper logic levels.

c. prevent writing the wrong data into the RAM.


The ROM shown here has the same configuration as the RAM (8K x 8) because it has the same

number of

a. address lines.

b. data lines.



A WE control input is not needed because you can only

a. read data from a ROM.

b. write data to a ROM.


3-55


The chip selects must be active for RAM

a. read cycles.

b. write cycles.



If MWTC# is active, which RAMs receive data if BE0# and BE1# are low and BE2# and BE3#

are high?

a. U34 and U35

b. U31 and U33


What is the overall configuration of the ROMs when they are connected as shown?

a. 8K x 32

b. 8K x 16


When the ROM outputs are enabled, the CPU can

a. write data to the ROMs.

b. read data from the ROMs.



The least significant address byte should be F0H, but is shows up as F4H. What is the possible

cause of the error?

a. A0, A1, and A3 shorted to ground

b. A2 shorted to ground

c. A2 shorted to Vcc


The most significant data byte should be 02H, but it shows up as 0AH. What is the possible

cause of the error?

a. D3 is shorted to VCC

b. D11 is shorted to VCC

c. D11 is shorted to ground.


3-56


The data at address at 5000H

a. is always AAAA AAAAH.

b. is always 5555 5555H.

c. alternates between AAAA AAAAH and 5555 5555H for each pass through the loop.


You can verify the levels in the table when the

a. RESET switch is pressed and released.

b. RESET switch is pressed and held.

c. CPU is in SINGLE CYCLE mode.

EXERCISE PROCEDURE


Do the first 8 bytes of ROM data appear in the LCD display as shown here?

a. yes

b. no


2. Press <WRT>, and enter the data "AA". The first byte in the display does not change to AA

because ROM

a. is volatile.

b. data can be written but not read.

c. data can be read but not written.


The data in the display remains the same because ROM is

a. volatile.

b. non-volatile.


What can you conclude from the LCD display?

a. The data you wrote is stored in RAM.

b. The data you wrote is stored in ROM.

c. You cannot write data into RAM.


3-57


What can you conclude from the resulting display data?

a. RAM is non-volatile because the data did not change when you interrupted power.

b. RAM is volatile because the data was lost when you interrupted power.

c. You cannot write data into a RAM.


Do the address and data LEDs appear as shown?

a. yes

b. no


The upper two bytes (FFFFH) in the program address appear on the

a. HIGH address LEDs.

b. LOW address LEDs.


Do the circuit board LEDs match the figure now shown?

a. yes

b. no


Do the circuit board LEDs match the figure now shown?

a. yes

b. no


Which instruction will the CPU execute on the next step?

a. jump to 000F C012

b. clear interrupt flag


18. Press STEP several times as you observe the logic probe LEDs. The LEDs indicate that

ADS#.

A. is always high.

B. is always low.

C. pulses once for each step.


3-58


The LEDs indicate that READY#

a. is always high.

b. is always low.

c. pulses once for each step.


What type of cycle is indicated by the levels of these signals?

a. memory data read

b. memory code read



The level is always

a. high because the transfers are in 32-bit memory.

b. low because the transfers are in 16-bit memory.


MROMSEL# and MRDC# are both

a. always high.

b. always low.

c. pulsing for each step.



24. Check the levels of RDY#, ADS#, and BS16#. Which of these signals is pulsing?

a. ADS#

b. RDY#

c. BS16#



25. Check the levels of W/R#, M/I0#, and D/C#. Which of these signals is pulsing?

a. W/R#

b. M/IO#

c. D/C#



3-59


Both of these signals are

a. high.

b. low.

c. pulsing.


CM 15 has been activated to insert a circuit fault into the ROM interface. What circuit board

element indicates that a fault exists?

a. the LCD display

b. the address LEDs

c. the ADS# line


The figure shows the correct LED information that normally appears for the first instruction

fetch. Do the circuit board LEDs match those in the figure?

a. yes

b. no


The correct address is FFFF FFF0H, and the correct data is 02EAH, as shown in the figure.

Which group of circuit board LEDs is incorrect?

a. data

b. HIGH address

c. LOW address

c. LOW address


What is the hexadecimal address?

a. 1EF8H

b. 8FE1H

c. E107H


You read a ROM address of 1EF8H, but you know that the correct ROM address is 1FF8H.

Which address bit is incorrect?

a. A8

b. A9

c. A10

d. A11


3-60


You can conclude from your observations that A8 is

a. shorted to ground.

b. shorted to Vcc.

c. shorted to A9.

d. open to the low byte ROM chip.


Which of the RAM control inputs is activated by MRDC#?

a. chip select

b. output enable

c. write enable


The write operations occur when MWTC# is

a. high.

b. low.


MWTC# does not appear on the scope but is shown here for reference. Do the RAMSEL# and

MRDC# waveforms appear as shown?

a. yes

b. no


The next two low pulses on RAMSEL# are due to

a. ROM instruction fetches.

b. RAM read cycles.

c. RAM write cycles.


What could the other (high-lighted) low pulses on MRDC# indicate?

a. ROM instruction fetches

b. RAM write cycles

c. RAM read cycles


3-61


Which memory block is involved in this transfer?

a. RAM

b. ROM



What operation is indicated by the address and data LEDs and the W/R# level?

a. write AAAAAAAAH to address 5000H

b. read AAAAAAAAH from address 5000H

c. write 55555555H to address 5004H

d. read 55555555H from address 5004H


The next instruction calls for a read from 5004H. What data should the CPU read from 5004H?

a. 55555555H

b. AAAAAAAAH



Does the data bus read 55555555H as shown?

a. yes

b. no


Which data bit is in the wrong state?

a. D4

b. D5

c. D20

d. D21


The address and data LEDs indicate that the CPU is writing

a. AAAAAAAAH to address 5000H.

b. AAAAAAAAH to address 5004H.

c. 55555555H to address 5000H.

d. 55555555H to address 5004H.


3-62


The D20 line reads high on

a. the logic probe but low on the data LED.

b. the data LED but low on the logic probe.

c. both the data LED and the logic probe.


43. Connect the logic probe lead to the RAM D20 pin (U33 pin 16). At this point, D20 is

a. high.

b. low.

c. pulsing.


You found a high D20 level at the CPU and the LED, and a low D20 level at the RAM chip.

From this you can assume that D20 is

a. shorted to ground.

b. shorted to VCC.

c. open to the CPU.

d. open to the RAM chip.

REVIEW QUESTIONS


1. Which of the following would you not find on a ROM IC?

a. output enable input

b. chip enable input

c. bidirectional data lines

d. address inputs


2. The RAM ICs on your circuit board

a. are volatile.

b. have bidirectional data lines.

c. have tristate data outputs.



3-63


3. This table shows 4 ROM locations starting at FFFF FFF0H, which is the address of the CPU's

first instruction fetch. If address bit A1 were shorted to VCC, what code will the CPU fetch?

a. EA 02

b. 00 00

c. FC FF

d. 80 FF


4. How can you locate a fault in a microprocessor circuit when you have determined that bus

cycles are not being executed?

a. Check the reset levels of the CPU control signals.

b. Check the reset levels of the PLD control signals.

c. Step through the CPU's first instruction fetch.



5. Which of the PLD outputs is not active for monitor ROM transfers?

a. MWTC#

b. MRDC#

c. MROMSEL#

d. BS16#

CMS AVAILABLE

CM 15

CM 14

FAULTS AVAILABLE

None


3-64

Exercise 2 – Memory Address Decoding

EXERCISE OBJECTIVE

Describe the memory address decoding system that is used to select individual blocks of

memory.

EXERCISE DISCUSSION


For which memory block(s) is BS16# active?

a. RAM

b. MROM

c. UROM

d. Both b. and c.


Which hex digit contains address bits A17 and A18?

a. DIG1

b. DIG2

c. DIG3

d. DIG4


# of doubleword locations =



Min/Max Value: (32768) to (32768)






3-65


What is the range of the monitor ROM block?

a. 60110H to 70111H

b. 60000H to 7FFFFH

c. 60000H to 70000H


Which address is an image of address 0ABCH?

a. 8ABCH

b. 18ABCH

c. 10ABCH



How many sections are in each ROM block?

a. 8

b. 16

c. 32


RAM has fewer sections because the RAM

a. chips are larger than the ROM chips.

b. byte addresses have a smaller range than the ROM byte addresses.

c. locations have 4 bytes each and the ROM locations have 2 bytes each.


By converting the image to its corresponding address in the first block, what have you

eliminated?

a. 3 hex digits

b. 12 bits



What address in the first block corresponds to the ROM image C4EF12AH?

a. 6712AH

b. C46312AH

c. 6312AH

d. 63000H


3-66

EXERCISE PROCEDURE


In this circuit, the BS16# output will be active for

a. RAM transfers.

b. ROM transfers.



4. Adjust the scope TIME VARIABLE control so that two cycles of W/R# occupy exactly 10

horizontal divisions. Does the scope trace appear as shown?

a. yes

b. no


Do the RAMSEL# and MROMSEL# signals on your scope match this figure?

a. yes

b. no


During horizontal interval 4, the CPU is

a. reading from RAM.

b. reading from the monitor ROM.

c. writing to RAM.


During which interval does the CPU write to RAM?

a. 2

b. 3

c. 5

d. 6


3-67


During which interval are RAM and monitor ROM selected at the same time?

a. 2

b. 4

c. 5



During which interval does the CPU generate a write to the monitor ROM?

a. 1

b. 3

c. 4



9. Move CH 1 to BS16#. The RAMSEL# signal still appears in the figure for reference. The

BS16# signal is identical to

a. W/R#.

b. RAMSEL#.

c. MROMSEL#.


Do the A17 and A18 waveforms on the scope match those in the figure?

a. yes

b. no


A17 and A18 are both

a. low when RAM is selected.

b. high when monitor ROM is selected.



3-68


The A17 and A18 signal levels on the scope agree with those in the table

a. when RAMSEL# is active.

b. when MROMSEL# is active.

c. at all points.


The W/R# signal does not appear on the scope but is shown here for reference. Do the

RAMSEL# and MROMSEL# signals on your scope match those in the figure?

a. yes

b. no


CM 13 has been activated to insert a fault into the memory address decoder circuit. What

happens to the block select outputs?

a. RAMSEL# changes to a constant high level.

b. MROMSEL# changes to a constant high level.

c. Both of above.


The logic probe shows that ADS# is high. This could indicate that the CPU

a. has stopped executing bus cycles.

b. is stuck in a program loop.


15. Turn the SINGLE CYCLE switch on, and press RESET. Do the LEDs show the jump

instruction 02EAH at address FFFF FFF0H?

a. yes

b. no


3-69


You can first check the address decoder outputs to see if the correct block is selected. Which

block should be selected at reset?

a. RAM

b. user ROM

c. monitor ROM


The logic probe indicates that monitor ROM is

a. selected.

b. not selected.


The A17 and A18 levels indicate that which memory block should be selected?

a. RAM

b. user ROM

c. monitor ROM


The logic probe indicates that A17

a. and A18 are both high.

b. and A18 are both low.

c. is high and A18 is low.

d. is low and A18 is high.


You read a high level for A18 at the CPU and a low level at the address decoder (PLD U23).

You can assume that the fault is

a. a defective PLD.

b. an open A18 line to the PLD.

c. a ground short on A18.

d. a short between A17 and A18.


3-70


You read a high level for A17 and a low level for A18 at the address decoder inputs. Which

memory block is selected?

a. RAM

b. user ROM

c. monitor ROM



The address in the first block is

a. 63FF0H

b. 6FFF0H

c. F3FF0H

d. 63000H


What are the first four bytes of this address?

a. random data

b. a jump instruction



21. Jump to location 63FF0H by pressing <GO> and entering "63FF 0000". The startup message

appears in the LCD display because the CPU

a. was reset.

b. executed its jump to the initialization program.


3-71

REVIEW QUESTIONS


1. An address decoder decodes

a. part of the CPU address bus.

b. all of the CPU address bus.

c. part of the CPU data bus.

d. part of the CPU data and address buses.


2. If 4 address bits were decoded, how many memory blocks could be selected?

a. 4

b. 8

c. 16

d. 32


3. Which conditions of A17 and A18 are always necessary for BS16# to be active?

a. 1 X

b. 1 0

c. 1 1

d. 0 0


4. The data you wrote to 0000H also appears at 10000H because

a. 10000H is an image of 00000H.

b. A17 is shorted to ground.

c. A18 is shorted to ground.



Which of these addresses is also an image of 0000H?

a. 80000H

b. 90000H




3-72

CMS AVAILABLE

CM 13

FAULTS AVAILABLE

None


3-73

Exercise 3 – Memory Data Transfers

EXERCISE OBJECTIVE

Describe 16-and 32-bit memory data transfers in an 80386 microprocessor circuit.

EXERCISE DISCUSSION


You can address individual bytes by using

a. A0.

b. byte enables.


How many transfers are needed for the bytes that are now highlighted?

a. one 2-cycle transfer

b. two 2-cycle transfers

c. four 1-cycle transfers


A second cycle is not required if the transfer involves

a. one byte.

b. two aligned bytes (both upper bytes or both lower bytes).



A BS16# transfer requires two bus cycles if the bytes are

a. aligned.

b. misaligned.


3-74

Location: Exercise Discussion page: se3d12, Question ID: e3d12e

In two-cycle transfers, the lower bytes are transferred

a. in the first cycle.

b. in the second cycle.

c. partly in the first cycle and partly in the second cycle.


When the CPU is instructed to jump to a certain byte location, the address on the bus is

a. a multiple of four.

b. a multiple of two.

c. the exact address of that byte location.

EXERCISE PROCEDURE


1. Turn the SINGLE CYCLE switch on, and momentarily press RESET. Does the data and

address information in step 0 in the table appear on the circuit board LEDs?

a. yes

b. no


What are the levels of the byte enable outputs?

BE3# BE2# BE1# BE0#

a. 0 0 0 0

b. 0 0 1 1

c. 1 1 0 0

d. 1 1 1 1


3. Press the STEP switch once. Do the circuit board LEDs match step 1 in the table?

a. yes

b. no


3-75


4. Use the logic probe to check the levels of the BEO# through BE3# outputs.

What are the levels of the byte enable outputs?

BE3# BE2# BE1# BE0#

a. 0 0 0 0

b. 0 0 1 1

c. 1 1 0 0

d. 1 1 1 1


Is the table correct based on your results?

a. yes

b. no


From the byte enable outputs you can conclude that

a. only the 2 upper bytes are transferred.

b. only the 2 lower bytes are transferred.

c. upper and lower bytes are transferred.


At step 6, the CPU has executed the jump. Although 000F C012 is the jump to address, 000F

C010H appears first because the CPU

a. always jumps to a word boundary.

b. always jumps to a doubleword boundary.

c. has jumped to the wrong address.


This table for the program you entered has no columns for BE0# through BE3# because the CPU

is executing only RAM instruction fetches. The byte enable levels will all be

a. high.

b. low.


3-76


11. Turn the SINGLE CYCLE switch on, and press STEP until the address 4FF0H appears on

the address bus LEDs. What bytes appear on the data LEDs?

(LSB) (MSB)

byte 0 byte 1 byte 2 byte 3

a. 00 01 EA 02

b. 02 EA 01 00

c. EA 02 00 01


The remaining bytes (11 22 33) in step 1 are not part of an instruction, but they appear on the

data bus because the CPU

a. fetched them along with the last byte of the jump instruction.

b. fetches the next instruction while decoding the current one.


14. Press STEP once. You can determine that the CPU has executed the jump to 04012H because

the address bus shows

a. the jump-to address.

b. the boundary of the doubleword location that contains the jump-to address.


The addresses in the program are multiples of four because

a. each address is a word address.

b. each address is a doubleword address.

c. there are 4 bytes in each instruction.


When you compare the tables, you can conclude that

a. more bytes are transferred in a 32-bit bus cycle than in a 16-bit cycle.

b. the ROM program required more bus cycles than the RAM program.



3-77

REVIEW QUESTIONS


1. 32-bit RAM transfers in your circuit are more efficient than 16-bit ROM transfers because

a. ROM is read-only memory.

b. RAM has more memory.

c. RAM transfers require fewer bus cycles to accomplish the same task.



2. How many cycles were needed to fetch the first jump instruction in the 32-bit RAM and 16-bit

ROM programs you executed in the PROCEDURE?

RAM ROM

a. 5 5

b. 2 3

c. 3 2

d. 1 1


3. When the CPU executes the jump at FFFF FFF0H, it jumps to the address determined by the

a. operand 02 00 01 FC.

b. operand 02 00.

c. operand 01 FC.

d. op code EA.


4. When BS16# is active, data that is normally transferred on lines D24 through D31 is

transferred on lines

a. D0 through D7.

b. D8 through D15.

c. D16 through D23.

d. D24 through D31.


5. Byte enables are used in your circuit to select individual bytes during a

a. RAM read cycle.

b. RAM write cycle.

c. ROM read cycle.

d. ROM write cycle.


3-78

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-79

UNIT TEST


You can determine the size of each location in a memory device by the number of

a. address lines.

b. data lines.

c. control lines.



Which chip select input(s) must be active to enable this RAM IC?

a. CS1 only

b. CS2 only

c. both CS1 and CS2

d. either CS1 or CS2


If the highlighted control signals are low and all others are high, what type of cycle is executed?

a. write bytes 0 and 1 to RAM

b. write bytes 2 and 3 to RAM

c. read bytes 0 and 1 from RAM



Which control input to PLD U23 is not necessary for the operation of the address decoder?

a. ADS#

b. M/IO#

c. CLK

d. All are necessary.


The address decoder's BS16# output activates when which block select is active?

a. RAMSEL#

b. MROMSEL#

c. UROMSEL#

d. Either b. or c.


3-80


Images occur in your circuit's memory because

a. the address bus is only partially decoded.

b. the address bus is fully decoded.

c. RAM and ROM share some of the same address lines.

d. there are 16- and 32-bit memory areas.


The least significant address bit (A0) is used in your circuit for addressing

a. RAM.

b. ROM.




One of the functions of PLD U20 in your circuit is to

a. decode byte enables from A0 and A1.

b. decode A0 and A1 from the byte enables.

c. synchronize the byte enables with A0 and A1.



Which group of bytes shown requires 2 bus cycles to transfer?

a. A

b. B

c. C



The highlighted RAM bytes are transferred in two bus cycles. Which byte enables are active in

the second cycle?

a. BE0#

b. BE1#, BE2#, and BE3#

c. BE0# and BE1#

d. BE2# and BE3#

32 Bit Microprocessor Unit 4 – I/O Interfacing

3-81

UNIT 4 – I/O INTERFACING

UNIT OBJECTIVE

Demonstrate the signals needed to transfer data between the 386 CPU by using the 32-BIT

MICROPROCESSOR circuit board and its associated input/output components.

UNIT FUNDAMENTALS

Location: Unit Fundamentals Page: sf6, Question ID: f6a

What is the address range for the digital-to-analog converter?

a. 00 to 0FH

b. 10 to 1FH

c. 20 to 2FH

CMS AVAILABLE

None

FAULTS AVAILABLE

None

NEW TERMS AND WORDS

unipolar - having one polarity.

bipolar - having two polarities.

retriggerable one-shot - a monostable multivibrator that can be triggered during its pulse time to

prevent time-out.

EQUIPMENT REQUIRED


Multimeter




3-82

Exercise 1 – DAC and ADC Ports

EXERCISE OBJECTIVE

Demonstrate the DAC and ADC ports on the 32-BIT MICROPROCESSOR circuit board. Use a

program, voltmeter, and oscilloscope to verify results.

EXERCISE DISCUSSION

Location: Exercise Discussion Page: se1d4, Question ID: e1d4a

What is the output in the bipolar mode when the input is 0V?

a. 00H

b. 80H

c. FFH

EXERCISE PROCEDURE

Location: Exercise Procedure Page: se1p2, Question ID: e1p2a

Which address line must be high to activate the DAC_EN# signal?

a. A4

b. A5

c. A6

Location: Exercise Procedure Page: se1p2, Question ID: e1p2c

3. Which address will enable the DAC?

a. 10H

b. 20H

c. 30H


What address is used to write data to the DAC?

a. 22H

b. 23H


3-83


What is the level of the DAC_EN# signal at U22 pin 17?

a. low

b. high


What is the resolution of the DAC?

a. 0.025V

b. 0.010V

c. 0.100V


Find the decimal value of 80H, and then calculate the DAC output voltage.

DAC Vo = Vdc

Recall Label for this Question:


Min/Max Value: (1.242) to (1.318)






Measure the output voltage.

DAC Vo = Vdc

Recall Label for this Question: v2


Min/Max Value: (1.242) to (1.318)






3-84


10. Is your calculated value of Vo (1.28 Vdc) approximately equal to your measured value of Vo

(#v2# Vdc)?

a. yes

b. no


12. Measure the DAC output voltage.

DAC Vo = Vdc



Min/Max Value: (2.483) to (2.637)






What is the resolution of the DAC when it is set for the 10V range?

a. 0.039V

b. 0.390V

c. 0.010V


14. Measure the DAC output voltage.

DAC Vo = Vdc



Min/Max Value: (9.7) to (10.3)






3-85


What kind of waveform is displayed on the oscilloscope?

a. ramp

b. sine wave


What is the address range of the ADC_CV signal?

a. 00H to 0FH

b. 10H to 1FH

c. 20H to 2FH


Does your scope display match the figure shown?

a. yes

b. no


Read the AL register contents. The AL register contents are between

a. 50H and 55H.

b. 7EH and 82H.

c. A0H and A4H


The AL register contents are between

a. 0DH-11H

b. 2DH-31H

c. 05H-09H


Read and record the AL register contents.

AL register contents = H









3-86

REVIEW QUESTIONS

Location: Review Questions Page: se1r1, Question ID: e1r1

1. Data lines D16 thru D23 represent which byte of the 4-byte data bus?

a. byte 0

b. byte 1

c. byte 2

d. byte 3


2. When the ADC is in the bipolar mode, what is the input voltage range?

a. +10V to –10V

b. +5V to –5V

c. 0V to +10V

d. 0V to –10V


3. The DAC is set to the 10V range and has a resolution of 0.039V. What is the output voltage

when a 10H is written to the DAC?

a. 0.62V

b. 5V

c. –10V

d. 0.39V


4. Before the ADC is read, what signal must be applied to the ADC?

a. DAC_EN#

b. ADC_EN#

c. ADC_CV

d. DR#


5. When the DAC is set to the 2.56V range, a change of 1 LSB on the input causes how much of

a voltage change on the output?

a. 0.010V

b. 0.256V

c. 0.100V

d. 0.0256V


3-87

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-88

Exercise 2 – PPI and Keypad Interface

EXERCISE OBJECTIVE

Demonstrate the programmable peripheral interface (PPI) and the keypad interface by using a

test program and an oscilloscope.

EXERCISE DISCUSSION


To access the control word, address lines A1 and A0 are

a. both low.

b. low and high, respectively.

c. both high.


The PPI is connected to which byte of the data bus?

a. byte 0

b. byte 1

c. byte 2

d. byte 3


3-89

EXERCISE PROCEDURE


What must the state of the input signals be to activate the PPI_EN#?

a. high

b. low


The PPI chip is selected when the signal is

a. low.

b. high.


What state must address line A4 be in to generate the PPI_EN# signal?

a. low

b. high



a. low

b. high



a. low

b. high


What state of the M/IO# signal is required to generate the PPI_EN# signal?

a. low

b. high


3-90


What state of the ADS# signal is required to generate the PPI_EN# signal?

a. low

b. high


What is the data on the PB port?

a. 1010 1010 AAH

b. 0101 0101 55H

c. 0000 0000 00H


What is the data on the PB port?

a. 1010 1010 AAH

b. 0101 0101 55H

c. 0000 0000 00H


15. Measure the period (T) of the KSCLK signal.

T = µs


Nominal Answer: 3.8







3-91


16. The one-shot pulse width equals R44 times C41. Calculate the pulse width (PW) of the one-

shot.

PW = ms









Is this signal high or low?

a. high

b. low


18. Press <0>. What level is the STROBE signal while the key is pressed?

a. high

b. low


What is the data in the AH register?

a. F0H

b. ECH

c. FCH


Press <6>. What data should be in the AH register?

a. F9H

b. 99H

c. 9FH


3-92


Does the AH register contain F9?

a. yes

b. no


2. CM 2 has been activated to modify the keypad circuit. Press RESET. Press any key. Is the key

closure recognized?

a. yes

b. no


Which signals can be checked to verify the keypad operation?

a. CLK2 and DAC_EN#

b. KSCLK and STROBE

Location: Exercise Procedure Page: se2p24, Question ID: e2p24e

24. Connect the scope channel 1 probe to U40 pin 13 to check the STROBE signal. Is there a

STROBE signal at this pin when you press a key?

a. yes

b. no


25. Next verify the input signals to U40. Is the KSCLK signal present at U40 pin 1?

a. yes

b. no


26. Check the input signal at U40 pin 2. Is this signal high and then does it go low when you

press a key?

a. yes

b. no

Location: Exercise Procedure Page: se2p25, Question ID: e2p25e

27. CM 2 has been turned off. Does the keypad work normally?

a. yes

b. no


3-93

REVIEW QUESTIONS


1. The PPI_EN# signal must be enabled to

a. write to the display.

b. read the keypad.

c. output data to the DAC.

d. input data from the ADC.


2. The key code generated by a pressed key is read on which port?

a. PPI PA

b. PPI PB

c. PPI PC



3. The PPI PB port is used as a(n)

a. serial port.

b. keypad interface.

c. parallel port.

d. analog output port.


4. Which signal is generated when one-shot U40 times out?

a. DAC_EN#

b. PPI_EN#

c. KSCLK

d. STROBE


5. The CPU reads DIP switch S3 during the intitialization routine by reading the PPI

a. PA port.

b. PB port.

c. PC port.



3-94

CMS AVAILABLE

CM 2

FAULTS AVAILABLE

None


3-95

Exercise 3 – Display and Serial Port

EXERCISE OBJECTIVE

Demonstrate the display and the serial port using test routines and an oscilloscope.

EXERCISE DISCUSSION


What must the level of A0 be to select byte 1 of the data bus?

a. high

b. low


What are the signal levels at the DB9 connector P2?

a. 5 volt logic levels.

b. RS-232C logic levels.

EXERCISE PROCEDURE


1. Observe the figure of U22 and determine what address range is required to generate the

display enable (DP_EN) signal?

a. 40H to 4FH

b. 50H to 5FH

c. 60H to 6FH


3-96


2. Which byte of the data bus is the display connected to?

a. byte 0

b. byte 1

c. byte 2

d. byte 3


What character does a 35H generate?

a. 5

b. H


5. Run the program from 0000:4000. What is the active level of the DP_EN signal?

a. high

b. low


6. Set the oscilloscope vertical mode to ALT and CH2 for 5 V/DIV. Connect the channel 2 probe

to A2. Why is A2 high when the display is enabled?

a. The display address is 55.

b. The display is being written to.


7. Use the UNIT HELP for the display instruction set and determine what writing an 01H to the

display would do.

a. read busy flag and address

b. clear display

c. return home


3-97


8. Connect the scope CH 2 to the R/W# signal at U29 pin 6. When the R/W# signal is low, what

operation is being done to the display?

a. read operation

b. write operation


9. How can you change the character written to the display?

a. Change the byte at 04000.

b. Change the byte at 04001.

c. Change the byte at 04005.


10. Change the data at 04001 from 35 to 48. Run the program. What is the character on the

display?

a. 6

b. H


15. What is the hex value of the byte displayed on the oscilloscope?

a. 0FH

b. F0H

c. FFH


3-98

REVIEW QUESTIONS


1. What is the address range of the DP_EN signal?

a. 30H to 3FH

b. 40H to 4FH

c. 50H to 5FH

d. 60H to 6FH


2. What address is used to write a character to the display?

a. 51H

b. 55H

c. 50H

d. 52H


3. What is the level for an RS-232C logic 1?

a. –5V to –15V

b. 0V

c. 5V

d. +5V to +15V


4. The serial port is used to

a. transmit serial data.

b. receive serial data.

c. transmit and receive serial data.

d. transmit and receive parallel data.


5. The display on the 32-BIT MICROPROCESSOR circuit board is a (an)

a. LED display.

b. fluorescent display.

c. incandescent display.

d. LCD display.


3-99

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-100

UNIT TEST

Location: Unit Test Page: sut1, Question ID: ut1

A DAC port is connected as shown. From what map is the DAC port addressed?

a. memory

b. I/O

c. ROM

d. RAM


The address range of the DAC_EN# signal is 20H to 2FH. What address is used to write to the

DAC?

a. 20H

b. 21H

c. 22H

d. 23H


To output data from the CPU to an I/O device, what instruction must be used?

a. JMP

b. OUT

c. IN

d. MOV


Which of the following devices is used to input analog information into a microprocessor

system?

a. ADC

b. DAC

c. serial port

d. PPI


3-101


The serial port can be used to communicate with other external

a. parallel ports.

b. RS-232C ports.

c. ADC ports.

d. DAC ports.


Which of the following instructions could be used to read the byte in the ADC after a conversion

has been completed?

a. IN AL, 90H

b. OUT AL, 13H

c. MOV AX, BX

d. IN AL, 13H


The resolution of a DAC with a 10-volt output and 8 input bits equals

a. 10 divided by 256.

b. 10 divided by 8.

c. 8 divided by 10.

d. 256 divided by 10.


What are the RS-232C signal levels?

a. Logic 1 is 5V and logic 0 is 0V.

b. Logic 0 is –5V to –15V and logic 1 is +5V to +15V.

c. Logic 1 is –5V to –15V and logic 0 is +5V to +15V.

d. Logic 0 is 5V and logic 1 is 0V.


3-102


When an ADC is used in a bipolar mode the input signal can be

a. 80H.

b. only negative.

c. only positive.

d. positive or negative.


What character will be on the display if a 45H is written to the character generator?

a. 5

b. E

c. F

d. d

32 Bit Microprocessor Unit 5 – Interrupt Processing

3-103

UNIT 5 – INTERRUPT PROCESSING

UNIT OBJECTIVE

Demonstrate how the 80386 CPU processes hardware and software interrupts. Verify results by

entering and analyzing test programs on the 32-BIT MICROPROCESSOR circuit board and by

observing signals with the oscilloscope and logic probe.

UNIT FUNDAMENTALS


In this figure, the stack pointer decrements by 2, indicating that data is stored in a. bytes.

b. words.

c. doublewords.


Is the data that you pop from the stack always the first or last data pushed onto the stack?

a. last

b. first


At the end of the service routine, the CPU pops the information off the stack in

a. the order in which it was pushed.

b. reverse order.


The maskable interrupts are masked when

a. IF is set.

b. IF is cleared.


Which type generates an interrupt after the instruction that causes the exception?

a. fault.

b. trap.

c. abort.


3-104


Which type numbers are for hardware interrupts?

a. 32-255

b. 2

c. All of the above.


At what address is the vector for a type 06 interrupt located?

a. 006H.

b. 018H

c.024H

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-105

NEW TERMS AND WORDS

interrupt - a process by which the CPU suspends operation of its program to service the needs of

an external device or an internal condition. When the interrupt has been serviced, the CPU

normally returns to the next instruction to be executed in the interrupted program.

interrupt service routine (ISR) - a set of instructions to which the CPU jumps when an interrupt

or exception occurs.

flags (FLG) register - a CPU register whose individual bits indicate or control the status

of various CPU functions

stack - an area of RAM set aside for sequential storage and retrieval of data. Stacks are

used for several microprocessor functions, including interrupt processing.

stack segment (SS) - a CPU register that contains the segment value of the currently active stack.

stack pointer (SP) - a CPU register that contains the address of the last data that was pushed onto

the stack.

push - an operation in which the CPU stores a word or a doubleword to the top of the stack and

decrements the stack pointer.

pop - an operation by which the CPU removes a word or doubleword from the top of the stack

and then increments the stack pointer.

last-in-first-out (LIFO) stack - a type of stack in which the last data pushed onto the stack is the

first data to be popped off the stack.

hardware interrupts - an interrupt caused by an external hardware signal.

exceptions - the CPU 's response to certain internal conditions during the execution of an

instruction.

maskable interrupts - a hardware interrupt that you can disable (mask) by setting the IF

bit in the FLG register.

type number - a number in the range 0-255 (00-FFH) that is used to identify the type of interrupt

or exception being processed by the CPU.

vector table - a table that contains the vectors for interrupt service routines. In the 80386 CPU's

real mode the vector table is normally located in the first 1 Kbyte of RAM (00-3FFH).

vector - a logical address value that points to the first location of an interrupt service routine.

programmed exceptions - an exception that results from the execution of software interrupt

instructions.

software interrupts - an instruction that causes a programmed exception.

Processor-detected exceptions - an exception that results from the CPU's recognition of certain

internal conditions.

breakpoint - a software interrupt that stops a program for the purpose of debugging or evaluating

system hardware or software.

overflow - a condition that occurs when the result of an arithmetic or logic operation changes the

MSB (sign bit) of an operand.

sign bit - a signed operand's MSB, which indicates the algebraic sign of the operand.

non-maskable interrupt (NMI) - a hardware interrupt that you cannot mask or disable.


3-106

EQUIPMENT REQUIRED





3-107

Exercise 1 – Non-Maskable Interrupts

EXERCISE OBJECTIVE

Demonstrate the non-maskable hardware interrupt operations of the 32-BIT


EXERCISE DISCUSSION


The CPU's NMI input is activated

a. only when the HALT switch is pressed and NMI# is activated at the same time.

b. when the HALT switch is pressed or NMI # is activated.


Why does the flow chart not show the code segment, instruction pointer, and flag register

contents being saved to the stack?

a. The CS, IP, and FLG register contents are not saved.

b. The CS, IP, and FLG register contents are pushed onto the stack before the CPU jumps

to the service routine.


How many additional pulses are ignored in this figure?

a. two

b. three

c. four


3-108

EXERCISE PROCEDURE


The vector 0000:7000 points the CPU to the NMI service routine. Where must the vector be

located?

a. 00002H

b. 00004H

c. 00008H


In this PROCEDURE section, you will establish 02000H as the first stack location to which the

CPU will store register information. How can you establish 02000H as the top of the stack?

a. Change the CS/IP register contents to 0000:2000.

b. Change the SS/SP register contents to 0000:2000.

c. Write the SS/SP register contents to 0000:2000.


When an interrupt occurs, what register contents are pushed onto the stack?

a. flags

b. code segment

c. instruction pointer



4. View the contents of the BP/FL registers. What number is currently contained in the flags

register?

a. 0002H

b. 00000000H


What is the status of the interrupt enable flag?

a. set

b. cleared


3-109


7. Switch to single cycle mode, and press the single cycle STEP switch several times as you

observe the low address LEDs. Where is the CPU executing instructions?

a. service routine

b. main program

c. stack


How can you generate a non-maskable interrupt to the CPU?

a. by pressing HALT

b. by connecting NMI# to ground



The LEDs indicate that the CPU is

a. about to fetch the interrupt vector.

b. about to jump to the service routine.

c. still in the main program.


According to the data and address LEDs, what will the CPU do next?

a. return from the ISR

b. push data to the stack

c. fetch the first ISR bytes


Do the data and address LEDs agree with the table?

a. yes

b. no


The LEDs indicate that the CPU will push the contents of the flags register onto the stack. You

previously set the top of the stack at 2000H. Why does the push occur at 1FFEH?

a. The stack pointer is decremented.

b. The stack pointer is incremented.


3-110


How can you confirm that this is a stack push and not a stack pop?

a. Read the FLG register contents.

b. Check the level of the W/R# line.

Location: Exercise Procedure page: se1p11, Question ID: e1p11g

12. Connect the logic probe to W/R#. Is the bus cycle at 1FFEH a read or a write cycle?

a. read

b. write


You determined in a previous unit that, for 16-bit write operations, the CPU writes on 16 data

lines and duplicates the data on the other 16 lines. How can you determine which 16 lines are

involved in the transfer?

a. by the address

b. by reading the byte enable lines



According to the address, the transfer takes place on the

a. upper 16 lines.

b. lower 16 lines.


13. Use the logic probe to check the levels of BE0# through BE3#. Which byte enables are

active?

a. BEO# and BE1#

b. BE2# and BE3#

c. all four


14. Press STEP once. According to the address, data, and logic probe LEDs, what operation will

take place?

a. push CS

b. pop CS

c. push FLG


3-111


15. Press STEP once. What operation is now indicated by the logic probe and LEDs?

a. pop CS

b. pop IP

c. push IP


17. Press STEP once to view the next address and data. The bytes that follow the return

instruction appear on the data bus because

a. they are part of the return instruction.

b. the CPU fetches these bytes at the same time it decodes the return instruction.

c. the bytes were popped off the stack.


The CPU will

a. pop IP from the stack.

b. push IP onto the stack.

c. pop FLG from the stack.


When the IP data is popped from the stack,

a. the data is restored to the IP register.

b. the stack pointer increments.



Each time register data was popped from the stack, the stack pointer incremented, and the

information was popped off in reverse order (IP-CS-FLG). What type of stack does this indicate?

a. Last-In-First-Out (LIFO)

b. First-In-First-Out (FIFO)


21. Press STEP several times as you observe the address LEDs. The LEDs indicate that the CPU

a. is repeating the interrupt service routine.

b. has returned to the main program at 4000H.


3-112


At the beginning of the PROCEDURE, you determined that the IF bit in the flags register was

cleared, indicating that interrupts should be masked out. Why was the interrupt signal recognized

in this program?

a. The IF bit was set during the program execution.

b. An exception occurred.

c. The interrupt signal you applied was a non-maskable type.


24. Press STEP once. The address LEDs indicate that the CPU has

a. ignored the interrupt.

b. recognized the interrupt.


26. Press STEP once, and read the address LEDs. The LEDs indicate that the CPU has

a. returned to the main program.

b. started to repeat the ISR.


27. Press STEP several times as you observe the address LEDs. Release the HALT switch. The

LEDs indicate that the CPU is

a. continuously executing the loop in the main program.

b. repeating the ISR.



You can conclude that the NMI input is

a. level sensitive.

b. edge sensitive.


30. Press STEP repeatedly to determine the number of times the CPU jumps to the ISR. The

number of NMI pulses that the CPU recognized is

a. one.

b. two.

c. four.


3-113

REVIEW QUESTIONS


1. When a non-maskable interrupt occurs, the CPU uses a vector type number

a. from anywhere in the range 00-FFH.

b. that is part of the interrupt instruction.

c. that is taken from the stack.

d. of 02.


2. Which register's contents are not automatically pushed onto the stack when an interrupt

occurs?

a. code segment

b. instruction pointer

c. stack pointer

d. flags register


3. How can you determine the address at which the NMI vector is located?

a. Multiply the type number by 4.

b. Divide the type number by 4.

c. The type number is the address.



4. Suppose the stack segment and stack pointer registers contain the address 0000:2006 before an

interrupt occurs. Assume that the service routine itself does not perform any stack operations.

What address is contained in SS/SP when the CPU returns from the service routine?

a. 0000:2000

b. 0000:2003

c. 0000:2006

d. cannot be determined


5. How can you disable a non-maskable interrupt?

a. by setting the IF bit in the FLG register

b. by clearing the IF bit

c. with an instruction



3-114

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-115

Exercise 2 – Maskable Interrupts

EXERCISE OBJECTIVE

Explain and demonstrate the operation of maskable hardware interrupts for the 80386

microprocessor.

EXERCISE DISCUSSION


Which device generates the INTA# signal?

a. CPU

b. bus controller

c. I/O decoder


What is the hex value of ICW1 when ICW4 is not needed and edge-triggered and SNGL modes

are specified?

a. 12H

b. 13H

c. 1AH

d. 1BH


What is the hex type number for IR6 if ICW2 = C8H?

a. CDH

b. CEH

c. CFH


After ICW1 and ICW2 are received, the PIC determines if cascade mode was specified. What

condition specifies cascade mode?

a. ICW1 bit D3 = 1

b. ICW1 bit D1 = 0

c. ICW2 bit D0 = 1


3-116


The PIC then determines if ICW4 is needed. For which condition is ICW4 needed?

a. ICW2 bit D0 = 0

b. ICW1 bit D0 = 0

c. ICW1 bit D0 = 1

d. ICW1 bit D3 = 1


The idle states are followed by the second INTA cycle. What signal levels are different from

those in the first INTA cycle?

a. BE0#, A3-A31, M/IO#, D/C#, and W/R#

b. BE1#, BE2#, and BE3#

c. A2

EXERCISE PROCEDURE


When a maskable interrupt occurs, the CPU reads the vector type from the PIC. The type number

is in the range 32-25510. What is the corresponding hexadecimal range?

a. 32-255H

b. 20-FFH

c. 20-FFFH


Before maskable interrupts can be processed, the CPU must program the PIC's operating mode

with initialization command words. The first PROCEDURE section calls for level-triggered

mode and ICW4 needed. What value must the CPU send for ICW1?

a. 12H

b. 13H

c. 1BH


What value of ICW2 must be sent to the PIC?

a. 40H

b. 47H

c. 28H

d. 2FH


3-117


The program you will use in this PROCEDURE section requires automatic end of interrupt.

What value of ICW4 is needed?

a. 03H

b. 02H

c. 01H


Why is the I/O address 30H for ICW1 and 34H for ICW2?

a. ICW2 is not sent to the PIC.

b. Address line A2 is 0 for ICW1 and 1 for ICW2.

c. Address line A2 is 1 for ICW1 and 0 for ICW2.


The next program line has a set interrupt (STI) instruction. What does this instruction do?

a. enables maskable interrupts

b. disables maskable interrupts

c. disables non-maskable interrupts


The address of each type is

a. twice the type number.

b. 4 times the type number.

c. any free memory location, independent of type number.


The CPU is executing the

a. initialization instructions from 05000H to 0500CH.

b. main program loop at 0500DH.


7. Press STEP once. What can you determine from the LEDs?

a. The CPU has recognized an interrupt request.

b. The CPU is still executing the main program.

c. The CPU is executing a service routine.


3-118


The 0004H on the address LEDs indicates the first interrupt acknowledge cycle.

How can you confirm that this is an INTA cycle?

a. Check the NMI input.

b. Check the W/R#, D/C#, and M/IO# outputs.



9. Press STEP once. How can you confirm that this is the second INTA cycle?

a. W/R#, D/C#, and M/IO# are low.

b. All 32 address lines are low.



The address and data for the second INTA cycle are now shown in the table. The value 2BH in

the lower data byte is the

a. vector type number.

b. vector address.

c. interrupt vector.


10. Press STEP once. What number appears on the address LEDs?

a. the vector type

b. the vector address

c. the interrupt vector


What is the number displayed on the data LEDs?

a. the interrupt vector

b. the ISR instruction


11. Press STEP once. The address LEDs read 7000H, although the vector is 7003H. Why is the

address 7000H?

a. The address LEDs are wrong.

b. The CPU is executing more than one service routine.

c. The CPU jumped to the doubleword address in which the vector is located.


3-119


14. Press STEP several more times. The address LEDs indicate that the CPU

a. is repeating the service routine.

b. has returned to the main program.


Why is the service routine repeated?

a. Service routines are always repeated.

b. The PIC is programmed for level-triggered mode.

c. The PIC is programmed for edge-triggered mode.


To program the PIC for edge-triggered mode, you must change bit D3 to 0 in ICW1. Assuming

that bit D0 remains 1, what is the resulting value of ICW1?

a. 03H

b. 13H

c. 1BH


The address alternates between 500CH and 5010H, indicating that the CPU is continuously

executing the main program without jumping to the service routine. This is because

a. the PIC is now programmed for edge-triggered mode.

b. there is no interrupt signal present.


An active level was maintained on an IR input while the PIC was programmed for edge-triggered

mode. Your results show that the CPU

a. jumps to the ISR once and then remains in the main program.

b. repeats the ISR as long as the level is applied.


The low data byte was previously 2BH, indicating an interrupt request on IR3. Why is this byte

now 2FH?

a. The interrupt signal was active for only the first INTA cycle.

b. The interrupt signal was active for both INTA cycles.

c. A different interrupt request was activated.


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The vector on the data bus is 0000:7007 because

a. this is the vector for the IR3 service routine.

b. the PIC always uses type number 7 when the IR signal is not present for both INTA

cycles.


You can conclude from this PROCEDURE section that, if the IR signal is absent for the second

INTA cycle, the PIC

a. does not interrupt the CPU.

b. interrupts the CPU but sends the type number 7.

c. interrupts the CPU and sends a type number based on which IR input was active.


Do the waveforms on your scope appear as shown?

a. yes

b. no


What operation occurs when the W/R# line is high?

a. The CPU pushes data onto the stack.

b. The CPU pops data from the stack.

c. The PIC sends a type number to the CPU.


Do the waveforms on your scope appear as shown here?

a. yes

b. no


Do the ADS# and RDY# waveforms on your scope appear as shown here?

a. yes

b. no


3-121


The idle states are the CLK cycles that occur

a. before the ADS# pulse.

b. after the RDY# pulse.

c. between the RDY# and ADS# pulses.


How many idle states occur between the INTA# pulses?

a. four

b. five

c. six


34. Turn off the SINGLE CYCLE switch and press RESET. Connect +5V to IR0, and then

remove the connection. What indication tells you that an interrupt has been recognized?

a. data LEDs

b. address LEDs

c. LCD display



36. Repeat step 35 for each remaining PIC input, IR2 through IR7. Does each message indicate

the correct IR number?

a. yes

b. no


38. Repeat step 37 for the remaining PIC inputs IR1 through IR7. According to the LCD display,

which interrupt requests are working properly?

a. IR0 through IR3

b. IR4 through IR7

c. None.


39. Use the logic probe to check the levels of the control inputs and outputs directly at the PIC.

Which of the following conditions accounts for the PIC's failure to process interrupts?

a. IOWC# shorted to ground

b. INTA# shorted to ground

c. A2 shorted to Vcc

d. IORC# shorted to Vcc


3-122

REVIEW QUESTIONS


1. You can disable the CPU's recognition of maskable interrupts by a. setting the IF bit in the flags register.

b. clearing the IF bit in the flags register.

c. changing command word ICW1.

d. changing command word ICW2.


2. The complete interrupt acknowledge sequence for maskable interrupts consists of

a. two INTA cycles and then four idle states.

b. four idle states and then two INTA cycles.

c. one INTA cycle, four idle states, and then a second INTA cycle.

d. one INTA cycle and then four idle states.


3. When a maskable interrupt occurs, the vector type number

a. is sent to the CPU by the PIC.

b. is sent to the PIC by the interrupting device.

c. can be anywhere in the range 00-FFH.

d. is always 02H.


4. If the CPU sends the PIC a value of A8H for ICW2, what is the hex type number for IR2?

a. A8H

b. AAH

c. ABH

d. ACH


5. Which PIC control signal is not used when the CPU sends command words?

a. CS

b. WR

c. A0

d. INTR


3-123

CMS AVAILABLE

CM 18

FAULTS AVAILABLE

None


3-124

Exercise 3 – Exceptions

EXERCISE OBJECTIVE

Explain and demonstrate how exceptions interrupt the 80386 microprocessor.

EXERCISE DISCUSSION


The INT3 software interrupt, also called a breakpoint, has a type number of 3. At what address

is the ISR's vector located?

a. 00003H

b. 00012H

c. 0000CH


Which addition results in an overflow?

a. 7EH + 01H

b. 7FH + 01H

c. Both of these.


What interrupt is specified by the op code CD 10? (Remember that the type numbers in the table

are in decimal and the op code bytes are in hexadecimal.)

a. invalid task state segment

b. coprocessor error

c. debug exception


3-125

EXERCISE PROCEDURE


At what address can you find the interrupt vector for INTO?

a. 00004H

b. 00010H

c. 00016H


What is the address of the INT3 interrupt vector?

a. 00003H

b. 0000CH

c. 00012H


The location's segment is contained in the data segment (DS) register. The first two lines set DS

to 0000H. What is the complete jump-to address?

a. 0000:0010

b. 0010:0000H


Which message appears in the LCD display?

a. A

b. B

c. C


3. Press any key on the keypad. The error message is

a. still displayed.

b. gone.


The flow diagram in the help window (click on Help) illustrates the operation of the main

program and the service routines. For what condition is an error message displayed?

a. overflow

b. no overflow


3-126


What should you do before running the main program?

a. Load values into the AL and BL registers.

b. Enter INTO and INT3 service routines into memory.



5. Use the register mode to load 7E into AL and 01H into BL. The sum is 7FH (7EH + 01H).

Will this addition result in an overflow?

a. yes

b. no


6. Exit the register mode, then press <GO> and enter "0000:6000" to run the program. Based on

the display, which type of interrupt occurred?

a. INTO

b. INT3


7. Read the contents of the FLG register. The overflow flag is bit 11, which is the MSB of digit

2. What is the status of the OF bit?

a. set

b. cleared


If you ran the main program again with the present values in AL and BL, what would happen?

a. The sum would exceed 7FH.

b. An overflow would occur.



What confirms your prediction that the addition of 7FH and 01H would cause an overflow?

a. An error message appears in the display.

b. The OF flag is set.

c. The sum (contained in AL) exceeds 7FH.



3-127


10. Press any key to cancel the error message. Read the contents of the EAX register. What is the

value of AL?

a. 7FH

b. 80H

c. 81H


11. Read the contents of the FLG register. Convert digit 2 to its binary value. The MSB of digit 2

is the overflow flag. The OF bit is

a. set.

b. cleared.


13. Press <GO> and enter "0000 4000" to run the program. Which message appears on the

display?

a. A

b. B

c. C


The CPU will execute the divide instruction

a. if BL = 0.

b. if BL χ 0.

c. on either condition.


If you run the program with these values, what type of interrupt will occur?

a. divide error

b. breakpoint

c. None


17. Exit the register mode, press <GO>, and enter "0000 5000" to run the program. The display

indicates that

a. a division has occurred.

b. no division has occurred.


3-128


19. Change the contents of BL to 00H. What type of interrupt will result if you run the program

with these values?

a. divide error

b. breakpoint


20. Exit the register mode and run the program at 0000:5000. The display shows the divide error

message. Read the contents of AL and BL. The values indicate that the divide instruction was

a. executed.

b. not executed.


22. Exit the register mode, and run the program at 0000:5000. Read the contents of AL and BL.

You can conclude that a divide error occurs when the CPU attempts to divide

a. a number by 0.

b. 0 by another number.



If the CPU fetches an instruction having an op code that is not defined for the 80386, a type 6

exception occurs (invalid op code). What type of exception must this be?

a. trap

b. fault


Where can you find the vector for the invalid op code service routine?

a. 00006H

b. 00018H

c. 00024H


23. An example of an invalid op code for the 80386 is FF FFH. Write "FF FF CC" to location

0000:7000. The CC (breakpoint) instruction is included to prevent the CPU from running beyond

this program. Jump to 0000:7000 by using the <GO> key. How do you know that an invalid op

code was detected?

a. A breakpoint occurred.

b. The display shows the message



3-129


What service routine would be called by the instruction CD 10?

a. debug exception

b. invalid task statement

c. coprocessor error


How are the vector addresses determined?

a. The hex type number is multiplied by 4.

b. The programmer assigns them at random.


What address contains the vector that points to the service routine for IR4?

a. 00036H

b. 00024H

c. 00090H


The instructions shown are individual INTn instructions. After each instruction is executed,

when will the CPU jump to the operand-specified service routine?

a. immediately

b. when an interrupt request signal is received


25. Press <GO> and enter "0000 4000". What message appears on the first line of the display?

a. PIC INTERRUPT R0

b. - press any key -

c. breakpoint address


26. Press any key to cancel the message. What can you do to execute the IR1 service routine?

a. activate the PIC's IR1 input.

b. press <STEP>



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27. Press <STEP>. Does the display show the interrupt message for IR1?

a. yes

b. no


29. Press any key to cancel the message, then press <STEP> to execute the INT 08 interrupt. The

INT 08 instruction causes a jump to the type 08 service routine. What message appears in the

first display line?

a. PIC INTERRUPT 08

b. Invalid OP-Code

c. Double Fault


You have demonstrated that the INTn instruction can be used to simulate

a. hardware interrupts.

b. other exceptions.


REVIEW QUESTIONS


1. What can cause an exception to interrupt the CPU?

a. a software interrupt instruction

b. an internal CPU condition

c. a hardware signal

d. either a or b


2. Which software interrupt instruction can you use to simulate any other exception or hardware

interrupt?

a. INTO

b. INT3

c. INTn



3-131


3. The invalid op code exception is a fault because

a. the CPU should be interrupted before executing an invalid instruction.

b. the CPU should be interrupted after executing an invalid instruction.

c. all exceptions are faults.

d. it has an even type number (06).


4. Which preliminary step is not required to prepare for exception processing?

a. programming of the PIC

b. loading interrupt vectors in the vector table

c. loading service routines into RAM

d. All three steps are necessary.


5. You can use the INT3 (breakpoint) software interrupt to stop a program in order to examine

a. memory.

b. CPU registers.

c. hardware conditions.


CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-132

UNIT TEST


The 80386 CPU recognizes an external maskable interrupt

a. any time the CPU receives an INTR signal.

b. only when a software interrupt instruction is executed.

c. only when the OF flag is set.

d. only when the IF flag is set.


When a return instruction occurs at the end of a service routine, the CPU executes the next

instruction

a. at the beginning of the service routine.

b. at the beginning of the program.

c. after the point at which the interrupt occurred.

d. at the top of the stack.


What type of interrupts are handled by the PIC?

a. exceptions

b. external maskable

c. external non-maskable

d. both b and c


What information is transferred on the data bus between the CPU and the PIC for processing

maskable interrupts?

a. PIC programming information

b. vector type numbers




How can you generate a non-maskable interrupt to the CPU?

a. Activate the NMI# input.

b. Press the PB HALT switch.

c. Insert an INT 02 instruction into a program.



3-133


When an interrupt occurs, the CPU saves its place in the main program by

a. pushing the CS, IP, and FLG register contents to the stack.

b. popping the CS, IP, and FLG register contents from the stack.

c. jumping to an interrupt service routine.

d. saving status information in a register.


If a valid NMI pulse occurs while the CPU is already executing an NMI service routine, the

a. pulse is ignored.

b. pulse is saved until the ISR is complete.

c. service routine is interrupted and begins again.

d. service routine is interrupted and the CPU returns to the main program.


Which 8-bit operation would result in an overflow exception?

a. dividing 7FH by 00H

b. dividing 00H by 7FH

c. adding 7FH to 00H

d. adding 7FH to 7FH


What type of service routine will be generated if an INTn instruction with the op code CD 0C is

executed?

a. segment not present

b. stack fault

c. general protection

d. page fault


At what address is the vector for the coprocessor segment overrun service routine located?

a. 00009H

b. 00018H

c. 00024H

d. 00036H


3-134

32 Bit Microprocessor Unit 6 – Programming: Addressing Modes

3-135

UNIT 6 – PROGRAMMING: ADDRESSING MODES

UNIT OBJECTIVE

Describe and execute the eleven addressing modes of the 80386 CPU by using the 32-BIT


UNIT FUNDAMENTALS


In the real mode, what is the maximum physical address size of external memory of the 80386

CPU?

a. 32 Kbytes (215)

b. 4 Gbytes (232)

c. 1 Mbyte (220)


In the real mode, what is the size of a data segement?

a. 64 Kbytes (216)

b. 4 Gbytes (232 bytes)


What is the function of registers within the 80386 CPU?

a. Registers provide very fast access to data in RAM.

b. Registers store data within the CPU and control the behavior of the processor.

c. Registers perform fast arithmetic calculations.

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-136

NEW TERMS AND WORDS

addressing modes - ways to write instruction, codes to locate an operand which may be in the

instruction in a general-purpose register or in memory.

physical address - an address that uniquely identifies a location in memory.

image addresses - different addresses that refer to the same memory location due to partial

address decoding.

paging - a memory management method that is used in the protected mode to provide access to

data structures and programs larger than the available memory space.

segmentation - a memory management method that allows memory to be divided into

independent secure address spaces.

segment - an independent secure address space.

operand - the data or address that is operated on by the op code.

op code - the part of the instruction that contains the code for the microprocessor operation to be

performed on the operand.

base address - the first location in a segment.

segment selector values - the 16-bit values that are in the visible part of the segment register.

hidden descriptor - the hidden part of a segment register that contains the segment's base

address, limit, and access information

limit - defines the size of a segment.

access information - information contained in the segment register's hidden descriptor; it

controls what programs can access data in a segment.

descriptor table - a table in memory that contains information for the hidden part

of a segment register.

linear address - an address equal to the segment's base address plus the offset, which determines

the physical address when paging is activated.

logical address - a representation of the physical address, written in the form of segment selector

value: offset value; The segment selector value is 2 bytes, and the offset value may be 2 or 4

bytes.

effective address (EA) - an offset (calculated from the sum of displacement, base, and index

values) that locates a memory operand within a selected segment.

EQUIPMENT REQUIRED




3-137

Exercise 1 – Immediate and Register Addressing Modes

EXERCISE OBJECTIVE

Explain the functions of the registers within the 80386 CPU. Use the immediate and register

addressing modes to transfer an operand to a register. Verify results by reading the contents of

the register before and after execution of a move (MOV) instruction.

EXERCISE DISCUSSION


In the real mode, what section of the 32-bit flags register is used?

a. the 32-bit EFLAGS section

b. the first byte of the FLAGS section

c. the 16-bit FLAGS section


To determine the physical address of the next instruction in memory, the CPU adds the offset

value in the IP register to the base address of what segment register?

a. DS register

b. CS register

c. SS register


What is the purpose of the 16-bit selector value in a segment register?

a. It gives the physical address of the next instruction.

b. It selects the active memory segment.


In the protected mode, the information in the hidden descriptor of the

segment register is obtained from what location?

a. the IP register

b. a descriptor table in memory

c. the paging system


3-138


What is the logical address for the physical address 05000?

a. 4000:1000

b. 1000:0400

c. 0400:1000


In the real mode, when must the hex 66 prefix be placed before the instruction?

a. when the instruction uses the 16-bit AX register for data

b. when the instruction uses a 32-bit general purpose register for data

c. when the instruction contains a 16-bit operand


Which instruction code uses the immediate operand addressing mode?

a. MOV EAX, EBX

b. MOV AX, 4567H

c. MOV AX, [SI+50H]

EXERCISE PROCEDURE


3. Are both of these registers, CS and IP, segment registers?

a. yes

b. no


4. What does the IP register contain?

a. the offset for the next instruction code

b. the next instruction code


5. What is in the visible part of the CS register?

a. the address of the next instruction

b. the code segment selection value


3-139


7. The CS register selector value is 0400. In the real mode, what is the hex value of the 20

significant bits of the 32-bit base address, which is in the hidden portion of the CS register?

a. 40000

b. 04000

c. 00400


8. In memory, what is the significance of the CS base address 04000?

a. It is the lowest physical address of the code segment.

b. It is the physical address of the instruction code.


10. What relationship does the value in the IP register (1000) have to the CS base address

(04000)?

a. The value in the IP register selects the CS's starting address in memory.

b. The IP register value is the offset for the CS base address.


11. With a CS base address of 04000 and an offset value of 1000 in the IP register, what is the

physical address of the instruction code?

a. 05000

b. 04100

c. 41000


12. What will be in the physical address of 05000?

a. the first byte of the instruction code

b. the data in the EBX register


13. What is an equivalent logical address for a physical address of 05000?

a. 0600:1000

b. 0400:1000

c. 4000:1000


3-140


What is the hexadecimal data in physical address 05002?

a. BB

b. 38

c. 25


Does the BX register contain the operand 2538?

a. yes

b. no


19. What data should be in the BX general purpose register?

a. 2538

b. BB38


21. Did the instruction BB 38 25 (MOV BX,2538H) put operand 2538 in the BX register?

a. yes

b. no


What type of operand addressing mode did the instruction use?

a. immediate

b. register


23. What did you accomplish by executing the MOV BX,2538H instruction?

a. The operand 2538 was moved from the AX register into the BX register.

b. The operand 2538 was specified in the instruction code and moved into the BX register.


Did the selector value in the CS register change after the instruction was executed?

a. yes

b. no


3-141


25. Did the value in the IP register change after execution of the instruction?

a. yes

b. no


30. With a CS register selector value of 0400 and an offset value of 1003 in the IP register, what

is the physical address of the instruction code?

a. 05003

b. 14030


33. Does the EAX register contain 00000000?

a. yes

b. no


38. What data should be in the EAX general purpose register?

a. 34CDAB12

b. 12ABCD34

c. 6689D8


39. To read the data in the EAX register, press <REG> and then <(A-B)>. Is the data in the

EAX register 12ABCD34?

a. yes

b. no


40. Did the 12ABCD34 data remain in the EBX register?

a. yes

b. no


The instruction used what type of operand addressing mode?

a. immediate

b. register


3-142


42. What did you accomplish by executing the MOV EAX,EBX instruction?

a. The operand was moved from the EBX register into the EAX register.

b. The operand was in a RAM location and moved into the EAX register.


Did the selector value in the CS register change after the instruction was executed?

a. yes

b. no


44. Did the value of the IP register change to 1006 after the execution of the instruction?

a. yes

b. no

REVIEW QUESTIONS


1. Where is the location of the instruction pointer, segment, general purpose, and flags registers?

a. These registers are in RAM.

b. The location of these registers depends on the application program.

c. These registers are within the 80386 CPU.

d. The instruction pointer, general purpose, and flags registers are within the 80386 CPU, and the

segment register is in RAM.


2. In the real mode, what does the physical address of the next instruction code equal?

a. the IP register's offset plus the CS register's selector value

b. the FLAGS register's offset status value plus the value in the AX register

c. the AX register's value plus the CS register's selector value shifted 4 bits to the left

d. the IP register's offset value plus the CS register's selector value shifted 4 bits to the left


3. What is a memory segment?

a. the contents of one of the segment registers

b. a region in memory that holds a specific type of data

c. the data stored in the general purpose registers

d. the location in memory for the next instruction


3-143


4. In the instruction MOV CX,ABE5H, what addressing mode is used, and after execution, what

will the CS register contain? (Click on Help.)

a. the register addressing mode; 217B

b. the immediate addressing mode; B9E5

c. the register addressing mode; 6BAF

d. the immediate addressing mode; ABE5


5. The ECX register contains 21AC68D9. In the instruction MOV EAX, ECX, what addressing

mode is used, and after execution, what data will the EAX register contain? (Click on Help.)

a. the register addressing mode; 21AC68D9

b. the immediate addressing mode; 6689C85B

c. the register addressing mode; 1424A6B7

d. the immediate addressing mode; 300589C8

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-144

Exercise 2 – Memory Addressing Modes - I

EXERCISE OBJECTIVE

Describe the ways to determine the effective address of a memory operand by using

displacement, base and index values and explain the six memory operand addressing modes that

can be used for 16-bit and 32-bit addressing. Verify results by reading the contents of a register

before and after execution of a move (MOV) instruction.

EXERCISE DISCUSSION


If the selector value in the DS register is 0300 and the EA is 65AB, what is the physical address

of the memory operand in the data segment?

a. 365AB

b. 67AB0

c. 095AB


In 16-bit addressing, the index value may be in what registers?

a. any 32-bit GP register except ESP

b. BX or BP registers

c. SI or DI registers

d. any 16-bit GP register


When the EBX register contains the base value, what alternate segments may be used to contain

data?

a. None

b. CS, SS, ES, FS, or GS

c. CS, DS, ES, FS, or GS


Which memory addressing mode instruction code addresses a 32-bit operand?

a. A1 70 30

b. 66 8B 40 10


3-145

EXERCISE PROCEDURE


2. Read the AX register. Does it contain the memory operand 83C5?

a. yes

b. no


4. What is the displacement value used to calculate the EA?

a. 83C5

b. 3070


5. What is the EA?

a. 3070

b. 0100


6. What is the logical address of the memory operand?

a. 0200:1000

b. 0100:3070


9. Read the AX register. Was the memory operand 83C5 moved into the AX register?

a. yes

b. no


10. The instruction used what type of memory operand addressing mode?

a. direct

b. based

c. register indirect


12. Read the AX register, does it contain the memory operand A3DC?

a. yes

b. no


3-146


14. What is the base value used to calculate the EA?

a. A3DC

b. 4578


15. What is the EA?

a. 4578

b. 1000



a. 0200:0050

b. 0100:4578


19. Read the AX register. Was the memory operand A3DC moved into the AX register?

a. yes

b. no



a. index

b. based



22. Read the CX register. Does it contain the memory operand AB12?

a. yes

b. no



a. 00002123

b. 00003000


3-147


25. What is the base value used to calculate EA?

a. 00000100

b. 00003000


26. What is the EA?

a. 00001000

b. 00005123



a. 0100:5123

b. 1000:2000


30. Read the CX register. Was the memory operand AB12 moved into the CX register?

a. yes

b. no



a. index

b. based



33. Read the EDX register. Does it contain the memory operand 1234ABCD?

a. yes

b. no



a. 0030

b. 0200


3-148


35. What is the base value used to calculate EA?

a. 0100

b. 3013


37. What is the index value used to calculate EA?

a. 1000

b. 0008


38. What is the EA?

a. 3051

b. 304B


39. What is the logical address of the operand?

a. 0100:304B

b. 0200:404B


42. Read the EDX register. Was the memory operand 1234ABCD moved into the EDX register?

a. yes

b. no



a. based scaled index

b. based index

c. based index with displacement


47. What is the sign-extended 16-bit displacement value of B0?

a. 00B0

b. FFB0


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50. Read the BX register. Was the memory operand 4321 moved into the BX register?

a. yes

b. no



a. index

b. based



55. What is the EA?

a. 301B

b. 3021


58. Read the DX register. Was the memory operand 89AF moved into the DX register?

a. yes

b. no



a. index

b. based index with displacement

c. based index


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REVIEW QUESTIONS


1. For 16-bit and 32-bit addressing, what value(s) can you use to compose an effective address

(EA)?

a. code and data segment selector values

b. instruction pointer and code segment selector values

c. segment selector and offset values

d. displacement, base, and index values


2. For 32-bit addressing, the base value is in what register(s)?

a. BX or BP

b. any 32-bit general purpose register except ESP

c. any 32-bit general purpose register

d. SI or DI


3. When the base value is in the BP register, what is the default segment for data?

a. SS

b. DS

c. CS

d. FS


4. The instruction MOV AX, DS:3070H uses what type of addressing mode?

a. register indirect

b. direct

c. based

d. index


5. The instruction MOV EDX, [DI+BX+0030H] uses what type of addressing mode?

a. based index

b. register indirect

c. based index with displacement

d. index


3-151

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-152

Exercise 3 – Memory Addressing Modes - II

EXERCISE OBJECTIVE

Determine the effective address of a memory operand by using displacement, base, and scaled

index values, and explain the three 32-bit memory operand addressing modes that use a scaled

index. Verify results by reading the contents of a register before and after execution of a move

(MOV) instruction.

EXERCISE DISCUSSION

No Questions

EXERCISE PROCEDURE


4. What is the index * scale value ?

a. 00000002

b. 00004000


5. What is the EA?

a. 00002002

b. 00003022


7. Read the AX register. Was the memory operand ABCD moved into the AX register?

a. yes

b. no



a. scaled index


c. based scaled index with displacement


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12. What is the index * scale value?

a. 0000000E

b. 0000502E


13. What is the EA?

a. 00002002

b. 0000102E


16. Read the AX register. Was the memory operand 6789 movedinto the AX register?

a. yes

b. no



a. scaled index




21. What is the index * scale value ?

a. 00000006

b. 00004000


22. What is the EA?

a. 00005006

b. 00004006


25. Read the AX register. Was the memory operand 3456 moved to the AX register?

a. yes

b. no


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a. scaled index

b. based scaled index


REVIEW QUESTIONS


1. What addressing mode can be used only for 32-bit addressing?

a. based index with displacement

b. based index

c. based scaled index

d. register indirect


2. For 32-bit addressing using a scaled index, what values can the scale factor have ?

a. 4, 8, or 16

b. 0, 1, 3, or 4

c. 1, 2, 4, or 8

d. 0, 8, or 32


3. In the real mode, what instruction code hexadecimal prefix must you use when applying a

scaled index in the EA calculation?

a. 66 - operand size prefix

b. 67 - address size prefix

c. 2E - CS alternate segment prefix

d. 36 - SS alternate segment prefix


4. The instruction MOV AX, [ ESI * 2 + 00001020H ] uses what type of addressing mode ?

(Click on Help to view the instruction code diagram.)

a. based index

b. scaled index


d. based index with displacement


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5. The instruction MOV AX, [ ESI * 2 + EBX + 00001020H ] uses what type of addressing

mode ? (Click on Help to view the instruction code diagram.)

a. based index with displacement

b. scaled index


d. based scaled index with displacement

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-156

UNIT TEST


What determines the physical address of the next instruction for the 80386 CPU?

a. the data segment's base address and the EA

b. the code segment's base address and the offset in the IP register

c. the addressing mode specified in the instruction code

d. the data in the EFLAGS register


What is the function of the six segment registers?

a. They contain data that specifies the six active segments in memory.

b. They contain the next six instruction codes.

c. They contain the results of arithmetic and logical operations.

d. The segment registers control operations and indicate the status of the 80386 CPU.


Where can an operand be located?

a. in an instruction

b. in memory

c. in a general purpose register



What is the purpose of the 80386 CPU addressing modes?

a. They specify the op code field of the instruction.

b. They determine the address size of the segments.

c. They specify the destination of the operand.

d. They locate an operand.


When the 80386 CPU operates in the real mode, what must the address size be?

a. 8 bits or 16 bits

b. 16 bits

c. 32 bits

d. 16 bits or 32 bits


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The instruction code MOV BX,CX uses what type of addressing mode?

a. direct

b. register operand

c. based

d. index


Which instruction code uses the based addressing mode?

a. MOV BX, [ SI + B0H ]

b. MOV AX, [ BP + 2000H ]

c. MOV AX, [ ESI * 2 + 00001020H ]

d. MOV EBX, BC47AA52


The instruction code MOV EDX, [ DI + BX + 1030H ] uses what type of addressing mode?

a. based

b. index

c. based index

d. based index with displacement


When an addressing mode uses a scale factor, how many bits must be in the address?

a. 8

b. 16

c. 32

d. Any of the above.


Which instruction code uses the based scaled index addressing mode?

a. MOV EBX, [ EDI + 4FA33B0H ]

b. MOV AX, [ ESI * 2 + EBX ]

c. MOV AX, [ ESI * 2 + 00001020H ]

d. MOV CX, [ BX + 2000H ]


3-158

32 Bit Microprocessor Unit 7 – Programming: 80386 CPU Instructions

3-159

UNIT 7 – PROGRAMMING: 80386 CPU INSTRUCTIONS

UNIT OBJECTIVE

Write instructions for the 80386 CPU with machine codes and use the instructions in memory

test programs that runs by using the 32-BIT MICROPROCESSOR circuit board.

UNIT FUNDAMENTALS


During one bus cycle, the 80386 CPU can fetch how many bytes of an instruction code?

a. 8 bytes

b. 4 bytes

c. 2 bytes


At what address does the above memory test program use a register indirect memory addressing

mode MOV instruction?

a. 04000

b. 04002

c. 04004

d. 0400B

CMS AVAILABLE

None

FAULTS AVAILABLE

None

NEW TERMS AND WORDS

machine language - a language that can be used directly by a microprocessor; a binary

language; also called object code.

EQUIPMENT REQUIRED




3-160

Exercise 1 – Instruction Formats - I

EXERCISE OBJECTIVE

Encode, into machine language, multibyte move (MOV) instructions for the * immediate

addressing mode * and register addressing modes. Verify results by executing the instructions

that you encode and by reading the contents of registers and memory locations.

EXERCISE DISCUSSION


What segment override prefix must you use to specify the ES segment as the alternate segment in

place of the default segment?

a. 2E

b. 26

c. 64


When the d bit equals 1, is the register specified by the reg field the source or the destination?

a. source

b. destination


Does the operand remain in the source location after the MOV instruction is executed?

a. yes

b. no


What mod code would you use for the based index memory addressing mode, which calculates

the effective address by adding the base and index values?

a. 00

b. 01

c. 10

d. 11


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If the data operation is 32 bits and w equals 1, what reg field code specifies the EBX register?

a. 001

b. 011

c. 110


If the data operation is 16 bits and w equals 0, what reg field code specifies the AL

register?

a. 111

b. 100

c. 000


If d equals 1, w equals 0, and reg equals 011, is the BL register the source or the destination of

the operand?

a. source

b. destination


What r/m field code specifies the DX register when mod equals 11, w equals 1, and the data

operation is 16 bits?

a. 010

b. 011

c. 001


3-162

EXERCISE PROCEDURE


For the instruction MOV CX,12ABH, what format is used?

a. IMMED TO MEM

b. IMMED TO REG

c. MEM TO ACCUM


The format for the MOV CX,12ABH instruction is shown. What fields are included in the MOV

CX,12ABH instruction? (Click on <?> to view the general instruction code format fields for the

80386 CPU.)

a. op code and displacement

b. operand size prefix, op code, and mod r/m

c. op code and immediate

d. op code, mod r/m, and immediate


1. The hex code for the instruction MOV CX,12ABH will contain how many bytes?

a. 2

b. 3

c. 4


2. What is the binary code of the first nibble (4 bits)?

a. 1101

b. 1011



3. What is the hex code for the first nibble (4 bits)?

a. 8

b. C

c. B


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4. From the table shown, what is the w bit?

a. 0

b. 1


5. From the table shown, what are the reg bits?

a. 001

b. 000

c. 011


6. What is the hex code for the second nibble?

a. 1

b. A

c. 9


7. What is the immediate operand of the instruction MOV CX,12ABH?

a. MOV

b. 12AB

c. CX12


8. For the immediate operand 12AB, what hex codes follow the first byte, B9?

a. 12 AB

b. BA 21

c. AB 12


9. What is the hex code for the mnemonic MOV CX,12ABH?

a. B9 AB 12

b. 12 AB B9

c. B9 12 AB


3-164


Read the CX register. Was the operand 12AB moved to the CX register?

a. yes

b. no


12. For the instruction MOV EBX,EDX, what format is used?

a. REG TO SEG REG

b. ACCUM TO MEM

c. REG TO REG


13. In the real mode, does the code for the instruction MOV EBX,EDX require a prefix?

a. yes

b. no


14. In the real mode, what type of prefix is required for the instruction MOV EBX,EDX?

a. instruction prefix

b. address size prefix

c. operand size prefix


15. What is the operand size hex prefix?

a. 65

b. 66

c. 67


The hex code for the instruction MOV EBX,EDX will contain how many bytes?

a. 2

b. 3

c. 4


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17. What are bits 7 to 2?

a. 100010

b. 010011



18. What is the hex code for the first nibble (4 bits) of the second byte?

a. C

b. 8

c. B


19. What is the d bit?

a. 0

b. 1

c. 0 or 1



a. 0

b. 1


22. What is the hex code for the second nibble of the second byte?

a. D

b. B

c. 9


23. From the table shown, what are the mod bits?

a. 00

b. 10

c. 11


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a. 100

b. 010

c. 011


25. What is the hex code for the first nibble of the third byte?

a. D

b. E

c. B


26. From the table shown, what are the r/m bits?

a. 001

b. 010

c. 011


27. What is the hex code for the second nibble of the third byte?

a. 2

b. A

c. C


28. What is the instruction code for the mnemonic MOV EBX,EDX?

a. DA 8B 66

b. 66 8B DA

c. 8B DA


30. The execution of the instruction code for MOV EBX,EDX should have moved (copied) the

32-bit operand BBBBAAAA from the EDX register to the EBX register. Read the EBX register.

Was the operand BBBBAAAA moved to the EBX register?

a. yes

b. no


3-167


31. If the instruction is changed to MOV EAX,EDX, making the EAX register the destination,

what are the reg bits?

a. 001

b. 000

c. 101


32. What is the new hex code for the third byte?

a. C2

b. B1

c. C4


34. The execution of the revised instruction code 66 8B C2 should have moved (copied) the 32-

bit operand BBBBAAAA from the EDX register to the EAX register. Read the EAX register.

Was the operand BBBBAAAA moved to the EAX register?

a. yes

b. no

REVIEW QUESTIONS


1. In the real mode, does the code for the above instruction require a hexadecimal prefix(s), and

if so, which of the following?

a. A hexadecimal prefix is not required.

b. 66

c. 67

d. 67 66


2. What does d bit equal to 0 mean?

a. The operand size is 8 bits.

b. The instruction code uses a register addressing mode.

c. The reg field specifies the source register.

d. The reg field specifies the destination register.


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3. What are the mod bits for the above instruction?

a. 00

b. 01

c. 10

d. 11


4. If the d and w bits equal 1 and the mod bits equal 11 (the register mode), what do the 3 bits in

the r/m field specify?

a. the effective address calculation

b. the second general-purpose register

c. a 16-bit operand

d. the destination register


5. For the above instruction, what is the hexadecimal code for the displacement?

a. ED EB 00 00 15 00

b. 00 00 15 00

c. 00 15 00 00 EB ED

d. 00 15 00 00

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-169

Exercise 2 – Instruction Formats - II

EXERCISE OBJECTIVE

Encode, into machine language, multibyte instructions used for the move (MOV) instruction

with the memory addressing modes, and understand how to format other 80386 CPU instruction

codes. Verify results by executing the encoded instructions and by reading the contents of

registers and memory locations.

EXERCISE DISCUSSION


For the instruction MOV DX,[BX + DI + 0040H], what is the r/m field code?

a. 000

b. 001

c. 011


For the instruction MOV EDX,[EBX + EDI*2], what is the r/m field code?

a. 100

b. 001

c. 111


What are the ss bits for a scale factor of 2?

a. 00

b. 01

c. 10

d. 11


3-170


What are the index bits for the EBX register?

a. 001

b. 101

c. 011


For the instruction MOV EDX,[EBX + EDI*2], what is the base field code?

a. 100

b. 010

c. 011

EXERCISE PROCEDURE


1. For the instruction MOV CX,[BX + SI + 0060H], what format is used?

a. MEM TO REG

b. ACCUM TO MEM

c. REG TO REG


2. When the 80386 CPU operates in the real mode, does the code for instruction MOV CX,[BX

+ SI + 0060H] require a prefix?

a. yes

b. no


The hex code for the instruction MOV CX,[BX + SI + 0060H] will contain how many bytes?

a. 2

b. 3

c. 4


4. What are bits 7 to 2?

a. 100010

b. 010011



3-171


5. What is the hex code for the first nibble (4 bits)?

a. C

b. 8

c. B



a. 0

b. 1

c. 0 or 1



a. 0

b. 1


8. What is the hex code for the second nibble?

a. D

b. B

c. 9



a. 00

b. 10

c. 11



a. 001

b. 010

c. 011


3-172


11. What is the hex code for the first nibble of the second byte?

a. A

b. 8

c. 9



a. 001

b. 011

c. 000



a. 9

b. A

c. 8


14. What is the hex displacement value in the instruction MOV CX, [BX + SI + 0060H]?

a. BX + SI

b. 0060

c. SI + 0060


15. For the displacement 0060H, what hex code follows the first two bytes 8B 88?

a. 00 60

b. 06 00

c. 60 00


16. What is the instruction code for the mnemonic MOV CX, [BX + SI + 0060H]?

a. 00 60 88 8B

b. 8B 88 60 00


3-173


With a base value of 3000, an index value of 0004, and a displacement of 0060, what is the EA?

a. 3604

b. 3064


19. The instruction code for MOV CX,[BX + SI + 0060H] moves the memory operand 7788 to

the CX register. Read the CX register. Was the memory operand 7788 moved to the CX register?

a. yes

b. no


20. What format is used for the instruction MOV [ECX + (EDI*2)],BX?

a. REG TO SEG REG

b. ACCUM TO MEM

c. REG TO MEM


21. In the real mode, does the code for the instruction MOV [ECX + (EDI*2)],BX require a

prefix?

a. yes

b. no


22. What type of prefix is required?

a. instruction prefix

b. address size prefix

c. operand size prefix


23. What is the address size hex prefix?

a. 65

b. 66

c. 67


3-174


The hex code for the instruction MOV [ECX + (EDI*2)],BX will contain how many bytes?

a. 2

b. 3

c. 4



a. 0

b. 1



a. 0

b. 1



a. D

b. B

c. 9



a. 00

b. 10

c. 11



a. 001

b. 010

c. 011


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a. 010

b. 101

c. 100


32. What is the hex code for the third byte?

a. 0E

b. 1C

c. 1B


33. The scaled index (EDI*2) is given in the mnemonic. What are the ss bits in the s-i-b byte?

a. 00

b. 01

c. 10


34. What are the 3 index bits?

a. 111

b. 010

c. 110


35. What are the 3 base bits?

a. 111

b. 010

c. 001


36. What is the hex code for the fourth byte?

a. C7

b. 79

c. F1


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37. What is the hex instruction code for the mnemonic MOV [ECX + (EDI*2)],BX?

a. 89 1C 79

b. 67 89 1C 79


What is the EA?

a. 00003008

b. 00003004


40. The instruction code for MOV [ECX + (EDI*2)],BX moves the operand 99CC from the BX

register to address 0100:3008 in memory. Read the data in logical address 0100:3008. Was the

operand 99CC moved to the memory location with the logical address 0100:3008?

a. yes

b. no

REVIEW QUESTIONS


1. For the above instruction, what are the mod field bits?

a. 00

b. 01

c. 10

d. 11


2. For the above instruction, what are the reg field bits?

a. 001

b. 000

c. 011

d. 111


3-177


3. For the above instruction, what are the r/m field bits?

a. 001

b. 011

c. 100

d. 111


4. For the above instruction, what are the index field bits?

a. 001

b. 010

c. 011

d. 111


5. For the above instruction, what are the base field bits?

a. 000

b. 110

c. 010

d. 001

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-178

Exercise 3 – Using the 80386 CPU Instructions - I

EXERCISE OBJECTIVE

Create a simple loop program to test a memory address by using 80386 CPU instructions. Verify

results by observing the display and/or address and data LEDs.

EXERCISE DISCUSSION


Which instruction causes the CPU to read from memory?

a. MOV DS:6050,AX

b. MOV AX,DS:6050


What is the 2's complement of hex 0C?

a. FC

b. 04

c. F4

EXERCISE PROCEDURE


3. What did the instruction MOV AX,9999H at 02000 do?

a. moved the operand in address 09999 to the AX register

b. moved the operand 9999 specified in the instruction to the AX register


4. Read the AX register. What data does it contain?

a. 9999

b. 0000

c. 0099


3-179


5. Press <EXIT>, and then press <STEP> to execute the second instruction at 02003. What did

the instruction MOV DS:6050,AX at address 02003 cause the CPU to do?

a. write the operand 9999 in the AX register to address 06050

b. read the operand at address 06050 and store it in the AX register.


6. Read the data in address 06050 (logical address 0000:6050). What 2 bytes of data does address

06050 contain?

a. 6050

b. 9999


7. Press <STEP> to execute the third instruction at 02006. What did the instruction MOV

AX,DS:6050 at address 02006 cause the CPU to do?

a. write the operand 9999 in the AX register to address 06050

b. read the operand 9999 at address 06050 and move it to the AX register.


8. What address will appear on the display after you press <STEP> to execute the instruction

JMP 2003H (EB F8) at address 02009?

a. 02003

b. 0200B

c. 02006


9. Press <STEP> to execute the fourth instruction at 02009. Did the JMP instruction return the

instruction pointer to address 02003?

a. yes

b. no


3-180


11. Set the SINGLE CYCLE switch to ON. Press the STEP switch on the SINGLE CYCLE

circuit block until 02000 appears on the address LEDs. Read only address lines A15 to A0. What

is the logic state of the W/R# line?

a. high

b. low


12. What are the four bytes of data appearing on data lines D7 to D0 (byte 0), D15 to D8 (byte

1), D23 to D16 (byte 2), and D31 to D24 (byte 3)?

a. B8 99 99 A3

b. A3 99 99 B8


13. What instruction will the CPU execute during the next bus cycle?

a. MOV DS:6050H,AX

b. None


14. Press the STEP switch once. What address appears on the address LEDs?

a. 02004

b. 02006


15. Does the logic state of the W/R# line indicate a CPU write or read operation?

a. write

b. read




a. 50 60 A1 50

b. 60 50 50 A1


3-181



a. None

b. MOV DS:6050H,AX



a. write

b. read




a. 50 CB F8 XX

b. 60 EB F8 XX



a. MOV DS:6050H,AX

b. MOV AX,DS:6050H

c. JMP 2003H



a. 06050

b. 60500



a. write

b. read


3-182


24. What are the two bytes of data appearing on data lines D7 to D0 (byte 0), and D15 to D8

(byte 1)?

a. 60 50

b. 99 99



a. JMP 2003H

b. MOV AX,DS:6050H

c. MOV AX,9999H



a. write

b. read


28. What are the two bytes of data appearing on data lines D7 to D0 (byte 0), and D15 to D8

(byte 1)?

a. 99 99

b. 60 50



a. JMP 2003H

b. MOV AX,9999H



a. 02000

b. 02003

c. 02004


3-183


31. Has the program completed one loop?

a. yes

b. no


36. With the present status of the address bus, data bus, and W/R# line, is the program in an odd

or even loop?

a. odd

b. even


37. Press the STEP switch until the W/R# line is HIGH again. What intruction is the CPU at?

a. MOV DS:[5004H],EAX - move AAAA AAAA from EAX to address 05004

b. MOV EBX,DS:[5000H] - move 5555 5555 from address 05000 to EAX


38. Press the STEP switch once. What instruction is the program at?

a. MOV EBX,DS:[5004H] - move AAAA AAAA from address 05004 to EBX

b. MOV EBX,DS:[5000H] - move 5555 5555 from address 05000 to EBX


39. Press the STEP switch until the address 05004 appears on the address bus. What instruction

is the program at?

a. JMP FCOBH - repeat the instructions starting at effective address FCOB

b. MOV EBX,DS:[5004H] - move AAAA AAAA from address 05004 to EBX


40. What instruction will be executed next?

a. JMP FCOBH - repeat the in structions starting effective address FCOB

b. MOV DS:[5000H],EAX-move AAAA AAAA from the EAX register address 05000


3-184


41. Press the STEP switch until 05000 appears on address bus and the W/R# line is HIGH. What

hex data appears on the data bus?

a. 5555 5555

b. AAAA AAAA


42. Is the program in an odd or even loop?

a. odd

b. even


46. Slowly step through the bus cycles. What does the CM affect?

a. address bus lines A7 to A0.

b. data bus lines D7 to D0

c. data bus lines D15 to D8

d. address bus lines A15 to A8.

REVIEW QUESTIONS


1. What memory address does the above loop program test? (The data segment base address is

00000.)

a. 0F0F0

b. 0B052

c. 052B0

d. 04003


2. What data does the above loop program use to test the memory address?

a. F0F0F0F0

b. 66A3B052

c. 66B8

d. EBF8


3-185


3. For how long will the above loop test program run?

a. 3 loops

b. 50 loops

c. 1000 loops

d. The program will run continuously.


4. How do you use the above program to detect a memory address fault?

a. step through each instruction

b. step through each bus cycle in the single cycle mode

c. let the program run until the fault is detected



5. Press STEP once. The W/R# signal changes to LOW. The fault is in which data bus line?

a. D3

b. D15

c. D20

d. D24

CMS AVAILABLE

CM 5

CM 14

FAULTS AVAILABLE

None


3-186

Exercise 4 – Using the 80386 CPU Instructions - II

EXERCISE OBJECTIVE

Use 80386 CPU instructions to create a program that tests a range of memory addresses. Verify

results by observing the display and/or address and data LEDs.

EXERCISE DISCUSSION


If the SI register contains 6000 and the DI register contains 6FFF, at what address will the

memory test begin?

a. 06FFF

b. 06000

c. 00000


What register contains the test data that is compared to the data in the address tested?

a. SI

b. DI

c. DL


Which loop tests each address for a specific byte of data?

a. 0400D to 04016

b. 0400B to 0401A


3-187

EXERCISE PROCEDURE


5. Press <STEP> to execute the first instruction, MOV DL,00. Read the DL register. Was hex 00

moved to the DL register?

a. yes

b. no


6. Press <EXIT>, and then press <STEP> to execute the second instruction, MOV BX,SI. Read

the BX register. Was the starting offset value 6000 moved to the BX register?

a. yes

b. no


7. Press <EXIT>, and then press <STEP> to execute the third instruction, MOV [BX],DL. This

instruction moves the contents of the DL register (00) to memory address 06000. Read address

06000. Was hex 00 moved to address 06000?

a. yes

b. no


8. Press <STEP> to execute the fourth instruction, INC BX. This instruction increments (INC)

the contents of the BX register by hex 01 from (6000 to 6001). Read the BX register. Was the

BX register incremented to 6001?

a. yes

b. no


8. At what address will the program be after you press <STEP> two times to execute CMP

BX,DI and JLE 4004H?

a. 0400B

b. 04004


3-188


10. What will occur when you press <STEP> again to execute MOV [BX],DL?

a. Hex 01 will be written (moved) to address 06000.

b. Hex 00 will be written (moved) to address 06001.


11. Press <STEP> to execute the instruction MOV [BX],DL again. Read address 06001. Was

hex 00 moved to address 06001?

a. yes

b. no


12. Press <STEP> two times so that 04009 appears in the display. When you press <STEP>

again to execute JLE 4004H, what will the program do?

a. jump back to address 04004

b. move to address 0400B


14. What will the instruction CMP DL,[BX] at address 0400D do?

a. compare the contents of address 06000 with the value in the DL register

b. read the contents of address 06000 to the DL register


16. What will the program do when you press <STEP> to execute JNE 401D at address 0400F?

a. jump to address 0401D

b. move to the next instruction at address 04011


Read address 06000. Were the contents of address 06000 incremented from hex 00 to 01?

a. yes

b. no


3-189


20. What will the program do when you press <STEP> to execute JLE 400DH at address 04016?

a. jump back to address 0400D

b. move to address 04018


What will the instruction CMP DL,[BX] at address 0400D do?

a. move the data in the BX register to the DL register

b. test the data in address 06001 for hex 00


23. What will the program do when you press <STEP> again to execute JLE 400DH at address

04016?

a. jump back to address 0400D

b. move to address 04018


25. Press <STEP> to execute INC DL at address 04018. Read the DL register. What value does

it contain?

a. 00

b. 01

c. 11


28. What does the memory test program do during the next pass through the address test loop

from addresses 0400D to 04016?

a. stops because addresses 06000 and 06001 were tested

b. tests addresses 06000 and 06001 with test data hex 01

c. increments the test data to hex 10


31. With the SI register containing 6000 and the DI register containing 6FFF, what address range

will this program test?

a. 06000 to 06FFF

b. 60000 to 6FFF0


3-190


33. What address is shown on the display when the program stops?

a. 0401D

b. 0401E


34. Did the program detect an error in address range 06000 to 06FFF?

a. yes

b. no


35. Read several addresses between 06000 and 06FFF. Address range 06000 to 06FFF contains

what hex data?

a. 10

b. 01

c. 00


39. What address is displayed?

a. 0401D

b. 0401E


40. Was there an error detected in address range 06000 to 06FFF?

a. yes

b. no


41. What register contains the offset value of the faulty address?

a. DI

b. SI

c. BX


42. Read the BX register. What value does it contain?

a. 6FCC

b. 7000


3-191

REVIEW QUESTIONS


1. What occurs during the first loop between addresses 04004 and 04009 within the memory test

program?

a. Each address is tested for hex 00.

b. The program writes hex 00 to the addresses to be tested.

c. The program loads the SI and DI registers with the starting and ending addresses, respectively.



2. The SI register contains 7500, the DI register contains 7AFF, the DS register contains 0000,

and the CS register contains 4000. What address range is tested?

a. 00000 to 07500

b. 04000 to 07AFF

c. 00000 to 04000

d. 07500 to 07AFF


3. What does the instruction CMP DL,[BX] at address 0400D cause the CPU to do?

a. compare the data in a memory address (offset in the BX register) with the test data in the

DL register

b. compare the values in the BX and DL registers

c. copy the value in the BX register to the DL register

d. write the data in a memory address (offset in the BX register) to the DL register


4. What does the instruction JNZ 400BH at address 0401A cause the CPU to do?

a. move to the next instruction if the value in the DL register is not hex 00

b. cause a jump to address 0400B if the value in the DL register is hex 00

c. cause a jump to address 0400B if the value in the DL register is not hex 00

d. reset the data in address 0400B to hex 00


3-192


5. The program stops at 0401E. The SI register contains 7500, the DI register contains 7AFF, the

DS register contains 0000, and the BX register contains 790A. What is the address of the error?

a. 0401C

b. 0790A

c. 07500

d. 07AFF

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-193

UNIT TEST


The general instruction format for the 80386 CPU contains 9 possible fields. What field always

appears in the instruction code?

a. op code

b. mod r/m

c. s-i-b

d. displacement


In the real mode, the above instruction requires which hexadecimal prefix? The operand is in the

data segment.

a. 66

b. 67

c. 2E

d. 26


What does the d bit determine?

a. the operand size

b. whether the r/m field specifies a register or memory location

c. whether the reg field specifies the source or the destination register

d. if an s-i-b byte is necessary


What are the mod bits for the above instruction?

a. 00

b. 01

c. 10

d. 11


If the operand is in memory, what do the r/m bits specify?

a. the destination operand

b. how the CPU calculates the effective address

c. the source operand

d. the register


3-194


When is it necessary to include an s-i-b byte in the instruction code?

a. with 32-bit addresses

b. with 32-bit operands

c. with scaling factors in the effective address calculation

d. with the memory addressing modes


What is the hex instruction code for the above mnemonic? Use the information provided below

and in the help window (click on Help).

a. 67 A1 B9

b. A3 A1 67

c. B1 67 A1

d. B9 A1 67


In the above loop test program, what instruction causes the CPU to read from memory?

a. MOV BX,AAAAH

b. MOV BX,DS:5070H

c. MOV DS:5070H,BX

d. JMP 3003H


In the above loop test program, what instruction causes the CPU to return to address 03003?

a. NOT BX

b. MOV BX,DS:5070H

c. MOV DS:5070H,BX

d. JMP 3003H


After the initial execution of the program's loop (the program returns to address 03003), what is

the hex data in the BX register?

a. 5555

b. AAAA

c. 5004

d. AA55

32 Bit Microprocessor Unit 8 – Troubleshooting

3-195

UNIT 8 – TROUBLESHOOTING

TROUBLESHOOTING

Location: Troubleshooting page: ttrba1, Question ID: trba1a

Does the performance check indicate that the circuit is working properly?

a. yes

b. no

Location: Troubleshooting page: ttrba2, Question ID: trba2

The fault is

a. CLK shorted to ground.

b. A1 shorted to A2.

c. MROMSEL# shorted to VCC.

d. W/R# open.

Location: Troubleshooting page: ttrbb1, Question ID: trbb1a


a. yes

b. no

Location: Troubleshooting page: ttrbb2, Question ID: trbb2

The fault is

a. ADS# shorted to VCC.

b. ADS# open.

c. RDY# shorted to VCC.

d. RDY# shorted to ground.

Location: Troubleshooting page: ttrbc1, Question ID: trbc1a


a. yes

b. no


3-196

Location: Troubleshooting page: ttrbc2, Question ID: trbc2

The fault is

a. INTR shorted to ground.

b. PPI not enabled.

c. keypad STROBE signal open.

d. CLR input of keypad one-shot (U40A) shorted to ground.

Location: Troubleshooting page: ttrbd1, Question ID: trbd1a


a. yes

b. no

Location: Troubleshooting page: ttrbd2, Question ID: trbd2

The fault is

a. RAMSEL# shorted to ground.

b. UROMSEL# shorted to VCC.

c. RESET shorted to ground.

d. CLK shorted to ground.

Location: Troubleshooting page: ttrbe1, Question ID: trbe1a


a. yes

b. no

Location: Troubleshooting page: ttrbe2, Question ID: trbe2

The fault is

a. MROMSEL# shorted to VCC.

b. BS16# shorted to VCC.

c. BS16# shorted to ground.

d. A1 shorted to A2.

Location: Troubleshooting page: ttrbf1, Question ID: trbf1a


a. yes

b. no


3-197

Location: Troubleshooting page: ttrbf2, Question ID: trbf2

The fault is

a. MRDC# shorted to VCC.

b. MWTC# shorted to VCC.

c. W/R# shorted to VCC.

d. D/C# shorted to ground.

Location: Troubleshooting page: ttrbg1, Question ID: trbg1a


a. yes

b. no

Location: Troubleshooting page: ttrbg2, Question ID: trbg2

The fault is

a. CLK shorted to ground.

b. ADS# shorted to ground.

c. RDY# shorted to VCC.

d. BE0# shorted to VCC.

Location: Troubleshooting page: ttrbh1, Question ID: trbh1a


a. yes

b. no

Location: Troubleshooting page: ttrbh2, Question ID: trbh2

The fault is

a. RESET switch n.o. contact shorted to common.

b. HALT switch n.o. contact shorted to common.

c. CLK2 shorted to ground.

d. CLK shorted to ground.


3-198

CMS AVAILABLE

None

FAULTS AVAILABLE

Fault 1

Fault 2

Fault 3

Fault 5

Fault 8

Fault 10

Fault 11

Fault 12

32 Bit Microprocessor Unit 9 – Microprocessor Applications (Optional)

3-199

UNIT 9 – MICROPROCESSOR APPLICATIONS (OPTIONAL)

NOTE: This unit is designed to work with the MICROPROCESSOR APPLICATIONS Board.

If you do not have this board and are interested in incorporating it into your curriculum, please

call your Lab-Volt representative or call 1-800-522-8658

UNIT OBJECTIVE

Demonstrate practical microprocessor applications by interfacing the 32-BIT

MICROPROCESSOR circuit board with the MICROPROCESSOR APPLICATION board.

Verify results by making observations and taking measurements.

UNIT FUNDAMENTALS


Which signals can you monitor with a logic probe?

a. ADCIN

b. DACOUT

c. PB7, PB0, and PC0



How many pulses per revolution does the encoder disc on your circuit board generate?

ppr =


Nominal Answer: 5.0







3-200


Over which signal line can the encoder output provide feedback to the microprocessor?

a. DACOUT

b. ADCIN

c. an input port bit

d. an output port bit

CMS AVAILABLE

None

FAULTS AVAILABLE

None

NEW TERMS AND WORDS

optical interrupter - an optoelectronic device with an LED and a phototransistor located on

opposite sides of an open slot. An object passing through the slot can interrupt the light beam and

cause the optical interrupter to generate output pulses.

temperature transducers - a transducer whose output is a function of its temperature.

open-loop temperature control - a form of temperature control by which a heater is activated but

no temperature information is fed back to the controlling device.

closed-loop temperature control - a form of temperature control by which a heater is activated

and its temperature is fed back to the controlling device in order to regulate temperature.

set point - the desired temperature at

which a temperature controller

is to regulate temperature.

EQUIPMENT REQUIRED


MICROPROCESSOR APPLICATION BOARD

Multimeter




3-201

Exercise 1 – Application Board Familiarization

EXERCISE OBJECTIVE

Explain the function of each circuit block on the MICROPROCESSOR APPLICATION board.

EXERCISE DISCUSSION


Which device on the microprocessor board provides the digital I/O lines?

a. PIC

b. PPI

c. DAC

d. ADC


Output bit PB7 turns the motor on or off. Which mode should be selected on the MOT header for

PB7 to operate the motor?

a. LIN

b. SWT

c. Does not matter.

EXERCISE PROCEDURE


8. Manually rotate the fan blade on the motor. Which LED is pulsing?

a. CW

b. CCW

c. ENCODER OUT


Which signal is used for the encoder output?

a. PB7

b. PB0

c. PC0


3-202


The MSB of this byte (PB7) controls the motor status (1 = on, 0 = off). What state would the

motor be in if the CPU outputs 80H as shown in the program?

a. on

b. off

c. Cannot be determined.


You can turn off the motor by clearing the PB7 bit. What byte can you enter at address 04001H

to turn off the motor?

a. 88H

b. 8FH

c. FFH

d. 00H


What happens when you execute the program?

a. PB7 switches low.

b. The motor stops running.



Why is the motor off?

a. PB7 is low.

b. The digital DAC value represents 0V.

c. The MOT shunt is in the LIN position.


20. Measure the motor voltage.

VM = Vdc


Nominal Answer: –1.5

Min/Max Value: (–1.73) to (–1.28)

Value Calculation: –1.500





3-203


What happens to the motor?

a. speed increases

b. direction changes



22. Measure the voltage across the motor.

VM = Vdc



Min/Max Value: (2.236) to (3.025)






This table shows the results of writing the two different values to the DAC. What accounts for

the change in motor direction between the first and second values?

a. the increase in voltage magnitude

b. the change in voltage polarity



What would be the result of writing the byte shown into Port B?

a. The heater would be turned fully off.

b. The heater would be turned fully on.

c. The heater would be turned partially on depending on the value of the DAC voltage.


3-204


27. Measure the ADCIN voltage.

VADCIN = V


Nominal Answer: 5.0

Min/Max VALUE: (4) to (6)






29. Observe the ADCIN voltage on the meter. The voltage is

a. decreasing.

b. increasing.

c. not changing significantly.

REVIEW QUESTIONS


1. The microprocessor board can send an analog value to the application board via the DACOUT

line to

a. switch the motor on and off.

b. switch the heater on and off.

c. control the speed of the motor.



2. Which byte can the CPU output to Port B to turn on both the heater and the fan in the SWT

mode?

a. 01H

b. 08H

c. 80H

d. 81H


3-205


3. Which control line can the microprocessor board use to switch the heater on and off?

a. PB0

b. PB7

c. PC0

d. DACOUT


4. Which circuit block on the 32-BIT MICROPROCESSOR circuit board is not used to interface

with the application board?

a. SERIAL PORT

b. PARALLEL PORT

c. POWER

d. ADC


5. The ADC shunt on the application board must be in the TEMP position in order for the

microprocessor board to

a. turn the heater on and off.

b. read the voltage that represents a temperature difference.

c. output a reference voltage to the temperature controller.


CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-206

Exercise 2 – DC Motor Control

EXERCISE OBJECTIVE

Explain and demonstrate how a microprocessor can control the speed and direction of rotation of

a small dc motor.

EXERCISE DISCUSSION


What happens when PB7 is high?

a. The motor runs full speed CW.

b. The motor runs full speed CCW.

c. The motor stops.


Which voltage would result in a higher speed?

a. –2V

b. +2V

c. Both would result in the same speed.


Why can the pulse-counting method not be used to determine direction of rotation?

a. Pulses are generated in only one direction of rotation.

b. The pulses appear the same in both directions.


3-207

EXERCISE PROCEDURE


Besides PB7, how many other outputs from port B perform a function on the application board?

a. one

b. two

c. three

d. all


The maximum speed of the motor is about 30 rps. How many pulses per second does the optical

interrupter output at maximum motor speed?

pps =

Recall Label for this Question: pps








9. Record the frequency of the resulting waveform.

f = Hz

Recall Label for this Question: f1


Min/Max VALUE: (120) to (180)






Is your measured frequency of # f1 # Hz close to your calculated value of 150 pulses per second?

a. yes

b. no


3-208


What would the DAC output be for an input of 40H?

VO(DAC) = decimal DAC value x 0.039

= V



Min/Max Value: (2.446) to (2.546)






Why is the motor stopped?

a. The microprocessor has not sent a speed value to the DAC.

b. The microprocessor sent a DAC value that corresponds to a zero speed.

c. The shunt is in LIN mode.


16. Measure the DACOUT voltage.

DACOUT = V

Recall Label for this Question: v40d


Min/Max Value: (2.246) to (2.746)






3-209


What is the op amp output for a DAC input of 40H?

VO(op amp) = (–0.0234) x (DAC input - 128)

= V

Recall Label for this Question: v40o


Min/Max Value: (1.467) to (1.527)






18. The DAC input value is still 40H. Measure the op amp output.

VO(op amp) = V



Value Calculation: # v40o #





Is your measured op amp voltage about the same as your calculated value of # v40o#V?

a. yes

b. no

* NOTE: Min/Max Values shown are based upon a calculation using the absolute

lowest and highest recall value. By using the actual input in your calculations, you

will determine the correct value.


3-210


What speed is indicated on the display?

speed = rps

Recall Label for this Question: s1


Min/Max VALUE: (9.9) to (12.1)






23. The PC0 signal is the output from the optical interrupter. Measure the frequency on the

scope.

f = Hz

Recall Label for this Question: f1a








Why are the motor rps and the optical interrupter output frequency not equal?

a. There are five black marks on the encoder disc.

b. There are four blades on the fan.

c. The motor is running too fast for the microprocessor to count all the pulses.


Why did the motor not stop when you wrote 00H to the DAC?

a. The DAC did not convert the value to an analog voltage.

b. The MOT shunt is in the LIN position.

c. The value for zero speed is not 00H.


3-211


Does the waveform on the scope have about a 50% duty cycle?

a. yes

b. no


What is the result of increasing the on-time value from 80H to FFH?

a. The motor speed increased.

b. The duty cycle increased.



What is the result of increasing the off-time value from 80H to FFH?

a. The motor speed decreased.

b. The duty cycle decreased.


REVIEW QUESTIONS


1. What line from the microprocessor board drives the motor in the LIN operating mode?

a. DACOUT

b. PB7

c. PB0

d. PC0


2. The microprocessor can determine the speed of the motor in rps from the optical interrupter

output by

a. measuring the output voltage via the ADCIN line.

b. counting the pulses in a 1-second interval.

c. counting the pulses in a 1-second interval and dividing by 5.

d. counting the pulses in a 1-second interval and multiplying by 5.


3-212


3. How can a microprocessor control a dc motor?

a. by turning the motor on and off with a single output bit

b. by sending an analog voltage to the motor via a DAC

c. by applying a square wave to the motor and varying the duty cycle to control the speed



4. This flow chart describes a micro processor program used to drive a dc motor with a square

wave. Which values written to CX in the on-time and off-time delay loops will result in a duty

cycle less than 50%?

on-time off-time

a. 08H 08H

b. 08H 80H

c. 80H 08H

d. 80H 80H


5. The microprocessor board can use the ADCIN line to

a. switch the motor fully on or fully off.

b. output an analog voltage to the motor.

c. count pulses from the optical interrupter.

d. read the voltage applied to the motor.

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-213

Exercise 3 – Temperature Control

EXERCISE OBJECTIVE

Explain and demonstrate the use of a microprocessor in open and closed-loop temperature

control applications. Verify results by loading and executing simple programs, making

observations, and taking measurements.

EXERCISE DISCUSSION


What byte can the microprocessor output to port B to turn the heater on?

a. 00H

b. 80H

c. 08H

d. None of these.


This current represents

a. the difference between room temperature and the temperature of the heater.

b. the sum of the room temperature and heater temperature.



What approximate voltage appears at the op amp's non-inverting input?

a. 5V

b. 10V

c. It depends on the output current from the transducers.


3-214

EXERCISE PROCEDURE


What type of temperature control is accomplished by this program?

a. open-loop

b. closed-loop


9. Measure the DACOUT voltage.

DACOUT = V









11. Measure the voltage at ADCIN.

ADCIN = Vdc

Recall Label for this Question: vr

Nominal Answer: 5.0







3-215


Calculate the rate of change of the op amp output voltage with temperature.

VO = (1 µA/°C) x 100 kΩ

= V/°C

Recall Label for this Question:

Nominal Answer: 0.1







If the temperature increases by 15°C, how much would the voltage change?

∆VO = V


Nominal Answer: 1.5







What temperature change is indicated by a 3.2V increase in output voltage?

∆T = °C









3-216


What happens when you run the program?

a. The HEATER ON LED turns on.

b. The ADCIN voltage increases.



15. Measure the ADCIN voltage.

ADCIN = V

Recall Label for this Question: vh


Value Calculation: # vr + 4 #





17. Calculate the difference between the voltage at room temperature and the voltage after

heating.

V = ∆VO (after heating) – VO (room temperature)

= V

Recall Label for this Question: dv


Value Calculation: # vh – vr #




* NOTE: Min/Max Values shown are based upon a calculation using the absolute lowest and

highest recall value. By using the actual input in your calculations, you will determine the correct

value.


3-217


18. Calculate the amount of temperature change during the three-minute heating period.

∆T = ∆V/(0.1 V/°C)

= °C



Value Calculation: # dv * 10 #





Which part of the operation represents temperature feedback?

a. switching the motor on and off

b. switching the heater on and off

c. reading the ADCIN voltage



22. Calculate the voltage that corresponds to B4H.

V = 180 x 0.039 V/bit

= V

Recall Label for this Question: vc1


Min/Max Value: (6.95 ) to (7.09 )





* NOTE: Min/Max Values shown are based upon a calculation using the absolute lowest and

highest recall value. By using the actual input in your calculations, you will determine the correct

value.


3-218


The motor is

a. stopped.

b. constantly turning.

c. cycling on and off.


23. Observe the ADCIN value on the voltmeter. If necessary, allow the reading to stabilize for

several more seconds. Is the ADCIN voltage on the meter close to your calculated value of # vc1

# ?

a. yes

b. no

REVIEW QUESTIONS


1. The current sensitivity of the temperature transducer is 1 µA/ºC. If the feedback resistance is

increased to 200 kΩ, what is the op amp output voltage sensitivity?

a. 0.02 V/°C

b. 0.05 V/°C

c. 0.1 V/°C

d. 0.2 V/°C


2. In a closed-loop temperature control application, the CPU reads 7FH as the digital value of

ADCIN. After heating, the value increases to EBH. How much did the temperature increase?

a. 22°C

b. 32°C

c. 42°C

d. 52°C


3. What is the approximate maximum temperature difference from room temperature that this

circuit can detect?

a. 25°C

b. 50°C

c. 75°C

d. 100°C


3-219


4. This is a portion of the program you used to demonstrate closed-loop temperature control.

Which byte can you change to alter the temperature set point?

a. E4H at address 0400F

b. 13H at address 04010

c. B4H at address 04012

d. 00H at address 04013


5. What would happen if the byte at 04010 were changed from 13H to 23H?

a. The set point is increased.

b. The set point is decreased.

c. The set point comparison is not performed.

d. The input value is not read from the ADC.

CMS AVAILABLE

None

FAULTS AVAILABLE

None


3-220

UNIT TEST


A microprocessor drives a dc motor with a square wave having a 50% duty cycle. How can the

CPU increase motor speed?

a. Increase the square wave's off-time.

b. Increase the square wave's on-time.

c. Decrease the square wave's on-time.

d. Increase the square wave's frequency.


What hex value could be written to the DAC to apply about +1.5V to the motor? (Note: Use the

digital DAC value in the equation.)

a. 20H

b. 40H

c. C0H

d. E0H


What is the function of the optical interrupter in the microprocessor motor control circuit shown?

a. feed back speed information to the microprocessor

b. feed back direction information to the microprocessor

c. regulate the motor speed



In linear motor control, a microprocessor controls speed by

a. switching the motor on and off.

b. varying the duty cycle of a square wave applied to the motor.

c. reversing the polarity of the voltage applied to the motor.

d. applying an analog voltage to the motor.


In the motor controller circuit shown in the help window (press Help), the DACOUT signal from

the microprocessor board has a 0-10V range. Op amp U5A converts the range to –3V to +3V for

what purpose?

a. to expand the range

b. to increase DAC resolution

c. to control maximum voltage and direction



3-221


Which DAC input value results in the slowest clockwise motor speed? (NOTE: Use digital DAC

value.)

a. 33H

b. 44H

c. AAH

d. BBH


7. In this circuit, the current sensitivity of the temperature transducers is 1 µA/°C. What feedback

resistance value could you select for an op amp output voltage sensitivity of 0.05 V/°C?

a. 25 kΩ b. 50 kΩ c. 100 kΩ d. 200 kΩ


In the temperature and motor controller circuits shown, what states are the heater and motor in if

the CPU writes 01H to port B?

motor heater

a. off off

b. off on

c. on off

d. on on


What byte can the CPU output to port B to turn on both the motor and heater?

a. 08H

b. 80H

c. 81H

d. 88H


For closed-loop temperature control, what function does the motor controller circuit have?

a. cool the heater

b. set a reference voltage

c. feed back speed information to the CPU

d. None


3-222

32 Bit Microprocessor Appendix A – Pretest and Posttest Questions and Answers

A-1

APPENDIX A – PRETEST AND POSTTEST QUESTIONS AND ANSWERS

Depending on configurator settings, these questions may be randomized onscreen. The pretest and posttest are the same.

1. CPU (Central Processing Unit) is another term for a(n)

a. memory chip.

b. I/O port.

c. microprocessor.

d. bus controller.

2. What type of circuit synchronizes control signals between the CPU and its support circuitry?

a. parallel port

b. bus control

c. DAC

d. ADC

3. When the 80386 CPU operates in the real mode,

a. the addressable memory space is 1 Mbyte.

b. only 20 of the 32 address lines are used.

c. any memory location can be represented by its hexadecimal five-digit physical address.


4. Which device in a microprocessor circuit accepts an analog input?

a. serial port.

b. parallel port.

c. ADC.

d. DAC.

5. An IR controller circuit manages the CPU's

a. internal registers.

b. internal ROM.

c. interrupt signals.

d. input rate.

6. Which register pair in an 80386 microprocessor always contains the address of the next

instruction that the CPU will fetch?

a. A-B

b. C-D

c. CS-IP

d. SI-DI


A-2

7. A group of eight bits transferred or operated on as a unit is called a

a. byte.

b. nibble.

c. word.

d. doubleword.

8. What 80386 CPU signal(s) can you use to identify all the types of bus states (T1, T2, Ti, or

wait)?

a. READY# only

b. ADS# only

c. ADS# and RDY#

d. address and data bus information.

9. What is the first thing the 80386 microprocessor does after a reset?

a. writes to the display

b. writes an instruction to address FFF FFF0H

c. fetches an instruction from FFFF FF0H

d. fetches an instruction from address 0000 000H

10. Every 80386 bus cycle begins when ADS# goes low and ends

a. when RDY# is low at the end of a T2 state.

b. when ADS# goes high.

c. after the next T2 state.

d. after the next wait state.

11. Which 80386 signal does not provide information about the type of bus cycle being

executed?

a. A/C#

b. M/IO#

c. W/R#

d. ADS#

12. What 80386 microprocessor signal can you use to distinguish a read cycle from a write

cycle?

a. M/IO#

b. D/C#

c. W/R#

d. any of these

13. Where does the information that the CPU writes to or reads from an external device appear?

a. on the address bus.

b. on the data bus.

c. at the status outputs.

d. at the control inputs.


A-3

14. Which group of signals does the CPU use to select the location for data to be transferred?

a. address bus

b. data bus

c. status outputs

d. control outputs

15. Which of the following would you not find on a ROM IC?

a. bidirectional data lines.

b. chip enable input.

c. output enable input.

d. address inputs.

16. Random-Access Memory (RAM) is also called

a. read-write memory.

b. read-only memory.

c. write-only memory.


17. What size group of bits can be involved in an 80386 aligned transfer?

a. byte.

b. word.

c. doubleword.

d. all of the above.

18. If 4 address bits were decoded by an address decoder, how many memory blocks could be

selected?

a. 4

b. 8

c. 16

d. 32

19. You can determine the size of each location in a memory device by the number of

a. data lines.

b. address lines.

c. control lines.

d. all of the above

20. An 80386 aligned transfer is faster than a misaligned transfer because an aligned transfer

requires

a. more data.

b. less data.

c. two bus cycles.

d. one bus cycle.


A-4

21. Images occur in an 80386 microprocessor's memory space when

a. RAM and ROM share some of the same address lines.

b. there are 16- and 32-bit memory areas.

c. the address bus is only partially decoded.

d. the address bus is fully decoded.

22. To output data from the 80386 CPU to an I/O device, what instruction must be used?

a. JMP

b. MOV

c. IN

d. OUT

23. A DAC is set to the 10V range and has a resolution of 0.039V. What is the output voltage

when 10H is written to the DAC?

a. 0.62V

b. 5V

c. 10V

d. 0.39V

24. When an 8-bit DAC is set to the 2.56V range, a change of 1 LSB on the input causes how

much voltage change on the output?

a. 0.100V

b. 0.256V

c. 0.010V

d. 0.0256V

25. A PPI (Programmable Peripheral Interface) can be used to process

a. interrupts.

b. digital input and output signals.

c. only digital input signals.

d. only digital output signals.

26. Data that is transferred in groups of several bits at once is called

a. grouped data.

b. serial data.

c. parallel data.

d. analog data.

27. What is the level for an RS-232C logic 1?

a. +5V to +15V

b. 0V

c. 5V

d. -5V to -15V


A-5

28. A serial port is used to

a. transmit serial data.

b. receive serial data.

c. transmit and receive parallel data.

d. transmit and receive serial data.

29. The 80386 CPU recognizes an external maskable interrupt

a. any time the CPU receives an INTR signal.

b. only when the IF flag is set.

c. only when the OF flag is set.

d. only when a software interrupt instruction is executed.

30. When a non-maskable interrupt occurs, the 80386 CPU uses a vector type number

a. of 02.

b. that is part of the interrupt instruction.

c. that is taken from the stack.

d. from anywhere in the range 00-FFH.

31. Which register's contents are not automatically pushed onto the stack when an 80386

interrupt occurs?

a. code segment.

b. stack pointer.

c. instruction pointer.

d. flags register.

32. When a return instruction occurs at the end of an interrupt service routine, the 80386 CPU

executes the next instruction

a. after the point at which the interrupt occurred.

b. at the beginning of the program.

c. at the beginning of the service routine.

d. at the top of the stack.

33. You can disable the 80386 CPU's recognition of maskable interrupts by

a. setting the IF bit in the flags register.

b. clearing the IF bit in the flags register.

c. changing command word ICW1.

d. changing command word ICW2.

34. Which 80386 software interrupt instruction can you use to simulate any other exception or

hardware interrupt?

a. INTn

b. INT0

c. INT3

d. all of the above


A-6

35. When an interrupt occurs, the 80386 CPU saves its place in the main program by

a. popping the CS, IP, and FLG register contents from the stack.

b. pushing the CS, IP, and FLG register contents to the stack.

c. jumping to an interrupt service routine.

d. saving status information in a register.

36. How can you determine the address at which the 80386 NMI vector is located?

a. The type of number is the same as the address.

b. Divide the type number by 4.

c. Multiply the type number by 4.

d. none of the above.

37. What is a memory segment?

a. the contents of one of the segment registers.

b. the location in memory for the next instruction.

c. the data stored in the general-purpose registers.

d. an independent region in memory space that can be assigned a specific type of data.

38. Where are the 80386 instruction pointer, segment, general-purpose, and flags registers

located?

a. in the CPU

b. it depends on the application program

c. in RAM.

d. The instruction pointer, general-purpose, and flags registers are in the CPU, and the

segment register is in RAM.

39. For 16-bit and 32-bit addressing, what values can the 80836 use to compose an effective

address (EA)?

a. code and data segment selector values

b. displacement, base, and index values

c. segment selector and offset values

d. instruction pointer and code segment selector values

40. For 32-bit addressing, the base value is in what 80386 register(s)?

a. any 32-bit general purpose register.

b. any 32-bit general purpose register except ESP.

c. BX or BP.

d. SI or DI.

41. Which 80386 addressing mode can be used only for 32-bit addressing?

a. based index with displacement.

b. based index.

c. register indirect.

d. based scaled index.


A-7

42. What is the purpose of the 80386 CPU addressing modes?

a. They specify the op code field of the instruction.

b. They determine the address size of the segments.

c. They specify the destination of the operand.

d. They locate an operand.

43. What determines the physical address of the next instruction for the 80386 CPU?

a. the data segment's base address and the EA.

b. the code segment's base address and the offset in the EIP register.

c. the addressing mode specified in the instruction code.

d. the data in the EFLAGS register.

44. For 32-bit 80386 addressing using a scaled index, what values can the scale factor have?

a. 4, 8, or 16

b. 1, 2, 4, or 8

c. 0, 8, or 32

d. 0, 1, 3, or 4

45. What does the 80386 instruction CMP DL,[BX] cause the CPU to do?

a. compare the data in a memory address (offset in the BX register) with the test data

in the DL register.

b. compare the values in the BX and DL registers.

c. copy the value in the BX register to the DL register.

d. write the data in a memory address (offset in the BX register) to the DL register.

46. When is it necessary to include an s-i-b byte in an 80386 instruction code?

a. with 32-bit addresses.

b. with 32-bit operands.

c. with the memory addressing modes.

d. with scaling factors in the effective address calculation.

47. In the 80386 real mode, what does the physical address of the next instruction code equal?

a. the IP register's offset plus the CS register's selector value

b. the FLAGS register's offset status value plus the value in the AX register

c. the AX register's value plus the CS register's selector value shifted 4 bits to the left

d. the IP register's offset value plus the CS register's selector value shifted 4 bits to the

left

48. In the 80386 real mode, what instruction code hexadecimal prefix must you use when

applying a scaled index in the EA calculation?

a. 66-operand size prefix.

b. 67-address size prefix.

c. 2E-CS alternate segment prefix.

d. 36-SS alternate segment prefix.


A-8

49. When an 80386 addressing mode uses a scale factor, how many bits must be in the address?

a. 8

b. 16

c. 32

d. any of the above

50. What does the 80386 instruction JNZ 400BH cause the CPU to do?

a. move to the next instruction if the value in the DL register is not 00H.

b. cause a jump to address 0400B if the ZF flag bit is not 0.

c. cause a jump to address 0400B if the value in the DL register is 00H.

d. reset the data in address 0400B to 00H.

32 Bit Microprocessor Appendix B – Faults and Circuit Modifications (CMs)

B-1

APPENDIX B – FAULTS AND CIRCUIT MODIFICATIONS (CMS)

CM SCHEMATIC

SWITCH NO.

FAULT ACTION

– S21 1 opens W/R path from

CPU (80386)

– S22 2 opens ADS path

from CPU (80386)

– S23 3 opens STRB path

from PPI (82C55)

– S25 5 shorts RAMS# to

ground through 39Ω

– S28 8 shorts BS16 to

ground through 39Ω

– 30 10 shorts MRDC# to

VCC through 39Ω

– 31 11 shorts RDY# to VCC

through 39Ω

– 32 12 shorts CLK to VCC

through 39Ω

2 2 – shorts KPD to

ground through 39Ω

18 18 – shorts INTA# to

ground through 39Ω

5 5 – shorts U35 CS2 ) pin

26 to ground through

39Ω

12 12 – Shorts CMSEL# to

ground through 39 Ω

13 13 – opens A18 to the

memory decoder

PLD

14 14 – opens D20 between

CPU and RAM

15 15 – Opens A9 to low

byte monitor ROM

U37, Pin 24

32 Bit Microprocessor Appendix B – Faults and Circuit Modifications (CMs)

B-2

Semiconductor Fundamentals Appendix C – Board and Courseware Troubleshooting

C-1

APPENDIX C – BOARD AND COURSEWARE TROUBLESHOOTING

Circuit Board Problems

The F.A.C.E.T. equipment is carefully designed, manufactured, and tested to assure long,

reliable life. If you suspect a genuine failure in the equipment, the following steps should be

followed to trace a problem.

A. ALWAYS insert the board into a base unit before attempting to use an ohmmeter for

troubleshooting. The schematic diagrams imprinted on the boards are modified by the

absence of base unit switch connections; therefore, ohmmeter checks will produce erroneous

results with disconnected boards. Do not apply power to the base unit when you perform

resistance checks.

B. Information describing fault switch functions is provided in Appendix B in this instructor

guide.

Courseware Problems

The F.A.C.E.T. courseware has been written to meet carefully selected objectives. All exercises

have been tested for accuracy, and information presented in discussions has been reviewed for

technical content. Tolerances have been computed for all procedure and review question answers

to assure that responses are not invalidated by component or instrument errors.

Nevertheless, you or your students may discover mistakes or experience difficulty in using our

publications. We appreciate your comments and assure you that we will weigh them carefully in

our ongoing product improvement efforts.

As we address courseware problems, we will post corrections for download from our web site,

www.labvolt.com. Select the customer support tab, and then choose product line: FACET. Select

a course, select from a list of symptoms that have been addressed, and follow the instructions.

Semiconductor Fundamentals Appendix C – Board and Courseware Troubleshooting

C-2

We will do our best to help you resolve problems if you call the number below. However, for

best results, and to avoid confusion, we prefer that you write with a description of the problem.

If you write, please include the following information:

• Your name, title, mailing address, and telephone number (please include the best time to

reach you).

• Publication title and number.

• Page number(s), and step and/or figure number(s) of affected material.

• Complete description of the problem encountered and any additional information that may

help us solve the problem.

Send your courseware comments to:

[email protected]

Lab-Volt Systems

P.O. Box 686

Farmingdale, NJ 07727

ATTN: Technical Support

If you prefer to telephone regarding hardware or courseware problems, call us between 9:00 AM

and 4:30 PM (Eastern time) at: (800) 522-4436 or (888)-LAB-VOLT.

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32-Bit Microprocessor



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Lab-Volt 32 Bit Microprocessor Instructors Guide