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LabVIEW C-RIO Hands On Session
Christian Howayek Applications Engineer- NI Arabia
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Agenda
• Introduction to Real-Time
•Configuring RT Target
•Using the Distributed System Manager
•Programming using the Scan Mode
•Programming with LabVIEW FPGA
•Communicating to Real-Time Targets
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When do I use an CRIO? Ball Bearing Video
Saw Blade Video
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Common Applications
CERN’s Large Hadron Collider
NASA James Webb Telescope
Custom Data Acquisition
Digital Communications Protocols
High Speed Control
Sensor Simulation
Onboard Signal Processing
Retinal Disease Treatment
Lexmark Ink-Jet Head Testing
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Graphical System Design • A Platform-Based Approach for Measurement and Control
PXI and Modular
Instruments
Desktops and
PC-Based DAQ RIO and Custom
Designs
Test Monitor Embedded Control Cyber Physical
Open Connectivity
with 3rd Party I/O
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FPGA
1 M or 3 M Gate
PCI Bus
CompactRIO Components
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CompactRIO Components
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Components
Custom circuitry for per
the measurement type.
Direct connection to
Industrial sensors
and actuators
Refer to ni.com for a current list of available modules
from NI and third-party vendors
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Components
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C Series I/O Modules • Analog Input
Up to 250 kS/s simultaneous sampling 4, 8, 16, and 32-ch options Built-in signal condition for
sensors • Strain gages, accelerometers,
thermocouples, RTDs
Up to 300 V, ± 60 V, ±20 mA 12, 16 and 24-bit resolution Available ch-to-ch isolation
• Analog Output Up to100 kS/s simultaneous
updating 4-ch per module 10 V, ±20 mA Isolation
• Digital I/O – Up to 30 MHz timing
– 8 and 32-channel options
– 5V/TTL, 12/24/48 V logic levels
– Available ch-to-ch isolation
• Other – 2-port CAN modules (high and low
speed)
– Brushed DC servo motor drive module
• Connector options – Screw terminal, spring terminal, BNC,
D-Sub
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A. What is Real Time?
Real Time Response: The ability to reliably and, without fail, respond to an event or perform an operation, within a guaranteed time period.
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Examples of Real-Time Applications
Event Response Closed-Loop Control Critical Tests
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Operating Systems
Processor time is shared between programs
Operating systems can preempt high priority VIs • Many programs run in the background—screen savers,
disk utilities, virus software, and so on
• It must service interrupts—keyboard, mouse, Ethernet, and so on
Cannot guarantee determinism—that is, it is a non-deterministic system
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Application Architecture
• Common RT Configurations
RT cRIO Controller
FPGA
RT VI(s)* FPGA VI
Windows User Interface
Windows
Computer
Windows VI
*Usually a Time Critical VI and a Normal Priority Communication VI
RT CompactRIO Controller
FPGA
FPGA VI
Stand alone
RT VI(s)
RT CompactRIO Controller
FPGA
FPGA VI
Stand alone
RT VI(s)
cRIO Controller
FPGA
FPGA VI
Stand alone
cRIO Controller
FPGA
FPGA VI
Stand alone
RT cRIO Controller
FPGA
FPGA VI
Windows User Interface
Windows
Computer
Windows VI
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Application Architecture
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Application Architecture
• FPGA Functions
I/O, Hardware-based timing and triggering
PCI bus communications
Low-level signal processing
Control
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Application Architecture
• Real-Time Controller Functions
FPGA interaction
• Configuring
• Communicating data
• Controlling
Processing data
Process and machine control
Logging data
Communications with remote PC host
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Application Architecture
• Windows PC Functions
Logging data
Accessing databases
Integrating with enterprise systems
Providing a human-machine (User) interface (HMI) and display
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LabVIEW Real-Time System
Execute Develop Deploy
Host Computer RT Target
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Configuring Your Hardware
Configure Network Settings
Install Software on Target
Connect to Target in LabVIEW
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Detect the Remote Target Use the Measurement & Automation Explorer (MAX) to
detect and configure your RT target
Host computer must be on the same subnet to configure RT target
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Configure Network Settings
Assign an IP address to your target using one of these methods:
• Automatically obtain an IP address
• DHCP
• Link Local
• Manually specify an IP address
• Static
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Configure Network Settings
2
3
1
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Installing Software on Target
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Exercise 1 : Configure RT Target
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Connecting to the Target in LabVIEW
• LabVIEW Project
• NI Distributed System Manager
• Programming with CompactRIO Scan Mode
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Connecting to the Target in LabVIEW
For LabVIEW to connect to the RT target you must configure the target in a project.
1. Create a project
2. Create a real-time target within the project
3. Connect to the target
4. Add VIs to the target
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LabVIEW Projects Projects manage files and
targets
Projects allow you to build executables or use source control
Targets represent systems that can run VIs
• Computer
• Real-time systems
• FPGA systems
• Mobile devices
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Adding Folders to a Project Virtual folder
• Organizes project items and does not represent files on disk
Auto-populating folder
• Adds a directory on disk to the project
• LabVIEW continuously monitors and updates the folder according to changes made in the project and on disk
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Project Libraries
Group a set of VIs, controls, and variables
• Libraries create a namespace
• Items can be public/private
• All shared variables must be in a library
Library
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Adding a Real-Time Target
Right-click the project in the Project Explorer window and selecting New»Targets and Devices
Select the type of RT target
Select a device
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Exercise 2 : Build a cRIO Project :
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Distributed System Manager
• Monitor systems on the network
• Manage published data
• Adds test panels to CompactRIO
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Demo : Configure and test I/O variable:
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Programming with CompactRIO Scan Mode
• Using the I/O Variable on the Block Diagram
Drag the I/O variable or alias from the Project Explorer window onto your LabVIEW Real-Time or host VI block diagram
Use the placed I/O variable to read from or write to the I/O channel programmatically
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Running VIs on a Target
The compiled code on the RT target and the VI on the host PC exchange data through front panel communication
Host PC RT Target
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Common RT Loop Types
• A time-critical loop (higher priority)
floating-point control
signal processing
analysis
point-by-point decision making
• Normal-priority loop (executes when time-critical loop waits)
embedded data logging
remote panel Web interface
Ethernet/serial communication
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Exercise 3: Acquire Temperature Data From an I/O Variable Creating a simple CompactRIO Scan mode VI
I/O
I/O
I/O
I/O
LabVIEW
Real-Time
I/O Scan
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Introduction to FPGA Technology
What is an FPGA? • Field programmable gate array (FPGA)
• A silicon chip with unconnected gates
• Enables user to define and re-define functionality
How does an FPGA work? • Defines behavior in software
• Compiles and download to the hardware
• Executes without OS
When is an FPGA used? • Custom hardware or ICs, replacement for ASICs
• Reconfiguration required after deployment
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Benefits of FPGA Flexibility
• Reconfigurable through software
True parallel processing • Simultaneous parallel circuits
• No CPU time sharing
High Performance (faster loops)
High Reliability and Determinism
Offload processing (Customization using off-the-shelf hardware)
Cost
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FPGA Technology
I/O Blocks
Programmable
Interconnects
Logic
Blocks
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Introduction Implements a VI that calculates a value for F from inputs A, B, C, and D where F= CD(A+B)
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True Parallelism
A
B
C
D
F E
Y W X
Z
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High Reliability and Determinism
Hard
ware
Op
erating
System
Driver A
PI
Ap
plicatio
n S
oftw
are
Calcu
lation
Decision Making in Software
~25 ms
Response
Outputs
UUT
Multiple Software Layers
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High Reliability and Determinism
Hard
ware
Op
erating
System
Driver A
PI
Ap
plicatio
n S
oftw
are
Calcu
lation
25 ns*
Response
Outputs
UUT
Decision Making in Hardware
* Faster response for
80 and 120 MHz clocks Highest Reliability
Highest
Determinism
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Do I have to learn VHDL in order to use FPGA
technology ?
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LabVIEW FPGA System
Reconfigurable I/O (RIO) Hardware
LabVIEW FPGA Module
NI-RIO Driver
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LabVIEW FPGA Module
Add-on module for LabVIEW
Develop VIs for FPGA target
Develop VIs for host PC or Real-Time interaction with FPGA
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LabVIEW FPGA: How Does it Work?
• LabVIEW VI
LabVIEW FPGA
• VHDL
Xilinx Compiler
• Bitfile
FPGA Target
User Generated
Auto Generated
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From LabVIEW to Hardware
Translation Optimization Synthesis Bit Stream
VHDL Generation Analysis
Logic Reduction
Place and Route
Timing Verification
Generation
Download / Run
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LabVIEW FPGA
Counter Analog I/O I/O with DMA
LabVIEW FPGA VHDL ~4000 lines
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LabVIEW »
LabVIEW to Hardware
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LabVIEW to Hardware LabVIEW » FPGAs »
• LabVIEW code is translated to hardware circuitry implemented on the FPGA
• Natural representation of FPGA logic
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LabVIEW to Hardware LabVIEW » FPGAs » COTS Hardware
• Use NI LabVIEW to design custom hardware circuitry with off-the-shelf devices
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Developing the FPGA VI
FPGA is fast and reliable
FPGA has limited space
FPGA RT or PC
Time critical control Data analysis
Acquisition File I/O
Timing in the FPGA User interface
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Developing the FPGA VI
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Developing the FPGA VI
• Add a VI under the FPGA target
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Developing the FPGA VI
VIs under the FPGA target inherit the FPGA Function Palette.
Many palettes are similar to LabVIEW for Windows except the FPGA I/O and FPGA Math & Analysis Palettes.
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Developing the FPGA VI
• FPGA I/O palette
Provide communication with I/O modules.
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Developing the FPGA VI
• FPGA Math & Analysis
• LabVIEW 2010
Allows for integer math and fixed-point calculations
• Keep calculations as simple as possible to preserve space on FPGA
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Developing the FPGA VI
• FPGA I/O items connect I/O to the FPGA logic
• Each FPGA I/O item has a type like analog or digital
• FPGA VIs can have multiple types of I/O items
• Refer to the I/O example VIs at NI Example Finder» Toolkits and Modules»FPGA»CompactRIO»Basic IO and Fundamentals
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Developing the FPGA VI
Digital I/O:
• Individual Lines – Boolean data type
• Ports (collection of 8 lines) – U8 data type (1 bit per line)
• Digital I/O can write or read. Disable with I/O Method Node before switching between I and O.
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I/O Types
Digital Line – Writes and/or reads Boolean value to/from digital line
Digital Port – Writes and/or reads unsigned integer value to/from digital port (grouping of digital lines)
Analog I/O – Writes or reads data to/from an analog channel
• CompactRIO – Fixed-point values
Other
• Motion
• CAN
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Fixed-Point Math
Greatly simplifies arithmetic on the FPGA
• Simplifies computations
• Size and speed advantages of integer math
Must configure the appropriate range when using fixed-point math
Limited to a maximum size of 64 bits.
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Fixed Point Terminology
Sign Encoding – The option that determines whether the fixed-point data is signed (±) or unsigned (+)
Word Length – The total number of bits used for the Fixed-Point data
Integer Word Length – The number of bits used in the integer portion of the Fixed-Point data
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Fixed-Point Context Help
Integer Word Length
Sign Encoding
Word Length
Minimum
Maximum
Delta
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Fixed Point Configuration
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Developing the FPGA VI
Place I/O Nodes from palette
or Project Explorer
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Developing the FPGA VI
• FPGA Front Panel
FPGA has limited memory
Use simple controls and indicators
Use the minimum necessary controls and indicators for programmatic Front-panel communication to a host
Add temporary controls and indicators for debugging if necessary, but remove them
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Interactive Front Panel Communication
• FPGA has no user interface
Must communicate data from FPGA to Host PC
• Requires no additional programming
Front Panel displayed on Host PC
Block Diagram executes on FPGA as compiled
Communication layer shares all control and indicator values
Cannot use debugging tools when running FPGA VI
• Test with Emulator first, or add indicators as probes
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Selecting an Execution Mode
Right-click the FPGA Target in the Project Explorer window and select Properties to launch FPGA Target Properties dialog box
Or Right-click the FPGA
Target and select Execute VI on to select mode directly
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Testing with the Development Computer
Compiling to run on the FPGA can require a few minutes to several hours
Verify logic before compiling by executing the VI on the development computer (Windows PC)
Traditional debugging tools are available
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Exercise 4: Part A- Deploy On PC Build and test an FPGA VI
• Create an FPGA VI that reads temperature from the NI 9211 and test it on the development machine before compiling.
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Compiling the FPGA VI
Click the Run button
Converts graphical code to VHDL
Generates intermediate files
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Compiling the FPGA VI
Disconnect – Disconnects from the Compile Server to continue working in LabVIEW
Run the VI again to reconnect
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Exercise 4: Part A Compile and Test an FPGA VI
• Compile and test a simple temperature
monitoring application on the FPGA.
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Developing the RT Host VI
• When designing an FPGA VI, consider communications with an RT or Windows host. Host FPGA Interface functions allow you to:
Establish and terminate communication with the FPGA.
Download, abort, reset, and run the FPGA.
Read and write data to the FPGA.
Wait for and acknowledge FPGA interrupts.
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Developing the RT Host VI
• Programmatic Front Panel Communication
Host VI
FPGA VI
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Developing the RT Host VI
• Add a VI under the cRIO target
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Developing the RT Host VI
Establish and terminate communication with the FPGA VI.
Download, abort, reset, and run the FPGA VI on the FPGA target.
Read and write data to the FPGA VI.
Wait for and acknowledge FPGA VI interrupts.
Read DMA FIFOs.
FPGA Interface Functions Palette
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Developing the RT Host VI
Opens a reference to: • the FPGA VI or
• bitfile
• and FPGA target
Must open a reference to the FPGA target before you can communicate between the host VI and the FPGA VI.
Open FPGA VI Reference
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Developing the RT Host VI
• Invokes method or action from a host VI
• Methods:
download
abort
reset
run
wait for and acknowledge interrupts,
Read/ Write DMA FIFOs
Invoke Method
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Developing the RT Host VI
Reads a value from or writes a value to a control or indicator in the FPGA VI on the FPGA target.
Read/Write Control
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Developing the RT Host VI
Stops and resets the FPGA
Right-click and select Close from the shortcut menu to close the reference without resetting
Default is Close and Reset, which closes the reference, stops the FPGA VI, and resets the FPGA
Use free label to describe functionality
Close FPGA VI Reference
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Exercise 4: Part B Build and Test a Simple RT Host VI
• Create an RT host VI that communicates
with the FPGA to monitor temperature and control sample rate
118
Which FPGA Platforms can I target with LabVIEW FPGA?
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NI CompactRIO
• Industrial Control and Monitoring
NI SingleboardRIO
• Embedded Systems
NI FlexRIO
• Manufacturing Test and Design Validation
R Series Multifunction RIO
• General Purpose I/O for Test and Control
Other
• IF-RIO
• PCIe Framegrabbers
• Compact Vision System
NI LabVIEW FPGA Hardware Targets
