Large-Scale Photonic Integration for Advanced All-Optical ...€¦ · alternative career path available when my childhood dreams of being a professional athlete and rock star (strangely)

UNIVERSITY OF CALIFORNIA

Santa Barbara

Large-Scale Photonic Integration for

Advanced All-Optical Routing Functions

A Dissertation submitted in partial satisfaction of the

requirements for the degree of

Doctor of Philosophy

in

Materials

by

Steven C. Nicholes

Committee in charge: Professor Larry A. Coldren, Co-Chair Professor Daniel J. Blumenthal, Co-Chair Professor Steven P. DenBaars Professor Arthur C. Gossard

December 2009

UMI Number: 3390764

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The dissertation of Steven C. Nicholes is approved:

________________________________________________

Professor Steven P. DenBaars

________________________________________________

Professor Arthur C. Gossard

________________________________________________

Professor Daniel J. Blumenthal, Co-Committee Chair

________________________________________________

Professor Larry A. Coldren, Co-Committee Chair

December 2009

iii

Large-Scale Photonic Integration for Advanced All-Optical Routing Functions

Copyright © 2009

by

Steven C. Nicholes

iv

To my angel wife Lisa—my better three-quarters.

v

ACKNOWLEDGMENTS

I have looked forward to writing this section of my dissertation for a long time, as

there are many people who deserve recognition for their contributions to both this

work and my sanity over the past several years. This acknowledgment section is my

chance to deliver my own version of an Academy Awards-style acceptance speech,

except there is no transition music or commercial break to cut me off if I go on for

too long. Even without that imposed time or length restriction, I am sure I will fail

to mention people who have made an impact. If you fall into that group, please

forgive my oversight.

First and foremost, I am deeply grateful to my outstanding advisors, Professors

Larry Coldren and Dan Blumenthal, for giving me the opportunity to work on an

interesting project in their research labs. I feel fortunate that Professor Coldren was

willing to take a gamble and allow me to join his research group when I was a new

and inexperienced grad student. His valuable guidance has helped me to develop as

an engineer. I also feel fortunate that Professor Blumenthal invited me to join his

group after my second year at UCSB. His enthusiastic support of my work gave me

the extra edge I needed to persevere through the rough patches.

I am also indebted to the other members of my committee, Professors Steve

DenBaars and Art Gossard. Professor DenBaars gave me the privilege to work in

the MOCVD lab, which enabled me to gain an appreciation for and an understanding

of crystal growth technologies. Professor Gossard not only taught me a great deal

vi

about solid state devices and material characterization, but also—and most

importantly—about genuine kindness and approachability.

Everyone needs a mentor when starting grad school. I was fortunate enough to

have three. In the beginning, Dr. James Raring took me under his wing and worked

tirelessly to fill my head with his 5 years worth of design, growth, and fabrication

knowledge during his final three months before he concluded his work at UCSB.

His motivation rubbed off on me and helped me to start this program on solid

footing. Next, Dr. Jon Klamkin stepped in and trained me on the skills I needed to

understand to keep the MOCVD system running. Before he concluded his Ph.D.

studies, he also showed me that my basketball abilities were not quite at the level I

thought they were. Lastly, I had the great opportunity to learn from Dr. Milan

Mašanović. Without his efforts, this dissertation work would not have been possible

(or at least would have been significantly slower). His help with design, along with

his general cleanroom know-how, made life much easier. Additionally, Dr.

Mašanović’s advocacy in my behalf ensured that I landed on projects that had a high

probability of success.

Several other people had a direct impact on this work. Biljana Stamenic bailed

me out more than once in the cleanroom and willingly lent a helping hand whenever

needed. Erica Lively gave up a day or two of her life to make gratings for me so that

my chip would lase. Demis John freely shared his initial results on low-stress

nitrides so that we could fix some problems in our process. The two Johns (Mack

and Garcia), along with Henrik Poulsen, showed me the ropes with the BERT and

vii

were (thankfully) available to fix the system after I messed it up. Yan Zheng

provided emergency x-ray services and the “magic touch” needed to fix the PL setup

on multiple occasions. Not to be forgotten, Erik Norberg logged many hours

developing processes on the Unaxis etch chamber and growing material on the

MOCVD system with me. His friendship, help and insights made those long days

filled with rotten results tolerable—even enjoyable.

I wish to also thank my other colleagues (both past and present) in the Coldren,

Blumenthal and Bowers groups. I could name names and say nice things about each

and every one of you, but at the risk of accidentally forgetting someone, I will thank

you collectively. (Of course, if you would prefer a gushingly detailed description of

why you matter to me, please send me a self-addressed stamped envelope and I

would be happy to oblige).

Moreover, this work would not have been possible without major support in the

lab. Brian Carralejo, Dr. Stacia Keller and David Whitlatch were invaluable

resources in the MOCVD lab and were always willing to help me troubleshoot the

reactor. The cleanroom staff is also first-rate, and their tireless efforts to maintain

equipment and fix tools quickly (even on weekends) benefit every cleanroom user. I

want to especially thank Tony Bosch for helping our group to get H2

I also want to acknowledge DARPA and the United States Army for funding this

work as part of the LASOR program. Furthermore, I want to acknowledge the

competent epitaxial work of the growers at LandMark Optoelectronics Corporation

installed on the

Unaxis, and for turning the tool into something that actually works.

viii

and the Alcatel III-V Lab. Landmark provided the base growth material used to

make the MOTOR chip. The III-V Lab provided both the regrowth for the MOTOR

chip and also the CBE material considered in this dissertation.

My family has also been a terrific support throughout this process. I am grateful

to my dad for sparking my interest in science when I was a toddler, so that I had an

alternative career path available when my childhood dreams of being a professional

athlete and rock star (strangely) did not materialize. I am thankful to my mother for

her consistent love and support, which did not falter even when (as a teenager) I

decided to use permanent black dye on my light brown hair before my high school

prom. Thanks also goes to my in-laws who looked past my temporarily jet black

hair when I arrived to escort their daughter to the high school prom, and who have

always shown genuine interest in my work. They have been among my biggest

cheerleaders. I am also grateful for great siblings and in-law siblings who have

shown their support along the way.

Last, but certainly not least (in fact, most importantly), I wish to express my

gratitude and thanks to my angel wife, Lisa. She is my best friend and has been by

my side since our days as high school sweethearts. In fact, were it not for her

willingness to sacrifice her own professional opportunities, I could never have come

to UCSB. I will forever marvel at her selflessness. Lisa’s encouragement gave me

strength when experiments failed or equipment broke (which was usually daily). At

the end of a hard day, she gave me reason to laugh, smile, and enjoy life. Her love

inspires me to do better and to be better. Thank you for marrying me.

ix

VITA OF STEVEN C. NICHOLES

PERSONAL December 9, 1979 Born Provo, Utah EDUCATION April 2005 B. S. Chemical Engineering Brigham Young University Provo, Utah December 2009 Ph. D. Materials University of California, Santa Barbara AWARDS

Micron Graduate Scholar: 2006–2008 Micron Scholar: 2003–2005

PROFESSIONAL EMPLOYMENT April 2005–Aug. 2005 / May 2004–Aug. 2004

Engineering Intern Micron Technology, Boise, Idaho

PUBLICATIONS [1] S. C. Nicholes, M. L. Mašanović, B. Jevremović, E. Lively, L. A. Coldren,

and D. J. Blumenthal, “Large-Scale Photonic Integration for Advanced All-Optical Routing Functions,” scheduled for presentation at Integrated Photonics Research, Silicon and Nano Photonics, July 2010 (invited).

[2] S. C. Nicholes, M. L. Mašanović, B. Jevremović, E. Lively, L. A. Coldren, and D. J. Blumenthal, “Integration technologies for an 8x8 InP-based monolithic tunable optical router with 40Gb/s line rate per port,” scheduled for presentation at International Conference on Indium Phosphide & Related Materials, May/June 2010 (invited).

[3] S. C. Nicholes, M. L. Mašanović, B. Jevremović, E. Lively, L. A. Coldren, and D. J. Blumenthal, “An 8x8 InP Monolithic Tunable Optical Router (MOTOR) Packet Forwarding Chip,” accepted for publication in IEEE Journal of Lightwave Technology, Jan/Feb 2010.

[4] E. J. Norberg, R. S. Guzzon, S. C. Nicholes, J. S. Parker and L. A. Coldren “Programmable Photonic Lattice Filters in InGaAsP/InP,” accepted for publication in an upcoming issue of IEEE Photonics Technology Letters.

x

[5] C.-H. Chen, J. Klamkin, S. C. Nicholes, L. A. Johansson, J. E. Bowers, and L. A. Coldren, “Compact Beam Splitters with Deep Gratings for Miniature Photonic Integrated Circuits: Design and Implementation Aspects,” Applied Optics, 48, F68-F75, Sept. 2009.

[6] S. C. Nicholes, M. L. Mašanović, E. Lively, L. A. Coldren, and D. J. Blumenthal, “An 8x8 Monolithic Tunable Optical Router (MOTOR) Chip in InP,” presented at Integrated Photonics and Nanophotonics Research and Applications Conference, paper no. IMB1, July 2009.

[7] S. C. Nicholes, M. L. Mašanović, J. Barton, E. J. Norberg, E. Lively, B. Jevremović, L. A. Coldren, and D. J. Blumenthal, “Novel Application of Quantum Well Intermixing Implant Buffer Layer to Enable High-Density Photonic Integrated Circuits in InP,” presented at International Conference on Indium Phosphide & Related Materials, paper no. WB1.2, May 2009.

[8] E. J. Norberg, R. S. Guzzon, S. C. Nicholes, J. S. Parker and L. A. Coldren, “Programmable Photonic Filters Fabricated With Deeply Etched Waveguides,” presented at International Conference on Indium Phosphide & Related Materials, paper no. TuB2.1, May 2009.

[9] S. C. Nicholes, M. L. Mašanović, B. Jevremović, E. Lively, L. A. Coldren, and D. J. Blumenthal, “The World’s First InP 8x8 Monolithic Tunable Optical Router (MOTOR) Operating at 40 Gbps Line Rate per Port,” presented at postdeadline session of Optical Fiber Communication Conference, paper no. PDPB1, Mar. 2009.

[10] M. L. Masanovic, E. Burmeister, M. M. Dummer, B. Koch, S. C. Nicholes, B. Jevremovic, K. Nguyen, V. Lal, J. E. Bowers, L. A. Coldren, and D. J. Blumenthal, “Advanced photonic integrated technologies for optical routing and switching,” presented at SPIE Photonics West Conference, Proc. SPIE 7219, 72190I, Jan. 2009 (invited).

[11] S. C. Nicholes, J. W. Raring, E. J. Norberg, C. S. Wang, M. M. Dummer, S. P. DenBaars, L. A. Coldren, “Highly Polarized Single-Chip ELED Sources Using Oppositely Strained MQW Emitters and Absorbers,” IEEE Photonics Technology Letters, vol.20, no.14, pp.1267-1269, July 2008.

[12] S. C. Nicholes, J. W. Raring, M. Dummer, A. Tauke-Pedretti, L. A. Coldren, “High-Confinement Strained MQW for Highly Polarized High-Power Broadband Light Source,” IEEE Photonics Technology Letters, vol.19, no.10, pp.771-773, May 2007.

xi

ABSTRACT

Large-Scale Photonic Integration for

Advanced All-Optical Routing Functions

by

Steven C. Nicholes

Advanced InP-based photonic integrated circuits are a critical technology to manage

the increasing bandwidth demands of next-generation all-optical networks.

Integrating many of the discrete functions required in optical networks into a single

device provides a reduction in system footprint and optical losses by eliminating the

fiber coupling junctions between components. This translates directly into increased

system reliability and cost savings. Although many key network components have

been realized via InP-based monolithic integration over the years, truly large-scale

photonic ICs have only recently emerged in the marketplace. This lag-time has been

mostly due to historically low device yields.

In all-optical routing applications, large-scale photonic ICs may be able to

address two of the key roadblocks associated with scaling modern electronic routers

to higher capacities—namely, power and size. If the functions of dynamic

wavelength conversion and routing are moved to the optical layer, we can eliminate

the need for power-hungry optical-to-electrical (O/E) and electrical-to-optical (E/O)

data conversions at each router node. Additionally, large-scale photonic ICs could

xii

reduce the footprint of such a system by combining the similar functions of each port

onto a single chip. However, robust design and manufacturing techniques that will

enable high-yield production of these chips must be developed.

In this work, we demonstrate a monolithic tunable optical router (MOTOR) chip

consisting of an array of eight 40-Gbps wavelength converters and a passive arrayed-

waveguide grating router that functions as the packet-forwarding switch fabric of an

all-optical router. The device represents one of the most complex InP photonic ICs

ever reported, with more than 200 integrated functional elements in a single chip.

Single-channel 40 Gbps wavelength conversion and channel switching using 231-1

PRBS data showed a power penalty as low as 4.5 dB with less than 2 W drive power.

Furthermore, this work presents: (1) our large-scale integration strategy, which was

designed to achieve high component yield; and (2) several techniques that were

developed to improve device performance without significantly increasing

fabrication or epitaxial growth complexity.

xiii

CONTENTS

Acknowledgments……………………………………………………………………v

Vita of Steven C. Nicholes…………………………………………………………..ix

Abstract…...…………………………………………………………………………xi

List of Figures…………………………………………………………………….xviii

List of Tables…………………………………………………………………….xxvii

Chapter 1 Introduction ............................................................................................. 1

1.1 All-Optical Packet Switching .......................................................... 2

1.1.1 Core Technologies ..................................................................... 4

1.1.2 Packet Switching Fabrics .......................................................... 5

1.2 Benefits of Photonic Integration ...................................................... 7

1.3 Preview of Dissertation .................................................................... 9

References….…………………………………………………………….11

Chapter 2 Large-Scale Photonic Integration: Background and Challenges ..... 13

2.1 The Need for Large-Scale Photonic Integration ............................ 14

2.2 Large-Scale Photonic Integration: Metrics and Considerations ... 16

2.2.1 Component Count .................................................................... 18

2.2.2 Device Yield ............................................................................ 20

2.2.3 Managing Component Diversity: Integration Platform

Choices .................................................................................... 24

2.3 Prior State of the Art ...................................................................... 28

2.3.1 Single-Channel Photonic Integrated Circuits .......................... 28

2.3.2 Multi-Channel Photonic Integrated Circuits ........................... 30

2.4 Development of a Monolithic Tunable Optical Router ................. 31

2.4.1 Core Functionality and Key Device Building Blocks ............. 32

2.4.2 Summary of Integration Challenge ......................................... 34

xiv

2.5 Chapter Summary .......................................................................... 35

References ................................................................................................ 37

Chapter 3 Integration Strategy .............................................................................. 41

3.1 General Integration Strategy used in this Work ............................. 42

3.2 General Integration Platform: Centered MQW Structure and

Quantum Well Intermixing ........................................................... 45

3.2.1 Base Structure Implementation ............................................... 45

3.2.2 QWI for Active/Passive Definition ......................................... 48

3.2.3 Cladding Regrowth Implementation ....................................... 54

3.3 Waveguide Architectures ............................................................... 55

3.3.1 Common Waveguide Architectures ........................................ 56

3.3.2 Waveguide Architectures Used in This Work ......................... 60

3.4 New Application of QWI Implant Buffer Layer for Lower Loss .. 61

3.4.1 Free-Carrier Absorption Loss in p-Type InP ........................... 61

3.4.2 Application of UID Implant Buffer Layer for Lower-Loss

Waveguides ............................................................................. 63

3.4.3 Implant Buffer Layer Quality for Regrowth ........................... 64

3.4.4 Effect of Implant Buffer Layer on Passive Loss ..................... 69

3.5 Chapter Summary .......................................................................... 72

References….…………………………………………………………….74

Chapter 4 Design Considerations for a Monolithic Tunable Optical Router .... 77

4.1 Wavelength Converter Array ......................................................... 77

4.1.1 Operational Principles ............................................................. 78

4.1.2 SG-DBR Laser Design ............................................................ 83

4.1.3 SOA Design ............................................................................. 85

4.1.4 Differential Delay Line ............................................................ 88

4.2 Arrayed-Waveguide Grating Routers ............................................ 89

xv

4.2.1 Operational Overview ............................................................. 90

4.2.2 General Design Parameters ..................................................... 92

4.2.3 Buried Rib Design ................................................................... 95

4.2.4 Practical Considerations .......................................................... 99

4.3 Passive Interconnects ................................................................... 103

4.3.1 MMI Splitters and Combiners ............................................... 103

4.3.2 Waveguide Transition Elements ............................................ 105

4.4 Chapter Summary ........................................................................ 109

References….…………………………………………………………...111

Chapter 5 Epitaxial Growth ................................................................................. 113

5.1 Epitaxial Growth Options ............................................................ 113

5.2 MOCVD at UCSB ....................................................................... 118

5.2.1 Reactor System ...................................................................... 118

5.2.2 Metal-Organic Precursors and Other Sources ....................... 120

5.3 Determination of Layer Properties and Growth Parameters ........ 121

5.3.1 Material Parameter and Flow Calculations ........................... 122

5.3.2 MOCVD Calibration Procedure ............................................ 125

5.4 Base Growth Considerations ....................................................... 130

5.5 Cladding Regrowth Considerations ............................................. 131

5.5.1 Zn Doping Profile .................................................................. 132

5.5.2 Conditions to Bury Non-Planar Features .............................. 135

5.6 Chapter Summary ........................................................................ 137

References….…………………………………………………………...139

Chapter 6 Device Fabrication and Process Improvements ............................... 141

6.1 Migration to 2” Wafers ................................................................ 141

6.2 Fabrication Overview .................................................................. 142

6.3 Grating Formation ........................................................................ 144

xvi

6.4 Waveguide Fabrication ................................................................ 145

6.4.1 Traditional RIE CH4/H2 /Ar Approach .................................. 146

6.4.2 Development of ICP Cl2/H2 /Ar Approach ............................ 148

6.4.3 Hard Mask Development ....................................................... 155

6.4.4 Summary of Surface Ridge and Deeply Etched Waveguide

Definition .............................................................................. 158

6.4.5 Rib Waveguide Etch .............................................................. 160

6.5 Unintentional Intermixing due to Dielectric Film Stress ............. 162

6.6 Chapter Summary ........................................................................ 171

References….…………………………………………………………...172

Chapter 7 Device Results ...................................................................................... 174

7.1 Experimental Procedure ............................................................... 174

7.1.1 Sample Mounting .................................................................. 174

7.1.2 Test Equipment Setup ............................................................ 175

7.2 Arrayed-Waveguide Grating Router Performance ...................... 177

7.2.1 Static Characteristics ............................................................. 177

7.2.2 Demonstration of Channel Switching ................................... 181

7.3 Wavelength Conversion and Routing .......................................... 183

7.3.1 Mach-Zehnder Interferometer Performance .......................... 183

7.3.2 10 Gbps NRZ Wavelength Conversion ................................. 184

7.3.3 40 Gbps RZ Wavelength Conversion .................................... 187

7.4 Multi-Channel Considerations ..................................................... 193

7.5 Power Consumption Considerations ............................................ 194

7.6 Yield Considerations .................................................................... 195

7.7 Chapter Summary ........................................................................ 196

References….…………………………………………………………...199

xvii

Chapter 8 Summary and Future Directions ....................................................... 200

8.1 Summary of Dissertation ............................................................. 200

8.1.1 Integration and Processing Technologies .............................. 200

8.1.2 Device Results ....................................................................... 204

8.2 Future Directions ......................................................................... 205

8.2.1 1.28 Tbps Capacity 16 x 16 MOTOR Design ....................... 205

8.2.2 Improved Preamplifier Design .............................................. 211

8.2.3 10 Gbps Label Writing Capability ........................................ 213

8.2.4 Packaging Options for Multi-Channel Operation .................. 215

8.2.5 Polarization Sensitivity .......................................................... 216

8.2.6 Further Study of Cl2/H2 Etch Chemistry .............................. 220

References….…………………………………………………………...221

xviii

LIST OF FIGURES

Fig. 1.1 Overall LASOR architecture. PED = payload envelope detection; CDR = clock data recovery; Deser = deserializer; Sync = synchronizer; WC = wavelength converter; AWGR = arrayed-waveguide grating router; 3R = retiming, reshaping, and reamplification. ............................................................. 3

Fig. 1.2 Schematic of a crossbar switch fabric connected to ingress and egress line cards. ..................................................................................................................... 5

Fig. 1.3 Schematic of the 8-input, 8-output monolithic tunable optical router (MOTOR) chip. ..................................................................................................... 9

Fig. 2.1 Total device (red and yellow bars) and per channel (yellow bar only) functional component density over time for several PICs. ................................. 17

Fig. 2.2 Two implementations of a Mach-Zehnder switch with differing levels of fabrication complexity and functionality. ........................................................... 18

Fig. 2.3 Qualitative illustration of the relationship between device complexity and fabrication complexity and the associated manufacturing risk. .......................... 23

Fig. 2.4 Summary of popular integration platforms: (a) offset quantum well; (b) dual quantum well; (c) quantum-well intermixing; (d) butt-joint regrowth; (e) selective-area growth; and (f) asymmetric twin-waveguide. .............................. 24

Fig. 2.5 (a) Schematic of overall MOTOR chip; (b) Expanded view of a single input wavelength converter showing several key device elements. ............................. 32

Fig. 2.6 Summary of MOTOR integration challenge. The box on the upper left lists the key components used in the device and their most important active (purple) and/or passive (maroon) attributes. ..................................................................... 35

Fig. 3.1 Integration platform used in this work. (a) Epitaxial structure of the initial base growth with an MQW region centered within a quaternary waveguide. (b) Epitaxial structure of the completed device showing both active and passive regions achieved through QWI and the cladding regrowth. ............................... 43

Fig. 3.2 Band diagram for c-MQW In(x)Ga(1-x)As(y)P(1-y)

46

active region showing the lowest energy transition from the conduction band (C1) to the heavy hole band (HH1). .................................................................................................................

xix

Fig. 3.3 Index profile of waveguide and MQW region (blue) with the normalized optical mode profile superimposed (green). ........................................................ 47

Fig. 3.4 Effect of QWI process on MQW region: (a) shows the change in band edge energy as the Group V elements diffuse between well and barrier for several diffusion lengths. (b) shows the expected shift in PL wavelength versus diffusion length. .................................................................................................. 51

Fig. 3.5 Summary of quantum-well intermixing processing steps. ............................ 53

Fig. 3.6 PL wavelength shift for c-MQW base structure showing three distinct band edges on the sample (Blue = Active, Green = Intermediate Band Edge; Red = Passive Band Edge). ............................................................................................ 53

Fig. 3.7 Overall band diagram for the MOTOR device, including the initial base growth (with n-type and intrinsic regions) and the p-type cladding regrowth. ... 54

Fig. 3.8 Popular waveguide architectures demonstrated previously in InP: (a) surface ridge waveguide; (b) shallow-etched ridge waveguide; (c) deeply-etched ridge waveguide; (d) buried rib waveguide; and (e) buried channel waveguide. .......................................................................................................... 55

Fig. 3.9 Ridge architectures used in MOTOR: Images (a), (b), (c) show schematic cross-sections of epitaxial layers with the optical mode power contours superimposed on top for surface ridge, deeply-etched ridge, and buried rib, respectively. Images (d), (e), (f) show corresponding SEM cross sections for surface ridge, deeply-etched ridge, and buried rib, respectively. ........................ 60

Fig. 3.10 Modified quantum-well intermixing processing steps. The base structure growth now ends with a 200 nm UID InP layer to protect the surface of the implant buffer layer. After QWI, the buffer protection layer is removed by wet etch everywhere, and the implant buffer layer is wet etched in active regions only. The UID implant buffer layer is then buried by the cladding regrowth. .. 64

Fig. 3.11 AFM roughness scans for the surface of Sample A for: (a) the as-grown base structure; and (b) the same structure after regrowth with no processing steps after the initial growth. ............................................................................... 65

Fig. 3.12 AFM scans after regrowth for: (a) Sample B—implant with no anneal; and (b) Sample C—implant and anneal. .................................................................... 66

xx

Fig. 3.13 Representative AFM scans after the following wet etches: (a) 3:1 H3PO4:HCl etch of the InP implant buffer layer; and (b) 1:1:10 H2SO4:H2O2 67:DI etch of the quaternary stop etch layer. ....................................

Fig. 3.14 SIMS profile for (a) Sample A and (b) Sample B. Sample A contains an extra 1.3Q stop etch layer because the regrowth was performed on the as-grown sample without removing the upper UID InP buffer protection layer. No difference in diffusion depth is seen between the samples. ................................ 68

Fig. 3.15 Cross section of waveguide structure with optical mode power contours superimposed for: (a) the deeply-etched waveguide; and (b) the buried rib waveguide. .......................................................................................................... 70

Fig. 3.16 Effect of the implant buffer layer thickness on the free-carrier absorption loss due to Zn doping in a buried rib and a deeply-etched waveguide (model assumes no Zn diffusion). A significant reduction in loss is expected for our 450 nm buffer layer. ............................................................................................ 71

Fig. 3.17 Differential efficiency versus the length of a passive surface ridge waveguide. The passive loss is determined by fitting the points to a curve as described in [5]. ................................................................................................... 72

Fig. 4.1 Schematic layout of SOA-based MZI wavelength converter. ...................... 79

Fig. 4.2 Response of the SOA gain and MZI phase when a pump pulse is input to a nonlinear SOA in the MZI (adapted from [1] and [6]). ...................................... 79

Fig. 4.3 (a) Schematic diagram of SG-DBR laser structure (active regions shown in blue). (b) Overlay of several SG-DBR lasing spectra, demonstrating the wide tunability of the device (courtesy of Dr. James Raring). .................................... 83

Fig. 4.4 Simulated large-signal gain curve for a c-MQW SOA (adapted from [10]). 87

Fig. 4.5 Differential delay line: (a) optical microscope image; (b) SEM image. ....... 89

Fig. 4.6 Schematic illustration of an N x N AWGR. ................................................. 90

Fig. 4.7 Wavelength-based routing pattern for an 8 x 8 AWGR (adapted from [16]). The ports are represented by letters and the wavelength channels are represented by numbers. ...................................................................................... 91

Fig. 4.8 Layer structure and optical mode contours for the buried rib waveguide design. ................................................................................................................. 96

xxi

Fig. 4.9 (a) Effective index contrast versus the rib height (or etch depth). The thickness of the implant buffer layer above the waveguide is not included in this plot. (b) Simulated crosstalk versus rib height. The waveguide layers (light green) and MQW region (yellow) are also depicted. .......................................... 97

Fig. 4.10 Excitation of higher order modes due to a tapering waveguide versus the taper length. ......................................................................................................... 98

Fig. 4.11 Simulated transmission for each input/output port combination an 8 x 8 AWGR. .............................................................................................................. 100

Fig. 4.12 Effect of random phase errors in the arrayed waveguides on the output spectral response. .............................................................................................. 101

Fig. 4.13 Several possible layouts for our AWGR. .................................................. 102

Fig. 4.14 Effect of MMI width and length on the splitting ratio for: (a) 1 x 2 configuration; and (b) 2 x 2 configuration. The optical power as it propagates through the MMI is also shown for each case. .................................................. 104

Fig. 4.15 Mode profiles for the various waveguide architectures in MOTOR: (a) surface ridge; (b) deeply-etched ridge; and (c) buried rib. ................................ 106

Fig. 4.16 SEM images of the “mode-matching” transition between the surface and deeply-etched waveguides (top view on left and side view on right). .............. 107

Fig. 4.17 Coupling efficiency from surface to deeply-etched waveguide as a function of the distance between the waveguide flare and the start of the deeply-etched section (zero on the graph represents the position of the waveguide flare.107

Fig. 4.18 Optical microscope image of surface ridge to buried rib butt-couple transition. ........................................................................................................... 109

Fig. 4.19 Coupling efficiency of our flared/tapered butt-couple transition between surface ridge and buried rib waveguides: (a) tolerance to lateral misalignment; and (b) tolerance to axial misalignment (zero represents perfect axial alignment of the surface ridge and buried rib waveguides). .............................................. 109

Fig. 5.1 Possible reaction pathways for MOCVD constituents. Figure is adapted from MATRL 227 class notes. .......................................................................... 115

Fig. 5.2 PL wavelength wafer map for (a) CBE-grown epi and (b) MOCVD-grown epi. ..................................................................................................................... 116

xxii

Fig. 5.3 Atomic force microscopy scan of the as-grown surface of: (a) CBE-grown epi; and (b) MOCVD-grown epi. The step-like pattern in (b) is due to a 0.2° miscut in the substrate surface. ......................................................................... 117

Fig. 5.4 Thomas Swan horizontal MOCVD reactor design. .................................... 119

Fig. 5.5 MOCVD growth and material parameter calculator. .................................. 125

Fig. 5.6 (a) X-ray scan of MQW sample showing both the raw scan data and a fit of that data using a thorough model of the layer structure. (b) PL measurement for the same sample. ............................................................................................... 126

Fig. 5.7 SIMS analysis of a Si doped calibration sample. ........................................ 129

Fig. 5.8 SIMS analysis of external cladding regrowth. Clearly, the Zn concentration falls off to low levels before reaching the waveguide layer. ............................. 134

Fig. 5.9 Comparison of growth over non-planar rib waveguide sections for (a) in-house regrowth conditions and (b) external vendor regrowth conditions. ........ 136

Fig. 6.1 Photograph of full MOTOR wafer before the QWI step. A single chip is highlighted in the black box. ............................................................................. 142

Fig. 6.2 Typical AFM scans for various stages of the e-beam grating process: (a) patterned resist; (b) patterned SiO2

145; and (c) the finished grating etched into

semiconductor. ..................................................................................................

Fig. 6.3 SEM image of (a) the adiabatic taper transition from surface-to-deep ridge and (b) the sidewall of a deeply etched waveguide. Figures courtesy of Dr. Milan Mašanović. .............................................................................................. 147

Fig. 6.4 Initial ICP screening experiment. The flow ratios are given for each SEM. Other reaction conditions are given as follows: Total flow = 21 sccm; P = 1.5 mTorr; PICP = 800 W; PRIE 150 = 125W. .................................................................

Fig. 6.5 Close-up image of the etched sidewall using a gas flow ratio of 4:6 Cl2:H2

152

. The images show that the quaternary layer in this sample did not undercut, but an undesirable ledge forms near the top of the waveguide due to mask erosion.

Fig. 6.6 Effect of ICP power on ridge profile (4:6 Cl2:H2153

; Total flow = 21 sccm; P = 1.5 mTorr; 210” etch time). ...............................................................................

xxiii

Fig. 6.7 Effect of RIE power on ridge profile (4:6 Cl2:H2154

; Total flow = 21 sccm; P = 1.5 mTorr; 210” etch time). ...............................................................................

Fig. 6.8 SEM images of a deeply-etched waveguide that was defined with poor-quality hard mask: (a) top view shows that the waveguide is very wavy and rough; (b) cross section shows a mask with poor adhesion where wet chemicals crept under the mask and etched the ridge. ....................................................... 155

Fig. 6.9 SEM images of: (a) a trapezoidal resist mask used to define a 400-nm oxide mask; and (b) a 50-nm Cr mask with straight sidewalls (sample etched in a Panasonic ICP chamber with: 23.25 sccm Cl2 and 6.75 sccm O2; PICP = 500 W; PRF 156= 15 W; and P = 1.37 Pa). ..........................................................................

Fig. 6.10 Cross-sectional images of the oxide profile using Cr as a hard mask and: (a) CHF3

157-based etching; and (b) SF6-based etching. Images courtesy of John

Parker. ...............................................................................................................

Fig. 6.11 Process steps used to define surface and deeply-etched ridge sections in MOTOR. ........................................................................................................... 159

Fig. 6.12 Final ridge waveguide using our new ICP etch process: (a) shows the transition between surface and deeply-etched ridge; and (b) shows the resulting smooth sidewall in the deeply-etched region. ................................................... 160

Fig. 6.13 (a) Cross section and (b) sidewall profile of the rib waveguide using MHA RIE-based etch chemistry. ................................................................................ 161

Fig. 6.14 (a) PL spectra for the non-implanted active region of MQW base structure grown by CBE before and after QWI. An unintentional shift in wavelength of ~30 nm is observed for a 350 second anneal. (b) Variation in PL wavelength across a larger region of the CBE sample. ........................................................ 162

Fig. 6.15 (a) 10 MQW base structure grown by CBE. (b) High-stress nitride experiment: Sample #1 was encapsulated with 40 nm nitride and annealed; Sample #2 had 500 nm nitride deposited on the implant buffer layer, the nitride was removed in HF, and the sample was encapsulated in 40 nm nitride and annealed; Sample #3 was first wet etched in 3:1 H3PO4

165

:HCl to remove the implant buffer layer, then 500 nm of nitride was deposited just above the waveguide, the nitride was removed in HF, and the sample was encapsulated in 40 nm nitride and annealed. ..............................................................................

Fig. 6.16 Peak PL wavelength shift versus anneal time for non-implanted CBE-grown samples (see Fig. 6.15b). ........................................................................ 166

xxiv

Fig. 6.17 Atomic force microscopy scan of the as-grown surface of the (a) CBE-grown epi and (b) MOCVD-grown epi used in this work. ............................... 167

Fig. 6.18 Effect of N2 flow on intrinsic stress level in SixNy168

film. (Data collected by Abirami Sivananthan). .................................................................................

Fig. 6.19 Peak PL wavelength shift versus anneal time for CBE-grown samples masked with high- or low-stress nitride films without an implant. The sample with exposure to only the low-stress nitride showed essentially no intermixing.170

Fig. 7.1 Experimental test setup and mounting configuration for MOTOR characterization. ................................................................................................ 175

Fig. 7.2 Schematic of BER test setup. Key to abbreviations: EOM = electro-optic modulator; EDFA = erbium-doped fiber amplifier; VOA = variable optical attenuator; BPF = band-pass filter; PC = polarization controller; PD = photodiode; BERT = bit error rate tester. .......................................................... 176

Fig. 7.3 Output ASE response of the integrated AWGR: (a) measured optical output from all output ports using the MZI SOAs of input wavelength converter #3; (b) measured optical output from output port #2 using the MZI SOAs of each input wavelength converter. ....................................................................................... 177

Fig. 7.4 Layout of power monitor (PM) pads within the MZI. ................................ 180

Fig. 7.5 (a) Lasing spectra for different biasing conditions using the SG-DBR of input wavelength converter #3, measured from output port #1. (b) Demonstration of channel-switching from a single input port to any output port by tuning the SG-DBR mirror biases. ............................................................... 182

Fig. 7.6 MZI transfer function for: (a) a constant input port (#3) measured at all output ports; and (b) various input ports measured from a constant output port (#3). ................................................................................................................... 183

Fig. 7.7 BER results for 10 Gbps conversion of PRBS 231

185-1 data for one input port

and two different output ports. ..........................................................................

Fig. 7.8 Eye diagrams for 10 Gbps signals: (a) back-to-back measurement; and (b) converted signal from input port #6 to output port #3 (1543 nm 1547.9 nm) with the time-delayed branch turned off. .......................................................... 185

Fig. 7.9 ASE power versus length for c-MQW based SOAs. .................................. 186

xxv

Fig. 7.10 BER measurements for PRBS 27

189-1 pattern lengths for input port #3 to

output ports #5 and #6. ......................................................................................

Fig. 7.11 (a) BER measurements for a single input wavelength converter at 40 Gbps monitored from different output ports. Back-to-back BER measurements are also included for the converted wavelengths. (b) Open eyes diagrams for a single input measured from all eight output ports. ............................................ 190

Fig. 7.12 (a) BER measurements for several input wavelength converters at 40 Gbps monitored from a constant output port. Back-to-back BER measurements are also included for the converted wavelengths. (b) Open eyes diagrams for several inputs measured from a constant output port. ....................................... 190

Fig. 7.13 Input power in the MZI SOA versus the input power measured in the preamplifier. The red line indicates the minimum pump power level required in the MZI. The total gain of the preamplifier is ~3 dB more than shown here due to a 50/50 MMI splitter between the preamplifier and the MZI. ...................... 192

Fig. 7.14 Effect of thermal crosstalk on the SG-DBR wavelength of an input port when the nearest neighboring pad in a second channel is biased. The measurement was done with and without the gain section of the neighboring SG-DBR biased. ................................................................................................ 194

Fig. 8.1 Comparison of 1st and 2nd

206 generation wavelength converter designs. The

new folded design uses TIR mirrors to reduce the chip length by 3 mm. .........


207

generation AWGR designs. The new design reduces the component footprint by using deeply-etched waveguides for the array arms. .........................................................................................................

Fig. 8.3 (a) Schematic cross-section of the shallow-etched portion of the array arms showing an InP wing above the waveguide layer. (b) Effect of the height of the InP wing on the index contrast and the ideal number of arrayed waveguides (the red line shows the target InP wing height for our new design). ........................ 208

Fig. 8.4 New 1.28 Tbps 16 x 16 MOTOR design. ................................................... 210

Fig. 8.5 Side view of dual-section SOA with high-gain c-MQW section and high-saturation-power regrown low-confinement SOAs. ......................................... 212

Fig. 8.6 Dual section SOA with a short c-MQW SOA followed by a low-confinement regrown MQW SOA with a CTL thickness of: (a) 60 nm; and (b) 105 nm. .............................................................................................................. 213

xxvi

Fig. 8.7 Schematic of a MOTOR wavelength converter port with EAMs to enable 10 Gbps label writing: (a) shows the device with EAMs in the MZI; and (b) shows a new external modulation approach to reduce the impact of thermal chirp. .................................................................................................................. 214

Fig. 8.8 PL spectra for three different band edges on the same chip achieved with QWI. A 40 second anneal is used to shift the PL peak to just shy of 1500 nm for efficient EAMs. ........................................................................................... 215

Fig. 8.9 Custom probe with spring-loaded tips designed to directly match up with the bond pads of a single MOTOR channel. (Image courtesy of Dr. Ashish Bhardwaj.) ......................................................................................................... 216

Fig. 8.10 (a) Modal overlap with a bulk tensile strained active region that is separated from the center of the optical mode by a layer of InP. (b) The effect of the thickness of an InP spacer layer between a bulk active layer and the waveguide on the confinement factor (shown for several bulk layer thicknesses). ...................................................................................................... 218

Fig. 8.11 Polarization selecting MZI structure (adapted from [8]). Diagram shows a slanted-wall polarizer component as in [9], but other rotator designs could be used instead. ...................................................................................................... 219

xxvii

LIST OF TABLES

Table 2.1 State-of-the-art single-channel wavelength converters .............................. 30

Table 3.1 QWI Implant and Anneal Parameters ........................................................ 52

Table 4.1 SG-DBR mirror design parameters ............................................................ 84

Table 4.2 AWGR design parameters ......................................................................... 91

Table 5.1 Metal-organic source conditions for the UCSB MOCVD system. .......... 121

Table 5.2 Base Structure Epitaxial Layer Design .................................................... 130

Table 5.3 In-house cladding regrowth profile. ......................................................... 133

Table 5.4 External vendor cladding regrowth profile. ............................................. 134

Table 6.1 Summarized process flow for MOTOR development ............................. 143

Table 6.2 Standard MHA RIE conditions for ridge definition ................................. 146

Table 6.3 New Cl2/H2 155/Ar etch process conditions ..................................................

Table 6.4 Standard UCSB Nitride Recipe Gas Flows .............................................. 164

Table 6.5 Wet and dry etching comparison of high- and low-stress nitride films .. 169

Table 7.1 Typical bias conditions for differential MZI wavelength converter ........ 187

Table 8.1 Potential design parameters for the 2nd 209 generation MOTOR AWGR ......

1

Chapter 1

Introduction

The Internet has exploded in the last 30 years, both in popularity and content. What

consisted of 562 networked computers in 1983 has grown exponentially, and by

2006, on average more than ten new computers were added to the Internet per

second [1]. Consumer use of bandwidth will continue to grow in the future,

especially with the increasing demand for high-definition video content.

Historically, electronic router manufacturers have been able to address rising

bandwidth demands by scaling the density of electronic components like transistors

within a router to enhance capacity. This roadmap was largely made possible

through performance improvements realized by the miniaturization of the underlying

silicon technology, which allowed for higher clock rates and lower required drive

voltages [2]. However, today’s line card speed requirements are now outpacing the

reductions in drive voltage achieved by shrinking the feature size in silicon

components. Therefore, the increase in component density that is necessary for

high-speed operation has resulted in a significant increase in power density. In

general, the power density can be reduced by partitioning a router into multiple

stages or racks, but this approach increases the total power consumption of the router

2

system [3]. As a result, power density and total power consumption are two of the

most pressing issues facing state-of-the-art electronic router designers. For instance,

the highest-end router produced by Cisco Systems, the CRS-1, has a maximum data

capacity of 92 Tbps, but the power consumption required for this configuration

approaches 1 MW (the equivalent of more than 16,000 60-watt light bulbs!).

Additionally, the physical size of the router is expanding with bandwidth—the 92-

Tbps Cisco solution requires 72 line card chassis and 8 switch fabric shelves. Next-

generation routers must address these power and size issues to keep pace with ever-

expanding Internet traffic.

1.1 ALL-OPTICAL PACKET SWITCHING

One promising alternative to electronic-based systems is all-optical packet

switching. In such a router, the functions of dynamic buffering, wavelength

conversion and routing are kept in the optical layer. This is different than electronic-

based systems in which optical signals are converted into the electrical domain (O/E)

at the router node for signal processing and then converted back into optical signals

(E/O) at the output. These O/E/O conversions occur at multiple points in a router

and consume significant power. Therefore, it is expected that an all-optical approach

to routing that eliminates these conversions should help to mitigate the power

density and power consumption problems of modern electronic routers [4].

3

Furthermore, all-optical routers can provide a path for size reductions via photonic

integration, wherein more and more optical functions are combined in a single chip.

Optical packet switching (OPS) is based on principles of wavelength division

multiplexing (WDM) in which multiple data signals are assigned different

wavelengths and are transmitted via fiber optic cables. In OPS, individual bits of

data are grouped together into “packets”, which are then transmitted across a

network. In contrast to electronic routers wherein data packets are processed at the

bit level, in the optical domain data packets are processed on a per packet basis,

which allows high-bit-rate data to be routed without complicated electronics [5]. In

addition to potential reductions in power and size, OPS offers several other

advantages, including high packet throughput and support for multiple data formats

and granularities [6]. However, there are still significant challenges with respect to

the cost and scalability of an OPS network that must be addressed [7].

Fig. 1.1 Overall LASOR architecture. PED = payload envelope detection; CDR = clock data recovery; Deser = deserializer; Sync = synchronizer; WC = wavelength converter; AWGR = arrayed-waveguide grating router; 3R = retiming, reshaping, and reamplification.

4

One approach to packet switching uses a label-swapped architecture in which

data packets are encapsulated with a lower bit rate label that contains information

about how a packet should be routed [8]. Labels can then be processed using

relatively simple electronics while high-bit-rate payloads are processed entirely in

the optical domain. One possible implementation of this type of router is shown in

Fig. 1.1. It enables synchronization and buffering of input packets in the optical

domain, and provides a means to write the input data onto a new wavelength for

wavelength-selective routing.

1.1.1 CORE TECHNOLOGIES

All-optical packet switching routers rely on several key technologies including

packet synchronizers, optical buffers, and high-speed wavelength converters.

Synchronizers are needed to align packets to a timeslot that corresponds to the clock

of an optical buffer [5],[9]. Once a packet is correctly aligned, optical buffering can

then be performed for contention resolution to ensure that two packets do not share

the same timeslot. Both technologies have been demonstrated by using an InP

switch matrix to control the number of circulations in either a fiber or waveguide

delay loop [9]. Unfortunately, optical buffering is still one of the limiting factors of

all-optical packet switching as it cannot yet compete with electronic buffering, which

uses high-capacity RAM.

5

Fig. 1.2 Schematic of a crossbar switch fabric connected to ingress and egress line cards.

High-speed wavelength conversion is another essential function for all-optical

routers to prevent wavelength blocking in an optical node [10]. Several approaches

to wavelength conversion have been proposed over the years that rely on either

carrier-based nonlinearities (such as cross-gain and cross-phase modulation, or four-

wave mixing in nonlinear SOAs) [11], or photocurrent-driven field modulation

[10],[12]. For modern-day packet switching applications, it is important that these

wavelength converters operate at high data rates (at least 40 Gbps) and are capable

of switching times on the order of nanoseconds.

1.1.2 PACKET SWITCHING FABRICS

At the heart of a router is a switching fabric that moves packets from one port to

another (Fig. 1.2). In modern electronic routers, the switch fabric links multiple line

cards which handle the conversion of optical signals into the electrical domain (or

vice versa) and buffering. The switch fabric itself may consist of several stages, but

the simplest implementation involves crossbar circuits that route the electronic signal

from one port to another [13]. However, as the number of line cards in a system

6

increases, the length of connections to the switch fabric also increases, so these high-

frequency signals tend to have high loss [14].

In order to move toward optical packet-switched networks, we need a switch

fabric that can route packets in the optical domain, thus avoiding the power

consumption of O/E/O conversions and the radiation losses of high-frequency

electrical signals characteristic of modern electronic switch fabrics. A variety of

optical switch fabrics have been proposed that rely on mechanical, thermal or

acoustic interactions with the optical signal (such as an array of MEMS mirrors), but

the switching time is typically on the order of milli- or microseconds in these

systems [7]. For high-speed, high-capacity applications switching times on the order

of nanoseconds are required. This can be accomplished using high-speed

wavelength converters in combination with a wavelength selective routing element

like an arrayed waveguide grating router (AWGR). Because the AWGR is a passive

element and requires no drive power, this type of switch fabric offers a significant

power density advantage over electronic routers. In this scheme, the input data

packets are converted to a new wavelength that corresponds to the output

wavelength of the destination port of the AWGR. The switch fabric thus functions

as a packet-forwarding engine for the optical packet-switched router. Earlier

proposals for this type of switch fabric architecture were made as part of the MOST

program at UCSB (1996-2001), but the conceptual designs were never translated

into actual devices [15]. Thus, the goal of this work was to realize the first, single-

chip, packet-forwarding engine for an optical packet-switched router.

7

1.2 BENEFITS OF PHOTONIC INTEGRATION

Optical networks have long relied on photonic components for WDM. For most of

their history, however, these components have come in the form of discrete modules.

For example, a transmitter circuit might consist of an array of individually packaged

lasers and an array of individually packaged modulators. Each laser-modulator pair

would necessarily be interconnected with fiber links. This approach requires a high

number of fiber alignments and fiber junctions, so coupling losses between

components eventually add up, leading to increased noise and reduced system

performance. Additionally, the size of discrete-component systems scales poorly as

more and more components are added, because of the real estate consumed by

packaging and discrete fiber links. Lastly, packaging costs add up quickly in

discrete-component systems, especially in high-capacity applications that require

significant numbers of modules.

Due to advances in InP-based epitaxial growth and processing, however, it is

now possible to integrate similar functions into a single chip. Just as VLSI

techniques in electronics have led to improved performance, size and cost, photonic

integration could revolutionize the optical components industry. Photonic

integration offers a number of important benefits over discrete-component solutions.

First, multiple components can be combined into a single chip, thus reducing the

number of fiber alignments and packaging steps. For instance, a transmitter circuit

could now consist of an array of lasers monolithically integrated with modulators in

8

a single package. The interconnects between the laser and modulator in this example

would be made of low-loss passive waveguides that are lithographically defined, so

coupling losses between the components are essentially eliminated. Second, the

overall system footprint would also decrease with this approach. Furthermore, this

implementation is inherently more stable since the relative alignment of components

is locked in place and the number of fiber interconnections (which can be sensitive

to their local environment) are minimized.

There is now growing interest in large-scale photonic integration, wherein the

total number of monolithically integrated components is substantially increased.

Large-scale photonic integration is well-suited for WDM applications that require

multiple input and/or output ports. These ports can be replicated many times over in

a single chip in order to more efficiently utilize the bandwidth of an optical fiber

with an even smaller device footprint. In fact, commercial products based on this

approach have been deployed in live networks [16]. OPS is another potential avenue

in which large-scale photonic integration could be beneficial. For instance, in the

label-swapped router illustrated in Fig. 1.1, each functional block (i.e., synchronizer,

buffer, wavelength converter and AWGR) could be realized with a discrete PIC.

However, the performance of this system in terms of reliability, coupling losses and

overall footprint can be significantly improved by integrating multiple building

blocks into a single large-scale photonic IC.

9

Fig. 1.3 Schematic of the 8-input, 8-output monolithic tunable optical router (MOTOR) chip.

1.3 PREVIEW OF DISSERTATION

In this dissertation work, we combine the wavelength conversion and passive routing

elements of the label-swapped router shown in Fig. 1.1 into a single InP chip to

demonstrate a monolithic tunable optical router (MOTOR) (Fig. 1.3). This chip

functions as the switching fabric of an OPS router, forwarding packets from one port

to another. The 8-channel InP/InGaAsP device operates at 40 Gbps line rate per port

(for a total potential data capacity of 640 Gbps) and integrates an array of 8 tunable

all-optical wavelength converters with an 8 x 8 arrayed-waveguide grating router

(AWGR). The device represents one of the most complex InP PICs ever reported

with more than 200 integrated functional elements on a single chip.

This dissertation will discuss the important considerations relating to the

design, epitaxial growth, fabrication and testing of the MOTOR chip. Chapter 2

introduces the challenges associated with large-scale photonic integration, discusses

the previous state-of-the-art achievements in this area, and establishes the metrics

10

used in developing our integration approach. In Chapter 3, we outline our specific

integration strategy and several techniques to deal with the inherent trade-offs in our

design. Chapter 4 discusses the theory, design and optimization of the various

components included in the MOTOR chip. Chapters 5 and 6 address the growth and

fabrication processes used to realize the MOTOR chip. This is followed with a

discussion of key device results in Chapter 7. Based on these results, several

recommendations for future work, along with some initial designs for the next

generation of this chip, are presented in Chapter 8.

11

REFERENCES

[1] D. E. Comer, The Internet Book. Upper Saddle River, NJ: Pearson Prentice Hall, 2007.

[2] J. Chabarek, et al., "Power Awareness in Network Design and Routing," in IEEE INFOCOM, 2008.

[3] W. Wu, Packet Forwarding Technologies. Boca Raton, FL: Auerbach Publications, 2008.

[4] T. E. Stern, G. Ellinas, and K. Bala, Multiwavelength Optical Networks: Architectures, Design and Control, 2nd ed. New York, NY: Cambridge University Press, 2009.

[5] J. P. Mack, "Asynchronous Optical Packet Routers," Ph.D. Dissertation, University of California, Santa Barbara, 2009.

[6] S. Yao, S. J. B. Yoo, B. Mukherjee, and S. Dixit, "All-optical packet switching for metropolitan area networks: Opportunities and challenges," IEEE Communications Magazine, vol. 39, no. 3, pp. 142-148, Mar. 2001.

[7] G. N. Rouskas and L. Xu, "Optical Packet Switching," in Emerging Optical Network Technologies: Architectures, Protocols and Performance, K. M. Sivalingam and S. Subramaniam, Eds. Springer Science, 2005, ch. 5, pp. 111-127.

[8] D. J. Blumenthal, et al., "All-optical label swapping networks and technologies," Journal of Lightwave Technology, vol. 18, no. 12, pp. 2058-2075, Dec. 2000.

[9] E. F. Burmeister, D. J. Blumenthal, and J. E. Bowers, "A comparison of optical buffering technologies," Optical Switching and Networking, vol. 5, no. 1, pp. 10-18, Mar. 2008.

[10] M. M. Dummer, "Monolithically Integrated Optical Transceivers for High-Speed Wavelength Conversion," Ph.D. Disseration, University of California, 2008.

[11] S. J. B. Yoo, "Wavelength Conversion Technologies for WDM Network Applications," Journal of Lightwave Technology, vol. 14, no. 6, pp. 955-966, Jun. 1996.

[12] A. Tauke-Pedretti, et al., "Separate Absorption and Modulation Mach-Zehnder Wavelength Converter," Journal of Lightwave Technology, vol. 26, no. 1, pp. 91-98, 2008.

12

[13] R. Ramaswami and K. N. Sivarajan, Optical Networks: A Practive Perspective, 2nd ed. San Diego, CA: Academic Press, 2002.

[14] P. Bernasconi, J. E. Simsarian, J. Gripp, M. Dulk, and D. T. Neilson, "Toward Optical Packet Switching," Photonics Spectra, pp. 4-9, Mar. 2006.

[15] L. A. Coldren, Personal Communication, Nov. 17, 2009.

[16] R. Nagarajan et al., "Large Scale Photonic Integrated Circuits," IEEE Journal of Selected Topics Quantum Electronics, vol. 11, pp. 50-65, Jan. 2005.

13

Chapter 2

Large-Scale Photonic Integration: Background and Challenges

The previous chapter introduced the compelling argument to migrate from traditional

systems consisting of discrete optical components towards systems that employ

photonic integrated circuits (PICs) to implement optical functions. However, in spite

of the inherent benefits of monolithic integration, the PIC industry is still in its

infancy because of the fundamental challenges associated with demonstrating high-

yield, complex photonic devices. Because these challenges were paramount in the

work of this dissertation, this chapter will address the important implications of

fabricating large-scale PICs (LS-PICs). This includes a detailed analysis of the key

manufacturing metrics that impact the trade-off between device complexity and yield

in LS-PICs and of potential options to minimize risk in the design and fabrication

processes.

As part of this discussion, we will present prior state-of-the-art developments in

both single-channel and multi-channel PICs from academia and industry. We will

then introduce the specific details of our monolithic tunable optical router chip. This

device pushes the envelope of both component density and channel complexity,

14

combining 273 optical functions into a single chip. Lastly, we outline the integration

challenge associated with MOTOR in terms of the manufacturing metrics introduced

in this chapter.

2.1 THE NEED FOR LARGE-SCALE PHOTONIC INTEGRATION

Fundamental circuit elements such as transistors in electronics and photodetectors in

photonics have historically been demonstrated first as discrete elements. However,

as a technology advances, there is a strong motivation to integrate multiple

components on a single chip to increase the overall functionality and reduce the

overall device footprint. The benefits of large-scale integration were first

demonstrated in the electronics world. In 1964, the most advanced silicon integrated

circuits (ICs) combined 32 components in a single chip [1]. A year later, Gordon

Moore made a simple ten-year forecast that component densities in future ICs would

likely double every two years in order to reduce cost. This prediction, known now as

Moore’s Law, became the defining metric in the advancement of silicon ICs. Today,

Intel’s next-generation quad-core Nehalem family of microprocessors is expected to

contain over 781 million transistors [2]. This exponential growth in component

density has led to tremendous performance gains with a significant reduction in

consumer costs.

Efforts to combine large numbers of photonic elements into a single device have

not followed a Moore’s law growth model despite the promised benefits of

15

monolithic integration. As with the integration of electronic components, photonic

integration can provide greater functionality and reliability with a significantly

reduced device footprint. In addition, photonic integration reduces the total number

of fiber coupling junctions in a photonic system, which directly impacts the optical

losses and the packaging costs. Integration also allows the realization of many

interferometric devices that have been historically limited to free-space experiments

on an optical bench, because the path lengths between components in a PIC are

defined by mask design and lithography rather than the precise alignment of discrete

components within a package.

In spite of these benefits, photonic integration has proceeded at a much slower

pace than electronic integration. In fact, a PIC with more than 32 components—the

equivalent of 1960’s electronics—was not reported until 1995 [3]. At present, there

have been few demonstrations of LS-PICs and, excluding this work, only one with

more than 100 integrated components [4]. The slow maturation process of LS-PICs

is attributable to a number of factors. First, photonic components in a given

application are often very diverse in function with differing design requirements.

For example, the integration of active and passive elements on a single chip can be

difficult [5], especially if the active components require different band edges (as in

the case of a laser and an electroabsorption modulator). Depending on the

integration platform used, device performance also can be hampered by reflections at

these active/passive interfaces [6]. Second, photonic integration requires epitaxial

growth techniques which can be costly and lead to low yields. Third, fabrication

16

technology is often more difficult with compound semiconductor materials. For

instance, the mechanical stability of InP is much lower than that of silicon, so even

something as commonplace as wafer handling can be problematic. Lastly, unlike

silicon electronics where more transistors lead to greater performance, many PIC

applications do not actually benefit from denser component integration. The most

beneficial applications for photonic integration are usually in WDM communications

components, where multiple input and/or output channels are desirable [7], [8]. As

the scope of this work involves optical communication technologies, we will focus

our discussion of LS-PICs in this arena.

Many of the challenges of moving toward dense PICs can be addressed through

the development of robust design and manufacturing techniques geared toward high-

yield production. Such efforts have been underway for several years, and the

benefits of large-scale integration are finally being seen commercially, as

demonstrated by a recent report from Infinera detailing plans to deploy a 400 Gbps

PIC pair with more than 300 optical functions in live networks [9]. Additionally,

using the integration strategy and tools developed in work, complex large-scale PICs

can now be successfully realized in academic environments.

2.2 LARGE-SCALE PHOTONIC INTEGRATION: METRICS AND CONSIDERATIONS

Over the last 20 years, many tremendous gains in processing technology and device

design have paved the way for increased PIC sophistication and functionality.

17

Fig. 2.1 Total device (red and yellow bars) and per channel (yellow bar only) functional component density over time for several PICs.1

Fig. 2.1

illustrates some of these milestones in terms of component density. While

there is some indication of exponential growth in this chart, the clear predictive

direction provided to electronics by Moore’s Law is not seen in these data. In terms

of large-scale photonic integration, there is not an obvious roadmap for the future.

In fact, there is not even a consensus on what constitutes a component [10]. In order

to sensibly address the opportunities and challenges in this and prior state-of-the-art

work, this section will lay a foundation for the key metrics and considerations of

large-scale photonic integration.

1 Adapted from a data set complied by Professor Meint Smit at T/U Eindhoven.

18

Fig. 2.2 Two implementations of a Mach-Zehnder switch with differing levels of fabrication complexity and functionality.

2.2.1 COMPONENT COUNT

The total number of components integrated in a chip can be a somewhat useful

metric in gauging the complexity of a device. Unfortunately, because the definition

of a “component” is murky at best, this count alone does not always convey the true

functionality of a PIC. Some favor a system of component counting in which only

large building blocks are counted. In this scheme, a laser or a modulator each count

as only one component regardless of the details within these components. While this

approach simplifies the counting process, it obscures the true complexity and

functionality of the device because these large building-block components are often

very different. Consider the case of two different Mach-Zehnder (MZ) switches

(Fig. 2.2). The top switch contains only MZ waveguides, multi-mode

interferometers (MMIs) and a passive phase tuning pad. The bottom switch also

contains MZ waveguides, MMIs and a passive phase tuning pad, but it is augmented

19

with SOAs in both branches. The bottom switch is more functional than the top

switch because it now can provide signal amplification. It is also more difficult to

fabricate because it requires active/passive integration. However, under the

building-block counting strategy, these switches each count as only one component

and any differentiating characteristics are lost. As a second example, consider the

case of a simple distributed feedback (DFB) laser and a sampled-grating distributed

Bragg reflector (SG-DBR) laser. The DFB laser is simple to fabricate, consisting of

a single active gain section with gratings, but has a limited wavelength tuning range.

In contrast, the SG-DBR laser has five sections (front and back mirrors with sampled

gratings, gain section, phase tuning pad, and rear absorber) and offers wide

wavelength-tunability of more than 40 nm. Again, the building-block approach

cannot appreciate the differences in these two lasers and would count each as one

component.

Since one of the rationales for counting components is to better understand the

level of complexity associated with a device, we instead suggest that a sub-

component counting scheme is a more appropriate metric. In this approach, any

element along the waveguide that performs a function the waveguide itself could not

perform is defined as a component (or a functional element). Referring back to Fig.

2.2, the top switch would then be counted as 3 components (1 phase pad and 2

MMIs) and the bottom switch would be counted as 5 components (1 phase pad, 2

MMIs , and 2 SOAs). Furthermore, a single-section DFB laser would be counted as

1 component while an SG-DBR laser would be counted as 5 components.

20

There are two other important considerations with component counting. First,

the total component density (by either counting method) does not always reveal the

device complexity. An array of 500 phase tuners and would garner a high point on a

component count graph, but the functionality of such a device would be limited. It is

important, therefore, to also consider the number of components per channel. This

metric provides an additional measure of how complex each port of a multi-channel

device really is. For instance, while Infinera's impressive 40-channel transmitter has

a large component count, each individual channel has only 6 components (see

Nagarajan 2006 in Fig. 2.1 [4]).

A second consideration with tracking component counts is that in many cases the

measure is only important from a marketing standpoint. Smart device design

principles should always govern PIC development. There is no reason to cram extra

components into a device if a simpler and equally functional approach is possible. In

reality, it is more important to achieve high device yields then to overcomplicate a

design solely to demonstrate higher component densities.

2.2.2 DEVICE YIELD

The most crucial concern when moving to LS-PIC designs is how to ensure high

device yields. The greater the complexity of a PIC, the greater the risk that one or

more components will fail either during fabrication or testing. In this section we will

21

discuss the factors that most significantly impact yield and how to leverage those

challenges to generate functional LS-PICs.

Yield management in PICs is extremely difficult to achieve due to the various

origins of defects across a sample and the point in manufacturing at which these

defects are manifested. In general, defect formation across an integrated circuit is

either systemic or random in nature [11]. Systemic defects arise from design or

process flaws such as a mask error or a poorly calibrated fabrication process. As

such, they usually appear in only certain areas of a wafer. In contrast, random

defects are arbitrarily distributed across all device die and tend to arise from various

fabrication steps such as regrowth or thin film deposition. Many of the tools

developed for yield management in electronic ICs can be adapted to LS-PIC

manufacturing, but there is still room for improvement. For instance, Infinera, the

most dominant commercial LS-PIC manufacturer, has implemented many of these

techniques, but as of 2005 still had 15X greater defect densities than that of silicon

ICs (which is roughly equivalent to the typical yield achieved in silicon back in

1987) [12].

Large data sets from multiple wafer runs are required to accurately model and

predict PIC failure. Unfortunately, at a research institution like UCSB where

production runs consist of only a few samples, these data are unavailable. However,

it is still possible to make some general statements on the factors affecting yield.

First, processing steps carry different levels of general intrinsic risk, but the actual

degree of risk varies depending on the tolerance of a particular component. For

22

example, a lithography step to define metal contacts has a low risk of failure,

because slight misalignments or poor focus during the exposure will not appreciably

affect the performance of the contacts. However, a lithography step to define MMIs

has a greater risk since a poor focus will affect the width of the MMI and

significantly change the splitting ratio. Second, some types of processing steps are

inherently higher risk because they cannot be repeated in the event of equipment

failure or user error. This is true for wet and dry etching and is typically true for

epitaxial regrowth. For this reason, the number of non-repeatable processing steps

should be minimized, or at least de-risked, for high-yield production. Finally, fatal

defects are not always visible at the time they are generated. For example, a sample

may look fine in an optical microscope while actually containing small surface

defects. These defects can grow and manifest themselves in undesirable locations

(i.e., in the center of where a ridge waveguide should be defined) during a regrowth

[13],[14]. Furthermore, these fatal defects can remain veiled throughout fabrication

and not appear until the device burn-in stage after costly packaging steps have been

performed. For this reason, yield must be monitored at various stages throughout the

production process. It is often more cost effective to discard questionable wafers

early in the manufacturing process [15].

Unfortunately, increased device functionality and complexity is usually achieved

by increasing fabrication complexity, creating a clear trade-off between device yield

and device functionality. This relationship is qualitatively illustrated in Fig. 2.3.

Yield concerns are multiplied in LS-PICs because chips have a larger footprint and a

23

greater number of components that must work simultaneous. Therefore, it is

important to minimize process complexity as much as possible. This means that it is

often more advantageous to not fully optimize every single component in a device,

as it is better to have a working component with somewhat imperfect characteristics

than a perfectly designed component with a very high probability of failure.

However, in order to achieve the required device functionality for a particular

application, some level of fabrication complexity is required. For the MOTOR chip

developed in this work, we opted to trade regrowth steps for additional etching steps,

since our etching systems offered us greater process control and repeatability (and

thus less risk). Although there are certainly cases where the opposite approach

would be appropriate, the ultimate goal with LS-PICs should be to keep the

manufacturing as simple as possible without compromising functionality.

Fig. 2.3 Qualitative illustration of the relationship between device complexity and fabrication complexity and the associated manufacturing risk.

24

(a) (b) (c) (d) (e) (f)

Fig. 2.4 Summary of popular integration platforms: (a) offset quantum well; (b) dual quantum well; (c) quantum-well intermixing; (d) butt-joint regrowth; (e) selective-area growth; and (f) asymmetric twin-waveguide.

2.2.3 MANAGING COMPONENT DIVERSITY: INTEGRATION PLATFORM CHOICES

The ability to integrate diverse components in an LS-PIC largely depends on the

integration platform used. This platform choice governs the number of band edges

available for various components in a device and impacts the difficulty associated

with fabrication. The platform decision for an LS-PIC depends on application, but in

general should provide a reliable means of defining all active and passive sections

with the minimum number of epitaxial (re)growths and processing steps (for the sake

of yield). Fig. 2.4 depicts several of the most prevalent platform designs in the

InP/InGaAsP materials family. Each approach has inherent limitations, so a number

of variants that augment these platforms with epitaxial regrowth steps have also been

demonstrated. Detailed descriptions of these platforms are given in [16] and [17],

25

but a brief analysis of these structures is provided here with a focus on how these

platforms translate to LS-PICs.

The simplest approaches in Fig. 2.4 are the offset quantum well (OQW) (Fig.

2.4a) and the dual quantum well (DQW) (Fig. 2.4b) structures. Active and passive

regions of the device can be defined via a simple selective wet etch to remove the

QWs above the waveguide, after which a low-risk blanket regrowth is used to define

the cladding layer. Because the upper QWs are outside of the waveguide, the optical

confinement in these wells (and hence the maximum possible gain) are reduced,

while the saturation power is increased. The DQW incorporates a second set of

larger-band-gap QWs in the center of the waveguide. These wells are useful in

applications that require efficient modulators, such as high-speed wavelength

converters, but they do lead to higher passive losses than those in the OQW structure

[18],[19]. Unfortunately, both of these structures can only provide two band edges

across the wafer, but in terms of large-scale integration, their simplicity is promising

for high-yield production of LS-PICs.

Alternatively, quantum-well intermixing (QWI) (Fig. 2.4c) allows the post-

growth definition of multiple band edges across a sample by a controlled diffusion of

well and barrier atoms to reshape the QWs and blue-shift the band edge [20], [21].

Unlike the OQW design, the QWs in this structure are typically placed in the center

of the waveguide, maximizing the optical confinement and gain but reducing the

maximum saturation power. This structure also uses a simple, low-risk blanket

regrowth to define the cladding above the waveguide. The intermixing process does

26

add some fabrication complexity, but the platform is still robust in terms of yield. If

very precise wavelength targeting is required, this approach may not be the best

choice since there can be some minor variation in intermixed wavelength from run to

run. However, since the intermixing step occurs early in the process it is easy to

weed out failed samples long before a significant investment of time and money.

The key advantage of the three techniques described above is that they only

require blanket epitaxial regrowth, which tends to be higher yield. However, other

approaches which utilize more complicated epitaxial growth techniques have also

been developed to provide greater flexibility to a PIC designer. One of the most

common approaches, butt-joint regrowth (Fig. 2.4d), involves etching away the

entire active QW and waveguide region and regrowing new material with a different

band edge in its place [22],[23]. The key advantage of butt-joint regrowth is that the

new material can be active or passive and have a completely different degree of

optical confinement than the as-grown structure, allowing the definition of the

widest variety of components on a chip. Unfortunately, butt-joint regrowth carries a

higher risk as the interface between the old and new waveguide regions must be

void-free with a high optical quality and must not introduce optical reflections

[24],[25]. Consequently, the device yield is expected to drop noticeably with each

butt-joint step.

Selective area growth (Fig. 2.4e) is another epitaxy-based technique for defining

multiple band edges on a sample [26]. This is achieved by selectively masking

regions of the sample surface with dielectric to enhance the surface diffusion of

27

MOCVD precursor elements. At the right growth conditions, the metal-organic

compounds will not stick to the dielectric mask but will diffuse to unmasked regions.

The size and shape of the open windows will affect the subsequent growth rate and

determine the subsequent band edge. However, this process requires significant

optimization to ensure high selectivity between the substrate and the dielectric mask

[27], and it can suffer from uniformity issues. Additionally, a cladding regrowth is

still required so the selective area growth approach does not really afford much

flexibility over the OQW platform. For these reasons, selective area growth does not

lend itself well to high-yield LS-PIC manufacturing.

Finally, an asymmetric twin-waveguide (ATW) approach (Fig. 2.4f) can be used

to realize multiple band edges on a sample without regrowth steps [28]. Instead,

multiple active and passive waveguiding layers are separated vertically by InP layers

during a single base growth. Sophisticated etching techniques are then required to

selectively remove these layers and create waveguide tapers to couple the optical

mode vertically from one waveguide to another. Because this technique completely

eliminates the need for regrowth, it should be favorable in terms of yield, provided

robust and repeatable etching techniques exist. In fact, there is currently some

commercial interest in PICs using this platform [29]. However, in LS-PIC

applications that require multiple active and passive transitions, the waveguide tapers

required for coupling between sections would result in a larger footprint compared to

other platform techniques.

28

2.3 PRIOR STATE OF THE ART

In this section, we will discuss several of the milestone achievements in both single-

channel and multi-channel photonic integration (see Fig. 2.1). These devices utilize

a combination of epitaxial growth and sophisticated fabrication techniques to

achieve a high-degree of functionality with a diverse set of components. The single-

channel devices included here do not have enough total components to technically be

classified as LS-PICs, but on a per-channel basis, the component count of these chips

is quite high. Also, many of the integration technologies used therein could be

extended to multi-channel PICs in the future.

2.3.1 SINGLE-CHANNEL PHOTONIC INTEGRATED CIRCUITS

Numerous single-channel PICs have been demonstrated throughout the years for

WDM applications, but 40 Gbps wavelength converters (WCs) represent one the

most notable achievements in terms of functionality and integration. Several

approaches to wavelength conversion have been demonstrated, but the most common

utilize either carrier-based modulation [30],[31] or field-based modulation [32].

Each of type of WC integrates a number of diverse elements through a combination

of epitaxial (re)growth and advanced processing techniques (Table 2.1). Bernasconi

et al. demonstrated a WC based on carrier modulation and a multi-frequency laser

(MFL). SOAs are the only active components in the device which simplifies the

29

fabrication, but their strategy to obtain low-loss passive waveguides requires two

regrowth steps [30]. Additionally, the device footprint is quite large. Lal et al. also

used SOA-based carrier modulation to achieve 40 Gbps wavelength conversion, but

their device is much smaller, and includes an SG-DBR laser that provides continuous

tuning across the C-band instead of an MFL which has a limited set of operating

frequencies. It also integrates EAMs to encode low-bit-rate labels onto converted

data packets [31]. The enhanced functionality and performance of this device

unfortunately requires two regrowths including a fairly complicated BJR. Dummer

et al. used a field-modulated approach to WC [32]. This WC also contained label

writing capabilities, but had an even smaller footprint, generated lower levels of

ASE, and did not require any output filtering. The device is fabricated using a

simple DQW platform and a single, low-risk cladding regrowth. However,

additional fabrication complexity was required to realize the high-speed traveling-

wave modulators. In order to reduce capacitance, the waveguide of the modulators

was undercut via wet etching to reduce the width. Unfortunately, it is hard to ensure

uniformity and precision with wet etches, so the increased modulator performance

comes at the expense of additional processing risk.

These single-channel devices each demonstrate interesting integration

technologies. However, they are limited in total data capacity because they have

only one input/output channel. If any of these WCs were deployed in a real system,

an array of separately packaged WCs, each with its own set of fiber alignments,

would be required.

30

Table 2.1 State-of-the-art single-channel wavelength converters

Bernasconi 2006[30] Lal 2007[31] Dummer 2008[32] Laser Source

Multi-frequency laser Laser Source

SG-DBR Laser Source

SG-DBR Components

SOAs (10) MZI (1) MMI couplers (4) AWGR (1)

Components SOAs (6) MZI (1) MMI couplers (5) EAM (2) Phase tuners (3) Delay line (1) Mode converters (4) Laser gain section (1) Tunable mirrors (2) Absorber (1) Variable optical

attenuators (2)

Components SOAs (3) MZI (1) MMI couplers (2) EAM (2) Photodiode (1) Phase tuners (3) Delay line (1) Mode converters (2) Laser gain section (1) Tunable mirrors (2) Absorber (1) Variable optical

attenuators (1) Signal monitor (2) Capacitors (2) Resistors (2) Traveling-wave

transmission line (1) Platform

OQW + 2 blanket regrowths

Platform OQW + BJR + blanket regrowth

Platform OQW + 1blanket regrowth

Footprint 6.5 mm × 4 mm

Footprint 7.0 mm × 0.5 mm

Footprint 4.1 mm x 0.55 mm

2.3.2 MULTI-CHANNEL PHOTONIC INTEGRATED CIRCUITS

The benefits of photonic integration can be amplified by moving from single-channel

PICs to multi-channel PICs that combine the similar functions of discrete ports into a

single device. Infinera was the first to commercially break through the LS-PIC

barrier with its 10 Gbps x 10-channel transmitter that integrated more than 50

components onto a single chip [33]. This type of LS-PIC has cumulatively logged

more than 100 million hours of operating time without any failures, thus

demonstrating the reliability gains from photonic integration [34]. More recently,

31

Infinera has pushed the limits of integration further with a 40-channel transmitter

PIC that integrates forty DFB-EAM transmitters (each capable of 40 Gbps operation)

with an AWGR [4]. This LS-PIC has a total component count of 241 with a total

data capacity of 1.6 Tbps, while requiring only a single fiber alignment. However,

on a per-channel basis, the functionality of this device is still far below that of the

single-channel PIC results reported above. In fact, each individual channel consists

of only 6 components. Earlier demonstrations of multi-channel PICs with more than

50 components have also been reported, such as the 4x4 laser amplifier gate switch

of [3] and the optical cross-connect of [35], but these devices were limited in overall

functionality.

2.4 DEVELOPMENT OF A MONOLITHIC TUNABLE OPTICAL ROUTER

The goal of this dissertation was to push the envelope of monolithic integration

further than ever before by demonstrating a monolithic tunable optical router

(MOTOR) chip that functions as the packet-forwarding engine of an all-optical

router (Fig. 2.5). The 8-channel InP/InGaAsP device consists of 273 functional

components (34 per channel plus one shared routing element) and provides

wavelength conversion and switching at 40 Gbps line rate per port for a total

potential data capacity of 640 Gbps. This section will apply the integration

considerations developed in this chapter to the MOTOR chip in order to define the

inherent integration challenges. Specifically, we will analyze the individual

32

Fig. 2.5 (a) Schematic of overall MOTOR chip; (b) Expanded view of a single input wavelength converter showing several key device elements.

component requirements of the chip to elucidate the key considerations for our

integration strategy. Later chapters will present the specific techniques developed to

solve this challenge and realize a functional chip.

2.4.1 CORE FUNCTIONALITY AND KEY DEVICE BUILDING BLOCKS

The MOTOR chip is the optical switch fabric of an all-optical packet switching

router. The device integrates an array of 8 tunable all-optical wavelength converters

with a passive 8 x 8 AWGR. Wavelength conversion is achieved by exploiting the

nonlinear interaction between carriers and input photons in a nonlinear SOA within a

delayed Mach-Zehnder interferometer (DMZI) structure as in [31]. This interaction

33

causes a phase change in the MZI which subsequently produces an amplitude change

on a continuous wave (CW) signal (the theory of operation will be discussed in more

detail in Chapter 4).

A number of key components are required for DMZI wavelength conversion

(Fig. 2.5b). First, a high-power, tunable CW source that sets the new wavelength for

the converted data signal is needed. The tuning range on this laser should be large in

order to precisely tune the signal to an allowed output wavelength of the AWGR for

channel switching. We chose an SG-DBR laser for this as it demonstrates both high-

power and a wide tuning range of more than 40 nm [36]. Next, MOTOR employs

several different types of SOAs. Short booster SOAs are used to amplify the SG-

DBR output power after it is split by a 50/50 MMI splitter and before it is input into

each branch of the MZI. Because the SG-DBR output power is already high, the

booster SOAs are saturated but provide enough gain to overcome the halving in

power from the MMI splitter. In the MZI, long nonlinear SOAs are required to

achieve a phase change in the MZI in the presence of input pulses. Also, linear

preamplifier SOAs are inserted before the input to the MZI to amplify the input data

signal. It is crucial that these SOAs provide an optimal combination of high gain (to

ensure that the input pulses have enough power to deplete the carriers in the MZI

SOAs) and high saturation power (to avoid pattern dependent distortions that arise if

the preamplifier SOAs are operated in the nonlinear regime). The wavelength

converters also contain variable optical attenuators (VOAs), phase tuning pads, and

power monitors. In addition to these probed components, there are a number of

34

important passive components integrated into the wavelength converters, including

an integrated delay line (for DMZI operation) and several MMI splitters.

The output from each wavelength converter is coupled into an AWGR which

routes the data to a particular output port based on the wavelength set by the SG-

DBR. This component has its own set of design parameters (which may not be

complementary to the wavelength converters). In general, the AWGR should have a

small footprint, which constrains some of the performance attributes like the channel

spacing. It also should have a low insertion loss and propagation loss, so proper

waveguide design and optimized etching techniques are essential.

2.4.2 SUMMARY OF INTEGRATION CHALLENGE

Integrating the active and passive components of MOTOR into a single chip is not a

simple proposition. Fig. 2.6 summarizes the important components of the chip along

with their important active and/or passive attributes. It is clear from this illustration

that there is not a simple and convenient overlap of properties among these

components and, therefore, there is not an obvious choice of integration platform

that will enable high-yield manufacturing of this chip. To address this challenge, we

have developed a comprehensive integration strategy that builds upon the standard

UCSB QWI integration platform. This strategy utilizes multiple waveguide

architectures across the chip instead of extra regrowth steps to provide more design

flexibility without compromising yield. It also exploits a previously-sacrificial InP

35

Fig. 2.6 Summary of MOTOR integration challenge. The box on the upper left lists the key components used in the device and their most important active (purple) and/or passive (maroon) attributes.

layer used for intermixing in a new way to reduce passive propagation losses. The

specifics, benefits and trade-offs associated with this strategy are explored in the

next chapter.

2.5 CHAPTER SUMMARY

This chapter discussed the motivation for migrating towards large-scale PICs. The

benefits of increased component integration are obvious, but to a large degree, have

remained elusive in photonics due to challenges associated with production. As a

result, large-scale photonic integration has only recently been adopted in a few

commercial applications. The future of these efforts is still somewhat unclear as

36

simply increasing the component density of a chip does not always guarantee

increased functionality. In general, however, the reduction in cost and size promised

by LS-PICs will not be widely realized without robust fabrication and design

techniques that focus on high-yield production. Much of this stems from the choice

of integration platform and how all the necessary band edges on a chip are achieved.

In this work, we have developed and demonstrated one of the most densely

integrated and complex PICs to date. This MOTOR chip combines an array of 8

tunable 40 Gbps wavelength converters with a passive AWGR and works as a

packet-forwarding engine of an all-optical router. However, the diversity of

functions required to implement this device does not lend itself to a simple

integration solution. The integration strategy used to mitigate these challenges will

therefore be the focus of subsequent chapters.

37

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[25] X. Song, N. Futakuchi, F. C. Yit, Z. Zhang, and Y. Nakano, "28-ps switching window with a selective area MOVPE all-optical MZI switch," IEEE Photonics Technology Letters, vol. 17, no. 7, pp. 1480-1482, Jul. 2005.

[26] M. Aoki, et al., "Novel structure MQW electroabsorption modulator/DFB-laser integrated device fabricated by selective area MOCVD growth," Electroincs Letters, vol. 27, no. 23, pp. 2138-2140, Nov. 1991.

[27] T. Van Caenegem, I. Moerman, and P. Demeester, "Selective area growth on planar masked InP substrates by metal organic vapour phase epitaxy (MOVPE)," Progress in Crystal Growth and Characterization of Materials, vol. 35, no. 2-4, pp. 263-288, 1997.

[28] X. Fengnian, V. M. Menon, and S. R. Forrest, "Photonic integration using asymmetric twin-waveguide (ATG) technology: part I-concepts and theory," IEEE Journal of Selected Topics in Quantum Electronics, vol. 11, no. 1, pp. 17-29, Jan. 2005.

[29] C. Watson, K. Pimenov, V. Tolstikhin, G. Letal, and R. Moore, "Enhanced Efficiency Laterally-Coupled Distributed Feedback Laser," U.S. Patent US 2009/0116522 A1, May 7, 2009.

[30] P. Bernasconi, et al., "Monolithically Integrated 40-Gb/s Switchable Wavelength Converter," Journal of Lightwave Technology, vol. 24, no. 1, pp. 71-76, 2006.

[31] V. Lal, M. L. Mašanović, J. A. Summers, G. Fish, and D. J. Blumenthal, "Monolithic Wavelength Converters for High-Speed Packet-Switched Optical Networks," IEEE Journal of Selected Topics in Quantum Electronics, vol. 13, no. 1, pp. 49-57, Jan. 2007.

[32] M. Dummer, J. Klamkin, A. Tauke-Pedretti, and L. Coldren, "40 Gb/s widely tunable wavelength converter with a photocurrent-driven high-impedance TW-EAM and SGDBR laser," in IEEE International Semiconductor Laser Conference, 2008, pp. 145-146.

[33] R. Nagarajan et al., "Large Scale Photonic Integrated Circuits," IEEE Journal of Selected Topics Quantum Electronics, vol. 11, pp. 50-65, Jan. 2005.

[34] Infinera. (Sept. 18, 2008) "Infinera PICs Surpass 100 Million Hours Operation Failure-Free". [Online]. http://www.infinera.com/j7/servlet/NewsItem?newsItemID=127

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[35] C. G. P. Herben, et al., "Polarization independent dilated WDM cross-connect on InP," IEEE Photonics Technology Letters, vol. 11, no. 12, pp. 1599-1601, Dec. 1999.

[36] V. Jayaraman, Z.-M. Chuang, and L. A. and Coldren, "Theory, design, and performance of extended tuning range semiconductor lasers with sampled gratings," IEEE Journal of Quantum Electronics, vol. 29, no. 6, pp. 1824-1834, Jun. 1993.

41

Chapter 3

Integration Strategy

The overall performance of photonic integrated circuits (PICs) depends largely on

the strategy employed for monolithic integration. The choice of integration platform

(which includes the epitaxial layer design and the method of defining active and

passive regions across the chip) combined with the design of the waveguide

architecture must be made appropriately to simultaneously optimize the diverse

components in the PIC while minimizing fabrication complexity. The epitaxial layer

design (including regrowth layers) governs the available active and passive band

edges in a PIC. The thickness and placement of these layers in the structure directly

impacts important device properties such as the gain and saturation power. Post-

growth techniques can also be utilized to define active and passive regions of the

PIC by selectively removing epitaxial layers or adjusting their local concentration to

shift the band edge. The waveguide architecture adds another degree of design

flexibility, impacting the possible layout options of a component (i.e., compact with

tight bends, large with straight waveguides, etc.). However, increasing the number

of growths or waveguide designs in the PIC usually increases the manufacturing

42

complexity and detrimentally impacts the device yield. This trade-off will ultimately

determine the degree of optimization possible for each individual component.

This chapter discusses the integration approach used for our monolithic tunable

optical router (MOTOR) chip that serves as the packet-forwarding switch fabric of

an all-optical router. As discussed in Chapter 2, MOTOR combines a diverse group

of active and passive elements into a single chip. Many of these components have

conflicting desirable attributes, so a sophisticated integration approach is necessary.

First, the epitaxial base structure and regrowth design will be discussed, along with

their innate trade-offs. Second, the need for multiple waveguide architectures in

different regions of the chip is demonstrated. Several possible candidates are

presented and the pros and cons of each structure are outlined. Next, quantum-well

intermixing (QWI) is presented as a robust technique for active/passive definition in

the MOTOR chip. The standard UCSB single-implant intermixing approach is

described along with a novel extension of this technique to reduce passive optical

losses. In this approach we exploit an unintentionally-doped (UID) InP implant

buffer layer (which is normally sacrificed after intermixing) as a permanent setback

layer that separates the optical mode from Zn-doped cladding regions.

3.1 GENERAL INTEGRATION STRATEGY USED IN THIS WORK

A three-pronged approach to large-scale photonic integration is used to realize the

MOTOR chip (Fig. 3.1):

43

1. A centered multiple quantum well (c-MQW) active region

2. Quantum-well intermixing for active/passive definition

3. A single, blanket cladding regrowth

The key advantage of this approach is the use of only a single, blanket InP

regrowth step. Regrowths add complexity to a process as the quality of the regrown

layers depends directly on the condition of the sample surface. For example, wafer

handling and general processing before the regrowth can lead to the generation of

additional defects on the surface that grow in size during the regrowth. As another

example, Si atoms inevitably collect on a sample surface due to their prevalence

throughout the lab atmosphere [1]. The incorporation of high levels of Si at the

regrowth interface can lead to the formation of an unwanted p-n junction at the

surface, and has also been shown to affect growth morphology [2].

(a) (b)

Fig. 3.1 Integration platform used in this work. (a) Epitaxial structure of the initial base growth with an MQW region centered within a quaternary waveguide. (b) Epitaxial structure of the completed device showing both active and passive regions achieved through QWI and the cladding regrowth.

44

The blanket nature of our cladding regrowth also avoids many of the

complexities associated with butt-joint and selective area regrowth techniques as the

majority of the sample surface is planar. Any defects that do form during the over-

growth of non-planar regions of the sample are fortunately above of the waveguide

layer so they can only interact with the optical mode tail, thereby minimizing loss.

In contrast, butt-joint regrowths are used to form a junction between two layers

directly in the path of the optical mode, so defects formed at this transition can be

detrimental to device yield [3],[4]. In this respect, the blanket regrowth approach

has a much higher probability of success.

The three-pronged integration approach proposed above seeks to minimize

growth and fabrication complexity in the interest of yield. In LS-PICs, component

yield is of the utmost importance because there are more components per chip. A

single defect in one port of a multi-channel device can render an entire chip that is

otherwise functional useless. An LS-PIC also has a larger footprint so it cannot be

replicated as many times across a wafer as a smaller PIC. The greater real estate

associated with a bigger chip translates directly into a more severe cost penalty per

failed device. To reduce the probability of fatal defects, we emphasize simplicity in

our integration approach. However, this introduces several notable trade-offs:

1. Reducing the total number of regrowths to one limits the diversity of band

edges in the chip. In order to achieve components with differing optical

properties, MOTOR instead utilizes multiple waveguide architectures across

the chip.

45

2. The single cladding regrowth allows us to optimize doping profiles for

efficient active diodes. However, because high doping concentrations will be

placed near the waveguiding layer, we must address the increase in passive

optical losses due to free-carrier absorption with Zn atoms in the cladding.

3. The c-MQW layer structure maximizes the optical confinement of the mode

and makes it easy to realize high-gain and low-saturation power elements.

Unfortunately, this introduces serious constraints on the design parameters of

the preamplifier SOAs which must be linear to avoid pattern dependence.

4. Lastly, our use of a strained c-MQW region introduces polarization

sensitivity in the device.

Steps have been taken in this work to mitigate the negative impact of the first

three of these trade-offs. These measures will be discussed in more details in

subsequent sections of this chapter. A discussion of potential steps that would

address the polarization sensitivity is deferred until Chapter 8.

3.2 GENERAL INTEGRATION PLATFORM: CENTERED MQW STRUCTURE AND

QUANTUM WELL INTERMIXING

3.2.1 BASE STRUCTURE IMPLEMENTATION

Our integration strategy begins with the initial epitaxial growth of the MOTOR chip,

which defines the active region of the device. It consists of ten 6.5-nm InGaAsP

46

Fig. 3.2 Band diagram for c-MQW In(x)Ga(1-x)As(y)P(1-y)

quantum wells (+0.9% compressive strain) and eleven 8.0-nm InGaAsP barriers (-

0.2% tensile strain) sandwiched by a 105-nm quaternary waveguide (

active region showing the lowest energy transition from the conduction band (C1) to the heavy hole band (HH1).

Fig. 3.2)2

5

. The

Group III concentration is held constant between the wells and barriers for ease of

growth calibration. Strain is induced in the active region by adjusting the

composition of the InGaAsP wells and barriers such that the lattice constant of these

layers differs from that of the substrate. Strain in QWs provides several useful

benefits [ ]. First, strain removes the degeneracy of the valence band (VB),

separating the light hole (LH) and heavy hole (HH) bands. In the case of

compressive strain, the LH band is pushed away from the conduction band (CB) so

CB-HH transitions become more energetically favorable and dominate the process.

For our design, the lowest energy transition (C1-HH1) provides a PL peak

2 The specific details of the layer structure, doping profile, and growth parameters are discussed inChapter 5.

47

wavelength of λPL

By placing the MQW active region in the center of the waveguide we can

maximize the overlap with the optical mode (

~ 1542 nm. The opposite effect occurs with tensile strained wells,

where the CB-LH transition dominates. Strain also increases the curvature of the

VB so that it is more symmetric with the CB. This means that the quasi-Fermi levels

during high-injection will separate more evenly in the CB and VB, so fewer injected

carriers are necessary to reach transparency. In addition, the increased symmetry

leads to an enhancement in the differential gain of the structure. However, the

separation of the HH and LH bands also means that transitions to and from the CB

will be polarization dependent. Lastly, strain will eventually lead to defect

formation if the thickness of the strained layer exceeds a so-called critical thickness,

which is typically only a few hundred angstroms or less.

Fig. 3.3). This modal overlap is known

Fig. 3.3 Index profile of waveguide and MQW region (blue) with the normalized optical mode profile superimposed (green).

48

as the optical confinement factor (Γ), which is defined by the ratio of the integrated

mode volume within the active region over the entire integrated mode volume, or

more qualitatively as in [5]:

Γ = 𝑉𝑉

𝑉𝑉𝑚𝑚𝑚𝑚𝑚𝑚𝑚𝑚 , (3.1)

where V is the volume of the active region. As Γ increases, so does the modal gain

of the device, which is the product of the material gain of the active region and the

confinement factor. This is ideal for creating the high-gain and low-saturation power

elements needed for MOTOR. The overall confinement factor could be increased by

adding more QWs to the active region, but this would raise two concerns: (1) the

greater the number of QWs, the more likely it is that injected carriers will not

distribute themselves evenly among the QWs; and (2) the overall net strain of the

active region will be increased and dislocations could form. For these reasons, our

design uses only 10 centered QWs, providing a 1-D optical confinement factor of

14.1%.

3.2.2 QWI FOR ACTIVE/PASSIVE DEFINITION

After the base growth, active and passive regions of the chip must be defined.

Because our MQWs are centered in the waveguide core, we can only remove them in

passive sections by etching them away and regrowing something in their place. As

this approach is undesirable, we instead use a non-destructive quantum-well

intermixing technique to change the band edge of the MQW in passive regions.

49

Several techniques have been demonstrated in the literature to promote the

interdiffusion of elements across the metastable quantum-well/barrier boundary in

order to reshape the quantum wells [6]. At UCSB, two approaches have been

explored and utilized successfully. The first involves an impurity-free vacancy

disordering (IFVD) technique wherein a dielectric capping layer (typically SiO2

7

) is

deposited on a Ga-containing sacrificial layer to encourage the out-diffusion of Ga to

generate vacancies [ ],[8]. The sample is subsequently annealed to diffuse these

vacancies through the MQW and promote intermixing. The second approach uses

impurity-free ion implantation enhanced disordering (IIED) to create point defects

which allow interdiffusion of the well and barrier elements during a high-

temperature anneal [9]. Not only does IIED provide larger band edge shifts than

IFVD [7], the ion implant tends to be more repeatable in terms of vacancy generation

than a dielectric deposition in which variations in process conditions from day to day

are common. Therefore, the epitaxial structure of our MOTOR chip was designed

for the implant-based QWI technique.

Intermixing between the wells and barriers is inherently a diffusion-based

process, so the change in concentration across the heterobarrier can be modeled

according to Fick’s second law, provided we assume that the diffusion is isotropic

and that the diffusion constants for each element are concentration independent [10].

This leads to an error function profile for the Group III (𝑥𝑥�) and Group V (𝑦𝑦�)

elements [11]:

50

𝑥𝑥�(𝑧𝑧) = 1 −1 − 𝑥𝑥

2 �𝑚𝑚𝑒𝑒𝑒𝑒 �𝐿𝐿𝑧𝑧 + 2𝑧𝑧

4𝐿𝐿𝑚𝑚𝐼𝐼𝐼𝐼𝐼𝐼� + 𝑚𝑚𝑒𝑒𝑒𝑒 �

𝐿𝐿𝑧𝑧 − 2𝑧𝑧4𝐿𝐿𝑚𝑚𝐼𝐼𝐼𝐼𝐼𝐼

�� , (3.2)

𝑦𝑦�(𝑧𝑧) =𝑦𝑦2 �𝑚𝑚𝑒𝑒𝑒𝑒 �

𝐿𝐿𝑧𝑧 + 2𝑧𝑧4𝐿𝐿𝑚𝑚𝑉𝑉

� + 𝑚𝑚𝑒𝑒𝑒𝑒 �𝐿𝐿𝑧𝑧 − 2𝑧𝑧

4𝐿𝐿𝑚𝑚𝑉𝑉�� , (3.3)

where z is the distance, x and y are the as-grown concentrations, Lz

is the well width

and 𝐿𝐿𝑚𝑚𝐼𝐼𝐼𝐼𝐼𝐼 and 𝐿𝐿𝑚𝑚𝑉𝑉 are the Group III and Group V diffusion lengths, respectively. The

diffusion length for either lattice site is given by:

𝐿𝐿𝑚𝑚 = √𝐷𝐷 ∙ 𝑡𝑡 , (3.4)

where D is the diffusion constant for the process and t is the diffusion time, or in our

process, the anneal time. With our base structure, the Group III concentration is the

same for the wells and barriers, so Eqn. 3.3 alone defines the diffusion profile. Fig.

3.4a demonstrates how the interdiffusion process reshapes the MQW region for

several diffusion lengths (i.e., different anneal times). For short diffusion lengths

(Ld ~ 1 Å), the shape of the QWs is essentially preserved and no change in the

energy levels within the QW are observed. With longer diffusion lengths (Ld =10

Å), the QWs band edges become parabolic in shape and the overall band gap energy

increases, resulting in a blue-shift in the PL wavelength of the material. If the

material is annealed for sufficiently long times (Ld

Fig. 3.4

= 40 Å), the MQW is smeared

out and the band edge becomes essentially bulk-like in character. b shows

the simulated shift in PL wavelength versus diffusion length. The magnitude of PL

shift is predominantly dictated by the Group V compositional gradient between the

wells and barriers. As shown in [12] when the As concentration difference between

51

(a) (b)

Fig. 3.4 Effect of QWI process on MQW region: (a) shows the change in band edge energy as the Group V elements diffuse between well and barrier for several diffusion lengths. (b) shows the expected shift in PL wavelength versus diffusion length.

the well and barrier is reduced, less intermixing is possible and the resultant blue-

shift in PL wavelength is smaller. Additionally, Fig. 3.4b shows that the PL

wavelength begins to saturate after diffusion lengths of about 30 Å. This can be

explained by the fact that the diffusion length is on the order of half of the well

width, so the compositional difference between well and barrier will be almost

equalized by this point, making the band edge bulk-like. In practice, the PL shift

actually saturates earlier than predicted by the error-function diffusion profile

because the model neglects the important role of point defects in catalyzing the

intermixing process. Once the concentration of point defects in the sample has been

depleted, intermixing ceases and additional PL wavelength shift is unattainable.

The effectiveness of the UCSB QWI IIED process depends on the implant and

anneal conditions as well as the base structure design, all of which were optimized in

[9]. As mentioned above, it is essential to generate a large reservoir of point-defects

52

Table 3.1 QWI Implant and Anneal Parameters

Implant Conditions Anneal Conditions Energy 100 keV Encapsulation 400Å SixNy

Dose 5E14 cm-2 Temperature 675°C Temperature 200°C Ramp Time 20 sec Tilt Angle 7°

to promote interdiffusion. The concentration of point defects generated by an

implant depends on several factors, including the implant dose, the mass of the

implanted species, and general implant conditions such as the implant angle, energy

and temperature [13]. The conditions used in our process are summarized in Table

3.1. Importantly, we use phosphorous as the implant species as it is already a

constituent element of our base structure. This prevents the incorporation of

impurities into the sample. The base epitaxial layer structure itself is also adapted

for QWI. A 450-nm undoped InP implant buffer layer is grown above the active

region as a collection zone for point defects (Fig. 3.5). The thickness of the buffer

layer is chosen so that the depth profile of the implanted phosphorous atoms is

mostly contained within this layer, avoiding damage to the active region.

The intermixing process is summarized in Fig. 3.5. It begins by depositing a

thick, 500-nm nitride hard mask across the sample, which is then patterned and

removed in passive regions of the device. The sample is implanted with

phosphorous to generate the point defect concentration. The thick hard mask is then

removed and the front and back sides of the sample are encapsulated in a thin layer

of nitride. This layer helps to prevent phosphorous desorption during the anneal

53

Fig. 3.5 Summary of quantum-well intermixing processing steps.

step. A rapid thermal anneal process at 675°C is used to drive the point defects

down through the MQW region and promote intermixing. Partial intermixing to

yield intermediary band edges is also possible by etching away the buffer layer in

certain regions after a short anneal. Once the buffer layer is removed, the point

defect concentration is eliminated and intermixing ceases. The anneal

Fig. 3.6 PL wavelength shift for c-MQW base structure showing three distinct band edges on the sample (Blue = Active, Green = Intermediate Band Edge; Red = Passive Band Edge).

54

process in passive regions is continued until the PL wavelength shift saturates, at

which point the buffer layer is typically wet etched away. Fig. 3.6 shows the PL

peak wavelengths for three different band edge regions formed using this technique.

3.2.3 CLADDING REGROWTH IMPLEMENTATION

Following some initial processing steps including QWI for active/passive definition,

a single, blanket p-type InP regrowth is performed to define the upper cladding of

the device. This regrowth also includes a heavily doped InGaAs layer for Ohmic

contacts. The resulting band profile of the device at equilibrium is shown in Fig. 3.7.

Fig. 3.7 Overall band diagram for the MOTOR device, including the initial base growth (with n-type and intrinsic regions) and the p-type cladding regrowth.

55

Fig. 3.8 Popular waveguide architectures demonstrated previously in InP: (a) surface ridge waveguide; (b) shallow-etched ridge waveguide; (c) deeply-etched ridge waveguide; (d) buried rib waveguide; and (e) buried channel waveguide.

3.3 WAVEGUIDE ARCHITECTURES

As discussed in Chapter 2, the device complexity (and hence the diversity of

components that can be integrated on chip) can be increased by adding epitaxial

regrowths and/or fabrication complexity to the design of a PIC. Because of the

complications associated with epitaxial regrowth, our strategy uses only a single

regrowth to reduce the defect density across the device and improve the component

yield. This necessarily means that we must turn to more sophisticated fabrication

techniques to integrate the components required for MOTOR. The most direct path

to do this is to use multiple waveguide architectures in order to realize components

with differing degrees of optical confinement, depending on the needs of a particular

56

component. A variety of waveguide structures have been demonstrated previously

in InP-based PICs, including the surface ridge waveguide (SRW) [14], shallow-

etched ridge waveguide (SERW) [15], deeply-etched ridge waveguide (DERW) [16],

buried rib waveguide (BRW) [17], and buried channel waveguide (BCW) [18]. Fig.

3.8 shows a cross-sectional view of our epitaxial structure for each of these cases.

Each approach varies in fabrication complexity and risk but is typically achieved

through wet and/or dry etching before or after the cladding regrowth. The pros and

cons of these architecture are discussed below in the context of the epitaxial structure

used for MOTOR.

3.3.1 COMMON WAVEGUIDE ARCHITECTURES

The SRW is the most prevalent waveguide architecture used at UCSB (Fig. 3.8a).

The ridge region is initially defined by a dry etch roughly 75% of the way through

the upper cladding (typically ~1.5-1.8 μm in UCSB structures). The dry etch is then

followed by a selective wet “cleanup” etch in an aqueous solution of 3:1

H3PO4

19

:HCl. This chemistry does not etch As-containing layers (even after days of

immersion [ ]), so the InP cladding can be completely removed down to quaternary

waveguide layer for reasonable lateral confinement of the optical mode. This

waveguide architecture is among the simplest to realize and also guarantees a correct

etch depth because of the selective nature of the wet etch. However, this etch

chemistry is crystallographic and etches different crystal planes at different rates. In

57

general, the ridge itself cannot deviate from the [011] direction by more than about

7° without significant undercutting and faceting of the waveguide [20].

Furthermore, in certain directions, such as the [011�] direction, this chemistry leads to

overcutting, resulting in a wider ridge with sloped sidewalls. For angles < 25° off

the [011] direction, it is possible to account for the undercut in waveguide width by

increasing the width of a ridge section on the lithography mask plate. An empirical

relationship between the degree of undercut and the waveguide angle is given in

[21]. However, since the degree of undercut changes with angle, waveguide bends

with large angles (>15°) are subject to high loss due to faceting along the ridge

sidewall. Lastly, because the SRW with the c-MQW base structure used in this work

provides only a moderate degree of index contrast between the ridge and the air-clad

waveguide, radiation losses can be high in tight bends. This constrains the minimum

ridge bend radius of the waveguide and results in a larger footprint.

The SERW design is similar to the SRW in terms of the guided mode profile, but

it is defined using a single dry-etch step (Fig. 3.8b). In order to avoid leaving thin

InP wings adjacent to the ridge that lead to high radiation loss, the dry etch stops

within the upper portion of the waveguide layer. This approach offers two

advantages over the SRW. First, since no crystallographic etching is required, the

constraint on ridge angle is removed. Second, because the etch goes partway into

the waveguide, the lateral index contrast is increased so tighter bends are possible.

For example, with the epitaxial design used in this work, a shallow-etch halfway

through the upper quaternary waveguide layer would increase the lateral index

58

contrast by ~37% over the SRW. However, dry etching to the correct depth

repeatedly is difficult in practice. Better etch-depth control is possible with an in-

situ laser monitoring system, but uniformity across the sample may still vary.

Slower-etching regions of a sample (for example, ridges close to the outer edges of

the sample) will thus end up with a shallower etch than originally targeted. This

could affect the relative performance of chips on a wafer and reduce the total yield.

Additionally, since the dry etch enters into the waveguide itself, surface roughness

from the etching process can lead to higher scattering losses in passive regions and

surface recombination effects can reduce the injection efficiency of active

components.

The DERW structure is formed by dry etching completely through the

waveguide layer (Fig. 3.8c). The dry etch can be performed in a single step or in

multiple etch steps. A DERW structure has much higher index contrast (almost 4X

that of the SRW) and provides strong lateral confinement of the optical mode so it is

possible define tight, low-bend-radius waveguides. In fact, unlike the SRW which is

limited by the selective wet etch step, it is possible to turn the propagation direction

of the optical mode by a full 360° to make ring structures. However, as bend radii

become smaller to make tight bends, the optical mode is pulled to the outer edge of

the waveguide. This means that a larger fraction of the optical mode will be in

contact with the etched surface and scattering losses can increase. It is therefore

paramount to use an etch chemistry that provides the smoothest sidewalls possible.

If active components are defined with this waveguide geometry, surface

59

recombination can determinately affect device performance, so again, smooth

sidewalls are critical. Lastly, the ridge width required to provide single-mode

operation is much narrower than that of the SRW and SEW designs and lithography

can be more difficult.

Another geometry that allows a full 360° turn of the waveguide is the BRW (Fig.

3.8d). Unlike the geometries described above, this waveguide is defined by dry-

etching some depth into the top of the waveguide layer before the cladding is

regrown. The depth of the etch determines the confinement of the mode, but in

general, this architecture has a lower index contrast compared with those mentioned

above. The etched rib is usually buried by either the doped cladding regrowth or a

separate UID regrowth. In order to ensure a good growth interface, the quality of the

etched rib sidewalls should be high. The BCW structure (Fig. 3.8e) is similar to the

BRW in terms of preparation, but in this case the dry etch is done through the entire

waveguide layer. This approach could be used to achieve square, polarization

insensitive waveguides, but the increase in etch depth over the BRW can complicate

the regrowth. It is important to optimize the growth conditions to avoid the

formation of bunny ears at the edges of the rib. Both the BRW and the BCW are

more subject to radiation loss than the DERW, so bend radii cannot be too extreme.

Lastly, the BRW and BCW do not easily lend themselves to active device

components. Typically, an additional semi-insulating regrowth is needed on the

sides of the rib or channel to provide lateral current confinement.

60

Fig. 3.9 Ridge architectures used in MOTOR: Images (a), (b), (c) show schematic cross-sections of epitaxial layers with the optical mode power contours superimposed on top for surface ridge, deeply-etched ridge, and buried rib, respectively. Images (d), (e), (f) show corresponding SEM cross sections for surface ridge, deeply-etched ridge, and buried rib, respectively.

3.3.2 WAVEGUIDE ARCHITECTURES USED IN THIS WORK

Fig. 3.9 shows the shape of the optical mode for each of the waveguide structures

used in MOTOR along with a corresponding cross-sectional SEM image. To reduce

the fabrication complexity of the MOTOR chip, we utilize the SRW design for all

active components and the vast majority of the passive regions of the wavelength

converter array. The SRW is the most ideal approach for active components because

it eliminates surface recombination problems and provides good lateral current

confinement (as the ridge is clad on the sides by air). As mentioned in the last

chapter, the differential delay consists of a long passive waveguide. In order to

reduce the footprint of the delay line as much as possible, we use the DERW to

61

achieve tight bends. In the AWGR, we use the BRW instead of the SRW or the

DERW for several reasons. First, to reduce the device footprint, the arrayed

waveguides turn 180° from the input to the output. This would not be possible with

the SRW because of the crystallographic wet etch. Second, the DERW (which

would allow us in principle to design our arrayed waveguide with tighter bends for

compactness) would introduce significant reflections at the star couplers of the

AWGR. The BRW alleviates these problems, but because of its reduced index

contrast, the AWGR footprint is increased.

3.4 NEW APPLICATION OF QWI IMPLANT BUFFER LAYER FOR LOWER LOSS

3.4.1 FREE-CARRIER ABSORPTION LOSS IN P-TYPE INP

Because our epitaxial design uses only one, low-risk, blanket, cladding regrowth, the

same doping profile will exist in both active and passive regions of the chip. Our

cladding is doped p-type with Zn atoms, which occupy Group III sites in the InP

lattice and provide holes to the system. These free carriers can lead to significant

optical loss due to intervalence band absorption [22],[23]. The doping profile must

be optimized to ensure low-resistance contacts can be made for the active device

components, but this requires high concentrations of Zn (up to 1E18 cm-3) in the

cladding layers. There is an obvious concern, therefore, on how the doping profile

will impact on propagation losses in passive section of the device. This is especially

62

important in the lengthy passive waveguide sections of our device like the AWGR

and the differential delay line. At 1.5 μm, the absorption loss as a function of Zn

concentration has been shown to be quite high, according to the following equation

[22]:

𝛼𝛼 = 20 𝑐𝑐𝑚𝑚−1 �p

1E18 cm-3� , (3.5)

where α is the loss in cm-1 and p is the Zn concentration3. Since our Zn dopant

concentration is on the order of 1E18 cm-3

24

levels in the cladding, we would

anticipate that passive optical loss would hamper device performance if this issue is

not addressed. One common approach to reduce free-carrier absorption in passive

regions involves the use of an additional regrowth step (i.e., butt-joint or selective

UID regrowth) to separate the mode from the p-type InP [ ]. While this approach

is able to address free-carrier absorption losses, it adds significant epitaxial

complexity into the process and can reduce yield. Furthermore, the extra regrowth

step adds cost to the manufacturing process. Alternatively, post-growth techniques

such as a Zn implant followed by dopant diffusion in the active device regions can

be used, but these processes are also complicated [25]. In order to avoid substituting

one challenge for another, we decided to reexamine the traditional UCSB QWI

procedure to see if an alternative to these regrowth- or implant-based solutions was

available.

3 The prefactor in Eqn. 3.5 tends to increase with wavelength so we expect that the actual losses at our desired wavelength of 1.55 μm will be slightly higher.

63

3.4.2 APPLICATION OF UID IMPLANT BUFFER LAYER FOR LOWER-LOSS WAVEGUIDES

Typically in our QWI process, the undoped implant buffer layer grown above the

waveguide is used only for QWI purposes and is then removed across the entire

sample via wet etching [26],[27]. In this work, however, we exploit this buffer layer

to address free-carrier absorption losses. If the layer is not removed by wet etching

in passive regions of the chip, we can essentially “insert” a UID setback layer

between the optical mode and the Zn dopant atoms from the subsequent p-type

cladding without an additional regrowth step. With proper growth conditions, the

450 nm UID layer can be successfully buried during the cladding regrowth so there

are no discontinuities in the ridge waveguide.

Since the cladding regrowth in passive regions will now begin at the surface of

the implant buffer layer, it is very important to ensure that this surface is smooth and

contains low levels of defects. Because the implant step physically bombards the

surface with phosphorous atoms that could affect the surface quality, we added an

additional 200 nm of UID InP with a thin quaternary stop etch layer above the

standard implant buffer layer to protect it from processing damage (Fig. 3.10). After

the QWI process is completed in passive regions, this surface protection layer can be

removed via wet etching everywhere to expose a clean implant buffer layer. The

buffer layer can then be selectively removed in active regions by wet etching before

regrowing the cladding. The new post-QWI procedure is illustrated in Fig. 3.10.

64

Fig. 3.10 Modified quantum-well intermixing processing steps. The base structure growth now ends with a 200 nm UID InP layer to protect the surface of the implant buffer layer. After QWI, the buffer protection layer is removed by wet etch everywhere, and the implant buffer layer is wet etched in active regions only. The UID implant buffer layer is then buried by the cladding regrowth.

3.4.3 IMPLANT BUFFER LAYER QUALITY FOR REGROWTH

For this technique to be effective, it is important to ensure that a high-quality

regrowth interface can be formed between the surface of the implant buffer layer and

the cladding. A study was performed to gauge the impact of the implant process on

the implant buffer layer surface morphology and diffusion properties. Atomic force

microscope (AFM) scans were performed at various stages of the implant process to

see how each processing step affects the surface roughness. Several samples were

prepared with a slightly modified version of our standard base structure (no QWs

were placed in the 1.3Q waveguide). A 1-um Zn-doped cladding layer was later

regrown on the surface after a certain combination of processing steps. Sample A

65

(a) (b)

Fig. 3.11 AFM roughness scans for the surface of Sample A for: (a) the as-grown base structure; and (b) the same structure after regrowth with no processing steps after the initial growth.

was designated as the control sample and was not subjected to any processing steps

between the initial growth and regrowth. Sample B was implanted with standard

conditions (Table 3.1) after the initial growth, and the buffer protection and upper

stop etch layers were removed via wet etching before the regrowth (no anneal step

was performed). Sample C was prepared in the same way as Sample B, except an

anneal step was performed immediately after the implant. Fig. 3.11 shows AFM

scans of the surface of Sample A after the initial base growth and after the regrowth

(the step like pattern is due to a 0.2° miscut of the substrate which enhances the

growth process). In both cases, the surface is extremely smooth—in fact, the surface

actually becomes smoother after the regrowth.

The surfaces of samples B and C appeared to be slightly rougher immediately

after the phosphorous implant. However, the noise level of the AFM system varies

from tip to tip, and subsequent measurements of the same surface had a standard

66

(a) (b)

Fig. 3.12 AFM scans after regrowth for: (a) Sample B—implant with no anneal; and (b) Sample C—implant and anneal.

deviation of ~0.02 nm. Since the difference in surface roughness of the samples we

were measuring was on par with this standard deviation, the slight increase measured

after the implant cannot be deemed statistically significant. However, there is a clear

difference in surface roughness between Samples B and C after the regrowth.

Sample C, which was subjected to both the implant and the anneal step, was rougher

than Sample B, which was subjected to only the implant step, post regrowth. Similar

to the control sample, the RMS roughness of Sample B decreased after the regrowth.

However, the final roughness of this implanted sample was about 1.2X greater than

the control. The RMS roughness of sample C, on the other hand, was actually

slightly rougher after the regrowth, indicating that the anneal step used in QWI has a

greater impact on surface roughness than the implant. This sample was

approximately 1.6X rougher than the control. A similar result was seen in [12] for

intermixed material. However, it must be emphasized that the surface of Sample C

67

(a) (b)

Fig. 3.13 Representative AFM scans after the following wet etches: (a) 3:1 H3PO4:HCl etch of the InP implant buffer layer; and (b) 1:1:10 H2SO4:H2O2

Surprisingly, the processing steps that made the biggest impact on surface

roughness were the wet etches used to remove the InP buffer layer and the

quaternary stop etch.

:DI etch of the quaternary stop etch layer.

after regrowth is still relatively quite smooth, so we conclude that the full QWI

process does not render the surface unsuitable for regrowth.

Fig. 3.13 shows typical AFM scans for our test samples after

wet etching. The 3:1 H3PO4:HCl InP etch is significantly worse in terms of

roughness than the quaternary etch, as it appears that small particles are left on the

surface. However, the isotropic nature of the 1:1:10 H2SO4:H2O2

In addition to the surface morphology, it was important to determine if the

diffusion properties of Zn change in an InP layer that has been subjected to the

intermixing process. Zn has a high diffusivity in InP at elevated temperatures, so Zn

:DI quaternary

etch does seem to remove most of these particles. This is important because the

regrowth in actual samples is always initiated on wet-etched surfaces.

68

(a) (b)

Fig. 3.14 SIMS profile for (a) Sample A and (b) Sample B. Sample A contains an extra 1.3Q stop etch layer because the regrowth was performed on the as-grown sample without removing the upper UID InP buffer protection layer. No difference in diffusion depth is seen between the samples.

atoms diffuse readily during growth [28]. A 1-um Zn-doped InP cladding regrowth

doped >1E18 cm-3

28

was performed on our test samples to place high concentrations of

Zn above the waveguide. The regrowth was initiated with 100 Å UID InP layer,

followed by a 3 second As spike in order to identify the surface of the sample. The

As spike is very short and should not impact diffusion properties noticeably [ ]. In

order to measure the diffusion of Zn, secondary ion mass spectroscopy (SIMS)

analyses were performed on Samples A and C from above after the regrowth. As

shown in Fig. 3.14, in the control and the intermixed sample the Zn in the cladding

regrowth diffuses to the regrowth interface where it piles up. It then drops off

quickly to background levels without any appreciable diffusion of Zn species into

the buffer layer. The Zn pile up is due to a silicon spike that inevitably accumulates

at the regrowth interface (see Chapter 5). It appears that the presence of this spike

essentially blocks most Zn species from entering the buffer layer region leaving

69

essentially then entire layer undoped. This is a very advantageous finding because it

means the as-grown buffer layer thickness is directly equal to the distance by which

the optical mode and the Zn atoms in the cladding are separated. Even if the As

spike acts as a partial diffusion barrier (contrary to the claims in [28]), there still

appears to be no difference in Zn diffusion properties between implanted and non-

implanted InP. Because the surface morphology and the diffusion properties are

relatively unaffected by the intermixing process, we conclude that the implant buffer

layer is suitable for high-quality regrowth.

3.4.4 EFFECT OF IMPLANT BUFFER LAYER ON PASSIVE LOSS

Both the deeply-etched waveguide and the buried rib waveguide designs used in

MOTOR are well suited to using the implant buffer layer as a UID setback layer.

Fig. 3.15 shows the resulting waveguide cross sections with the contours of the

optical mode superimposed. In the deeply-etched ridge region, we etch completely

through the waveguide and MQW layers, so the optical mode can only interact with

Zn-doped material directly above the waveguide. Therefore, the presence of an

undoped InP setback layer is expected to provide a major improvement in optical

loss. In the buried rib structure, however, the mode is not tightly confined and

expands laterally outside of the rib region. Leaving the buffer layer directly above

the rib will only reduce optical loss over a portion of the mode volume. Because the.

70

(a) (b)

Fig. 3.15 Cross section of waveguide structure with optical mode power contours superimposed for: (a) the deeply-etched waveguide; and (b) the buried rib waveguide.

lateral portion of the mode remains in the Zn-doped cladding, the expected reduction

in optical loss is not as large as that in the deeply-etched waveguide

To verify this reduction in loss, we estimated the propagation loss as a function of

implant buffer layer thickness. Eqn. 3.5 was used to estimate the absorption

coefficient for our regrowth doping profile, and 3D beam propagation software was

employed to calculate the modal overlap with the cladding. The diffusion of Zn

during the regrowth was neglected in these calculations. As anticipated, loss in the

deeply-etched region drops off more quickly and to a lower limit than in the buried

rib structure, as there is no lateral mode interaction with Zn dopant atoms (Fig. 3.16).

This result also shows that there is no measureable advantage to increase the implant

buffer layer thickness beyond its current value of 450 nm. In reality, the magnitude

of these loss values will be larger in an actual sample due to diffusion effects within

71

Fig. 3.16 Effect of the implant buffer layer thickness on the free-carrier absorption loss due to Zn doping in a buried rib and adeeply-etched waveguide (model assumes no Zn diffusion). A significant reduction in loss is expected for our 450 nm buffer layer.

the cladding and scattering losses due to roughness from the etching process, but the

general trends should be unchanged.

This technique cannot be readily applied to passive regions which employ the

surface ridge waveguide, however, because the surface ridge process ends with a

selective wet etch. In order to facilitate removal of the implant buffer layer in active

regions before the cladding regrowth, a quaternary stop etch layer is included

directly below the buffer (Fig. 3.10). If the implant buffer layer was left in the

surface ridge region, the wet etch used to define the ridge would stop on this

quaternary stop etch layer instead of the waveguide, and a 60 nm InGaAsP/InP wing

would remain above the waveguide, resulting in detrimental radiation loss at any

waveguide bends.

72

Fig. 3.17 Differential efficiency versus the length of a passive surface ridge waveguide. The passive loss is determined by fitting the points to a curve as described in [5].

To help manage absorption losses in the surface ridge sections we use a proton

implant in all passive waveguides after the regrowth. Hydrogen atoms can interact

with and essentially neutralize negatively charged Zn atoms in the cladding [29].

Using the cleave-back method of Fabry-Perot lasers consisting of active and passive

sections [5], we confirmed that a proton implant with energies large enough to

penetrate throughout the cladding could reduce optical loss by a factor of about 3.3X

to only 2.1 cm-3 Fig. 3.17( ).

3.5 CHAPTER SUMMARY

In the case of large-scale photonic integration, the demand for increased

functionality and high-yield often conflicts with the goal of minimizing fabrication

complexity. Therefore, the development of a comprehensive integration strategy

73

will almost unavoidably involve a number of important trade-offs. This chapter

presented the integration approach that we have used to realize a monolithic tunable

optical router chip. By electing to use a centered MQW active region, QWI for the

definition of active and passive regions, and a single blanket cladding regrowth, we

have simplified the epitaxial demands on our process. However, in order to increase

the functionality of our chip, we have of necessity increased the number of etch steps

in our process in order to define three different waveguide architectures in the

device. We also have demonstrated several techniques to address the optical loss in

our device that results from using only a single p-type regrowth. Most notably, we

have proposed using the implant buffer layer grown in the base structure for more

than just intermixing. If this layer is left in passive regions of the device instead of

being removed everywhere as is typical in our standard QWI process, we can

successfully separate the optical mode from Zn-doped material without the need for

a special undoped InP regrowth. We also demonstrated that the implant and

annealing processes involved in QWI do not adversely impact the surface quality of

the implant buffer layer, leaving it suitable for high-quality regrowth. Furthermore,

we have demonstrated that a proton implant can be used to neutralize Zn atoms in

the cladding and reduce free-carrier absorption losses by a factor of more than three.

74

[1]

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[2] J.-L. Gentner, P. Jarry, and L. Goldstein, "Single Run Etching and Regrowth of InP/GaInAsP by GSMBE," in International Conference on Indium Phosphide and Related Materials, 1996, pp. 529-532.

[3] Y. Cheng, et al., "Butt-coupled MOVPE growth for high-performance electro-absorption modulator integrated with a DFB laser," Journal of Crystal Growth, vol. 308, no. 2, pp. 297-301, 2007.

[4] J. J. M. Binsma, et al., "Characterization of Butt-Joint InGaAsP Waveguides and Their Application to 1310nm DBR-Type MQW Gain-Clamped Semiconductor Optical Amplifiers," IEICE transactions on electronics, vol. 80, no. 5, pp. 675-681, 1997.

[5] L. A. Coldren and S. W. Corzine, Diode Lasers and Photonic Integrated Circuits. John Wiley & Sons, Inc., 1995.

[6] J. H. Marsh, "Quantum well intermixing," Semicondutor Science and Technology, vol. 8, pp. 1136-1155, 1993.

[7] S. K. Si, D. H. Yeo, H. H. Yoon, and S. J. Kim, "Area selectivity of InGaAsP-InP multiquantum-well intermixing by impurity-free vacancy diffusion," IEEE Journal of Selected Topics in Quantum Electronics, vol. 4, no. 4, pp. 619-623, Jul. 1998.

[8] C. Wang, "Short-Cavity DBR Lasers Integrated with High-Speed Electroabsorption Modulators using Quantum Well Intermixing," Ph.D. Dissertation, University of California, Santa Barbara, 2007.

[9] E. Skogen, "Quantum Well Intermixing for Wavelength-Agile Photonic Integrated Circuits," Ph.D. Dissertation, University of California, Santa Barbara, 2003.

[10] E. H. Li, B. L. Weiss, and K. S. Chan, "Effect of interdiffusion on the subbands in an Al(x)Ga(1-x)As/GaAs single-quantum-well structure," Physical Review B, vol. 46, no. 23, pp. 181-192, 1992.

[11] E. H. Li and W. C. H. Choy, "Electro-absorptive properties of interdiffused InGaAsP/InP quantum wells," Journal of Applied Physics, vol. 82, no. 8, pp. 3861-3869, 1997.

75

[12] J. Raring, "Advanced InP Based Monolithic Integration Using Quantum Well Intermixing and MOCVD Regrowth," Ph.D. Dissertation, University of California, Santa Barbara, 2006.

[13] S. Charbonneau, et al., "Photonic integrated circuits fabricated using ion implantation," IEEE Journal of Selected Topics in Quantum Electronics, vol. 4, no. 4, pp. 772-793, Jul. 1998.

[14] J. S. Barton, E. J. Skogen, M. L. Masanovic, S. P. Denbaars, and L. A. Coldren, "A widely tunable high-speed transmitter using an integrated SGDBR laser-semiconductor optical amplifier and Mach-Zehnder modulator," IEEE Journal of Selected Topics in Quantum Electronics, vol. 9, no. 5, pp. 1113-1117, Sep. 2003.

[15] J. H. den Besten, et al., "Low-loss, compact, and polarization independent PHASAR demultiplexer fabricated by using a double-etch process," IEEE Photonics Technology Letters, vol. 14, no. 1, pp. 62-64, Jan. 2002.

[16] E. J. Norberg, R. S. Guzzon, S. C. Nicholes, J. S. Parker, and L. A. Coldren, "Programmable photonic filters fabricated with deeply etched waveguides," in IEEE International Conference on Indium Phosphide & Related Materials, 2009, pp. 163-166.

[17] Y. Shani, et al., "Buried rib passive waveguide Y junctions with sharp vertex on InP," IEEE Photonics Technology Letters, vol. 3, no. 3, pp. 210-212, Mar. 1991.

[18] C. Ji, et al., "Monolithically integrated InP-based photonic chip development for O-CDMA systems," IEEE Journal of Selected Topics in Quantum Electronics, vol. 11, no. 1, pp. 66-77, Jan. 2005.

[19] S. B. Phatak and G. Kelner, "Material-Selective Chemical Etching in the System InGaAsP/InP," Journal of the Electrochemical Society, vol. 126, no. 2, pp. 287-292, 1979.

[20] S. Uekusa, K. Oigawa, and M. Tacano, "Preferential Etching of InP for Submicron Fabrication with HCl/H3PO4 Solution," Journal of the Electrochemical Society, vol. 132, no. 3, pp. 671-673, Mar. 1985.

[21] J. A. Summers, "Monolithic Multi-Stage Wavelength Converters for Wavelength-Agile Photonic Integration," Ph.D. Dissertation, University of California, Santa Barbara, 2007.

76

[22] H. C. Casey Jr. and P. L. Carter, "Variation of intervalence band absorption with hole concentration in p-type InP," Applied Physics Letters, vol. 44, no. 1, pp. 82-83, 1984.

[23] C. H. Henry, R. A. Logan, F. R. Merritt, and J. P. Luongo, "The Effect of Invervalence Band Absorption on the Thermal Behavior of InGaAsP Lasers," IEEE Journal of Quantum Electronics, vol. QE-19, no. 6, pp. 947-952, Jun. 1983.

[24] Y. Yoshikuni, "Semiconductor Arrayed Waveguide Gratings for Photonic Integrated Devices," IEEE Journal of Selected Topics in Quantum Electronics, vol. 8, no. 6, pp. 1102-1114, Nov. 2002.

[25] P. Harmsma, "Integration of Semiconductor Optical Amplifiers in Wavelength Division Multiplexing Photonic Integrated Circuits: Application of Selective Area Chemical Beam Epitaxy," Ph. D. Dissertation, 2000.

[26] E. J. Skogen, J. S. Barton, S. P. DenBaars, and L. A. Coldren, "A quantum-well-intermixing process for wavelength-agile photonic integrated circuits," Journal of Selected Topics in Quantum Electronics, vol. 8, no. 4, pp. 863-869, Jul. 2002.

[27] J. W. Raring, et al., "Advanced integration schemes for high-functionality high-performance photonic integrated circuits," in Proceedings SPIE, San Jose, CA, Jan. 23-25, 2006, p. 61260H.

[28] S. N. G. Chu, R. A. Logan, M. Geva, and N. T. Ha, "Concentration dependent Zn diffusion in InP during metalorganic vapor phase epitaxy," Journal of Applied Physics, vol. 78, no. 5, pp. 3001-3007, Sep. 1995.

[29] E. V. K. Rao, et al., "A significant reduction of propagation losses in InGaAsP-InP buried-stripe waveguides by hydrogenation," IEEE Photonics Technology Letters, vol. 10, no. 3, pp. 370-372, Mar. 1998.

77

Chapter 4

Design Considerations for a Monolithic Tunable Optical Router

The integration strategy outlined in the last chapter provides a framework for the

design of our monolithic tunable optical router (MOTOR). In addition to a

discussion of the underlying physics of the most important MOTOR components,

this chapter will outline specifically how our choice of integration platform and

waveguide design impacts the physical dimensions and layout of components in the

chip and their subsequent performance. The wavelength converter array and its

associated components will be discussed first, followed by an analysis of the

arrayed-waveguide grating router (AWGR). Important passive interconnects in the

chip, including the mode converters between different waveguide architectures, will

then be presented.

4.1 WAVELENGTH CONVERTER ARRAY

The active core of the MOTOR chip contains an array of eight wavelength

converters. The technology used to implement these wavelength converters must

78

provide: (1) error-free high-speed operation at 40 Gbps; (2) wide-tunability across

the C band; (3) a small footprint; and (4) low power consumption (i.e., no O/E/O

conversions). Two popular monolithic approaches to achieve these goals with 40

Gbps data rates involve carrier-modulation effects in nonlinear SOAs [1],[2] or field-

modulation effects with a photodiode and a modulator [3],[4]. While each approach

has inherent advantages, the design and fabrication of field-modulation based

wavelength converters tends to be more complex than that of carrier-modulation

based devices, as they require integrated resistors and more complex modulator

structures. In order to target high device yields, we use an SOA-based carrier-

modulation approach to wavelength conversion in the MOTOR chip.

4.1.1 OPERATIONAL PRINCIPLES

Our wavelength converter design exploits cross-phase (XPM) and cross-gain

modulation (XGM) effects in nonlinear (i.e., saturated) semiconductor optical

amplifiers (SOA) within a Mach-Zehnder interferometer (MZI) [2]. In general,

XGM occurs in an SOA when pump signal (i.e., modulated data pulses) depletes the

carriers in an SOA and modulates the gain. If a probe signal (i.e., a CW source) is

also present, the gain modulation changes the amplitude of the probe signal, thereby

transferring an inverted copy of the original data pattern onto the CW source [5].

If the SOA is placed in an MZI, XPM effects can be used for either inverting or

non-inverting wavelength conversion (Fig. 4.1). In the non-inverting mode of

79

Fig. 4.1 Schematic layout of SOA-based MZI wavelength converter.

Fig. 4.2 Response of the SOA gain and MZI phase when a pump pulse is input to a nonlinear SOA in the MZI (adapted from [1] and [6]).

operation, the phase of the MZI is adjusted so that the probe source has an opposite

phase in both branches of the MZI (i.e., the gate is closed). When pump pulses are

input to one side of the MZI, they deplete the carrier concentration in the SOA and

change the overall phase. This opens the MZI gate to emit a signal. The process of

opening and closing the gate carves the original data signal onto the probe

wavelength. This process is limited in speed by the gain recovery time (the time

required for carriers to return their steady-state level after depleted by a pulse) at

which point the original phase of the MZI is restored and the gate is closed (Fig.

80

4.2). This recovery time is a relatively slow exponential process and does not

happen fast enough for wavelength conversion of 40 Gbps data signals.

To operate at high data rates, we use a differential MZI (DMZI) scheme for

wavelength conversion. In this approach, the pump data are split into two parts with

a 50/50 MMI at the input of the chip. The divided signal is then sent to opposite

branches of the MZI. However, the path lengths traversed by the two signals are

different so that the signals reach the MZI at different times. When the first portion

of the data signal reaches an MZI SOA, the process of carrier modulation and phase

change described above begins and the MZI gate is opened. Before the gain

recovers completely, the delayed signal enters the opposite branch of the MZI. This

depletes the carriers in the opposite SOA and realigns the relative phase in the MZI

to close the gate. Opening and closing of the MZI gate is now governed by the

carrier depletion effects in the MZI SOAs rather than the gain recovery. A rigorous

mathematical examination of the carrier and phase dynamics can be found in [6].

In general, improved wavelength conversion efficiency can be achieved if the

input pump power levels to each side of the MZI are slightly imbalanced [2],[6]. In

order to achieve good extinction of the MZI, the delayed and non-delayed pulse

should be matched in amplitude when the delayed pulse enters the MZI. This means

the power of the delayed pulse should be about 1 dB lower than the non-delayed

pulse. Because the path length of the inputs to the MZI differs (and hence the

propagation losses differ), and because the observed splitting ratio of the MMI is

81

highly sensitive to lithographic resolution, variable optical attenuators (VOA) are

included on each input line to control the relative power levels in each branch.

The efficiency of a DMZI wavelength converter depends heavily on two

important characteristics of the nonlinear SOAs used in the MZI [6]:

1) Gain recovery time: The speed at which the gain returns to its normal state

in the MZI SOA is the limiting factor on the speed of operation (without the

differential delay). This is governed by the carrier recovery lifetime, τ’:

1𝜏𝜏′

=1𝜏𝜏

+Γ𝐴𝐴𝑎𝑎𝑃𝑃0

ℏ𝜔𝜔 (4.1)

where Γ is the confinement factor, A is the area of the active region, a is the

differential gain and P0

6

is the probe power. This relationship shows that the

recovery lifetime can be reduced by increasing the ratio of the confinement

factor to the active region area. This ratio was calculated and the subsequent

recovery lifetime was measured in [ ] for several different epitaxial

structures. For a c-MQW structure with 7 QWs, Γ/A is 65%/μm2 and the

gain recovery time was ~60 ps. In our structure, we have increased the

number of QWs from seven to ten which increases the confinement factor

from 9.5% to 14.1%. This gives Г/A of 72%/μm2, so the recovery lifetime

should be closer to that of bulk SOAs (Г/A = 82%/μm2

6

), which was measured

to be ~45 ps [ ]. This recovery time is low enough to perform 10 Gbps

wavelength conversion directly, but 40 Gbps operation still requires the

DMZI approach. Additionally, the gain recovery time decreases with SOA

length because the optical pulse grows in intensity as it passes through the

82

SOA. Thus, carriers at the back end of the SOA are depleted much faster

than those at the front end.

2) Nonlinear phase change: The next parameter of importance is the amount of

phase change that can be achieved in the MZI SOAs. Ideally, we want a

phase change of at least π to maximum output power. The phase swing is

related to the gain of the SOA, so again the confinement factor and length of

the SOA should be large. The overall phase change, Δϕ, is given by:

∆𝜙𝜙 = −𝛼𝛼′2Γ𝐴𝐴𝑎𝑎Δ𝑁𝑁𝑠𝑠 (4.2)

where α’ is the linewidth enhancement factor and ΔNs is the change in sheet

carrier density (Ns – Ntr,s

One important additional consideration with DMZI wavelength conversion is the

possibility of wavelength blocking. Unlike the field-modulated wavelength

). Just like the with the gain recovery, the phase

change can by increased by increasing the ratio of Г/A. The high-gain c-

MQW base structure is thus an ideal candidate in terms of phase swing.

However, the probe power also impacts the amount of phase swing available.

High input CW powers deplete carriers in the MZI SOA leaving fewer total

carriers available to interact with the pump pulses. This means that the pump

pulses will not be able to change the carrier density as much and the

associated phase change decreases. However, high CW power actually

speeds up the gain recovery time. The optimal biasing point for the CW

probe signal will thus be a balancing act between fast gain recovery and large

phase swing.

83

(a) (b)

Fig. 4.3 (a) Schematic diagram of SG-DBR laser structure (active regions shown in blue). (b) Overlay of several SG-DBR lasing spectra, demonstrating the wide tunability of the device (courtesy of Dr. James Raring).

converters of [4], the input data signal exits the device from the same waveguide as

the converted signal. Therefore, in a real routing application the input frequency

comb must be different than the output frequency comb and either a high- or low-

pass filter must be used at the output to remove the original frequencies. This also

means that it is not possible to convert back to the input wavelength with our

wavelength converter design.

4.1.2 SG-DBR LASER DESIGN

The wide tunability of the wavelength converter is accomplished by incorporating a

sampled-grating DBR (SG-DBR) laser as the on-chip CW source (Fig. 4.3a) [7],[8].

Over 40 nm of wavelength tuning is possible with this type of laser by exploiting the

Vernier effect. Efficient SG-DBR lasers have been successfully demonstrated with

84

multiple integration platforms, including QWI [9]. By sampling the grating pattern

in the front and back mirrors (i.e., periodically blanking out grating sections and

leaving only bursts of gratings), the reflectance spectrum becomes comb-like. The

period of the sampling is different in the front and back mirrors so the spacing

between reflectance peaks for each mirror is also different. Therefore, the comb-like

spectra for the front and back mirrors will line up at only one wavelength at a time.

By applying a forward biasing to either mirror, the local refractive index can be

changed to shift the comb of one mirror relative to the other. When two different

reflectance peaks align, the lasing wavelength will change accordingly (Fig. 4.3b).

Using this technique, it is possible to precisely tune our laser to any of the allowed

output wavelengths of the AWGR in order to route the wavelength converted signal

to a specific output port.

Our laser consists of five sections: a 550-μm active gain section, a 470-μm front

and a 910-μm back tuning mirror, a short 100-μm phase tuning pad, and a 175-μm

active absorber. The grating period used in our design was 236 nm, based on a

wavelength of 1540 nm. The etch depth of the grating was targeted at 70 nm to

ensure good filling of the gratings during the regrowth. The width of a grating burst

(Z1) and the sampling period (Z0 Table 4.1) used in our mirrors are given in .

Table 4.1 SG-DBR mirror design parameters

Periods Z1 Z (μm) 0 (μm) Front Mirror 6 3.4 90.8

Back Mirror 10 5.8 99.6

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4.1.3 SOA DESIGN

The most important SOA design parameters for the MOTOR chip are the maximum

gain and output saturation power. The incremental optical gain in an SOA, g0

, is

basically an increase in the density of photons over some length:

𝑔𝑔0 =1𝑁𝑁𝑝𝑝

𝑚𝑚𝑁𝑁𝑝𝑝𝑚𝑚𝑧𝑧

, (4.3)

where Np 7 is the photon density and z is the position [ ],[10]. The unsaturated large-

signal gain, G0

, can then be expressed by:

𝐺𝐺0 = exp(Γ𝑔𝑔0𝐿𝐿) , (4.4)

where L is the length of the SOA. This means that we can increase the maximum

gain in our SOA by increasing the optical confinement, the incremental gain or the

SOA length. Our epitaxial design already provides us with relatively large values of

optical confinement and incremental gain through the use of a strained MQW that is

centered in the waveguide to maximize the active region overlap with the optical

mode. These parameters can only be substantially changed by altering the epi

design, so we are left with the length of the SOA as the simplest way to change the

gain of our SOA.

However, Eqn. 4.2 does not include the effect of gain saturation. Saturation

occurs when the number of input photons exceeds the number of carriers in the SOA

available for stimulated emission. This leads in a significant reduction in gain with

increasing input power. The incremental gain is reduced according to:

86

𝑔𝑔 =𝑔𝑔0

1 + 𝑃𝑃/𝑃𝑃𝑠𝑠 , (4.5)

where g is the saturated gain, P is the power and Ps

is the saturation power.

According to Eqn. 4.5, we want to increase the saturation power of the SOA to

values much greater than the input power to minimize this effect. The saturation

power is related to the width, w, and thickness, d, of the active region, the optical

confinement factor, the differential gain, a, and the carrier lifetime, τ:

𝑃𝑃𝑠𝑠 =𝑤𝑤𝑚𝑚ℎ𝜐𝜐𝑎𝑎Γ𝜏𝜏

. (4.6)

The saturation power can thus be increased by increasing the active region

dimensions or reducing either the differential gain, the optical confinement or the

carrier lifetime. Thus we see that there is an inherent trade-off between maximizing

the gain (↑ a and ↑ Γ) and maximizing the saturation power (↓ a and ↓Γ). The

dependence of saturation power on SOA length is seen in the output saturation power

of the SOA, Pos, or the point at which G0

has been reduced by half:

𝑃𝑃𝑚𝑚𝑠𝑠 =𝐺𝐺0ln(2)𝐺𝐺0 − 2

𝑃𝑃𝑠𝑠 , (4.7)

Since G0

Fig. 4.4

increases with length, we expect longer SOAs to saturate more readily.

shows a simulated gain curve for a c-MQW SOA, showing the roll-off

from the maximum gain for increasing input powers due to saturation effects. In

some cases, operating an SOA in the nonlinear (i.e., saturated) regime is very useful.

For instance, the MZI SOAs used in our device should be operated in the nonlinear

region so that input pump pulses deplete all the carriers in the SOA and cause a large

phase swing. However, there are many cases in which SOAs should only be

87

Fig. 4.4 Simulated large-signal gain curve for a c-MQW SOA (adapted from [10]).

operated in the linear (i.e., unsaturated) regime. This is true for our preamplifier

SOAs. If these SOAs are operated in the nonlinear regime, the carriers cannot

recover fast enough to ensure that subsequent pulses in a bit stream experience the

same gain as the first pulses into the SOA. This leads to pattern dependence in the

SOA and results in an increased power penalty for wavelength conversion. To avoid

this, it is important to operate the SOA above the 1-dB output saturation power point,

or the point at which the maximum gain has dropped by 1-dB (see Fig. 4.4).

The MOTOR chip integrates SOAs with three very different functions. First,

285-μm booster SOAs are used in conjunction with the CW source. The SG-DBR

output power is split by a 50/50 MMI and fed into the MZI region. It is important to

supply sufficient and equal CW power to the MZI SOAs in both branches so that the

phase is balanced. The booster SOAs help to overcome losses in the splitting

process and provide control over the relative power input to the MZI (since

88

fabrication variations can alter the splitting ratio of the MMI). Because the SG-DBR

output power is already high, the booster SOAs are saturated. This is actually

beneficial in reducing the ASE noise from the boosters.

Second, nonlinear SOAs are required in the Mach-Zehnder for XPM and XGM.

These SOAs are ~1000 μm in length in order to reduce the carrier recovery time. In

[6] it was shown that more than a full π phase swing is possible with 7 centered QWs

of similar composition. Our epitaxial design was adjusted to include 10 centered

QWs to increase the confinement factor, which should provide improved

performance in the cross-phase response of our MZI SOAs.

Finally, 300-μm preamplifier SOAs are inserted before the input to the MZI to

amplify the input data signal. These SOAs must provide an optimal combination of

high gain (to ensure that the input pulses have enough power to deplete the carriers

in the MZI SOAs) and high saturation power (to avoid pattern dependent distortions

that arise if the preamplifier SOAs are operated in the nonlinear regime). Because

we cannot change the confinement factor or the differential gain of these SOAs, we

deliberately kept the length of these SOAs relatively short. We also use a wider

ridge width of 5.6 μm in the preamplifier region for improved saturation power.

4.1.4 DIFFERENTIAL DELAY LINE

DMZI operation is accomplished by splitting the input data signal and time-delaying

the arrival of the data in one branch of the MZI with respect to the other. As shown

89

(a) (b)

Fig. 4.5 Differential delay line: (a) optical microscope image; (b) SEM image.

in [11], this delay should be about 11-12 ps (roughly the pulse width of the input data

in our system). If the delay time is too short, the delayed pulse will realign the phase

of each branch of the MZI before the gate can open all the way in response to the

non-delayed pulse. This leads to a reduced output power and a higher power penalty.

In principle, the delay could be made longer but that would increase the overall

footprint of the component. To minimize the size of this delay we employ a deeply-

etched waveguide with compact, 105-μm radius bends (Fig. 4.5). The delay line in

our device was ~760 μm, which corresponds to a 9.7 ps delay. Although this is

slightly shorter than the ideal delay time shown in [11], it allows us to decrease the

size of delay and should contribute < 1 dB power penalty in the final device.

4.2 ARRAYED-WAVEGUIDE GRATING ROUTERS

The realization of robust AWGRs (also known as phased-arrays or PHASARs) was a

significant breakthrough for integrated optics, driven by the need for an integrated

Deeply-etched delay line

90

Fig. 4.6 Schematic illustration of an N x N AWGR.

(de)multiplexer solution [12]. When used for this purpose, an AWGR can combine

(or separate) multiple data signals encoded on different wavelengths to significantly

improve the transmission capacity of optical fiber. Since their conception in 1988 by

Smit [13], the arrayed-waveguide concept has been extended to produce N x N

wavelength-selective routers [14],[15] which is the key application of interest for the

8 x 8 MOTOR chip.

4.2.1 OPERATIONAL OVERVIEW

Fig. 4.6 shows a typical N x N AWGR consisting of several important components:

input and output access waveguides, input and output star couplers (also known as

free-propagation regions or FPRs) and an array of waveguides with varying length

between the star couplers. As light enters the slab waveguide of the input star

coupler through one of the input access waveguides, the beam is no longer confined

91

Fig. 4.7 Wavelength-based routing pattern for an 8 x 8 AWGR (adapted from [16]). The ports are represented by letters and the wavelength channels are represented by numbers.

laterally and it diverges. The length of the star coupler is chosen so that the input

signal is imaged onto all arrayed waveguides. Each waveguide in the array is

incrementally longer than the previous by a constant path length difference, based on

a specific design (or center) wavelength. If the input signal is at this center

wavelength, the light in each arrayed waveguide will add up in phase at the output

star coupler, and will converge in the mirror-image port. If the signal wavelength is

not at the center wavelength, the light in the arrayed waveguides will not be in phase

at the output star coupler so the beam will be tilted and converge toward a different

output access waveguide.

This effect allows one to design a system for wavelength-based routing. Fig. 4.7

shows how various input wavelengths are routed in an N x N AWGR (with N = 8 as

in the MOTOR chip). Each input port can support N different wavelengths that

correspond to one of the N output ports [16]. These N wavelengths are periodic and

repeat over some wavelength range, known as the free spectral range (FSR). Since

the MOTOR chip contains input wavelength converters, it can accept data of any

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Table 4.2 AWGR design parameters

Parameter Value Star coupler index 3.284401

Index contrast 0.02015

Waveguide width (wg) 2.2 μm

V-parameter 3.2395 Center wavelength (λc) 1.55 nm

Channel spacing (Δλch) 200 GHz

Number of ports (N) 8

Receiver spacing (dr) 9 μm

Array spacing (da) 9 μm

Free spectral range 12.8 nm

Length difference in array arms (ΔL) 49.5 μm

Star coupler length (Ra) 1373.1 μm

Aperture width (θa) 0.1949

Number of arrayed waveguides 34

wavelength in one of the input ports and convert that data to the wavelength that

corresponds to the destination port of interest.

4.2.2 GENERAL DESIGN PARAMETERS

There are many freely-specified variables in the design of an AWGR that determine

the overall performance and footprint. The most important independent and

dependent variables are summarized in Table 4.2 along with the values used in this

work. In general, we follow a design philosophy similar to [12], but we also employ

commercial beam propagation software to analyze the expected spectral response for

93

various parameters including unintentional phase errors. The parameters used in an

AWGR design should be selected with the goal of minimizing crosstalk between

ports and reducing the overall loss.

Specifying the geometry of an AWGR largely depends on several key user-

defined variables:

1) Waveguide architecture: The waveguide structure plays a vital role in

determining the footprint, geometry, and effective index of the AWGR. For

example, increasing the lateral index contrast between the core and the

cladding allows for tighter bends in the arrayed waveguides so more compact

solutions are possible. The designer can also arbitrarily select the waveguide

width which determines the V-parameter. However, if the waveguide width

supports multiple modes, the performance of the AWGR will degrade. In our

device, we use a 2.2-μm wide buried rib structure with a relatively low index

contrast. The impact of the etch depth on index contrast and AWGR

performance will be analyzed further in the next section.

2) Basic AWGR parameters: There are several basic design parameters that

depend solely on the application of interest, such as the number of input and

output ports. The center wavelength, λc, of the device can also be freely

chosen (1550 nm in our case). The channel spacing (i.e., the difference in

wavelength between two consecutive allowed output wavelengths) can also

be freely selected for a given application. However, the channel spacing

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(Δλch

) is inversely proportional to the path length difference between arrayed

waveguide arms, ΔL, given by:

Δ𝐿𝐿 =𝑐𝑐

𝑁𝑁𝑔𝑔𝑁𝑁∆𝜆𝜆𝑐𝑐ℎ , (4.8)

where c is the speed of light in vacuum, Ng

3) Star coupler waveguide spacing: The spacing of the input receiver

waveguides (d

is the group index, and N is the

number of input waveguides. This means that the AWGR footprint will

increase with narrower channel spacings.

r) and output array waveguides (da

16

) at the star coupler can also

be specified by the designer. These spacings can be the same or different,

but both are limited by lithographic resolution. The receiver spacing directly

impacts the crosstalk of the AWGR. If the receiver waveguides are too close

to each other, coupling can occur between adjacent waveguides through the

exponential mode tails [ ]. The array spacing, on the other hand, should be

chosen as close together as possible to reduce coupling losses between the

divergent beam in the star coupler and the arrayed waveguides. We chose a

spacing of 0.8 μm as a conservative estimate of our lithographic limits, but in

future designs, this value should be cut in half to reduce coupling losses.

With the above parameters selected, the dependent variables of the design can be

determined. Since our final aim is a router, we need a cyclic FSR without dead

space in between. This condition can be satisfied by:

𝐹𝐹𝐹𝐹𝐹𝐹 =𝑐𝑐

𝑁𝑁𝑔𝑔𝑁𝑁∆𝐿𝐿= 𝑁𝑁∆𝑒𝑒𝑐𝑐ℎ . (4.9)

95

In reality, the FSR has a dependence on the input and output port [17], so Eqn. 4.9 is

only approximate. Next, we calculate the length of the star coupler, which is equal

to the ratio of da

12

to the divergence angle of the arrayed waveguides. Rearranging the

equations in [ ] yields the following relationship for the star coupler length, Ra

:

𝐹𝐹𝑎𝑎 =𝑁𝑁𝑠𝑠𝑡𝑡𝑎𝑎𝑒𝑒 𝑚𝑚𝑒𝑒𝑚𝑚𝑎𝑎𝑁𝑁

𝜆𝜆𝑐𝑐 , (4.10)

where Nstar

18

is the effective index in the slab waveguide of the star coupler. We next

need to determine the number of waveguides to use in the array. Too many

waveguides in the array can actually degrade the filter function and increase the

crosstalk [ ]. The number of waveguides, Na

, is given by:

𝑁𝑁𝑎𝑎 =2𝜃𝜃𝑎𝑎𝐹𝐹𝑎𝑎𝑚𝑚𝑎𝑎

+ 1, (4.11)

where θa is the aperture width, which is typically 2-3X the width of a Gaussian far-

field, θ0 12. This is estimated as in [ ] by:

𝜃𝜃0 ≈𝜆𝜆𝑐𝑐

𝑁𝑁𝑠𝑠𝑡𝑡𝑎𝑎𝑒𝑒1

𝑤𝑤𝑤𝑤𝑔𝑔 �0.5 + 1𝑉𝑉 − 0.6�

(4.12)

where wwg

4.2.3 BURIED RIB DESIGN

is the waveguide width and V is the V-parameter.

Using the above equations and the parameters in Table 4.2, we have designed an 8 x

8 AWGR using a buried rib waveguide structure (Fig. 4.8). The choice of

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Fig. 4.8 Layer structure and optical mode contours for the buried rib waveguide design.

waveguide architecture is important in the AWGR design as it will impact the

overall footprint and the excess loss in this component. The buried rib design allows

us to turn the waveguide at any angle since the dry etch used to define the rib is

anisotropic and not crystallographic. It also helps to minimize reflections at the

inputs to and outputs from the star coupler since we etch only partially into the

waveguide layer.

The rib is defined by etching through the implant buffer layer (left in the AWGR

section to reduce free-carrier absorption), and into the upper portion of the

waveguide layer. The depth of this etch directly determines the index contrast

between the rib and the lateral cladding. As shown in Fig. 4.9a, the index contrast

increases as the rib height in the waveguide layer increases, until the etch has gone

through the entire waveguide and MQW region (creating a buried channel

waveguide structure). The index contrast determines several important parameters

97

(a) (b)

Fig. 4.9 (a) Effective index contrast versus the rib height (or etch depth). The thickness of the implant buffer layer above the waveguide is not included in this plot. (b) Simulated crosstalk versus rib height. The waveguide layers (light green) and MQW region (yellow) are also depicted.

in the AWGR including the V-parameter (which impacts the number of waveguides

in the array), the minimum bend radius for the arrayed waveguides (which decreases

with rib height, allowing more compact bends), and the crosstalk. Fig. 4.9b shows

the relationship between rib height and crosstalk holding all other parameters

constant. From the perspective of compactness and crosstalk, it would make sense to

etch through the waveguide entirely to make a channel waveguide. However, this is

problematic on two fronts. First, increasing the rib height can complicate the

regrowth as there is a larger vertical quaternary interface that must be buried without

air voids. Second, the further down we etch the more the mode will interact with

etched sidewalls. If the etch is rough, this will translate into high scattering loss. To

avoid these complications, we target a rib height of 70 nm. This only provides an

index contrast of ~0.02 between the core and lateral cladding, but should provide

98

sufficient optical confinement and low crosstalk. However, this also increases the

minimum bend radius in the arrayed waveguides and result in a larger footprint.

In addition to reducing crosstalk, we want to reduce losses at the inputs to and

outputs from the star coupler. Our design thus employs flared waveguides at the

inputs to the star couplers and tapered waveguides at the outputs. The flares and

tapers are 100 μm long in order to minimize the excitation of higher order modes

(Fig. 4.10). Because the index contrast in our buried rib design is low, the mode is

weakly confined. If our arrayed waveguides are placed too close to each other over

a long enough propagation length, we can expect that coupling between the

waveguides will occur. Since we need to keep da small at the star couplers, these

tapers allow us collect the divergent field and rapidly increase the distance between

the arrayed waveguides to reduce crosstalk.

Fig. 4.10 Excitation of higher order modes due to a tapering waveguide versus the taper length.

99

With our waveguide geometry and design parameters specified, we can simulate

the expected spectral response of our AWGR. This was done using an AWGR

design utility that is part of the RSOFT BeamProp software package4

17

. This utility

first simulates the input star coupler response and determines the coupling into each

arrayed waveguide. The propagation length difference between each array arm is

then simulated using the field profile from the input star coupler. The new field,

including the phase differences in the array arms, is then coupled into the output star

coupler which is simulated using beam propagation techniques [ ]. Fig. 4.11 shows

the spectral response for all 8 input ports of our device. This simulation predicts a

crosstalk of < -30 dB for all ports.

4.2.4 PRACTICAL CONSIDERATIONS

The simulated results from the last section represent an optimistic view of our

AWGR performance and assume that the fabrication will be perfect. In reality,

however, fabrication imperfections, etch depth variations across the AWGR and

errors in the lithography mask due to resolution limitations in the mask writer will

contribute to phase errors that will increase the crosstalk and loss. BeamProp can

simulate the effect of these random phase errors by changing the phase in each

arrayed waveguide by a random amount between zero and a user-specified value.

Fig. 4.12 shows the spectral response for input port #4 with random phase errors of 4 The BeamProp utility uses a more complicated relationship than Eqn. 4.3 to calculate the slab length (see [17]) so slab properties are slightly different in the simulation than those calculated above.

100

Fig. 4.11 Simulated transmission for each input/output port combination an 8 x 8 AWGR.

101

various amounts. When compared with the spectral response for input port #4 in

Fig. 4.11, these results demonstrate how phase errors can significantly increase the

crosstalk in the device and diminish overall performance. It is therefore critical to

optimize the fabrication conditions as much as possible to reduce these errors.

Additionally, because it is so important to maintain the phase relationship in the

arrayed waveguides, it is also good practice to use either commercial or custom

software to plot out the AWGR structure rather than attempting to draw out the

device by hand5.

Fig. 4.12 Effect of random phase errors in the arrayed waveguides on the output spectral response.

5 In this work, we used a custom Matlab script written by Walter Donat at UCSB to generate the actual AWGR layout.

102

Fig. 4.13 Several possible layouts for our AWGR.

The final design decision regards the actual geometry of the AWGR as there are

many different implementations of the arrayed waveguides. Three of the possible

designs considered in this work are shown in Fig. 4.13. The first design maintains a

constant radius between the array arms which are linked together with a straight

section of variable length to achieve a compact footprint. The design is similar to

that of Takahasi et al. [19], but avoids any sharp 90° bends when transitioning to the

straight section of the array. The second design in Fig. 4.13 allows the bend radius

to change so the mode propagates without seeing any sharp bend or waveguide

junctions. These junctions can lead to the excitation of higher order modes and

generate unequal losses in the array arms [12]. The third option shown in Fig. 4.13

is designed so that the input and output access waveguides are perpendicular to each

other. This design was considered because we decided that the input and output

waveguides of the entire MOTOR device should be perpendicular to each other for

103

compactness. However, this design is significantly larger than the other two and

may perform worse because of the number of waveguide junctions involved. In the

final MOTOR chip, we elected to use the constant radius AWGR design with a bend

radius of ~800 μm since it was the most compact solution.

4.3 PASSIVE INTERCONNECTS

In discrete component systems, each element is connected via fiber optic cable. In a

PIC, however, we use passive waveguide elements to link components. These

waveguides can be straight or bent and should be optimized to minimize propagation

losses. We also need elements for splitting and combining optical signals and

elements that enable efficient mode conversion between different waveguide

architectures. As these are crucial components in the MOTOR chip, this section will

briefly discuss their important design aspects.

4.3.1 MMI SPLITTERS AND COMBINERS

All splitting and combining of optical signals in our device is handled with multi-

mode interferometers (MMIs). These structures are highly compatible with PICs as

they typically have compact dimensions and a large optical bandwidth [20]. MMIs

operate on the principle of self-imaging, meaning that an input field is replicated

periodically along a multi-mode waveguide. This implies that the waveguide

104

(a)

(b)

Fig. 4.14 Effect of MMI width and length on the splitting ratio for: (a) 1 x 2 configuration; and (b) 2 x 2 configuration. The optical power as it propagates through the MMI is also shown for each case.

section must support many modes, so the width of the MMI will be an important

parameter in the imaging process. The MMI length is also important as the field

profile at the end of the interferometer will be coupled to output waveguides. In the

MOTOR chip, we use both 1 x 2 and 2 x 2 MMI configurations. The 1 x 2 MMI is

located at the output of the SG-DBR to split the CW signal and send it to both sides

105

of the MZI. 2 x 2 MMIs are found in several locations in the chip, including one at

the input of the device for differential operation, one after each preamplifier to

combine the pump and probe signals and one at the output of the MZI. In the case of

the MZI MMIs there are two output MMI ports but only one output is needed.

Although a 2 x 1 MMI might seem more appropriate here, a 2 x 1 (or 1 x 2) MMI

always causes about 3 dB of scattering loss. Rather than create stray light by

scattering, we use a 2 x 2 configuration with one output terminated. We still lose 3

dB of light, but we can at least control where the light it is going.

Fig. 4.14 shows the optical field in both types of MMIs along with the impact of

MMI width and length. Because of the sensitivity of these MMIs to width

variations, it is very important to ensure that the lithography step used to define these

structures comes out correctly. Variations in focus across the sample can actually

widen or narrow device features, significantly changing the splitting ratio of the

MMIs.

4.3.2 WAVEGUIDE TRANSITION ELEMENTS

Because our integration strategy calls for the use of multiple waveguide architectures

in different regions of the device, it is important to ensure that the optical mode can

propagate between these regions without significant loss or reflections. The optical

mode shape and width is different in each of the three waveguide structures in

MOTOR due to the difference in index contrast between the core and lateral

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Fig. 4.15 Mode profiles for the various waveguide architectures in MOTOR: (a) surface ridge; (b) deeply-etched ridge; and (c) buried rib.

cladding (Fig. 4.15). We thus use compact mode converter elements to resize the

optical mode and improve the coupling between waveguide designs. There are two

types of transitions in our device: one between the surface and deeply-etched ridges

at the delay line and one between the surface ridge and the buried rib at the input to

the AWGR section.

One approach that has been proposed for the transition from surface ridge to

deeply-etched ridge at the delay line is to adiabatically taper the surface ridge section

into the deeply-etched region [6]. Although simulations show that this type of

transition provides more than 98% coupling even with a 0.3 μm lateral misalignment

of the taper, any lateral misalignment leads to the excitation of higher order modes in

the deeply-etched ridge. Higher order modes will be lossy due to scattering at the

waveguide sidewalls so the actual loss through the delay line is higher than

predicted.

Instead, we use a “mode-matching” transition similar to that of [21], in which the

surface ridge waveguide is rapidly flared by ~0.25 μm in width on each side just

107

Fig. 4.16 SEM images of the “mode-matching” transition between the surface and deeply-etched waveguides (top view on left and side view on right).

Fig. 4.17 Coupling efficiency from surface to deeply-etched waveguide as a function of the distance between the waveguide flare and the start of the deeply-etched section (zero on the graph represents the position of the waveguide flare.

before the transition to the deeply-etched section (Fig. 4.16). This widening of the

waveguide allows the mode to expand into a shape that is more similar to that of the

deeply-etched waveguide. The waveguide then tapers down over some distance to

the desired width of the deeply-etched section. In our design we use a taper length

of 100 μm to minimize loss, but simulations show that this length can be reduced to

around 50 μm without a significant increase in loss. Unlike the adiabatic taper

Top View

Side ViewWaveguide

Flare

108

design, this type of transition is essentially completely tolerant to lateral

misalignment, barring a severe mistake during the lithographic exposure (Fig. 4.16).

Fig. 4.17 shows that the transition is also very tolerant to axial misalignment. As

long as the deeply-etched region begins after the flare, very efficient coupling

between the two waveguide structures can occur. In fact, > 99% coupling from the

surface ridge to the deeply-etched region is possible with proper alignment. Since

the flared waveguide region is only 0.25 μm wider on each side than the initial

surface ridge region, the excitation of higher order modes is kept below 1% at this

junction. The optical loss measured through delay lines with this type of transition

showed significant improvement over those with the adiabatic transition (see

Chapter 6).

Coupling between the surface ridge and the buried rib waveguide of the AWGR

region was achieved using butt-coupled waveguides. The surface ridge waveguide is

flared to a width of 5 μm over a length of 100 μm, and is then directly butt-coupled

to a 5 μm wide buried rib waveguide (Fig. 4.18). The buried rib waveguide is then

tapered down to 2.2 μm (the waveguide width used in the AWGR). The length of

the taper and flare are chosen to minimize the excitation of higher order modes. This

transition is not as tolerant to misalignment as the surface to deeply-etched

transition, but Fig. 4.19a shows that > 97% coupling is still achieved with a ± 0.2 μm

lateral misalignment (which can be reasonably obtained with our current stepper

system). In addition to lateral alignment, it is important to butt-couple the ridge and

109

Fig. 4.18 Optical microscope image of surface ridge to buried rib butt-couple transition.

(a) (b)

Fig. 4.19 Coupling efficiency of our flared/tapered butt-couple transition between surface ridge and buried rib waveguides: (a) tolerance to lateral misalignment; and (b) tolerance to axial misalignment (zero represents perfect axial alignment of the surface ridge and buried rib waveguides).

rib as tightly as possible. Fig. 4.19b shows that the coupling eventually degrades if a

large gap is left between the ridge and rib.

4.4 CHAPTER SUMMARY

This chapter provides an overview of the key design considerations of our

monolithic tunable optical router chip. The wavelength converters operate at 40

RidgeRib

110

Gbps using a DMZI structure. Input pump pulses deplete carriers in saturated SOAs

within a MZI to cause a phase change which modulates the MZI. This phenomenon

can be used to write an input data pattern onto a CW source. The DMZI approach is

possible by integrating a passive delay line at the input of the chip, which helps to

overcome the limits of gain recovery in the MZI SOA, so that 40 Gbps wavelength

conversion is possible.

The wavelength converter array is connected to an AWGR. This component

should be compact, low-loss, and have low crosstalk between ports. We have

outlined the design methodology used in this work, including the equations needed

to calculated important component parameters. Our device has an 8 x 8

configuration with a 200 GHz channel spacing. The AWGR is realized using a

buried rib waveguide architecture and uses a constant bend radius design to

minimize the overall footprint.

This chapter also addressed the key issues for other active and passive

components in the MOTOR chip, including SOAs, the delay line, splitters and

couplers, and the transitions between waveguide architectures. In each case, we

have attempted to optimize these components without adding unnecessary

processing complexity. The results of these designs will be shown in Chapter 7.

111

REFERENCES

[1] M. L. Mašanović, "Wavelength-Agile Photonic Integrated Circuits For All-Optical Wavelength Conversion," Ph.D. Dissertation, University of California, Santa Barbara, 2004.

[2] V. Lal, M. L. Masanovic, J. A. Summers, G. Fish, and D. J. Blumenthal, "Monolithic Wavelength Converters for High-Speed Packet-Switched Optical Networks," IEEE Journal of Selected Topics in Quantum Electronics, vol. 13, no. 1, pp. 49-57, Jan. 2007.

[3] A. Tauke-Pedretti et. al, "Separate Absorption and Modulation Mach-Zehnder Wavelength Converter," Journal of Lightwave Technology, vol. 26, no. 1, pp. 91-98, 2008.

[4] M. Dummer, J. Klamkin, A. Tauke-Pedretti, and L. Coldren, "40 Gb/s widely tunable wavelength converter with a photocurrent-driven high-impedance TW-EAM and SGDBR laser," in IEEE International Semiconductor Laser Conference, 2008, pp. 145-146.

[5] T. Durhuus, B. Mikkelsen, C. Joergensen, S. L. Danielsen, and K. E. Stubkjaer, "All-Optical Wavelength Conversion by Semiconductor Optical Amplifiers," IEEE Journal of Lightwave Technology, vol. 14, no. 6, pp. 942-944, Jun. 1996.

[6] V. Lal, "Monolithic Wavelength Converters for High-Speed Packet Switched Optical Networks," Ph.D. Dissertation, University of California, Santa Barbara, 2006.


[8] V. Jayaraman, Z. Chuang, and L. A. Coldren, "Theory, design, and performance of extended tuning range semiconductor lasers with sampled gratings," IEEE Journal of Quantum Electronics, vol. 29, no. 6, pp. 1824-1834, Jun. 1993.


[10] J. Raring, "Advanced InP Based Monolithic Integration Using Quantum Well Intermixing and MOCVD Regrowth," Ph.D. Dissertation, University of California, Santa Barbara, 2006.

[11] V. Lal, M. L. Masanovic, J. A. ,. C. L. A. Summers, and D. J. Blumenthal,

112

"Performance Optimization of an InP-Based Widely Tunable All-Optical Wavelength Converter Operating at 40 Gb/s," IEEE Photonics Technology Letters, vol. 18, no. 4, pp. 577-579, Feb. 2006.

[12] M. K. Smit and C. v. Dam, "PHASAR-Based WDM-Devices: Principles, Design and Applications," IEEE Journal of Selected Topics in Qunatum Electronics, vol. 2, no. 2, pp. 236-250, Jun. 1996.

[13] M. K. Smit, "New focussing and dispersive planar component based on an optical phased array," Electronics Letters, vol. 24, no. 7, pp. 385-386, Mar. 1988.

[14] C. Dragone, "An N*N optical multiplexer using a planar arrangement of two star couplers," IEEE Photonics Technology Letters, vol. 3, no. 9, pp. 812-815, Sep. 1991.

[15] C. Dragone, C. A. Edwards, and R. C. Kistler, "Integrated optics NxN multiplexer on silicon," IEEE Photonics Technology Letters, vol. 3, no. 10, pp. 896-899, Oct. 1991.

[16] C. van Dam, "InP-based polarisation independent wavelength demultiplexers," Ph.D. Disseration, Delft University of Technology, Eindhoven, 1997.

[17] RSOFT Design Group, BeamProp AWG Utility Manual. 2004.

[18] M. L. Mašanović, Univeristy of California, Santa Barbara Personal Communication, 2009.

[19] H. Takahashi, K. Oda, H. Toba, and Y. Inoue, "Transmission Characteristics of Arrayed Waveguide N x N Wavelength Multiplexer," Journal of Lightwave Technology, vol. 13, no. 3, pp. 447-455, Mar. 1995.

[20] L. Soldano and E. C. M. Pennings, "Optical Multi-Mode Interference Devices Based on Self-Imaging: Principles and Applications," Journal of Lightwave Technology, vol. 13, no. 4, pp. 615-627, Apr. 1995.


113

Chapter 5

Epitaxial Growth

The InP/InGaAsP materials system is an ideal candidate for PIC development,

especially for telecommunications applications. By adjusting the composition of

Group III and Group V elements, a wide range of lattice-matched or strained

In(x)Ga(1-x)As(y)P(1-y) epitaxial layers with photoluminescence (PL) wavelengths

spanning across the entire C-band can be grown on an InP substrate. This chapter

will explore some of the epitaxial options available both at UCSB and commercially.

Specific focus will be given to the metal-organic chemical vapor deposition

(MOCVD) process, as it was predominantly used in this work. Our base epitaxial

structure and cladding regrowth design will be discussed in detail and important

considerations with each growth will be addressed.

5.1 EPITAXIAL GROWTH OPTIONS

Several methods of epitaxial growth have been developed over the last 30 years in

order to generate single-crystal layers of InP and related materials. The most

common techniques used today include liquid phase epitaxy (LPE), metal-organic

chemical vapor deposition (MOCVD), and molecular or chemical beam epitaxy

114

(MBE or CBE) [1]. Each technique has strengths and weaknesses, but all

approaches have reached a sufficient maturity level such that they are used

commercially and in academia. LPE involves transferring a substrate between liquid

solutions composed of the constituent elements of a desired layer at near equilibrium

conditions. The bath and substrate are heated to promote growth of a solid film.

The preparation for LPE growth requires very accurate measurement of the

components in the melt to ensure that the correct compositions are grown. Because

of these requirements, this technique is declining in popularity and was not

investigated in this work. Instead we chose to explore the use of MOCVD-grown

and CBE-grown material. The MOCVD-grown epi was prepared either in our in-

house reactor system or was purchased from LandMark Optoelectronics Corporation

in Taiwan or the Alcatel III-V Lab in France. The CBE-grown material was

purchased from the III-V Lab, as UCSB does not presently house such a system for

InP growth.

MOCVD growth involves the transfer of metal atoms that are bonded to organic

compounds to a heated substrate in the gas phase [2]. The metal-organic source

materials are either in liquid or solid form. A nonreactive carrier gas is bubbled

through the source material to pick up metal-organic vapor above the source and

transport it to the reaction chamber. The source material must then diffuse through a

stagnant gas boundary layer at the substrate surface before it adsorbs to the surface.

The substrate is heated to around 600°C or more to allow the metal-organic to

pyrolyze at the surface and release the organic ligands, leaving the metal atom

115

behind. Metal-organic sources are common for Group III elements, but are also

available for Group V elements, although gas sources are probably more common in

industry. The pressure in the reactor is typically on the order of a few hundred torr,

but lasers have also been demonstrated using atmospheric pressure MOCVD [3].

The gas flows are adjusted using computer-controlled mass flow controllers (MFCs),

so abrupt interfaces can be grown between layers of different composition (such as

QWs and barriers). Because MOCVD is a gas-phase reaction process, a wide

number of intermediary reactions are possible as depicted in Fig. 5.1. Additionally,

gas flow dynamics play a major role in the growth patterns. For instance, if the

switching between gas flows is slow, memory effects can be present in the growth

and interfaces will not be sharp. For the most part, these issues can be addressed

with the proper design of the gas control system, the substrate chuck and the quartz

reactor itself. However, MOCVD films generally show some thickness and PL

variations across the wafer because of the gas-flow dependent growth.

Fig. 5.1 Possible reaction pathways for MOCVD constituents. Figure is adapted from MATRL 227 class notes.

116

CBE growth is a relatively new technique that is based on the principles of gas-

source MBE [4]. Unlike the solid sources used in traditional MBE, in CBE growth

the precursor material is obtained from either gas sources or from the vapor of metal-

organic sources. The substrate is typically kept around 500°C during growth

(notably lower than that of MOCVD growth). This temperature is sufficient to

pyrolyze the metal-organic sources at the substrate, but high temperature cells are

typically required to crack the gas-phase sources. This growth method occurs at

very low pressures (< 10-4

5

torr) so elements approaching the substrate have a long

mean free path and impinge on the surface as a molecular beam, without the need to

diffuse through a boundary layer as in MOCVD [ ]. Additionally, a fast-moving

mechanical shutter system can be employed to quickly modulate the molecular

beam, allowing the growth of digital interfaces between different layers of material.

This provides greater control over composition, film thickness, and PL.

(a) (b)

Fig. 5.2 PL wavelength wafer map for (a) CBE-grown epi and (b) MOCVD-grown epi.

117

(a) (b)

Fig. 5.3 Atomic force microscopy scan of the as-grown surface of: (a) CBE-grown epi; and (b) MOCVD-grown epi. The step-like pattern in (b) is due to a 0.2° miscut in the substrate surface.

The trade-offs in terms of material quality between the CBE-grown and the

MOCVD-grown epi used in this work are illustrated above. Fig. 5.2 compares the

PL wavelength for our standard MQW stack across a 2” wafer. Clearly, the CBE-

grown sample has much tighter PL control than the MOCVD-grown sample.

However, as shown in Fig. 5.3, AFM scans reveal that the RMS roughness of the

CBE-grown epi purchased from the III-V Lab is significantly larger (~2.8X) than

that grown by our in-house MOCVD. The roughness of the CBE-grown film is most

likely a result of the growth conditions used by our external vendor, and could likely

be made smoother in the future by adjusting parameters such as the substrate

temperature. Even though CBE-grown material has a more uniform PL (which is

important in large-scale PICs so that all device components have essentially the

same gain spectrum), we found that CBE material performed far worse in the QWI

process than MOCVD grown material (see Chapter 6). Therefore, the base growth

118

and subsequent regrowth used to fabricate the MOTOR chip were performed using

only MOCVD-grown structures. The material used in many experiments in this

work, including the characterization of the quality of the new implant buffer process

(see Chapter 3) was grown on our in-house MOCVD system. The base growth and

cladding regrowth used for the actual MOTOR chip were grown via MOCVD by

LandMark and the III-V Lab, respectively.

5.2 MOCVD AT UCSB

Since a good portion of this work involved growth and characterization in the UCSB

MOCVD lab, a basic overview of the reactor system and our standard growth

procedure (including the determination of flow and growth parameters) is included

here. More extensive analysis of the reactor system is available in [6], [7], and [8].

5.2.1 REACTOR SYSTEM

At UCSB we use a Thomas Swan Ltd. reactor system for InP/InGaAsP MOCVD

growth. The reactor section of the system consists of an inner and an outer quartz

liner (Fig. 5.4). The inner liner is the primary reactor vessel. Input gases are mixed

at the entrance of the inner liner using a stainless steel nozzle, before they flow over

a SiC-coated graphite susceptor block that contains a 2” chuck on which a sample

sits. The chuck is rotated during growth to improve uniformity using an airfoil

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Fig. 5.4 Thomas Swan horizontal MOCVD reactor design.

mechanism. H2 is fed to the backside of the chuck through a dog-bone shaped quartz

tube to gently raise it from the susceptor and rotate it. The top side of the reactor

tapers vertically downward across the susceptor so that the growth rate is uniform in

the front and back of chuck. The outer liner provides an additional protective barrier

between the reactor and the ambient environment and is purged during growth with

pure carrier gas. The reactor is heated using a bank of six consecutive IR lamps

directly below the susceptor. The lamps are divided into three zones (two bulbs

each) that can be independently programmed. The center zone is usually held

between 600-630°C (depending on the desired layer structure) and is kept 10°C

higher than the front and back zones as this has been shown to improve growth

uniformity. The reactor pressure is pumped to < 15 torr and then backfilled to

atmospheric pressure three times prior to growth to purge the system of any

unwanted gases. The reactor pressure is then held at 350 torr during growth.

120

Our system uses H2 as a carrier gas for all sources. The total carrier flow in the

system is 16 slpm and is evenly divided between an upper and a lower carrier line.

The upper line feeds the Group V and n-type dopant sources and the lower line feeds

the Group III and p-type dopant sources. The lines flow H2 to each source bubbler,

which carries precursor material to the reactor or the vent. The switching between

the run and vent lines is handled through a computer controlled valve system.

5.2.2 METAL-ORGANIC PRECURSORS AND OTHER SOURCES

The sources and bubbler conditions used in our reactor are listed in Table 5.1.

Unlike many commercial MOCVD manufacturers, we utilize metal-organic sources

for both Group III and Group V constituents. Arsine and phosphine gas are often

preferred in industry as the Group V sources because of their cost and purity [7].

However, these gases are extremely toxic and flammable, so we instead use metal-

organic-based sources for safety. Not only are these sources significantly less toxic,

they also have high vapor pressures and low pyrolysis temperatures [6].

Furthermore, it has been shown that these sources do not contribute significant levels

of unwanted carbon into growing films [9]. On the Group III side, the gallium

source is in liquid form, but the indium source is in solid form. To increase the

partial pressure above the solid InP source (i.e., the amount of material that can be

picked up by the carrier gas), we use a dual bubbler configuration with the outlet of

the first In bubbler is connected to the inlet of a second In bubbler.

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Table 5.1 Metal-organic source conditions for the UCSB MOCVD system.

Metal-Organic Bubbler Bath Temperature

(°C)

Bubbler Pressure

(Torr) Trimethyl Indium (TMI) 21.9 1000

Trimethyl Gallium (TMG) -3.9 1100 Tertiarybutyl Arsine (TBA) -1.9 1000

Tertiarybutyl Phosphine (TBP) 17.9 1100 Diethyl Zinc (DEZ) 0 1000

Our system also contains sources for n- and p-type doping. N-type doping is

achieved using disilane gas to incorporate Si at a Group III site. Disilane is a much

safer source of Si than silane which is explosive. P-type doping is achieved using a

liquid metal-organic zinc source. The dopant concentration in the final film will be

directly correlated with the flow rate used.

Our reactor system is equipped with an Epison gas concentration analyzer. This

system can determine the concentration of a particular source relative to the carrier

gas. These values are crucial for determining proper gas flows for a growth and to

indicate when source material is running out. Once a bubbler’s supply is nearly

gone, the Epison concentration will begin to steadily drop.

5.3 DETERMINATION OF LAYER PROPERTIES AND GROWTH PARAMETERS

The design of an epitaxial layer structure involves the determination of a number of

important material parameters such as the strain and band gap. These parameters are

especially important when designing MQW regions. Fortunately, the composition of

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quaternary In(x)Ga(1-x)As(y)P(1-y) layers can be tailored to target a wide range of strains

and band gaps. However, in order to properly predict compositions, we need an

accurate model for ternary and quaternary material properties. We can then extend

this model to predict the flows required for each metal-organic source in order to

achieve a desired composition. This section will discuss the model we use at UCSB

to calculate material properties and flows, and the procedure we use to characterize

grown films.

5.3.1 MATERIAL PARAMETER AND FLOW CALCULATIONS

In order to accurately predict the characteristics of a ternary or quaternary film, it is

necessary to either compile an extensive database of material parameters for all

compositions of interest or to estimate these parameters based on know binary and

ternary parameters. Because there is such a wide range of possible quaternary

compositions, the former approach is not practical. Several interpolation techniques

have been suggested to determine parameters for layers of arbitrary composition.

The most common approach, based on binary compounds of the In(x)Ga(1-x)AsyP(1-y)

family, is known as Vegard’s law [1]:

𝑝𝑝(𝑥𝑥,𝑦𝑦) = 𝑥𝑥𝑦𝑦𝑝𝑝𝐼𝐼𝐼𝐼𝐴𝐴𝑠𝑠 + 𝑥𝑥(1 − 𝑦𝑦)𝑝𝑝𝐼𝐼𝐼𝐼𝑃𝑃 + (1 − 𝑥𝑥)𝑦𝑦𝑝𝑝𝐺𝐺𝑎𝑎𝐴𝐴𝑠𝑠 + (1 − 𝑥𝑥)(1 − 𝑦𝑦)𝑝𝑝𝐺𝐺𝑎𝑎𝑃𝑃 (5.1)

where p is some parameter of interest. This law works sufficiently well for basic

parameters like the lattice constant or Poisson’s ratio, but it is not accurate enough to

predict the energies and band gaps of strained quaternary layers. Instead we use a

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more sophisticated model as proposed by Krijn [10] that accounts for the nonlinear

bowing between binary parameters:

𝑄𝑄(𝑥𝑥,𝑦𝑦) =𝑥𝑥(1 − 𝑥𝑥)[𝑦𝑦𝑇𝑇𝐼𝐼𝐼𝐼𝐺𝐺𝑎𝑎𝐴𝐴𝑠𝑠 (𝑥𝑥) + (1 − 𝑦𝑦)𝑇𝑇𝐼𝐼𝐼𝐼𝐺𝐺𝑎𝑎𝑃𝑃 (𝑥𝑥)]

𝑥𝑥(1 − 𝑥𝑥) + 𝑦𝑦(1 − 𝑦𝑦)

+𝑦𝑦(1 − 𝑦𝑦)[𝑥𝑥𝑇𝑇𝐼𝐼𝐼𝐼𝐴𝐴𝑠𝑠𝑃𝑃(𝑦𝑦) + (1 − 𝑥𝑥)𝑇𝑇𝐺𝐺𝑎𝑎𝐴𝐴𝑠𝑠𝑃𝑃 (𝑦𝑦)]

𝑥𝑥(1 − 𝑥𝑥) + 𝑦𝑦(1 − 𝑦𝑦) ,

(5.2)

where TABC is the ternary contribution which is defined as:

𝑇𝑇𝐴𝐴𝐴𝐴𝐴𝐴(𝑥𝑥,𝑦𝑦) = 𝑥𝑥𝐴𝐴𝐴𝐴𝐴𝐴 + (1 − 𝑥𝑥)𝐴𝐴𝐴𝐴𝐴𝐴 + 𝑥𝑥(𝑥𝑥 − 1)𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 , (5.3)

In Eqn. 5.3, B represents a binary parameter and C is the bowing factor (tabulated

values are available in [10]). Using both Eqns. 5.1 and 5.2 we can estimate with

reasonable accuracy the material parameters for any quaternary composition. Once

the basic properties are determined, we can use them to calculate information about

the band structure of the layer(s) using the approach in [10] and [11].

The required gas flows to obtain a quaternary layer with a certain composition

must also be determined. To do this, we need to know the concentration of metal-

organic compounds in the carrier flow (measured with the Epison) and ratio between

the gas-phase composition and the solid-phase composition, known as the

segregation coefficients for the layer. There are two segregation coefficients—one

for the Group III elements (keff) and one for the Group V elements (kseg). The gas-

phase composition is determined from the relative flows of gases while the solid-

phase composition represents the actual composition of the grown film. The amount

of metal-organic that is actually flowing to the reactor, or the pure component flow

is:

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𝐹𝐹𝑃𝑃𝐴𝐴𝐹𝐹 =𝐸𝐸𝑝𝑝𝐸𝐸𝑠𝑠𝑚𝑚𝐼𝐼(%)

100𝐹𝐹𝑚𝑚𝑒𝑒𝑒𝑒 . (5.4)

Feff is the effective flow, given by:

𝐹𝐹𝑚𝑚𝑒𝑒𝑒𝑒 =𝐹𝐹𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑚𝑚𝑒𝑒

𝐹𝐹𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑚𝑚𝑒𝑒 + 𝐹𝐹𝑚𝑚𝐸𝐸𝑏𝑏𝑏𝑏𝑡𝑡𝐸𝐸𝑚𝑚𝐼𝐼𝐹𝐹𝐸𝐸𝐼𝐼𝑖𝑖𝑚𝑚𝑐𝑐𝑡𝑡𝐸𝐸𝑚𝑚𝐼𝐼 , (5.5)

where Fbubbler is the actual carrier gas flow through the bubbler, Fdilution is the an

additional flow of H2 used to dilute the amount of metal-organic in the total flow,

and Finjection is the actual flow injected into the reactor. The Epison concentrations

vary from day to day, so it is necessary to update the flow information in a growth

recipe periodically.

To simplify the calculation of both material parameters and flow rates, an

extremely helpful FORTRAN-based growth calculator was developed several years

ago by Dr. Patrick Abraham. It allows the user to accurately determine important

ternary and quaternary parameters with relative ease. The program uses many of the

binary constants tabulated in [10], but also relies on a number of parameters

determined in-house using real growth data. However, the architecture of this

program requires cycling through a large number prompts which can slow down the

computation process and make it difficult to adjust growth recipes quickly in the

middle of a growth. The program also underestimates ternary band gaps since it

simply applies the quaternary approximations with either x or y equal to zero. In this

work, this program was updated with a graphical interface using Python for easier

125

Fig. 5.5 MOCVD growth and material parameter calculator.

use. The new version also contains a more accurate approximation for the ternary

InGaAs band gap. A screenshot of this new tool is shown in Fig. 5.5.

5.3.2 MOCVD CALIBRATION PROCEDURE

Once the desired composition and flows have been calculated using the MOCVD

calculator program, we can program the reactor software to grow a specific layer or

set of layers. However, random changes in ambient conditions can lead to variations

in growth properties from run to run. This is especially noticeable if an extended

break of several days occurs between runs. Therefore, it is necessary to characterize

a film after growth and update the MOCVD calculator with the keff and/or kseg values

126

(a) (b)

Fig. 5.6 (a) X-ray scan of MQW sample showing both the raw scan data and a fit of that data using a thorough model of the layer structure. (b) PL measurement for the same sample.

for that growth. The flows can then be updated appropriately for precise targeting of

PL and strain.

Ternary layers are much easier to calibrate than quaternary layers because they

have only one compositional degree of freedom (either x or y). An x-ray scan or a

PL measurement can be used to determine either the layer strain or the band gap,

respectively, which completely define the composition. Quaternary layers, on the

other hand, have two compositional unknowns so both x-ray and PL data are

necessary to specify the layer composition. A typical omega-2θ x-ray scan for our c-

MQW base structure is shown in Fig. 5.6a. This scan shows several characteristic

peaks. The major peak at 0 sec belongs to the InP substrate. Any peaks to the left of

this peak represent compressively-strained layers while peaks to the right are from

tensile-strained layers. Using commercial software6

6 RADS Mercury by BEDE Scientific

, the raw x-ray scan can be fit to

127

a model of the layer stack that was grown. The model requires values for

compositions and thicknesses of each layer in the structure. The values are adjusted

to get an initial fit of the x-ray scan and are then plugged into our MOCVD

calculator to determine the expected PL wavelength based on those compositions

and thicknesses. Most often, the calculated PL corresponding to the values used in

the x-ray model is different than the experimentally measured PL (Fig. 5.6b). This

occurs because a wide range of quaternary compositions can actually yield the same

strain. One can iterate along these constant strain contours using the following

relationship:

Δ𝑥𝑥 = −2.1368Δ𝑦𝑦 (5.6)

where Δx is the change in In fraction and Δy is the change in As fraction. The

compositions in the x-ray model can then be adjusted until the predicted PL matches

the experimental value. When the solid compositions are known, these can be

combined with the flows used during the growth to determine the new values of keff

and kseg, which will be used to determine the flows for the next growth. Although

this method is extremely effective for calibration, the actual composition values

determined through this method do not necessarily exactly represent the true atomic

concentrations of the constituent atoms. The compositions determined using this

approach are only as good as the model used to calculate PL and strain. In fact, we

have found that the material parameters we use in our model do differ somewhat

from the models used by external vendors. Therefore, when outsourcing a growth it

128

is more important to specify the desired strain and PL than the actual x and y

compositions.

There are two other important considerations for calibration when growing an

MQW region with a quaternary waveguide. First, as more and more layers are

added to a structure, it becomes increasing difficult to model accurately the x-ray

curve. Additionally, it is often only possible to discern PL peaks for the brightest

layers in the stack (usually the QWs). The PL intensity tail of the bright peaks tends

to swamp out the intensity of dimmer layers (such as a bulk layer with a band edge

close to that of the QWs). For this reason, we first calibrate the quaternary

waveguide separately from the MQW region. Because this is a bulk film, the

measured PL is not representative of the actual band gap energy. Thermal effects

increase the transition energy in the conduction band by a factor kT/2, so this must

be accounted for in the calibration [12]. Second, we can simplify the calibration

process of an MQW region by using a constant Group III value for the QWs and

barriers. The x-composition for the wells and barriers will then be the same in the x-

ray model, and the well and barrier will have same the growth rate and thus their

thicknesses can be scaled to each other based on the relative growth times. This

method eliminates the need to calibrate the barrier and the QW separately.

Dopant flows are calibrated by growing InP layers of a specific thickness

separated by a short As pulse that forms a monolayer of InAsP. The dopant flow is

typically changed every two periods. The actual doping levels are measured by

129

Fig. 5.7 SIMS analysis of a Si doped calibration sample.

analyzing the completed structure with SIMS (Fig. 5.7). This procedure can be more

complicated if the dopant has a high diffusivity in the layer being grown (i.e., Zn in

InP), as we will not see clearly defined concentration levels and will have to

interpolate between As spikes. The dopant incorporation is temperature dependent

so this type of calibration is required for every growth temperature that will be used

for doped layers. Additionally, the activated doping concentration (or the

concentration of dopant that can actually contribute to conduction) is not always

equal to the physical concentration measured by SIMS. Although Si is almost 100%

activated, Zn is only about 70% activated in our InP layers. Because SIMS

measurements cannot be done for Zn-doped material at UCSB, this procedure can

only be performed periodically. Therefore, we also measure dopant incorporation

using an on-site Hall measurement system.

130

Table 5.2 Base Structure Epitaxial Layer Design

5.4 BASE GROWTH CONSIDERATIONS

The specific of our base structure are listed in Table 5.2. The active region is

undoped for the eventual formation of a p-i-n junction. The QWs have high

compressive strain to improve the differential gain of our structure. This strain

limits the total well thickness that can be grown before the structure relaxes and

misfit dislocations form. The barriers are therefore grown with tensile strain to

provide some degree of strain compensation. The waveguide is also grown under

x y

Implant Buffer 1 0 0 2,000 UID

Stop Etch (1.3Q) 0.711 0.611 -400 300 UID

Implant Buffer 1 0 0 4,500 UID

Stop Etch (1.3Q) 0.711 0.611 -400 300 UID

InP Regrowth 1 0 0 150 8E16 (Si)

InP Regrowth 1 0 0 150 5E16 (Si)

Upper Waveguide (1.3Q) 0.711 0.611 -400 1,050 3E16 (Si)

Barrier 0.735 0.513 -2050 80 UID

Well (10X) 0.735 0.835 8800 65 UID

Barrier (10X) 0.735 0.513 -2050 80 UID

Lower Waveguide (1.3Q) 0.711 0.611 -400 1,050 1E17 (Si)

n-Buffer 1 0 0 500 4E17 (Si)

n-Buffer 1 0 0 500 7E17 (Si)

n-Buffer 1 0 0 17,000 1E18 (Si)

Substrate 1 0 0 - >5E18 (S)

Layer

Material (InxGa1-

xAsyP1-y) ┴ Strain (ppm)

Thickness (Å)

Doping (cm-3)

131

slight tensile strain for strain compensation. Although the net strain of our structure

is still compressive, the strain compensation provided by the barriers and waveguide

allows us to exceed the typical critical thickness of our wells, which is on the order

of 120 Å. The upper waveguide and InP regrowth layers were grown slightly n-type

to give us the possibility of including another regrowth for a second band edge.

However, this avenue was not actually pursued in MOTOR, so in principle these

layers could be undoped in the future.

5.5 CLADDING REGROWTH CONSIDERATIONS

We use a single regrowth step to define our waveguide cladding. It consists of 1.75

μm of InP with a specific doping profile, a 150-nm heavily doped, p-type InGaAs

contact layer for efficient current injection, and a 400-nm InP protective cap layer.

The purpose of the cap layer is protect the InGaAs contact layer from contamination

before metal probe pads are defined. Regrowth is always a more significant

undertaking than a base growth because unseen surface flaws can lead to fatal

defects in the final device. Additionally, several processing steps have been

performed by the time of the regrowth so the investment of resources is higher at this

stage. It is important, therefore, to ensure that techniques exist to optimize the

regrowth quality. In this work, there were two primary regrowth concerns: (1) the

proper placement of our p-i-n junction using an optimized doping profile; and (2) the

132

determination of growth conditions that enable us to fully bury the rib waveguide of

the AWGR and the 450-nm QWI UID buffer layer.

5.5.1 ZN DOPING PROFILE

It is important that the Zn doping profile in the cladding be optimized to provide

high-quality active diodes without significantly increasing the passive propagation

loss. This means we want to place just enough p-type Zn at the surface of the upper

waveguide to create our p-i-n junction. If our doping concentration is too high, we

run the risk of diffusing excess Zn into the waveguide itself and increasing passive

losses. Additionally, as mentioned previously, Si atoms accumulate on the sample

surface prior to regrowth (on the order of 1-2E18 cm-3)

13

due to the abundance of this

element in the lab [ ]. The incorporation of Si at the regrowth interface can lead to

the formation of an unwanted p-n junction that is more favorable for injected current

than the desired p-i-n junction. Therefore, Zn levels must be high enough at the

interface to compensate for the Si spike without diffusing into the waveguide layer.

It was found that we can reduce the magnitude of the Si spike by putting the sample

in a UV-ozone reactor for 30-60 minutes, removing the newly formed oxide layer in

buffered HF, and then immediately transferring the sample to the reactor with the

sample upside down in the sample holder [7]. The doping profile was optimized for

our in-house MOCVD system to deal with both the Si spike and the desire to keep

Zn out of the waveguide. This is accomplished by first growing 30 nm of UID InP

133

followed by 20 nm of lightly doped InP to initiate the growth, and then growing a

highly doped (~2E18 cm-3 7) Zn spike layer [ ]. The complete in-house regrowth

profile is given in Table 5.3.

When out-sourcing the regrowth to an external vendor, however, it was difficult

to ascertain whether or not a Zn doping spike was necessary in their reactor to

combat the inevitable Si at the regrowth interface. Based on the vendor’s previous

experiences with their own reactor, we opted not to include the Zn spike layer in our

regrowth specifications (Table 5.4). This turned out to be an unwise decision that

was not realized until after device fabrication was completed. During initial

Table 5.3 In-house cladding regrowth profile.

x y

p-Cap 1 0 0 4,000 (p) 1E18 590p-Contact 0.531 1 0 1,500 (p) ~2E19 590

p-Clad 1 0 0 7,000 (p) 1E18 590p-Clad 1 0 0 5,000 (p) 7E17 590p-Clad 1 0 0 3,000 (p) 5E17 590p-Clad 1 0 0 1,500 (p) 5E17 615

Zn Spike 1 0 0 500 (p) 2E18 615p-Clad 1 0 0 200 (p) 5E17 590

0.50 Rg Set Back 1 0 0 200 UID 5900.25 Rg Set Back 1 0 0 100 UID 590

Layer

Material (InxGa1-xAsyP1-y) ┴ Strain

(ppm)Thickness

(Å)Doping (cm-3)

Tg (ºC)

134

Table 5.4 External vendor cladding regrowth profile.

screening of the MOTOR chip, the diodes of the device showed substandard diode

performance and active devices showed no generation of photons whatsoever. A

SIMS scan of a non-processed portion of the sample showed that the Zn levels

dropped off well above the waveguide layer (Fig. 5.8). Because of the Si spike at the

interface, this formed a p-n junction above the waveguide so no carriers were

Fig. 5.8 SIMS analysis of external cladding regrowth. Clearly, the Zn concentration falls off to low levels before reaching the waveguide layer.

x y

p-Cap 1 0 0 4,000 (p) 1E18

p-Contact 0.531 1 0 1,500 (p) 1E19

p-Clad 1 0 0 8,000 (p) 1E18

p-Clad 1 0 0 10,000 (p) 7E17

p-Clad 1 0 0 500 UID

Layer

Material (InxGa1-xAsyP1-y) ┴ Strain

(ppm)Thickness

(Å)Doping (cm-3)

135

recombining in the MQW region to generate photons. In spite of this depressing

outcome, we decided to see if it was possible to diffuse the Zn dopant to its proper

location (even though all processing steps were complete). Since the concentration

of Zn above the waveguide was constant at 7E17 cm-3

14

for about 1 μm, we used the

constant source diffusion equation [ ] to develop an anneal procedure to diffuse Zn

to the proper location:

𝐴𝐴(𝑥𝑥) = 𝐴𝐴𝑠𝑠�1 − erf(𝑥𝑥/2(𝐷𝐷𝑡𝑡)1/2)� (5.7)

where C is the concentration as a function of position, Cs is the initial concentration

at position x, D is the temperature dependent diffusion constant and t is the time.

Using readily available data for Zn diffusion, we estimated that an anneal time of 30-

45 sec at 675°C was needed to achieve a concentration of 7E17 cm-3

5.5.2 CONDITIONS TO BURY NON-PLANAR FEATURES

at the top of the

waveguide. Surprisingly, the anneal process did not destroy the contacts or the

sample itself and was successful at restoring the optical properties of the device.

However, we found that because the samples had been thinned for mounting this

process needed to be performed on a device by device basis or else the sample would

bow and crack due to thermal stress.

Although most of the wavelength converter regions of the MOTOR chip are planar,

there are two regions of the sample that have topology that must be buried during the

cladding regrowth. The first non-planar region is the rib waveguide of the AWGR.

136

(a) (b)

Fig. 5.9 Comparison of growth over non-planar rib waveguide sections for (a) in-house regrowth conditions and (b) external vendor regrowth conditions.

The surface of the rib itself is InP, but the surface of the surrounding areas is the

InGaAsP waveguide layer. The second non-planar region is found in the area that

will eventually become the deeply-etched delay line. This area contains the UID

implant buffer layer and the underlying quaternary stop etch layer. Since this region

was defined via wet-etching, the sidewall profile is not perfectly straight, so it is

more difficult to bury. The regrowth over both of these areas should be smooth and

free of air voids to minimize reflections at the interface between planar and non-

planar regions. Our in-house regrowth procedure was optimized in [7] to bury

features of roughly this height. The process begins by heating up the sample in a

TBA and TBP overpressure since both InP and InGaAsP surfaces are exposed.

However, this means that there will be some exchange of P atoms with As atoms in

the InP regions of the chip. The growth then continues with 10 nm of InP grown at a

quarter of the standard growth rate, followed by 20 nm grown at half of the standard

growth rate. The slower growth rate is used to allow time for increased surface

137

migration of the metal-organic constituents to smooth over the step-like features.

We found this technique worked sufficiently well, but there is definitely some

roughness and striations in the overgrowth pattern (Fig. 5.9a). In samples that were

regrown externally by the III-V Lab, however, a much smoother overgrowth profile

was seen (Fig. 5.9b). This is most likely due to the specific precursor sources and/or

the growth conditions used in their regrowth procedure. For instance, they use PH3

for both the sample heat-up step and the epitaxial growth. PH3 typically requires

higher substrate temperatures for pyrolysis and, if higher temperatures were used,

this may have enhanced the migration length of elements at the surface, allowing for

a smoother overgrowth profile. Unfortunately, most of the specifics of their growth

procedure are not available, so there may be other factors involved of which we are

unaware. Regardless, Fig. 5.9 indicates that there is clearly room for improvement

with our in-house overgrowth profile, so it would be beneficial to reexamine our

growth conditions in the future.

5.6 CHAPTER SUMMARY

In this chapter we presented the key considerations for epitaxial growth as it applies

to the development of a monolithic tunable optical router chip. Material prepared by

two different growth techniques was compared and MOCVD-grown epi was

determined to be more suitable for the integration requirements of this work.

MOCVD material can be grown either in-house at UCSB or by an external vendor.

138

Several of the growths related to this work were performed at UCSB, so the reactor

system and calibration procedure were described. We also presented the details of

the base structure and regrowth used for MOTOR. The most obvious area for

improvement with in-house regrowths is the growth over non-planar sections of the

sample, which was not a problem with the regrowth from our external vendor.

However, the doping profile recommended by our external vendor needs to be

adjusted before any additional out-sourced regrowths are performed.

139

REFERENCES


[2] G. B. Stringfellow, Organometallic Vapor-Phase Epitaxy: Theory and Practice, 2nd ed. Academic Press, 1998.

[3] M. E. Heimbuch, et al., "Low threshold 1.5 mu m quantum well lasers grown by atmospheric pressure MOCVD with tertiarybutylarsine (TBA) and tertiarybutylphosphine (TBP)," Electronic Letters, vol. 29, no. 4, pp. 340-341, Feb. 1993.

[4] P. Harmsma, "Integration of Semiconductor Optical Amplifiers in Wavelength Division Multiplexing Photonic Integrated Circuits: Application of Selective Area Chemical Beam Epitaxy," Ph.D. Dissertation, Technishe Universiteit Delft, 2000.

[5] W. T. Tsang, "Chemical beam epitaxy of InP and GaAs," Applied Physics Letters, vol. 45, no. 11, pp. 1234-1236, Dec. 1984.

[6] M. E. Heimbuch, "Optimization of MOCVD Growth Using Tertiarybutylarsine and Tertiarybutylphosphine for the Realization of 1.55 um Low Threshold Current Lasers," Ph.D. Dissertation, University of California, Santa Barbara, 1997.

[7] J. W. Raring, "Advanced InP Based Monolithic Integration Using Quantum Well Intermixing and MOCVD Regrowth," Ph.D. Dissertation, University of California, Santa Barbara, 2006.

[8] J. Klamkin, "Coherent Integrated Receiver for Highly Linear Microwave Photonic Links," Ph.D. Dissertation, University of California, Santa Barbara, 2008.

[9] G. B. Stringfellow, "Non-hydride group V source for OMVPE," Journal of Electronic Materials, vol. 17, no. 4, pp. 327-335, Jul. 1998.

[10] M. P. C. M. Krijn, "Heterojunction band offsets and effective masses in III-V quaternary alloys," Semiconductor Science and Technology, vol. 6, pp. 27-31, Sep. 1991.

[11] J. R. Flemish, H. Shen, K. A. Jones, M. Dutta, and V. S. Ban, "Determination of the composition of strained InGaAsP layers on InP substrates using photorelectance and

140

double-crystal x-ray diffractometry," Journal of Applied Physics, vol. 70, no. 4, pp. 2152-2155, Aug. 1991.

[12] Y. Paltiel, et al., "Voltage tunability of high performance Zn doped p-type QWIP grown by MOVPE," Infrared Physics & Technolgoy, vol. 47, no. 1-2, pp. 37-42, Oct. 2005.

[13] D. G. Knight, G. Kelly, H. J., S. P. Watkins, and M. L. W. Thewal, "Characterization of interfacial dopant layer for high-purity InP," Journal of Crystal Growth, vol. 182, pp. 23-29, 1997.

[14] B. Goldstein, "Diffusion in Compound Semiconductors," Physical Review, vol. 121, no. 5, pp. 1305-1311, 1961.

141

Chapter 6

Device Fabrication

and Process Improvements

Robust fabrication processes are a key element to realize a LS-PIC like MOTOR. It

is desirable to develop the simplest processing plan possible as unnecessary

complexity can lead to the formation of fatal defects in the device. This chapter will

describe the fabrication approach used for MOTOR. It will also highlight two major

challenges faced during production: (1) low-quality waveguide etching; and (2)

unintentional intermixing of the MQW region. The details for new and improved

techniques developed and used in this work to circumvent these issues are then

presented.

6.1 MIGRATION TO 2” WAFERS

Traditionally at UCSB, devices are fabricated on one quarter of a 2” InP wafer. This

helps to conserve material and also allows a PIC developer to try alternative

fabrication techniques with each quarter. However, because the MOTOR chip has

relatively large dimensions (14.5 mm x 4.25 mm), only three chips can fit on a

quarter of a wafer. With so few potential chips per sample, yield becomes an even

142

Fig. 6.1 Photograph of full MOTOR wafer before the QWI step. A single chip is highlighted in the black box.

more critical concern. In this work, we migrated to processing full 2” wafers (Fig.

6.1). This allowed us to fabricate 16 chips per sample. However, this decision

impacted our standard processing techniques in two ways. Wafer handling became

more difficult because a full InP wafer is more delicate than a quarter wafer and can

break much more easily. The full wafer also impacted several processing steps like

dry etching, as loading effects changed some process parameters like the etch rate.

Because of these difficulties, we actually cleaved the full wafer into three larger

pieces after the regrowth. Inevitably, a few MOTOR chips were lost in this process,

but the largest two of these pieces still had 4 to 5 potential chips on it.

6.2 FABRICATION OVERVIEW

The MOTOR fabrication process consists of 14 lithographic exposures for etching,

QWI, implants and metallization. Because the MOTOR chip is 14.5 mm in length, it

was determined that good focus was not maintained across a single die if each die

143

was exposed in one shot. Instead, the chip was divided into two lithography regions

(the left side contained the wavelength converters and the right side contained the

AWGR) and the left and right sides of each die were exposed separately. The

stepper was programmed to stitch these windows together without needing to realign

the wafer. In theory, random fluctuations in the stepper stage can lead to some

misalignment between these sections, but this did not prove problematic in practice.

Table 6.1 summarizes the key processing steps used to develop MOTOR. Many of

these processing steps have been described in detail elsewhere [1],[2], so we will

only focus here on those techniques that are novel to this work.

Table 6.1 Summarized process flow for MOTOR development

Processing Step Purpose Equipment Used Alignment marks Etch alignment marks for future

stepper alignments RIE #2 (CH4/H2/Ar)

Active/passive definition Deposit and etch hard mask for QWI implant

PECVD + RIE#3 (CF4/O2)

QWI Shift the band edge in implanted regions

RTA

Buffer protection layer removal

Remove the upper InP buffer protection and stop etch layers

Wet etch (3:1 H3PO4:HCl + 1:1:10 H2O2:H2SO4:DI)

UID buffer definition Remove UID buffer everywhere but the delay line and AWGR regions

Wet etch (3:1 H3PO4:HCl + 1:1:10 H2O2:H2SO4:DI)

Rib waveguide definition Etch the rib waveguide of the AWGR RIE #2 (CH4/H2/Ar)

Gratings Etch square gratings for the SG-DBR E-beam lithography + RIE #2 (CH4/H2/Ar)

Cladding regrowth Regrow the cladding and the p-type contact layer

MOCVD

Initial ridge definition Etch the wavelength converter ridges 1.5-1.8 μm

Unaxis (Cl2/H2/Ar)

Wet etch protection Protect deeply etched regions and perform selective wet-etch cleanup etch

Wet etch (3:1 H3PO4:HCl)

144

Deep ridge definition Dry etch the deep ridge sections Unaxis (Cl2/H2/Ar)

Semi-self via Open partial windows where contacts will be formed and etch back the resist until the ridge top is exposed

RIE#3 (O2 for resist and CF4/O2 for dielectric)

Direct via Open via on wide features that will be contacted by metal

RIE#3 (O2 for resist and CF4/O2 for dielectric)

InP cap etch Remove the top InP layer to expose the InGaAs contact layer

Wet etch (3:1 H3PO4:HCl)

P-metal deposition Deposit Ti/Pt/Au probe pads E-beam #4

InGaAs isolation Wet etch the InGaAs that is not covered in metal to isolate contacts

Wet etch (3:1:50 H3PO4:H2O2:DI)

Isolation proton implant Passivate Zn dopant between metal pads to reduce waveguide loss

Resist mask on metal pads + ion implant

Lapping Thin the sample for cleaving Manual lapping tool

N-metal Ti/Pt/Au backside contacts E-beam #3

Device cleaving and mounting

Separate devices and prepare for testing

Automated cleave tool

6.3 GRATING FORMATION

Prior to this work, grating patterns were formed at UCSB using holographic

exposure [3]. This technique is popular because it has a high throughput, low cost,

and can be used over large areas [4]. Unfortunately, the UCSB holography stage is

too small to accommodate full 2” wafers. We instead turned to e-beam lithography

to define our gratings. Although this technique is slower than holography because

each individual grating is defined line-by-line, it provides more accuracy in defining

the pitch and is more uniform across the sample. 50 nm of SiO2 is first deposited on

the sample as a hard mask. E-beam resist (2:1 ZEP520A:Anisol) is then spun across

the sample. The grating pattern is defined using an exposure dose that is calibrated

to prevent overexposure due to proximity effects. Because the grating pitch is so

narrow, AFM scans are used to measure the pattern to see if it is fully developed.

145

(a) (b) (c)

Fig. 6.2 Typical AFM scans for various stages of the e-beam grating process: (a) patterned resist; (b) patterned SiO2; and (c) the finished grating etched into semiconductor.

Ideally, the AFM scan should reveal flat trenches, but sometimes the AFM tip is not

long enough to reach to the bottom of the trench. Once the resist pattern is verified

(Fig. 6.2a), this pattern is transferred into the SiO2 using a dry etch (Fig. 6.2b). The

resist is stripped from the sample and the SiO2 hard mask is used to etch the grating

pattern into the semiconductor via dry etch. The final grating pattern is illustrated in

Fig. 6.2c. In general, the e-beam process proved to be much more repeatable and

uniform than what is typically seen using our holography system, so future work

would benefit from continued use of e-beam-defined gratings.

6.4 WAVEGUIDE FABRICATION

One of the most critical points in the entire fabrication process of the MOTOR chip

is the definition of the surface ridge and deeply etched ridge waveguides. The etches

associated with these steps are permanent and cannot be repeated if the equipment

fails or is calibrated incorrectly. The etch process should yield ridges with smooth

146

sidewalls to reduce scattering losses and should be defined in such a way that there is

no misalignment between the surface and deeply etched ridge sections. It will be

shown below that the fabrication process that existed at UCSB prior to MOTOR

development was problematic and unable to meet these requirements. Therefore, the

process was completely re-developed and a new ICP-based InP dry etch was

developed and qualified. This new etch process proved superior in almost every way

to the old technique and has now become the de-facto InP etch for several research

groups at UCSB.

6.4.1 TRADITIONAL RIE CH4/H2/AR APPROACH

Historically, a CH4/H2/Ar (MHA) etch chemistry has been used at UCSB for dry

etching InP and related materials. This is done in a Materials Research Corporation

parallel plate, 13.56 MHz reactive ion etch (RIE) system. Typical etch conditions

for the surface and deeply etched ridge are listed in Table 6.2. This etch system is

satisfactory for the surface ridge, because it is finished with a selective wet etch that

helps to smooth the sidewalls somewhat. However, these etch conditions are not

able to provide high-quality deep etches. One problem with the MHA chemistry in

plasma is that it leads to the formation of polymers on or near the ridge. Because the

etch time is so long, this can lead to significant polymer buildup that roughens the

sidewall of the ridge. One approach to deal with this polymer is to periodically

interrupt the etch with an O2 plasma ash (see Table 6.2), but some polymer

147

Table 6.2 Standard MHA RIE conditions for ridge definition

Surface Ridge Deeply Etched RidgeMHA (sccm) 4/20/10 MHA 4/20/10

Pressure (mT) 75 Pressure (mT) 75

Voltage (V) 450 Voltage (V) 425

Time (min) ~27 Time (min) 9 + 1’ O2 descum (3-4X)

Target Etch Depth (μm) 1.5-1.8 Target Etch Depth (μm) 1.5-2 below waveguide

deposition is unavoidable. Furthermore, this etch is slow and non-uniform across a

sample and tends to undercut quaternary layers. The undercut can be accounted for

by increasing the width of the ridge on the mask plate, but this increases the

likelihood of introducing systemic defects into the process as the degree of

undercutting may not be constant in all areas of the sample.

Fig. 6.3 shows an SEM image of the sidewall from what would qualify as a

“good” deeply etched ridge formed by this RIE process. This roughness will lead to

a high degree of scattering loss. In fact, the average loss measured through several

(a) (b)

Fig. 6.3 SEM image of (a) the adiabatic taper transition from surface-to-deep ridge and (b) the sidewall of a deeply etched waveguide. Figures courtesy of Dr. Milan Mašanović.

148

RIE-etched delay lines (with the adiabatic taper transition between surface and

deeply-etched ridge reasons) was 7.6 dB7

6.4.2 DEVELOPMENT OF ICP Cl2/H2/Ar APPROACH

. The best case loss measured for these

delay lines was 6.4 dB. This degree of loss will lead to very poor device

performance, so it was crucial to develop a better etching technique.

One of the major issues with traditional parallel plate RIE systems is that the plasma

is generated directly above the sample. The ion density of the plasma in this type of

system can only be increased by raising the RF power, which simultaneously

increases the energy of the ions as they approach the sample surface [5]. If this

bombardment energy increases, the sample can be damaged or roughened. Higher

ion energies also reduce the selectivity between the hard mask layer and the etching

semiconductor. Since the roughness of ridge sidewalls is crucial in our application,

we must seek an etching solution that alleviates this problem. An RIE-ICP

(inductively coupled plasma) system is an ideal choice because the plasma is

generated in a separate chamber away from the sample. This means high plasma

densities can be achieved without increasing the ion energy above the wafer and

damaging the surface. The higher plasma density in this system also enables much

faster etch rates.

7 The loss was measured by coupling a known power into the chip and measuring the photocurrent in both preamplifier SOAs. This means that the loss of the input 2 x 2 MMI is also lumped into this value. We also assume a coupling loss of 4 dB since the input facets of the device were AR coated.

149

Several etch chemistries have been suggested in the literature for InP, but the

most promising in terms of achieving straight and smooth sidewalls for deeply-

etched waveguides is based on Cl2 and H2 [6],[7],[8]. Cl2 is a well know etchant of

InP, but a pure Cl2 etch leads to serious undercutting of the waveguide. However,

one or more additive gases can be included in the reaction to obtain anisotropic

etching. A number of additive gases have been proposed for this purpose including

CH4, N2, Ar, Xe, or H2 [8], [9]. CH4 is a popular choice with Cl2, but it tends to

polymerize during the reaction, leading to unwanted polymer deposition on the

surface (similar to our RIE process) [10]. N2 can also be used, but high

concentrations are needed for sidewall passivation and that tends to reduce the

selectivity between the mask and semiconductor [8]. H2, on the other hand, provides

good sidewall passivation during the etch without degrading selectivity and also

helps to enhance the InP etch rate. The exact ratio of Cl2/H2 needed to yield straight

sidewalls appears to be sensitive to the actual reactor system, as a wide range of gas

flow ratios are proposed in the literature (i.e.; Guilet et al. recommend about 4:3

Cl2:H2 [8]; Rommel et al. recommend 1:1 Cl2:H2 [6]; Doctor et al. recommend 7:12

Cl2:H2 [11]). Additionally, there is disagreement over the benefits of including Ar

gas in the etch.

We began our investigation of this etch process by performing an initial

screening experiment in which we varied only the ratio of Cl2:H2:Ar (all other

parameters were held constant). The etch was performed in a Unaxis VLR ICP

etching system with a chuck temperature of 200°C. The total flow during the etch

150

was maintained at 21 sccm regardless of the gas ratio. Other reaction conditions for

this initial test like the ICP and RIE power were mostly taken from [8]. However,

we found that our reactor system could not maintain the 0.5-1.0 mTorr pressure used

in [8] so we used the lowest pressure our reactor could handle (1.5 mTorr). The InP

samples were placed on a 4” silicon carrier wafer during the reaction due to the 4”

wafer size requirement of our etch system.

The results of this screening experiment are shown in Fig. 6.4. These images

clearly show that the amount of H2 in the etch determines how straight the resulting

sidewall will be. For low H2 flows, the mask is completely undercut, creating a

triangular shaped waveguide. As the H2 concentration is increased, the

Fig. 6.4 Initial ICP screening experiment. The flow ratios are given for each SEM. Other reaction conditions are given as follows: Total flow = 21 sccm; P = 1.5 mTorr; PICP = 800 W; PRIE = 125W.

PICP= 800W / PRIE = 115W(b)1:0:0 Cl2:H2:Ar

Etch rate = Unknown

(a) 4:1:0 Cl2:H2:ArEtch rate = Unknown

(b) 4:3:0 Cl2:H2:ArEtch rate = 1.54 μm/min

(c)

PICP= 800W / PRIE = 115W(b)4:6:0 Cl2:H2:Ar

Etch rate = 1.46μm/min

(d) 4:3:1 Cl2:H2:ArEtch rate = 1.41 μm/min

(e) 4:3:3 Cl2:H2:ArEtch rate = 1.26 μm/min

(f)

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waveguide begins to straighten out. We found that with a Cl2:H2 ratio of about 4:6, a

straight, 90° sidewall could be achieved with an etch rate of almost 1.5 μm/min

(~30X faster than the original RIE process). Ar gas did not have an appreciable

effect on the waveguide geometry, but it did consistently reduce the etch rate

(mainly due to the fact that the total flow in our experiment was held constant and

increased Ar flow meant decreased Cl2 and H2 flow).

The reason the sidewall straightens with increasing H2 flow has to do with the

role of H2 in passivating the sidewall. In [12], EDX-TEM measurements

demonstrated that the passivation layer in this process was predominantly composed

of silicon and oxygen atoms (provided of course that a Si carrier wafer was used

during the etch). Their EDX system could not detect H, but intuition would suggest

it is also incorporated in the passivation layer. In the case of a pure Cl2 etch,

Bouchoule et al. showed that the passivation layer was very thin and consisted of

near-stoichiometric SiO2. However, as the concentration of H2 increased, the

passivation layer thickness increased by a factor of five to about 10-15 nm, and the

ratio of Si to O changed to roughly 1:1. In each case, the passivation layer was

thicker near the top of the ridge. A thicker passivation layer is less likely to break

down from lateral exposure to the etchants in the system, so vertical sidewalls can be

achieved. Using a carrier wafer of a different material like Al2O3 would radically

change the nature of the passivation and can actually lead the formation of grass-like

structures on the etched surface.

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The sidewall of the 4:6 Cl2:H2 etch displayed two notable features (Fig. 6.5).

First, there was no sign of undercut at the quaternary waveguide. Rommel et al.

showed that the etch rates of InP and InGaAsP can be very different depending on

the flow ratio, especially for higher H2 concentrations in which the InP etch rate can

be more than double that of ternary/quaternary layers [6]. As expected with our high

H2 flow, we noticed higher InP etch rates than that of ternary or quaternary layers.

However, the sidewall passivation in this process seems sufficient to prevent

appreciable lateral etching of the quaternary layers. Second, each etch in this

screening experiment showed the formation of a ledge near the top of the waveguide.

Although this ledge is far enough from the waveguide core that it should not

contribute to optical loss, it is an undesirable feature. We believe this ledge is due to

erosion of the hard mask during the etch. Improvements in the hard mask

technology to address this ledge will be discussed in the next section.

Fig. 6.5 Close-up image of the etched sidewall using a gas flow ratio of 4:6 Cl2:H2. The images show that the quaternary layer in this sample did not undercut, but an undesirable ledge forms near the top of the waveguide due to mask erosion.

Ledge

Mask erosion leads to ledge

Noundercut ofquaternary material

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Once the relative flow rates of Cl2 and H2 were know, we next investigated the

impact of ICP power of the etch. Increasing the ICP power will increase the ion

density in the chamber and the subsequent etch rate [8]. Fig. 6.6 shows a cross-

sectional SEM for three different ICP powers. As expected, we see an increase in

etch rate with increasing ICP power. No change in the verticality of the ridge is

observed. However, as the ICP power increases, the depth of the ledge formed near

the top of the waveguide also increases. This suggests that mask erosion is more

prevalent at higher ICP powers, probably due to a decrease in selectivity between the

mask and the semiconductor with increased ion density. Next, we considered the

impact of RIE power on the ridge profile. Fig. 6.7 shows cross sections of the ridge

for different RIE powers with a constant ICP power. Again, no change in vertically

was observed. It also appears that the depth of the ledge marginally decreases with

increasing RIE power.

Fig. 6.6 Effect of ICP power on ridge profile (4:6 Cl2:H2; Total flow = 21 sccm; P = 1.5 mTorr; 210” etch time).

PICP= 800W / PRIE = 100W PICP= 900W / PRIE = 100W

Ledge depth = 1.66 μmEtch rate = 1.89 μm/min


Ledge depth = 0.65 μm

PICP= 600W / PRIE = 100WEtch rate = 1.58 μm/min

(a) (b) (c)

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Fig. 6.7 Effect of RIE power on ridge profile (4:6 Cl2:H2; Total flow = 21 sccm; P = 1.5 mTorr; 210”etch time).

With these results as a starting point, the reaction conditions were fine tuned to

develop a repeatable etch recipe with good uniformity across the sample (the

variation for a 1.55 μm etch was measured to be ~0.5%). The final conditions for

this process are listed in Table 6.3. A small amount of Ar was also included in the

final etch chemistry to help stabilize the plasma. In order to provide consistent

results from run to run, two additional procedural elements were added to the

process. First, the reaction chamber is prepared for etching by running the etch

recipe for 2’ with only the silicon carrier wafer to coat the reactor sidewalls. No

other cleaning steps are necessary. Second, because we found that the amount of

material being etched had a significant impact on the etch rate, we include two

pieces of blank InP (~1/3 of a 2” wafer each) on the carrier wafer next to the real

sample. This helps to load the etch so the etch rate is less dependent on sample size.

As long as the same pieces are used from run to run, the etch rate is fairly repeatable.

PICP= 800W / PRIE = 115W PICP= 800W / PRIE = 125W



Ledge depth = 1.23 μm

PICP= 800W / PRIE = 100WEtch rate = 1.77 μm/min

(a) (b) (c)

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Table 6.3 New Cl2/H2/Ar etch process conditions

Unaxis ICP Etch ConditionsCl2:H2:Ar 7.4:11.6:2

Total Flow (sccm) 21Temperature (°C) 200

PICP (W) 800PRIE (W) 125

Pressure (mTorr) 1.5InP Etch Rate (nm/s) ~14

In0.532Ga0.468As Etch Rate (nm/s) ~10

6.4.3 HARD MASK DEVELOPMENT

Much of the quality of a dry etch depends on the hard mask used during the etching

process. If the hard mask is rough, that roughness will be directly transferred into

the semiconductor. If the mask breaks down during the process, etching will occur

in unintended areas. If the mask material tends to sputter due to ion bombardment,

(a) (b)

Fig. 6.8 SEM images of a deeply-etched waveguide that was defined with poor-quality hard mask: (a) top view shows that the waveguide is very wavy and rough; (b) cross section shows a mask with poor adhesion where wet chemicals crept under the mask and etched the ridge.

156

particles can stick to the sample creating micro-pillars in random locations. Also,

the adhesion of the mask to the semiconductor is important, especially with wet

chemical etching. Fig. 6.8 demonstrates how a poor-quality hard mask can ruin the

final ridge geometry.

As discussed in the previous section, one of the concerns seen initially in our

new ICP etch process was the formation of a ledge near the top of the ridge. SEM

images of our oxide hard mask before the etch showed that the mask profile was

very trapezoidal. It was surmised that since the edges of the mask at the base of the

trapezoid were very thin, this region of the mask was likely eroding at some point

during the etch. The trapezoidal pattern of our hard mask was a direct result of the

trapezoidal shape of the resist mask used to define the hard mask (Fig. 6.9a). We

also noticed that the aggressive nature of the hard mask etch often sputtered

(a) (b)

Fig. 6.9 SEM images of: (a) a trapezoidal resist mask used to define a 400-nm oxide mask; and (b) a 50-nm Cr mask with straight sidewalls (sample etched in a Panasonic ICP chamber with: 23.25 sccm Cl2 and 6.75 sccm O2; PICP = 500 W; PRF = 15 W; and P = 1.37 Pa).

157

photoresist across the sample. In order to both improve the straightness of the

sidewalls and eliminate this sputtering, we decided that a resist mask should not be

used to directly define the oxide hard mask. Instead, we deposit a 50-nm layer of

chrome on top of the oxide as an additional hard mask layer. The Cr mask is much

thinner than the oxide layer so it is much easier to define straight sidewalls in the Cr

with a resist mask (Fig. 6.9b). We can also use a non-aggressive etch process that

does not sputter resist.

Unfortunately, while the straight Cr mask did lead to somewhat straighter oxide

sidewalls (Fig. 6.10a), the CHF3 etch chemistry itself seems to preferentially etch

oxide trapezoidally. It is possible, however, to achieve more vertical sidewalls in the

oxide mask by switching to an SF6-based dry etch procedure (Fig. 6.10b). This

process still requires the thin Cr hard mask above the oxide, but is able to produce

near 90° sidewalls in the oxide hard mask. If SF6 is used to etch the oxide, there is

essentially no ledge formed in ridge etch. There is some residual roughening at the

top of the ridge that resembles paint flakes, but this is likely due to the breakdown of

the sidewall passivation layer after prolonged exposure to plasma-based etchants.

(a) (b)

Fig. 6.10 Cross-sectional images of the oxide profile using Cr as a hard mask and: (a) CHF3-based etching; and (b) SF6-based etching. Images courtesy of John Parker.

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6.4.4 SUMMARY OF SURFACE RIDGE AND DEEPLY ETCHED WAVEGUIDE DEFINITION

With these new technologies developed, we now turn to the important issue how to

etch both the surface and the deeply-etched ridge on the same sample. Fig. 6.11

illustrates the step-by-step procedure. First, 400 nm of PECVD SiO2 and 50 nm of

Cr are deposited on the sample surface after regrowth. A single lithography step is

used to pattern the surface and deep ridge sections in resist. This pattern is

transferred into the Cr via dry etching, the resist is stripped in solvent (to prevent

sputtering), and the SiO2 is etched. The Cr mask is removed by dry etching with the

same recipe that was used for the initial mask definition—this helps to prevent

sputtering of Cr during the ridge etch. Next the semiconductor is etched 1.5-1.8 μm

everywhere using the oxide mask. The regions that should be deeply etched are then

protected with a thick layer of photoresist and the open area is wet etched in 3:1

H3PO4:HCl. This wet etch defines the surface ridge regions and stops selectively at

the surface of the quaternary waveguide. The resist is then stripped and two layers

of PMGI and a layer of resist are spun on the sample. The sample is exposed and

developed such that the resist remains in the deeply etched regions with an undercut

profile. It is very important to ensure that the resist is properly developed at this step

and is not left in any unintended areas. 300 nm of PECVD SiO2 is then deposited

everywhere at 50°C in the Unaxis deposition chamber. Low temperature is required

in this step to prevent the resist from flowing and changing the pattern. The resist in

the deeply etched region is then lifted-off in solvent to expose the sections that will

159

Fig. 6.1 Process steps used to define surface and deeply-etched ridge sections in MOTOR.

be deeply etched (the surface ridge regions are protected by the 300 nm of oxide). If

there is residual resist that was not properly developed prior to this step, it will also

lift-off and exposure the semiconductor. A second InP dry etch with the same

conditions is performed to a depth of 1.5-2 μm below the waveguide layer in the

deeply-etched waveguide sections. The SiO2

Fig. 6.12

mask layers are then removed in BHF.

shows SEM images of a real sample prepared with this procedure.

160

(a) (b)

Fig. 6.12 Final ridge waveguide using our new ICP etch process: (a) shows the transition between surface and deeply-etched ridge; and (b) shows the resulting smooth sidewall in the deeply-etched region.

Notably, as shown in Fig. 6.12b, the sidewall of the deeply-etched waveguide is

far smoother than what was attainable using RIE technology (see Fig. 6.3). When

this etching technique is combined with the new mode-matching transitions between

the surface and deeply-etched ridge regions (see Chapter 4), the average loss through

the delay line drops substantially to 2.97 dB8

6.4.5 RIB WAVEGUIDE ETCH

. In fact, losses as low as 1.28 dB were

seen in one input port.

The rib waveguide etch for the AWGR was not performed using the new ICP

process because it initially appeared that the etch rate was too fast to stop the etch

accurately in the upper waveguide layer (it was not until after the rib etch was

8 The loss was measured as before for the RIE etched delay lines, but in this case we assume a coupling loss of 5 dB since the input facets of the device were not AR coated.

161

completed that it was realized that the ICP etch rate could be slowed down

significantly by loading the etch). Instead, an MHA RIE etch process with a slower

etch rate (~2.9 Å/s) was used. Because the etch was long, we were concerned about

the buildup of polymer on the sidewalls. To assist in removing polymer from the

sample, the etch was cycled 4X with a 15-30” O2 descum in between each cycle.

The resulting rib cross section and sidewall using this process are shown in Fig. 6.13.

The sidewall image of this structure is problematic, because we want a smooth

interface to bury the rib without voids. This roughness will increase the propagation

losses in the AWGR. Additionally, the etch depth was less uniform than that of the

Unaxis process (1-2% variation across the sample). If the etch depth varies across a

single AWGR, this will lead to index variations that could result in phase errors. In

the future, this step should be done using the Cl2/H2-based ICP process used for the

surface and deep ridge to improve the sidewall roughness and etch depth uniformity.

(a) (b)

Fig. 6.13 (a) Cross section and (b) sidewall profile of the rib waveguide using MHA RIE-based etch chemistry.

162

6.5 UNINTENTIONAL INTERMIXING DUE TO DIELECTRIC FILM STRESS

One paramount consideration in QWI is the preservation of the compositional profile

in the active region during the anneal process. As described in Chapter 3, a 500-nm

SixNy hard mask protects the active areas of the sample during the phosphorous

implant that is used to promote intermixing. With typical material grown by

MOCVD, this masked region exhibits only a marginal shift in PL wavelength (5-10

nm) after annealing [13], likely due to intrinsic defects formed in the sample during

the base growth. However, when a CBE-grown sample with essentially the same

layer structure was intermixed, an unintentional PL shift of >30 nm was seen in the

masked active areas (i.e., the areas not implanted with phosphorous) (Fig. 6.14a). A

PL scan of a larger area of the sample also demonstrates that the actual magnitude of

this wavelength shift varies widely with position (Fig. 6.14b). This random PL shift

(a) (b)

Fig. 6.14 (a) PL spectra for the non-implanted active region of MQW base structure grown by CBEbefore and after QWI. An unintentional shift in wavelength of ~30 nm is observed for a 350 second anneal. (b) Variation in PL wavelength across a larger region of the CBE sample.

163

would have a major impact on overall device performance because many

components, such as gratings and AWGRs, are designed for operation at particular

wavelengths. It is critical, therefore, to understand the nature of this shift and adjust

QWI processing conditions to eliminate it.

The fact that this undesired PL shift occurs with CBE-grown samples and not

with MOCVD-grown samples indicates that CBE-grown material either: (1)

incorporates a higher level of intrinsic point defects during growth; or (2) interacts

differently with one or more standard QWI processing steps. Point defect

concentrations are difficult to measure directly so the processing steps used in QWI

were examined first for any incompatibles. Since a popular alternative to implant-

based QWI utilizes dielectric capping layers to promote intermixing [14], the thick

500-nm nitride hard mask, which is blanket deposited across the sample before the

phosphorous implant, was a reasonable starting point for our investigation.

Our nitride films at UCSB are typically deposited in a PlasmaTherm PECVD

system through a reaction between 2%:98% SiH4:He and a mixture of N2 and NH3 at

265°C, 900 mT and a bias power of 22 W. In general, a reaction between only

SiH4:He and N2 in the range of 200-400°C tends to produce nitride films closer in

stoichiometry to Si3N4 [15]. However, a reaction between only SiH4 and NH3 below

500°C yields a H-rich nitride film containing silicon diimide groups (Si(NH)2) as

there is insufficient energy to severe the N-H bonds. Table 6.4 lists the flow rates

for our standard recipe. Since this recipe uses both N2 and NH3 it is likely that the

deposited film is not fully stoichiometric and contains some N-H bonds.

164

Table 6.4 Standard UCSB Nitride Recipe Gas Flows

Gas Flow Rate (sccm) SiH4/He (2%/98%) 150

N2 450

NH3 1.53

It is well known that the deposition conditions and gas flows used in a PECVD

nitride process can have a major impact on film properties, especially the subsequent

film stress [16],[17]. The residual stress in a deposited film can be measured by

analyzing the difference in curvature of a substrate before and after deposition as

described in [18]. If the residual stress in our hard mask layer is high, it could

impact the epitaxial layers below it. To determine if stress was a factor in our

process, a 500-nm nitride film was deposited onto a 2” InP substrate using the

standard UCSB recipe, and the residual film stress was measured using a Tencor

Flexus 2320. The resulting film was under tensile strain with a total stress of ~274

MPa. This large degree of stress could definitely impact the surface of an InP layer

underneath the nitride and could perhaps affect the intermixing properties.

To determine if the stress of the nitride mask played a role in the unintentional

QWI of CBE-grown material, we prepared three test samples from a CBE-grown

base structure wafer (Fig. 6.15a). Each sample was annealed at 675°C in N2 for

various time increments after coming in contact with a nitride film without any

phosphorous implant. The control sample (Sample #1) was only exposed to 40 nm

of nitride, which was deposited on the top and bottom of the sample to prevent any

desorption of phosphorous during the anneal (Fig. 6.15b). Because the thick, high-

165

stress nitride mask was never deposited on Sample #1, any unintentional intermixing

in this sample would be due to intrinsic defects. Sample #2 was prepared by first

depositing the standard 500 nm nitride hard mask layer on the sample. The nitride

film in this case was separated from the MQW region by both the upper waveguide

and the implant buffer layer. The nitride was subsequently wet etched in buffered

HF and the sample was encapsulated in 40 nm of nitride for the anneal. Sample #3

was first wet etched in 3:1 H3PO4:HCl to remove the implant buffer layer and then

the high-stress nitride was deposited. In this case the high-stress nitride

Fig. 6.15 (a) 10 MQW base structure grown by CBE. (b) High-stress nitride experiment: Sample #1 was encapsulated with 40 nm nitride and annealed; Sample #2 had 500 nm nitride deposited on the implant buffer layer, the nitride was removed in HF, and the sample was encapsulated in 40 nm nitride and annealed; Sample #3 was first wet etched in 3:1 H3PO4:HCl to remove the implant buffer layer, then 500 nm of nitride was deposited just above the waveguide, the nitride was removed in HF, and the sample was encapsulated in 40 nm nitride and annealed.

(a)

(b)

166

Fig. 6.16 Peak PL wavelength shift versus anneal time for non-implanted CBE-grown samples (see Fig. 6.15b).

was much closer to the MQW region than it was with Sample #2. After the

deposition, the layer was also removed in HF and the sample was encapsulated in 40

nm of nitride.

The PL shift was then measured for each sample after various anneal times (Fig.

6.16). Sample #1 showed very little PL shift after more than 3 minutes of annealing,

comparable to MOCVD-grown material. This indicates that intrinsic point defects

are not the cause of unintentional intermixing. However, both Sample #2 and #3

showed >30 nm of wavelength shift after more than 3 minutes of annealing,

indicating that simply being exposed to the high-stress nitride film is enough to

promote intermixing. Given the high stress level of the film, it is likely that

sufficient strain is transferred into the underlying epi structure to either create a point

defect concentration at the surface or unlock frozen defects within the sample.

However, the PL wavelength shift is time-delayed in Sample #2 by at least 90 sec

167

over Sample #3. This argues in favor of the hypothesis that the nitride actually

creates a point defect concentration at the interface between the dielectric and the epi

structure. The delay in intermixing represents the finite time associated with the

diffusion of these defects down through the implant buffer layer. Once the new

point defect concentration is depleted, intermixing ceases.

The stress in the nitride mask does not affect MOCVD-grown material. Two

MOCVD-grown samples with the same MQW structure were prepared identically to

Samples #2 and #3 above and were annealed. Neither sample showed any

significant PL shift due to interaction with the high-stress nitride film (<6.2 nm after

210 s). The reason for this different behavior is likely due to a fundamental physical

difference between CBE- and MOCVD-grown material at the surface. Chemically

speaking, the surface of samples grown by both methods is essentially identical

according to x-ray photoelectron spectroscopy measurements. However, Fig. 6.17

(a) (b)

Fig. 6.17 Atomic force microscopy scan of the as-grown surface of the (a) CBE-grown epi and (b) MOCVD-grown epi used in this work.

168

Fig. 6.18 Effect of N2 flow on intrinsic stress level in SixNy film. (Data collected by Abirami Sivananthan).

shows that the physical surfaces of each sample are quite different. The MOCVD-

grown sample was almost 3X smoother (RMS roughness = 0.106 nm) than an

identical CBE-grown layer structure (RMS roughness = 0.294 nm). Given this clear

morphological difference, it is not surprising that the CBE material interacts

differently with the high-stress nitride film.

In the case of CBE-grown material, replacing the standard nitride hard mask with

a low-stress (or ideally zero-stress) nitride film is the obvious route to prevent

unintentional intermixing. It was found that changing the flow of N2 (while holding

the flows of all other gases constant) during deposition had a significant impact on

film stress9 Fig. 6.18. As shown in , the intrinsic stress in the nitride layer becomes

less tensile with decreasing N2 flow and eventually turns compressive as that flow

drops below ~48 sccm. The flow rate of N2 can therefore be specifically chosen to

yield an essentially zero-stress film. Obviously, fluctuations in temperature and gas

9 Based on initial experiments by Demis John.

169

Table 6.5 Wet and dry etching comparison of high- and low-stress nitride films

Nitride Film Wet Etch Rate (Å/s)

Dry Etch Rate (Å/s)

Standard high-stress 5.70 ± 0.49 7.39 ± 0.16

New low-stress 5.37 ± 0.50 7.33 ± 0.17

flows do occur during deposition so the new film in practice will be “low-stress” as

opposed to “zero-stress”. Reducing the flow of N2 decreases the deposition rate, and

we expect that the reaction between SiH4 and NH3 is more prevalent in the process.

This would change the film stoichiometry as more hydrogen would be incorporated

due to the difficulty of dissociating the N-H bond at the deposition temperature used

in our process [15]. To ensure that the new low-stress film performs acceptably in

our QWI process, wet (buffered HF) and dry (20:1.8 sccm CH4:O2 at 250V and 10

mTorr) etching comparisons were performed between the high- and low-stress films.

Table 6.5 shows that the etch rates are statistically identical. Furthermore, no

obvious change in the density of pinhole defects was observed in an optical

microscope.

To verify the impact of this new low-stress nitride on unintentional intermixing,

two CBE-grown samples were prepared and annealed in a similar manner as Sample

#2 in the previous experiment. However, one of the two samples was exposed to the

low-stress nitride instead of the standard film. Fig. 6.19 shows the observed PL

wavelength shift for these samples versus anneal time. This result provides further

170

Fig. 6.19 Peak PL wavelength shift versus anneal time for CBE-grown samples masked with high- or low-stress nitride films without an implant. The sample with exposure to only the low-stress nitride showed essentially no intermixing.

evidence that the stress in the standard nitride film is in fact the responsible agent for

the shift in PL wavelength.

As a general rule, high-stress dielectric films can be problematic in a number of

processing steps. It is always advisable to use a low-stress dielectric film when

possible. The low-stress SixNy film investigated in this work is compatible with all

other processing steps in MOTOR fabrication, so it was used exclusively. In the

case of SiO2, our standard PECVD recipe is highly compressive (~-500 MPa). It is

not possible to simply adjust the flow of N2 in this recipe to reduce the stress to zero.

However, the N2O flow in the recipe can be changed to yield a low-stress oxynitride

film [19]. This oxynitride etches like an SiO2 film, so it can be substituted into any

steps using a standard oxide layer. In fact, this low-stress oxynitride was used

successfully in the ridge definition process described above.

171

6.6 CHAPTER SUMMARY

In this chapter we discussed some of the issues involved with the fabrication of the

MOTOR chip. Because the device is quite large compared with typical PICs at

UCSB, we fabricated full 2” InP wafers up through the regrowth. Although this

decision required some nuanced adjustments to our standard fabrication techniques,

it was a reliable way of increasing the number of devices per sample. We also

addressed some new processes that were developed in order to successfully fabricate

the MOTOR chip. Extensive effort was expended to improve the quality of our

ridge etching. A new Cl2/H2/Ar etch chemistry was developed for an ICP etch

system. This process yielded ridges with much smoother sidewalls and lower losses.

We also discussed the development of PECVD recipes that yield low-stress

dielectric films. High-stress films can be problematic in a number of processing

steps, especially in QWI with CBE-grown material. Exposure to a high-stress nitride

film can induce unintentionally intermixing of the QWs in the active region of the

device. Therefore, a new low-stress nitride film was developed and qualified to

eliminate this problem. Each of these new processes is a major improvement in

UCSB InP processing technology with wide application to many different projects.

172

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[17] J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling. Upper Saddle River, New Jersey: Prentice Hall, 2000.

[18] S. Habermehl, "Stress relaxation in Si-rich silicon nitride thin films," Journal of Applied Physics, vol. 83, no. 9, pp. 4672-4677, May 1998.

[19] J. S. Barton, Personal Communication, 2007.

174

Chapter 7

Device Results

In this chapter, the static and dynamic performance of our monolithic tunable optical

router (MOTOR) chip are demonstrated. Following a discussion of the experimental

setup and equipment used, the static performance of the AWGR is characterized, and

channel switching between input and output ports is demonstrated using the SG-

DBR laser. Next, single-channel wavelength conversion and routing results with

PRBS data is shown. Lastly, commentary is provided on the power consumption of

MOTOR and on the overall device yield.

7.1 EXPERIMENTAL PROCEDURE

7.1.1 SAMPLE MOUNTING

The first consideration in the characterization of a large-scale PIC is how to mount

the device securely and in such a way to enable efficient probing of the electrical

contact pads. Typically, single-channel PICs are soldered to Au-coated AlN carriers,

and all device contact pads are wire-bonded to larger probe pads on the carrier.

175

Fig. 7.1 Experimental test setup and mounting configuration for MOTOR characterization.

Because of the MOTOR chip’s size and large diode count, wire-bonding proved

impractical. Therefore, a fabricated MOTOR chip was soldered directly to a copper

block and pads were probed directly (Fig. 7.1). Because the chip has a large surface

area in contact with the Cu block, the thermal expansion mismatch between InP and

Cu is large enough to shatter the sample at high temperatures. To avoid this, a solder

composition (62.5% Sn, 36% Pb, and 1.5% Ag) with a low melting-point was used.

In general, this testing configuration is not ideal in terms of heat sinking, so a

thermoelectric cooler (TEC) was affixed to the base of the block to maintain an

operational temperature of 16°C. This lower temperature helps to reduce thermionic

emission of carriers from the MQW region of the device and improve performance.

7.1.2 TEST EQUIPMENT SETUP

Light was coupled to and from the chip using Corning OptiFocus collimating lensed

fibers, with an estimated coupling loss of 4-5 dB. The response of the AWGR was

176

Fig. 7.2 Schematic of BER test setup. Key to abbreviations: EOM = electro-optic modulator; EDFA = erbium-doped fiber amplifier; VOA = variable optical attenuator; BPF = band-pass filter; PC = polarization controller; PD = photodiode; BERT = bit error rate tester.

characterized using on-chip sources (i.e., MZI SOAs and the SG-DBR) and coupling

the output from each port to an optical spectrum analyzer (OSA). Wavelength

conversion and routing functions of the MOTOR chip were tested under single-

channel operation with PRBS data at 10 and 40 Gbps. The input data signal for

these experiments was generated with a modulated, external cavity, tunable laser

source. This signal was subsequently amplified with an erbium doped fiber

amplifier (EDFA) and filtered with a band-pass filter (1- or 5-nm depending on the

input bit rate). Because the device employs compressively strained MQWs, it is TE-

polarization sensitive and a polarization controller is required at the input to rotate

the data signal to a TE orientation. Although the AWGR provides on-chip filtering

at most wavelengths, an external band-pass filter was placed at the output. The signal

from the chip was then transmitted to a preamplified receiver. Bit error rate (BER)

measurements were made using a 40 Gbps SHF BERT. A schematic of the BER test

setup is shown in Fig. 7.2. Back-to-back BER measurements were made using all

test elements in this setup with the MOTOR chip removed.

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(a) (b)

Fig. 7.3 Output ASE response of the integrated AWGR: (a) measured optical output from all output ports using the MZI SOAs of input wavelength converter #3; (b) measured optical output from output port #2 using the MZI SOAs of each input wavelength converter.

7.2 ARRAYED-WAVEGUIDE GRATING ROUTER PERFORMANCE

7.2.1 STATIC CHARACTERISTICS

The overall performance of the MOTOR chip is largely governed by the

characteristics of the AWGR. The easiest way to determine important AWGR

properties such as the channel spacing and crosstalk is to examine the response of

the AWGR to amplified spontaneous emission (ASE). The wavelength converter

section of the chip contains long SOAs in the MZI that, when forward biased,

behave like edge-emitting LEDs (ELEDs) and generate an ASE signal. To

characterize the spectral response from a single input port, both MZI SOAs were

biased at 300 mA and the output from each egress port was individually measured.

Fig. 7.3a shows a well-defined ASE response with an average channel spacing of

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1.36 nm, corresponding to 173 GHz at 1536.2 nm. The free spectral range (FSR) for

the 8-port router was measured to be approximately 11 nm. It should be noted that

due to variations in the etching of the rib (including the etch depth and sidewall

roughness) there was some variation in channel spacing across the output ports,

which ranged from about 150 to 190 GHz. The single-channel crosstalk is

determined from Fig. 7.3a by measuring the difference between the peak

transmission at the center wavelength of the port of interest and any unwanted

transmission coupled into that port from other channels. For the case of a constant

input port, a crosstalk of -15.8 to -20.9 dB was measured across all output ports. The

most likely reason the observed crosstalk was greater than that predicted in

simulations is that fabrication imperfections and lithographic limitations in our

processing led to phase errors in the arrayed waveguides[1]. However, these

crosstalk levels are still sufficient for our application.

Next, the MZI SOAs in each input wavelength converter were biased pair-by-

pair at a constant bias level of 300 mA and the resulting spectra were measured from

a single output port (Fig. 7.3b). Although some difference in power level is expected

between the center and outer ports of an AWGR [1], this figure illustrates that the

performance of each input port varies, likely due to fabrication and general material

variations across the device. With a constant bias level on all ports, all but one input

port showed crosstalk values in excess of -15.6 dB. Input port #8 only demonstrated

a crosstalk of -12.3 dB, most likely due to a significant waveguide imperfection

somewhere within this port. This reduced crosstalk will translate into a reduced

179

signal to noise ratio (and consequently a larger power penalty) when using port #8,

relative to the other input wavelength converters. However, it is important to note

that the spectral uniformity between input ports and the maximum crosstalk could be

improved by optimizing the biasing conditions for the MZI SOAs of each port

individually. Aside from simplifying the programming of the control circuitry for

the MOTOR chip, there is no reason that the bias levels from port to port must be the

same.

The next important AWGR parameter to determine is the insertion loss, or the

total optical loss associated with traversing the AWGR region. Given the current

architecture of our device, it is not possible to directly measure this loss without

cleaving between the AWGR and the wavelength converter array, thereby sacrificing

an entire device. As this is not desirable, a procedure was devised to estimate the

total throughput loss between the exit of the wavelength converters and the output of

the AWGR. This was accomplished by measuring the total power (including ASE)

directly at the exit of the wavelength converter in an integrated power monitor diode

(with the SG-DBR, booster SOAs, and MZI SOAs forward biased at typical

operating conditions) and comparing this power with the fiber-coupled power from

the chip. It was first necessary, however, to calibrate the power monitors (as a

function of length) in order to estimate the quantum efficiency of these diodes. To

do this, a CW signal was coupled “backwards” into the MZI region through the

AWGR. The wavelength of this signal was carefully chosen to maximize the power

into the wavelength converter. As shown in Fig. 7.4, two power monitor pads lie in

180

Fig. 7.4 Layout of power monitor (PM) pads within the MZI.

the same path as the long SOA on the upper branch of the MZI. Because this SOA is

~1000 μm in length and consists of centered MQWs, we can assume that the

quantum efficiency is essentially unity and all input light in this waveguide is

detected. We can then measure the detected power into each power monitor in this

path to roughly gauge the absorption as a function of length and reverse bias. We

can then extrapolate from these points to estimate the absorption in the shorter power

monitor positioned at the output of the wavelength converter (here we assume that

the absorption is linear versus diode length to first order). Using this technique, we

estimate that the power monitor at the output of the wavelength converter detects

approximately 1/20 of the actual power in the waveguide. The total output power at

the exit of the wavelength converter was thus measured to be ~8.3 dBm. The power

out of the AWGR was coupled into an output fiber and measured in an OSA and

determined to be on the order of -4.5 dBm. Assuming 4-5 dB of coupling loss, the

total power loss through the AWGR is estimated to be ~8-10 dB. It is important to

note that this loss also includes the loss associated with transitioning from the

SOAs 175 μm PM 83.26 μm PM

To AWGR52.75 μm PMMZI

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surface ridge waveguide of the wavelength converter to the buried rib waveguide of

the AWGR, which could not be measured directly.

To improve overall device performance, the total loss in the AWGR region

should be reduced. The higher than desired loss in our structure is likely due to two

main factors. First, because the input and output lines of the arrayed waveguides are

defined with the buried rib structure in which the waveguide layer is etched, sidewall

roughness can result in high scattering losses. This would especially affect the input

and output waveguides to and from the star couplers, which range in length from 6 to

10 mm. In future designs, a more compact AWGR design similar to that of [2] would

be an interesting alternative, as it would significantly reduce the propagation length

in the AWGR. A second contribution to our AWGR loss is the coupling loss between

the star couplers and the arrayed waveguide. Our lithographic capabilities should

allow us to bring the waveguide separation down from the current value of 0.8 μm to

at least 0.5 μm in the future to help reduce these losses.

7.2.2 DEMONSTRATION OF CHANNEL SWITCHING

One of the essential functions of the MOTOR chip is the ability to route data from

any input port to any output port based on the wavelength of the data signal. The

wavelength of the converted signal is set by the biasing conditions of the SG-DBR.

This wavelength must correspond to the allowed output wavelength of a given

AWGR port in order for the light to propagate. To verify the tuning characteristics

182

(a) (b)

Fig. 7.5 (a) Lasing spectra for different biasing conditions using the SG-DBR of input wavelength converter #3, measured from output port #1. (b) Demonstration of channel-switching from a single input port to any output port by tuning the SG-DBR mirror biases.

of the SG-DBR, we adjusted the forward bias levels on the front and back mirror

pads (the phase pad can also be biased for fine-tuning, but this is generally not

needed) and monitored the output. The booster and MZI SOAs, which lie between

the laser and the output of the chip, were also forward biased to allow the signal to

propagate into the AWGR without being absorbed. Fig. 7.5a shows the resulting

spectra for two different mirror biasing conditions from a single input wavelength

converter to a single output. In this configuration, we measured output powers of

more than -5 dBm. Once the mirror bias conditions are mapped out, it is then

possible to address all output ports from each input port to perform the channel

switching function of the chip. Fig. 7.5b demonstrates this result for input port #3,

showing the ASE spectra for each output port superimposed on the corresponding

lasing spectra.

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(a) (b)

Fig. 7.6 MZI transfer function for: (a) a constant input port (#3) measured at all output ports; and (b) various input ports measured from a constant output port (#3).

7.3 WAVELENGTH CONVERSION AND ROUTING

7.3.1 MACH-ZEHNDER INTERFEROMETER PERFORMANCE

The integrated MZI switch is a critical element to achieve wavelength conversion in

our device. As explained in Chapter 4, input data pulses change the phase within the

MZI to open or close the switch. This process carves the data pattern onto the CW

probe signal. The MZI switch should therefore have a high extinction ratio between

its open and closed state to maximize the output signal to noise ratio. Fig. 7.6 shows

the electrical transfer function of our MZI with an input CW signal from the SG-

DBR as a function of applied current to a 175-μm integrated phase tuning pad within

the MZI. Applying current to the phase pad induces a negative refractive index

change in this section of waveguide [3], so that a full π phase difference can be

184

created between opposite branches of the MZI. With the proper bias on the phase

pad, our structure can provide 25.1 dB to 29.6 dB extinction of the on-chip CW

signal. The bias point for maximum extinction is not constant from wavelength

converter to wavelength converter, but is essentially constant for all output ports

when biasing a single input port. However, this variation between ports is not

problematic in practice because the proper value of the phase tuning pad for each

port would simply be programmed into the electronic control system for the chip.

7.3.2 10 GBPS NRZ WAVELENGTH CONVERSION

To investigate the combined process of wavelength conversion and routing in the

MOTOR chip, we first considered 10 Gbps NRZ data. Although our device is not

designed specifically for 10 Gbps operation, the gain recovery time in the MZI

SOAs is fast enough to modulate the MZI gate. The propagation time in our delay

line is specifically chosen to create a 40 Gbps switching window, so the time-

delayed branch of the chip is turned off in this experiment by reverse biasing the

preamplifier that follows the delay line.

Fig. 7.7 shows BER measurements for a single input port and two different

output ports using PRBS 231

4

-1 data. Power penalties as low as 1.3 dB at a BER of

1E-9 and open eyes with extinctions of 8.8 dB were demonstrated. This power

penalty is on par with that reported in [ ] for a QWI platform and that reported in [5]

185

Fig. 7.7 BER results for 10 Gbps conversion of PRBS 231

for a field-modulated wavelength converter on a dual quantum well integration

platform. One of the main reasons the power penalty was higher with our SOA-

based approach to wavelength conversion is that each SOA generates a significant

amount of amplified spontaneous emission (ASE). ASE leads to noise which is

visible in the zero and one levels of the eye diagram (

-1data for one input port and two different output ports.

Fig. 7.8). This effect is even

(a) (b)

Fig. 7.8 Eye diagrams for 10 Gbps signals: (a) back-to-back measurement; and (b) converted signal from input port #6 to output port #3 (1543 nm 1547.9 nm) with the time-delayed branch turned off.

186

Fig. 7.9 ASE power versus length for c-MQW based SOAs.

more pronounced in our device because we use a c-MQW active region with high

optical confinement. The ASE for various length SOAs is shown in Fig. 7.9.

Substantial ASE is generated in long SOAs because photons created by spontaneous

emission at the front end of the SOA can stimulate recombination events over a

longer length.

Additionally, the converted eye diagram shows slow rise and fall times. This is

likely due to a pattern dependence arising from the preamplifier SOAs, which have

been shown to have relatively slow gain recovery times (in contrast, the gain

recovery times in the MZI SOAs are much faster due to the CW optical power from

the SG-DBR) [4]. However, this pattern dependence does not appear to impact the

power penalty significantly, likely because the 10 Gbps data rate used in this

experiment was slow enough to allow some gain recovery in the preamplifiers

between bits.

187

7.3.3 40 GBPS RZ WAVELENGTH CONVERSION

Having confirmed that the device functions well at a 10 Gbps data rate, we now turn

our attention to the conversion and routing of 40 Gbps data. As explained in Chapter

4, the gain in the MZI SOAs cannot recover fast enough to convert 40 Gbps signals

using the single-sided MZI approach used for 10 Gbps data. To overcome this

limitation, we utilize the differential delay line on the chip and its associated

preamplifier. Typical biasing levels for 40 Gbps operation are listed in Table 7.1. As

described in [6], a differential MZI-based wavelength converter will have a lower

power penalty if operated with a slight power imbalance between the two branches

of the MZI. This helps to match the power level of the delayed pulse with the non-

delayed pulse for more efficient extinction in the MZI. In principle, a power

imbalance can be created in our device in two ways: (1) the relative CW power into

the MZI can be changed by adjusting the two booster SOAs; or (2) the

Table 7.1 Typical bias conditions for differential MZI wavelength converter

Component Bias (mA) Preamplifier (Non-Delay Side) 130-140

Preamplifier (Delay Side) 90-110

Booster SOAs 30-60

MZI SOAs 210-290

MZI Phase Tuner 0-8

SG-DBR Gain 100-1100

SG-DBR Front Mirror 0-25

SG-DBR Back Mirror 0-25

188

relative input pump power can be changed by controlling the preamplifier biases or

reverse biasing one of the on-chip VOAs. Creating an imbalance of the CW signal is

not desirable because it leads to different gain recovery times in the MZI SOAs,

which causes poor phase matching in the MZI. Therefore, it is more desirable create

a power imbalance with the input data signal. Often, the loss through the delay line

is sufficient to create this imbalance. However, in our case, we consistently saw

lower loss on the delay-line side of the chip, so we chose to bias the preamplifiers at

slightly different levels. We also found that greater extinction in the MZI could be

achieved by unequally biasing the MZI SOAs and then adjusting the phase tuning

pad.

Since we saw some pattern dependence for long pattern lengths at 10 Gbps data

rates, we first measured single-channel 40 Gbps wavelength conversion with PRBS

27 Fig. 7.10-1 patterns. shows BER measurements for two different output ports

using a constant input port. Although we see indications of the beginning of an error

floor at low BERs, we can still achieve error-free operation for our device with a

power penalty of 3.5 dB (at a BER of 1E-9) for this pattern length. The error floor

will become more of a dominant factor as we move to longer pattern lengths. These

results also demonstrate the ability of MOTOR to operate as a switch fabric as the

input data in one port can be transferred to a different output port by simply

changing the SG-DBR mirror biasing conditions.

189

Fig. 7.10 BER measurements for PRBS 27-1 pattern lengths for input port #3 to output ports #5 and #6.

Fig. 7.11a shows the BER for wavelength conversion with PRBS 231

Fig. 7.12

-1 patterns.

These results demonstrate that BERs below 1E-9 are still possible for the combined

wavelength conversion and routing process with longer pattern lengths, but the

power penalty increases. Open eye diagrams were also obtained for all eight output

ports using this single input channel ( b). Next, we measured the BER and

the associated eye diagrams for wavelength conversion of PRBS 231-1 patterns from

multiple input channels through a constant output port (eye diagrams are not shown

for three of the eight wavelength converters due to yield issues that will be explained

in a later section). Overall, the measured power penalties in the chip for this bit rate

and pattern length range from approximately 4.5 to 7.0 dB (depending on the input

port). The maximum extinction achieved in the eye diagrams from this experiment

190

(a) (b)

Fig. 7.11 (a) BER measurements for a single input wavelength converter at 40 Gbps monitored from different output ports. Back-to-back BER measurements are also included for the converted wavelengths. (b) Open eyes diagrams for a single input measured from all eight output ports.

(a) (b)

Fig. 7.12 (a) BER measurements for several input wavelength converters at 40 Gbps monitored from a constant output port. Back-to-back BER measurements are also included for the converted wavelengths. (b) Open eyes diagrams for several inputs measured from a constant output port.

was 11.24 dB. As expected, the error floor is higher for these longer pattern lengths

and the power penalty increases. This error floor makes it difficult to optimize

191

wavelength converter conditions to achieve error-free operation. Any deviation from

this “sweet spot” pushed us to BER > 1E-9, so it was not possible to measure the

dynamic range of the device.

The noise floor and high power penalty seen in these results are likely attributable

to reflections in the chip and saturation effects in the preamplifiers. Reflections

cause optical feedback that can lead to noise and thus an increased power penalty

[7]. We expect that reflections exist in our device from two sources. First, the tested

MOTOR chip was not antireflective (AR) coated. This important step was not

included in the process flow because there is currently no reliable in-house AR

coating solution at UCSB. Sending the chip to an external vendor was deemed

impractical because the chip would not likely survive the process, given its large size

and fragility. Additionally, reflections may exist at the transitions between the three

different waveguide architectures. Unfortunately, it is not possible to determine how

much of an issue this is from our data. However, the most obvious source of

reflections at the facets can be solved in future MOTOR designs with an optimized

AR coating.

Second, the data above show a clear pattern dependence during wavelength

conversion. This is most likely due to saturation in the preamplifier SOAs which are

made from the centered MQW band edge. Ideally, the input pump power to the MZI

SOA should be greater than 4 dBm to deplete the MZI SOAs of carriers and

modulate the gate. The actual unsaturated gain from the preamplifier would

probably be enough if the MZI SOA were in a direct path with the preamplifier, but

192

Fig. 7.13 Input power in the MZI SOA versus the input power measured in the preamplifier. The red line indicates the minimum pump power level required in the MZI. The total gain of the preamplifier is ~3 dB more than shown here due to a 50/50 MMI splitter between the preamplifier and the MZI.

an MMI coupler is used to combine the amplified input signal with the CW probe

signal before the MZI. As a result, at least 3 dB of the input signal is lost in the

combining process. In order to reach the 4 dBm power level, we found we must

operate the SOA beyond the 1-dB saturation point, in the nonlinear gain regime (Fig.

7.13). This resulted in pattern distortion effects and an increased BER. In order to

overcome these limitations, a more complex preamplifier structure will be required.

This would likely involve modifying our integration strategy to allow an additional

regrowth step of MQWs outside of the center of the waveguide to reduce the

confinement factor and increase the saturation power. These options will be further

explored in Chapter 8.

193

7.4 MULTI-CHANNEL CONSIDERATIONS

The results reported here apply only to single-channel operation. Moving to multi-

channel operation will not only require more elaborate biasing and fiber coupling

schemes, but will also increase the expected power penalty for the switching process.

One key reason for this is the increased heating in the device with all diodes biased.

This heating will lead to signal degradation and reduced output power due to thermal

crosstalk effects in both the wavelength converters and the AWGR. Efficient heat

sinking will therefore be vital to overall performance.

In general, dual-channel measurements are not trivial as they require twice as

many current sources, twice as many fiber stages, and twice as many data sources.

Our current testing approach of mounting the chip on a copper block and directly

probing the bond pads is not amenable to multi-channel testing because there is

simply no way to double the number of probe holders and safely probe the chip.

Future plans for more efficient device mounting will be discussed in Chapter 8.

However, because thermal crosstalk effects are important to understanding full

operation of this chip, we examined how biasing pads in nearest-neighbor

wavelength converters impacted operation. Fig. 7.14 shows the impact on the SG-

DBR wavelength as a function of bias on neighboring pads. We measured a

noticeable wavelength shift when a pad close to the SG-DBR gain section was

biased. This shift was even more pronounced when two nearby pads were biased.

Indications of thermal crosstalk in this simple experiment suggest that multi-channel

194

Fig. 7.14 Effect of thermal crosstalk on the SG-DBR wavelength of an input port when the nearest neighboring pad in a second channel is biased. The measurement was done with and without the gain section of the neighboring SG-DBR biased.

performance will be strongly affected by heating. It is important in future designs to

consider methods to better thermally isolate each channel.

7.5 POWER CONSUMPTION CONSIDERATIONS

One of the major advantageous of moving towards an all-optical approach to packet

switching is a reduction in power consumption and power density over electronic-

based routers. The wavelength conversion and switching functions of the MOTOR

chip come at a relatively low cost in terms of power consumption. Under normal

operating conditions, the single-channel drive power is less than 2 W, giving an

overall expected drive power of less than 16 W for 8-channel operation. However,

additional power is necessary for TEC cooling. In our current testing configuration,

the TEC requires ~0.5 W to maintain a single channel at the 16°C temperature used

195

during testing. This translates into an overall power consumption of 0.0625

W/Gbps. The TEC demand will necessarily increase with multiple channels

running, but it is not safe to assume that this demand will scale linearly. In a real

application, the chip would be packaged with a more efficient heat-sinking solution

(i.e., flip-chip bonded for top side heat transfer) so it may be possible to reduce the

overall TEC demand. While the results reported here are promising, further work to

characterize TEC demands for multi-channel operation is needed before accurate

comparisons with electronic switch fabrics can be drawn.

7.6 YIELD CONSIDERATIONS

Many of the trade-offs inherent in our design were a result of an integration strategy

geared towards fabrication simplicity with the goal of improving fabrication yield.

However, the overall yield was difficult to quantify due to a critical error while

processing. As discussed in Chapter 5, the cladding regrowth was outsourced to an

external vendor. Unfortunately, the doping profile specified for the cladding did

have a high enough Zn dopant concentration in the beginning stages of the growth to

compensate for the inevitable Si spike at the regrowth interface. This resulted in the

formation of a p-n junction above the waveguide, so very few photons were

generated when the sample was biased. Luckily, we were able to diffuse the Zn to

the correct depth post-growth through a high-temperature anneal. Because the chip

had already been thinned for cleaving at the time this problem was discovered, the

196

chip had a propensity to bow slightly in the anneal, causing the backside n-metal to

delaminate. We found that encapsulating the chip in thin layers of nitride removed

this problem, but two chips were lost while dialing in the process. Once calibrated,

the anneal step proved to be extremely repeatable, but had to be done on a chip-by-

chip basis. Therefore, it is hard to make conclusive statements about chip yield

across the wafer. In the future, this problem can easily be avoided by correcting the

cladding regrowth doping profile.

In terms of the component yield for the main chip tested in this work, the number

of functioning diodes was quite high (only one critical diode was found non-

functional during our initial screening). Two input ports did not function because of

a random ridge defect in the MZI region, so these channels could not process data.

The preamplifier of a third channel was damaged during testing, so only 10 Gbps

data could be processed in this port. However, all working channels have an

identical structure, so we know that these failures were random in nature and not

indicative of systemic problem. In spite of the damaged channels, these yield results

are reasonable for work in a cleanroom environment in which equipment is shared

among many experimental projects. If a dedicated InP manufacturing fab was

available for MOTOR chip fabrication, the chip yield could certainly be improved.

7.7 CHAPTER SUMMARY

We have demonstrated the functionality of an 8 x 8 monolithic tunable optical

197

router. The router consists of an AWGR that provides reasonable crosstalk levels in

excess of -15 dB for all but one port. The 8-10 dB total loss of the AWGR was

slightly higher than anticipated, most likely due to sidewall roughness in the buried

rib waveguides and coupling loss to and from our star couplers. We have also

demonstrated the ability to perform channel switching by simply tuning the mirrors

of the SG-DBR laser.

The full wavelength conversion and routing properties of the MOTOR chip have

also been investigated for single-channel operation. 10 Gbps NRZ operation is

possible with a power penalty as low as 1.3 dB. Using a DMZI approach, we can

operate the device at 40 Gbps. The power penalty associated with RZ wavelength

conversion and routing depends on the pattern length due to nonlinearities in the

preamplifiers, but is as low as 3.5 dB for PRBS 27-1 patterns and 4.5 dB for PRBS

231

Lastly, we discussed the yield of the MOTOR chip. A critical element of our

integration strategy was to reduce the epitaxial growth complexity to improve the

yield. Unfortunately, a problem with the doping profile in our chip led to the

formation of an unwanted p-n junction at the regrowth interface that initially

-1 patterns. Although error-free operation (i.e., BER < 1E-9) is possible, the

nonlinear behavior of the preamplifiers and reflections within the chip lead to the

formation of an error floor at low BERs. These issues will likely become more

problematic when moving to multi-channel operation due to thermal crosstalk

effects. The power consumption of our chip during single-channel operation is less

than 2 W with a TEC of about 0.5 W, which equates to 0.0625 W/Gbps.

198

rendered our device optically dead. Although an anneal procedure was developed to

fix this issue, several chips were lost in the process so across-wafer yield statistics

are not available. On a single-chip level, we found that the vast majority of

components in the chip functioned, but a few random defects led to two ports not

functioning as desired. In the future, improved yield should be attainable by

correcting the cladding dopant profile and moving the fabrication to a dedicated PIC

processing facility.

199

REFERENCES

[1] M. K. Smit and C. v. Dam, "PHASAR-Based WDM-Devices: Principles, Design and Applications," IEEE Journal of Selected Topics in Qunatum Electronics, vol. 2, no. 2, pp. 236-250, Jun. 1996.

[2] J. H. d. Besten, et al., "Low-Loss, Compact, and Polarization Independent PHASAR Demultiplexer Fabricated by Using a Double-Etch Process," IEEE Photonics Technology Letters, vol. 14, no. 1, pp. 62-64, Jan. 2002.




[6] A. Bhardwaj, et al., "Wavelength conversion using semiconductor optical amplifiers in differential mach-zehnder interferometer with tunable input coupler," Electronics Letters, vol. 45, no. 4, pp. 225-227, Feb. 2009.

[7] G. P. Agrawal, Fiber-Optic Communication Systems, 3rd ed. John Wiley & Sons, Inc., 2002.

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Chapter 8

Summary and Future Directions

8.1 SUMMARY OF DISSERTATION

The goal of this work was to demonstrate a monolithically integrated tunable optical

router chip that functions as the switch fabric in an all-optical router. The chip

consists of an array of eight 40 Gbps widely-tunable wavelength converters and a

passive arrayed waveguide grating router (AWGR), providing a total potential data

capacity of 640 Gbps. The device requires a very high level of integration,

incorporating diverse components like tunable lasers, linear SOAs, nonlinear SOAs,

and low-loss waveguides on the same chip. The chip has over 200 functional

elements in a 14.5 mm x 4.25 mm footprint. This is on par with or exceeds the

component density of other state-of-the-art PICs in both academia and industry.

8.1.1 INTEGRATION AND PROCESSING TECHNOLOGIES

In order to realize a PIC with this level of complexity, a comprehensive integration

strategy that is designed to achieve high fabrication yield is required. In general, the

201

functional complexity of a PIC can be increased by incorporating epitaxial regrowths

or additional fabrication steps into the manufacturing plan. However, both epitaxial

growth and fabrication complexity can detrimentally impact yield, so the optimal

design for large-scale PIC development must leverage the inherent risk of these steps

with the flexibility they provide the PIC designer. In this work, we opted to limit the

number of regrowth steps to one, as we typically have more control over the

outcome of our standard processing steps.

Our integration strategy for MOTOR has three main thrusts. We use:

1. A centered multiple quantum well (c-MQW) active region

2. Quantum-well intermixing for active/passive definition

3. A single, blanket cladding regrowth

The key advantage of this approach is that the manufacturing process calls for only a

one InP regrowth step. Regrowths add complexity to a process, as the quality of the

regrown layers depends directly on the condition of the sample surface. Non-visible

defects at the sample surface prior to growth can spawn very large fatal defects

during the growth process. This is especially important in large-scale PICs like

MOTOR where the chip area is large and the number of components that must

function properly is high.

This approach introduces several notable trade-offs. First, using only one

regrowth limits the type of band edges on the chip to whatever exists in the initial

base growth. Since the components in MOTOR have differing desirable optical

properties, we instead fabricate multiple waveguide architectures across the chip.

202

This gives us flexibility as we can control the degree of optical confinement in

particular components. In our device, we use surface ridge, deeply-etched ridge, and

buried rib waveguides. The surface ridge is used for the majority of the wavelength

converter array, because it is simple to fabricate through a combination of dry and

selective wet etching. Although the selective wet etch allows us to target very

precise etch depths, it is crystallographic in nature, so waveguide angles must be

kept below about 15° off of the [011] direction. For our differential delay line we

use a deeply-etched waveguide structure in which we dry etch completely through

the waveguide layers so that the optical mode is clad laterally by air. This allows us

to utilize tight bends to keep the delay line compact. In the AWGR, we use a low-

index-contrast buried rib design defined by dry etching. This waveguide structure

should provide low loss and is not constrained to any particular angles.

By incorporating different waveguide designs, we can significantly improve the

performance of MOTOR, but we also increase the fabrication risk by adding

additional etch steps. For this reason, significant effort was invested in improving

our in-house etching techniques. We developed a new Cl2/H2 based ICP etch

chemistry that provides smooth and straight sidewalls. This improves scattering

losses which would otherwise be quite high in our long passive sections.

Additionally, this etch chemistry is extremely repeatable from run to run and is very

uniform across a wafer. This new development helps to de-risk the waveguide

definition steps.

203

Next, our use of a single regrowth means that Zn-doped cladding, which is

optimized for efficient active diodes, is directly above passive waveguide sections.

This will significantly increase the passive optical losses due to free-carrier

absorption. To circumvent this problem, we leave the UID implant buffer layer

(which is included in the base growth for intermixing purposes) in certain passive

regions of the chip. This allows us to separate the optical mode from Zn-doped

material without the need of a special undoped InP regrowth. We have demonstrated

that the implant and anneal steps used in QWI do not adversely affect the surface

quality of the implant buffer layer, so it can be used for high-quality regrowth. This

technique has been applied in both the differential delay line and the AWGR. The

surface ridge areas of the chip are finished by wet etching, so this technique could

not be applied in these regions. Therefore, we also use a proton implant to neutralize

Zn atoms in the cladding, which reduces the optical loss by more than three times.

An additional trade-off exists because we use a c-MQW layer structure. This

design maximizes the optical confinement of the mode and makes it relatively easy

to realize high-gain and low-saturation power elements. Unfortunately, this means

that the preamplifier SOAs (which should be highly linear) also use a c-MQW active

region. In an effort to avoid nonlinear behavior, we keep the length of this SOA

short. Unfortunately, this also reduced the maximum gain. In order to get enough

input power into the MZI for wavelength conversion, we found we had to operate the

preamplifiers beyond the 1-dB output saturation power point. This led to pattern

dependence in the device and an increased power penalty.

204

Lastly, because our integration strategy uses strained QWs for improved

performance, the device is polarization sensitive. We overcame this obstacle while

testing the chip by using an external polarization controller just before the input fiber

to the chip. While this is acceptable for device characterization, it is not practical for

a real system in which the incoming polarization state changes with time.

Suggestions on how to overcome this obstacle are provided later in this chapter.

8.1.2 DEVICE RESULTS

Using the integration strategy above, we successfully demonstrated MOTOR chips

capable of wavelength conversion and routing. Single-channel operation was

demonstrated at two different data rates. We have shown 10 Gbps NRZ operation

with a power penalty as low as 1.3 dB by running the wavelength converter single

sided (i.e., not using the differential delay side of the chip). We also demonstrated

40 Gbps RZ operation using the differential MZI approach. The drive power to

operate a single channel at 40 Gbps was less than 2 W with a TEC demand of only

0.5 W. The power penalty for wavelength conversion and routing is as low as 3.5

dB for PRBS 27-1 patterns and 4.5 dB for PRBS 231-1 at BER < 1E-9. The power

penalty in our device stems mainly from the nonlinear behavior of the preamplifiers

and reflections within the chip and at the input/output facets, which were not AR

coated. At low BERs, we start to see an error floor so very fine tuning of the laser

205

and amplifier biases is required to achieve error-free operation. These issues will

likely be magnified under multi-channel operation due to thermal crosstalk effects.

The yield of the MOTOR chip was difficult to quantify due to a problem with the

doping profile in the cladding regrowth. This error led to the formation of a p-n

junction at the regrowth interface that shunted carriers away from the MQW region.

Although a repeatable high-temperature anneal procedure was developed to correct

the doping profile, we were not able to accumulate across-wafer yield statistics. On

a chip-by-chip basis, we found that the vast majority of the diodes in the chip

functioned, but random defects affected the performance of several ports. In two

cases, these random defects were fatal, leaving an entire port non-functional. In

principle, improved yield could be achieved if the fabrication of the MOTOR chip is

performed in a dedicated InP foundry with tight process controls, as opposed to the

shared research cleanroom used in this work.

8.2 FUTURE DIRECTIONS

8.2.1 1.28 TBPS CAPACITY 16 X 16 MOTOR DESIGN

The techniques developed in this work can be used to expand the overall data

capacity of the next-generation MOTOR chip to 1.28 Tbsp. The simplest way to

accomplish this is to double the number of input and output ports. However, simply

doubling the channel count using our existing design would also approximately

206

double the chip size. If such a plan is pursued, the chip area will be so large that we

could only fit one MOTOR chip on a single InP quarter wafer or about seven chips

on a full 2” wafer. Therefore, our overarching design goal should be to double the

capacity without doubling the size. In order to meet this goal, we must redesign the

wavelength converter and the AWGR to minimize their footprint.

On the wavelength converter side, this can be accomplished by substituting

deeply-etched TIR mirrors for many of the waveguide bends (including the delay

line) in the chip. These TIR mirrors allow us to turn the mode by 90°, so a more

compact configuration is possible. Previous TIR mirrors demonstrated at UCSB had

about 1 dB loss per mirror, but these mirror facets were etched using the old RIE

process. We believe we should be able to push the losses well below 1 dB using the

Unaxis etch chemistry developed in this work. Fig. 8.1 shows that this approach can

shrink the length of the wavelength converter by 3 mm over the current design.

Fig. 8.1 Comparison of 1st and 2nd generation wavelength converter designs. The new folded design uses TIR mirrors to reduce the chip length by 3 mm.

7.5 mm

4.5 mm

1st Generation Wavelength Converter:

2nd Generation Wavelength Converter (Folded Design):

SG-DBRλin λout

TIR Mirror

207


The AWGR also needs to be redesigned for compactness. In our current device,

we utilize a buried rib waveguide that has low index contrast. Because the mode is

not tightly confinement, bend radii in the array arms cannot be small without

significant radiation losses. However, if we instead deeply etch the array arms, we

can decrease the bend radius to around 100 μm and reduce the overall footprint

significantly while doubling the number of input and output ports (

generation AWGR designs. The new design reduces the component footprint by using deeply-etched waveguides for the array arms.

Fig. 8.2).

Although the deeply-etched waveguide architecture is well-suited for the array

arms, it should not be used on the star couplers themselves. Because lithographic

resolution limits do not allow us to have an infinitely narrow spacing between array

arms at the star coupler, a deep etch of the star coupler would essentially create tiny

mirrors at the entrance to and exit from the arrayed waveguides. This would lead to

very high insertion losses. Instead, we can employ a shallow-etched waveguide in

the star coupler region that allows for better coupling to the arrayed waveguides [1].

208

(a) (b)

Fig. 8.3 (a) Schematic cross-section of the shallow-etched portion of the array arms showing an InP wing above the waveguide layer. (b) Effect of the height of the InP wing on the index contrast and the ideal number of arrayed waveguides (the red line shows the target InP wing height for our new design).

To transition into the deeply-etched array arms, we will need to incorporate shallow-

to-deep waveguide transitions like the ones used in our current delay line.

An additional benefit of this deeply-etched design is that we would no longer

need a separate etch step to define the AWGR prior to the regrowth. The initial

definition of all ridges (including the TIR mirrors, star couplers, and arrayed

waveguides) can now be done simultaneously in a single dry etch step. This etch

must be timed such that a thin layer of InP is left on top of the quaternary wave

guide layer. The TIR mirrors and the entire AWGR would be masked and the

exposed areas of the wavelength converters would then be wet-etched as before.

Because this etch is crystallographic, the waveguides that run parallel to the major

flat of the wafer will overcut and widen somewhat, but this effect will not prove

deleterious to device performance. Thick SiO2 can be deposited across the sample

and lifted-off in the TIR mirrors and arrayed waveguides (as was done before for the

209

deeply-etched delay). A second dry etch can then be performed to deeply etch the

mirrors and array arms.

It is important to note that the star coupler region is only etched during the first

etch step. This means that a thin layer of InP will be left on both sides of the ridge

(Fig. 8.3a). This is not important in the star coupler itself, but does have an impact

on the shallow-etched portion of the array arms. The thickness of this InP wing will

affect the index contrast and, hence, the number of array arms needed in the AWGR.

As the wing height increases, the mode in the shallow-etched portion of the array

Table 8.1 Potential design parameters for the 2nd

Parameter

generation MOTOR AWGR

Value InP wing height 150 nm

Star coupler index 3.282237

Index contrast 0.0206

Waveguide width (wg) 1.7 μm

V-parameter 4.4599 Center wavelength (λc) 1.55 nm

Channel spacing (Δλch) 100 GHz

Number of ports (N) 16

Receiver spacing (dr) 4 μm

Array spacing (da) 3.75 μm

Free spectral range 12.8 nm

Length difference in array arms (ΔL) 49.3 μm

Star coupler length (Ra) 508.2 μm

Aperture width (θa) 0.1655

Number of arrayed waveguides 46

210

Fig. 8.4 New 1.28 Tbps 16 x 16 MOTOR design.

arms is less confined and larger in size so fewer arrayed waveguides are needed to

collect the diffracted beam from the star coupler (Fig. 8.3b). The complication with

this approach will be ensuring that the correct etch depth is achieved in the star

coupler region. Fortunately, the Unaxis etch chamber has a fairly repeatable etch

rate and is equipped with an etch monitoring system that could be used for more

accuracy. Even if the etch depth is off by ± 50 nm, the required number of

waveguides will only change by four, so the filter function of the AWGR should not

change significantly. Potential design parameters for this new AWGR using a wing

height of 150 nm are given in Table 8.1.

A preliminary 16 x 16 MOTOR design is shown in Fig. 8.4. By employing the

folded wavelength converters and deeply-etched AWGR presented in this section,

the 1.28 Tbps MOTOR chip area can be reduced to about 9 mm x 8.2 mm for a total

211

area of ~74 mm2

8.2.2 IMPROVED PREAMPLIFIER DESIGN

. This is only 1.2X larger than the first generation MOTOR chip

even though it has twice the data capacity. The width of the chip is limited by the

spacing of the wavelength converters. The length of the chip is fixed by both the

length of a single wavelength converter and the required spacing of the output

waveguides from the AWGR. In order to package the chip with an array of fibers,

the output waveguides must be spaced by at least of 250 μm. With 16 channels, this

means at least 4 mm of real estate is consumed just for output coupling.

Nonlinearities in the preamplifier SOAs were one of the major sources of power

penalty in the 1st generation MOTOR chip. It is important to address this issue in

either future runs of the current design or the next generation chip. One possible

approach that is being considered with the 2nd

One promising option would be to create a dual-section SOA consisting of a high

gain element and a high saturation power element [

generation device is to simply

eliminate the preamplifiers altogether and increase the input power. While this may

be acceptable for a laboratory demonstration, it would be more ideal to incorporate a

new preamplifier design that leads to improved performance.

2]. This would involve

combining a short c-MQW SOA with a long MQW SOA section that is regrown

some distance above the center of the waveguide (Fig. 8.5). This method has

demonstrated SOAs with gains as high as 15 dB and output saturation powers of

212

Fig. 8.5 Side view of dual-section SOA with high-gain c-MQW section and high-saturation-power regrown low-confinement SOAs.

more than 19 dBm. However, the additional blanket regrowth could have a negative

impact on device yield. Furthermore, these regrown SOAs are typically 1200-1700

μm in length so drive biases are on the order of 350-500 mA. Two of these SOAs

(one on each side of the chip) would significantly increase the power consumption of

chip, but the improved performance may warrant the additional power cost.

We have fabricated test structures for this dual-SOA structure with the regrown

wells placed different distances from the center of the waveguide. This is achieved

by varying the thickness of an InP spacer layer (or confinement tuning layer (CTL))

between the regrown wells and the waveguide core (see Fig. 8.5). As the thickness

of this layer increases, the confinement factor in the wells goes down and the

saturation power increases [3]. The first design used a relatively thin CTL of 60 nm

and the second used a thicker CTL of 105 nm (Fig. 8.6). As expected, Design 1

provides higher gain and lower saturation power because the regrown wells have a

higher overlap with the optical mode. Design 2 shows a much more linear gain

response because of the enhanced saturation power that results from the thicker CTL

213

(a) (b)

Fig. 8.6 Dual section SOA with a short c-MQW SOA followed by a low-confinement regrown MQW SOA with a CTL thickness of: (a) 60 nm; and (b) 105 nm.

layer used in this design. The overall gain in Design 2 was slightly lower than

expected due to a complication with the regrowth. However, either of these two

designs provides more than enough unsaturated output power to deplete the carriers

in the MZI SOAs for efficient wavelength conversion, and would be a good addition

to our device.

8.2.3 10 GBPS LABEL WRITING CAPABILITY

As shown in Chapter 1, MOTOR was designed for use in a label-swapped all-optical

network. Optical packets in this system consist of a 10 Gbps NRZ label (or header)

and a 40 Gbps RZ payload. Header detection can then be performed at low bit rates

using electronics while high-bit-rate payloads can be processed entirely in the optical

domain [4]. The label is stripped before the payload reaches the MOTOR chip, so

each wavelength converter needs to have the ability to wavelength convert the 40

214

(a)

(b)

Fig. 8.7 Schematic of a MOTOR wavelength converter port with EAMs to enable 10 Gbps label writing: (a) shows the device with EAMs in the MZI; and (b) shows a new external modulation approach to reduce the impact of thermal chirp.

Gbps payload and write new 10 Gbps labels on the same wavelength. The current

configuration of our device only allows for payload conversion and routing.

However, it was shown in [5] that label writing can be accomplished by

incorporating an electro-absorption modulator (EAM) inside the MZI (Fig. 8.7a).

However, given the proximity of these EAMs to the high power MZI SOAs, the

labels are distorted by thermal chirp effects. One possible strategy to avoid this is to

move the label writing function outside of the MZI as shown in Fig. 8.7b.

The QWI platform used in this work is well-suited for the incorporation of

EAMs. If the intermixing anneal is halted after a short time period and the implant

buffer layer is selectively removed, an intermediate band edge can be created on the

chip (Fig. 8.8). As shown in [3], an intermediate band edge of around 1505 nm is

ideal for efficient EAMs.

215

Fig. 8.8 PL spectra for three different band edges on the same chip achieved with QWI. A 40 second anneal is used to shift the PL peak to just shy of 1500 nm for efficient EAMs.

8.2.4 PACKAGING OPTIONS FOR MULTI-CHANNEL OPERATION

To better understand the real performance of the MOTOR chip in an all-optical

router, multi-channel operation must be examined. The current method of directly

probing bond pads is not adequate for multi-channel operation given the number of

probes required. At least two possibilities exist for testing multiple ports of the chip

simultaneously. First, custom probes consisting of multiple spring-loaded tips that

are arranged in the exact configuration of the bond pads on the MOTOR chip could

be designed (Fig. 8.9). This approach should allow testing of up to two ports at a

time, but it requires precise alignment of the probe tips and some sort of camera

system to ensure that the tips all touch down in the correct location. Additionally,

because the diameter of the probe tips is wide, it may be necessary to redesign the

location of probe pads on the MOTOR chip itself. A second testing option would be

to flip-chip bond the MOTOR chip to a specially designed carrier. This approach

216

Fig. 8.9 Custom probe with spring-loaded tips designed to directly match up with the bond pads of a single MOTOR channel. (Image courtesy of Dr. Ashish Bhardwaj.)

would require some optimization of the flip-chip process to ensure that the pressure

used to mate the chip and carrier does not shatter the chip. Flip-chip bonding would

allow all ports to be run simultaneously, but fiber alignments would be more difficult

since the chip would be upside down and it would not be possible to see where the

inputs and outputs of the device are. An additional advantage of this approach,

however, is that it would provide much better heat sinking than the former option.

However, whichever route is pursued, it is important to remember that two-port

operation inevitably means that the number of optical fibers, transmitters, and

current sources would have to be doubled.

8.2.5 POLARIZATION SENSITIVITY

As mentioned earlier in this work, one of the key trade-offs with using

compressively-strained quantum wells in our base structure is that the device

217

becomes inherently TE-polarization sensitive. While this can be dealt with in the lab

by a manual polarization rotator, the polarization state of input signals in a real

router can change randomly, so this issue must be addressed before the MOTOR

chip could be deployed in a real system. There are two potential ways to address this

sensitivity in our device: (1) alter the epitaxial structure; or (2) incorporate dynamic

polarization controllers at the input of each port. Adjusting the epitaxial design will

require significant optimization and characterization, but it may yield a solution with

wide applicability across multiple projects. Ideally, we want to continue to use

quantum wells in our device (at least for the laser) because of the improved

performance over bulk active regions. One approach to achieve polarization

insensitive MQW regions is to alternate compressive- and tensile-strained QWs

within the MQW stack [6]. However, the carrier distribution between tensile and

compressive wells can be different if the wells have different thicknesses.

Additionally, compressive wells usually provide more gain than tensile wells so the

relative number of wells is usually not the same. There are also considerable growth

concerns since we do not typically grow tensile wells at UCSB. Therefore, although

this developing this kind of MQW could be invaluable, significant modeling efforts

and test growths would be needed before it is practical.

A simpler epitaxial alternative might be to use bulk active regions in certain

areas of our device. We could continue to make the laser and booster SOAs from

our current c-MQW base structure and then regrow bulk preamplifiers and MZI

SOAs in intermixed regions. If these bulk sections are grown with tensile strain, the

218

(a) (b)

Fig. 8.10 (a) Modal overlap with a bulk tensile strained active region that is separated from the center of the optical mode by a layer of InP. (b) The effect of the thickness of an InP spacer layer between a bulk active layer and the waveguide on the confinement factor (shown for several bulk layer thicknesses).

gain can be tailored to account for the difference in propagation constants between

the TE and TM modes [7]. Fig. 8.10 shows some preliminary modeling for this type

of bulk amplifier with a passive MQW in the waveguide. It should be possible to

target a wide range of confinement factors using this approach depending on the

thickness of the bulk active region and how close it is placed to the center of the

optical mode.

Instead of changing the epitaxial layer structure, it may be possible to incorporate

a polarization rotation component on chip. One approach suggested in [8] is to

incorporate a polarization-splitting MZI at the input of the chip (Fig. 8.11). Both

branches of the MZI would contain TE-sensitive SOAs of equal length. However,

the lower branch of the MZI would also contain a component designed to rotate the

polarization of the incoming signal by 90°. The operation of the polarization-

splitting MZI is as follows: An input signal with random, mixed

219

Fig. 8.11 Polarization selecting MZI structure (adapted from [8]). Diagram shows a slanted-wall polarizer component as in [9], but other rotator designs could be used instead.

polarization is split evenly at the input MMI. The TE component in the upper

branch is amplified in the SOA while the TM-polarized light propagates without

amplification. In the lower waveguide, the polarization state is rotated such that the

TM contribution of the polarization becomes TE and the TE becomes TM. The TE

portion is then amplified in the SOA and the two signals are merged using an MMI

coupler. In theory, no matter what the polarization state of the input signal, 3 dB of

the signal will become TM and be lost. Unfortunately, this type of component

would add substantial length to the overall chip. The success of this approach

depends largely on the conversion efficiency of the polarization rotator and on how

well the MZI can be balanced to ensure phase matching of the combined signals.

Many different designs have been proposed for rotating polarization, but one of

the simplest possibilities involves a passive waveguide with a single, slanted

sidewall as shown in Fig. 8.11. This type of device is butt-coupled with straight

waveguides to excite hybrid polarization modes [9]. If the length is chosen properly

(typically on the order of a few hundred microns), full conversion between TE and

TM modes can be achieved. Generally speaking, no matter which approach is

220

investigated to manage polarization, this is one of the most important unresolved

issues with PICs at UCSB. Significant future effort in this area is strongly

encouraged.

8.2.6 FURTHER STUDY OF Cl2/H2 ETCH CHEMISTRY

The TEM-EDX investigation of Bouchoule et al. discussed in Chapter 6 provided

some key insights into the role of H2 in Cl2/H2-based InP dry etching [10]. However,

there are still several unanswered questions regarding this etch chemistry. First, it

would be helpful to identify the source of oxygen atoms that are present in the

passivation layer. Presumably, oxygen is released into the system as the oxide hard

mask is sputtered during the etch. However, it is also possible that moisture in the

reactor provides a source of H2O. An etch study could be performed with hard

masks of various types to see if the passivation layer is still formed. Additionally, it

would be interesting to determine if the thickness of the passivation layer could be

increased by deliberatly increasing the amount of oxygen present during the etch.

Second, the EDX analysis of [10] was unable to measure H2 concentration. Since

the relative amounts of silicon and oxygen are strongly dependent on the H2 flow, it

is important to determine how H2 is incorporated into the passivation layer. Fourier

transform infrared spectroscopy might be able to illuminate information on hydrogen

incorporation by examining the Si-O bonds energies for samples etched with

differing H2 concentrations.

221

REFERENCES


[2] J. W. Raring, E. J. Skogen, M. L. Masanovic, S. P. DenBaars, and L. A. Coldren, "Demonstration of high saturation power / high gain SOAs using quantum well intermixing based integration platform," Electronics Letters, vol. 41, no. 24, pp. 1345-1346, Nov. 2005.

[3] J. Raring, Advanced InP Based Monolithic Integration Using Quantum Well Intermixing and MOCVD Regrowth. Ph. D. Dissertation, University of California, Santa Barbara, 2006.

[4] J. P. Mack, et al., "Demonstration of Contention Resolution for Labeled Packets at 40 Gb/s Using Autonomous Optical Buffers," in Optical Fiber Communication Conference, San Diego, CA, 2009, p. OMU2.


[6] M. Silver, A. F. Phillips, A. R. Adams, P. D. Greene, and A. J. Collar, "Design and ASE Characteristics of 1550-nm Polarization-Insensitive Semiconductor Optical Amplifiers Containing Tensile and Compressive Wells," IEEE Journal of Quantum Electronics, vol. 36, no. 1, pp. 118-122, Jan. 2000.

[7] J.-Y. Emery, et al., "High performance 1.55μm polarisation-insensitive semiconductor optical amplifier based on low-tensile-strained bulk GaInAsP," Electronics Letters, vol. 33, no. 12, pp. 1083-1084, Jun. 1997.


[9] J. J. G. M. van der Tol, U. Khalique, and M. K. Smit, "Using Polariation in the Integration of Optoelectronic devices," in Integrated Photonics Research and Applications Conference, 2000, p. ITuC2.

[10] S. Bouchoule, et al., "Sidewall passivation assisted by a silicon coverplate during Cl2-H2 and HBr inductively coupled plasma etching of InP for photonic devices," Journal of Vacuum Science & Technolgoy B, vol. 26, no. 2, pp. 666-674, Mar. 2008.

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