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EE141
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EE141 EECS141 1 Lecture #18
EE141 EECS141 2 Lecture #18
Project Phase 2 now on the web-site. Hw 6 due today. New homework to be posted in a week. Cory Hall closed on Monday (Power Outage)
Instructional computers in 353 Cory should come back on line on Tu.
Enjoy Spring Break!
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EE141 EECS141 3 Lecture #18
Last lecture Domino Logic Introduction to registers
Today’s lecture Registers Timing
Reading (Ch 7)
EE141 EECS141 4 Lecture #16
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EE141 EECS141 5 Lecture #16
Output = f ( In ) Output = f ( In, Previous In )
EE141 EECS141 6 Lecture #16
D Clk
Q D Clk
Q
Register: edge-triggered stores data when clock rises
Clk Clk D D Q Q
Latch: level-sensitive clock is low - hold mode clock is high - transparent
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EE141 EECS141 7 Lecture #16
Register Latch
Clk
D Q
t C → Q
Clk
D Q
t C → Q
t D → Q
EE141 EECS141 8 Lecture #16
t CLK
t D
t c → q
t hold t su
t Q DATA
STABLE
DATA STABLE
Register
CLK
D Q
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EE141 EECS141 9 Lecture #16
D
CLK
CLK
Q
Dynamic Static
EE141 EECS141 10 Lecture #16
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EE141 EECS141 11 Lecture #16
Gain should be larger than 1 in the transition region
EE141 EECS141 12 Lecture #16
D
CLK
CLK
D
Converting into a MUX Forcing the state (can implement as NMOS-only)
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
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EE141 EECS141 13 Lecture #16
D
CLK
CLK
D
EE141 EECS141 14 Lecture #16 EE141
Negative latch (transparent when CLK= 0)
Positive latch (transparent when CLK= 1)
CLK
1
0 D
Q 0
CLK
1 D
Q
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EE141 EECS141 15 Lecture #16
EE141 EECS141 16 Lecture #16
NMOS only Non-overlapping clocks
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EE141 EECS141 17 Lecture #16
N latch is transparent when Φ = 0
P latch is transparent when Φ = 1
EE141 EECS141 18 Lecture #16
Two opposite latches trigger on edge Also called master-slave latch pair
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EE141 EECS141 19 Lecture #16
Multiplexer-based latch pair
EE141 EECS141 20 Lecture #16
D
Q
CLK
2 0.5
0.5
1.5
2.5
tclk-q(LH)
0.5 1 1.5 2 2.5 0 time, nsec
Volts
tclk-q(HL)
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EE141 EECS141 21 Lecture #16
EE141 EECS141 22 Lecture #16
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EE141 EECS141 23 Lecture #16
Circuit before clock arrival (Setup-1 case)
EE141 EECS141 24 Lecture #16
Circuit before clock arrival (Setup-1 case)
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EE141 EECS141 25 Lecture #16
Circuit before clock arrival (Setup-1 case)
EE141 EECS141 26 Lecture #16 26
Circuit before clock arrival (Setup-1 case)
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EE141 EECS141 27 Lecture #16 27
Circuit before clock arrival (Setup-1 case)
EE141 EECS141 28 Lecture #16 28
Hold-1 case
0
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EE141 EECS141 29 Lecture #16
Hold-1 case
0
EE141 EECS141 30 Lecture #16
Hold-1 case
0
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EE141 EECS141 31 Lecture #16
Hold-1 case
0
EE141 EECS141 32 Lecture #16
Hold-1 case
0
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EE141 EECS141 33 Lecture #16
Keepers can be added to “staticize (?!)”
EE141 EECS141 34 Lecture #16
Negative latch (transparent when CLK= 0)
Positive latch (transparent when CLK= 1)
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EE141 EECS141 35 Lecture #16
AND latch Example: logic inside the latch
EE141 EECS141 36 Lecture #16
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EE141 EECS141 37 Lecture #16
Master-Slave Latches
D Clk
Q D Clk
Q
Clk
Data D Clk
Q Clk Data
Pulse-Triggered Latch
L1 L2 L
Ways to design an edge-triggered sequential cell:
EE141 EECS141 38 Lecture #16
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EE141 EECS141 39 Lecture #16
EE141 EECS141 40 Lecture #16
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EE141 EECS141 41 Lecture #16
D Clk
Q
D
Q
Clk tclk-q thold
PWm tsetup
td-q
Delays can be different for rising and falling data transitions
T
EE141 EECS141 42 Lecture #16
D Clk
Q
D
Q
Clk
tclk-q
thold
T
tsetup
Delays can be different for rising and falling data transitions
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EE141 EECS141 43 Lecture #16
Cycle time (max): TClk > tclk-q + tlogic + tsetup
Race margin (min): thold < tclk-q,min + tlogic,min
tclk-q tclk-q,min
tlogic tlogic,min
tsetup, thold
EE141 EECS141 44 Lecture #16
Clock skew Spatial variation in temporally equivalent clock
edges; deterministic + random, tSK
Clock jitter Temporal variations in consecutive edges of the
clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL
Variation of the pulse width Important for level sensitive clocking
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EE141 EECS141 45 Lecture #16
Sources of clock uncertainty
EE141 EECS141 46 Lecture #16
Both skew and jitter affect the effective cycle time Only skew affects the race margin (usually)
Clk
Clk
tSK
tJS
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EE141 EECS141 47 Lecture #16
# of registers
Clk delay Insertion delay Max Clk skew
Earliest occurrence of Clk edge Nominal – δ/2
Latest occurrence of Clk edge
Nominal + δ /2
δ