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8/14/2019 Layout techniques for symmetry and Matching
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LayoutTechniques
Symmetry and Matching
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 1
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Matching
Matching : When engineering circuits, you want partnereddevices to react exactly the same way, this is called matching .
All of the devices in an integrated circuit occupy the same piece ofsilicon, so they all experience the similar manufacturing conditions.If one components value increases by 10%, then all similar devicesexperience similar increases. Devices specifically constructed toobtain a known constant ratio are called matched devices .
The ration between two similar components on the same
integrated circuit can be controlled to better than +/- 1%. Analog Integrate Circuits usually depend on matching to obtainmuch of their precision and performance.
Digital Integrated Circuits depend on matching to obtain compactness.E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 2
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Mismatch
Mismatch : a deviation of the measured device ratio from theintended device ratio is called mismatch .
1)/(
)/()/(
12
21
12
1212 =
= x X x X
X X X X x x
Mismatch for a specific pairof devices.
X 1 and X 2 are the intended values, x1 and x2 are the measured values.
The same measurements performed on a second pair of devices will
yield a different mismatch . Measurements of a large number ofdevice pairs will produce a random distribution 1, 2, 3, ..
Standarddeviation of
mismatch
=
= N
ii m
N N s
1
2)(1
11
=
= N
i
i
N m
1
1
The averagemismatch
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 3
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Examples of mismatch in passive devices
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 4
Examples :Consider the case of two matched Poly resistors having widths of 2umand 4um respectively. Suppose that Poly etching introduces a processvariations of 0.1um. Then the resulting mismatch is: {[(2 + 0.1)/(4 + 0.1)
0.5 ]/0.5}= 2.4%.
Consider a couple of matched resistors one having 20um long and theother 40um long. Suppose that contacts of resistors have a processvariations of 0.2um. This introduces a mismatch of about {[(20.2)/(40.2)
0.5]/0.5} = 0.5%
Suppose a pair of poly-poly capacitors, one measuring 10x10um andthe other 10x20um, both experience a poly etch variation of 0.1um, thenthe systematic mismatch is {[(102.1/203.1) 0.5]/0.5} = 0.6%.
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Causes of Mismatch
Random mismatches stem from
microscopic fluctuations indimensions, dopings, oxidethickness, etch rate,
photolithography, and otherparameters that influencecomponent values.
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 5
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Approaches to reduce Mismatch
Random statistical fluctuations in deposited layers
Aspect of depositedPoly layer
Peripheralfluctuations
arealfluctuations
Designed mask ofPoly layer
For capacitors, the contribution of peripheral fluctuations termdecreases as the capacitance increases and the arealfluctuations term dominates.
For resistors, the effect of process variations can be sharply
reduced by making both two resistors the same width.E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 6
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Approaches to reduce Mismatch
Etch rate variations
Fasteretchrate
Sloweretchrate
Larger openings grant more accessto the etchant and thus clear morequickly than small openings.
Consequently, sidewall erosionoccurs to a greater degree aroundthe edges of a large opening thanaround the edges of a small one.
Effect of etch rate variations on matched resistors
Drawnsize(outline)
Finalsize(shaded)
Dummyor etchguards
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 7
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Approaches to reduce Mismatch
Matched resistors arrayemploying connecteddummies for reducingetch rate variations
Matched capacitors arrayemploying grounded dummies
real
capacitors
Dummycapacitor
Poly1 plate
contacts
Dummy resistor
Dummy resistor
Matched resistor
Matched resistor
Matched resistor
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 8
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Approaches to reduce Mismatch
Effect of diffusion interactions The resistors occupying the endsof the array will have slightlydifferent values of diffusion
interactions than the resistorsoccupying the middle of the array.
End array resistor
Middle array resistor
End array resistor
Matched array ofdiffused resistorsincluding groundeddummies forreducing diffusioninteractions
Matched resis tor
Matched resis tor
Dummy resistor
Dummy resistor
Tank
NBL
Tank
contact
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 9
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Approaches to reduce Mismatch
The same width for matching resistors
As an example, if you want four resistors to match eachother, then do not select one of those resistors as 5umwide, another 10um wide, another 2um wide and a fourthone as 20um wide. They all need to match each other , sochoose one universal width that is sensible and have allthe same width. Vary only the lengths.
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Approaches to reduce Mismatch
Improved serpentineresistor layoutPoor serpentineresistor layout
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Mismatch in CMOS transistors
Device orientation
M1M1 M2 M2
Bad matched transistors,
transistors have different kpGood matched transistorsvariations in kp are cancelled
Effect of photolithographic misalignment when device is mirrored
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 12
M2 is amirror of M1M1 M2M1
L1 >>, L2 >, L2 >>
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Mismatch in CMOS transistors
Deep diffusions can affect the matching of nearbyMOS transistors. The tails of these diffusions extend aconsiderable distance beyond their junctions and theexcess dopants they introduce can shift Vth and alterthe transconductance of nearby transistors
PMOS
NMOS
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Mismatch in CMOS transistors
Poly etch rate variations
M1 M2 M3
Dummygate
Gate array for reducing Poly etch rate variations
M1 M2 M3
Interdigited transistor
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Mismatch in CMOS transistors
NMOS transistors usually match more precisely
than PMOS transistors.Several authors have reported that PMOStransistors exhibit 30 to 50% moretransconductance mismatch than comparableNMOS transistors
(Ref. Lakshmikumar et al ., Characterization and Modeling of Mismatchin MOS Transistors for precision Analog Design, pp 1060. )
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E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 16
Compact layout
Easy to tile
Difficult to tile
Matched devicesshould reside asclose as possible
to minimize theinfluence of stressbetween them.
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Symmetry
Circuit A
Circuit B
Circuit C
Circuit A
Circuit B Circuit C
Line ofsymmetry
Imaginary line of symmetry
helps components match
Rearranging placementof circuits
Poor matching
Keep everything in symmetry,particularly in high frequency, if youwant to match parasitics, you haveto layout blocks across a line of
symmetry.
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 17
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Common-centroid
Axis of symmetry
Centroid
Location the centroid
Centroid
Axis of symmetry
Placing devices around a common centralpoint is known as common-centroid .
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Common-centroid Layout
Axis ofsymmetry Axis of symmetryof device A Axis of symmetryof device B Common axis ofsymmetry
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 19
A AB B A AB B A AB
One-dimension interdigitatated arrays
Examples of common-centroid in interdigitated arrays
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Cross coupled pair
A B
B A
A B
B A
B A
A B
Two-dimension interdigitated patterns
or cross-coupled pair patterns
These arrays are adequate to lay out capacitors, diodes, and
transistorsE. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 20
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Construction of Interdigitated Arrays
Procedure:1.- Identify all the components comprising the array.
2.- Divide components in segments and see if all thevalues have a greatest common factor.
3.- In case where a large common factor does notexist, try using the value of the smallest device as
the value of a segment, then determine the numberof segments in the other devices.
4.- Once the segment has been found make sure
that it is not so small that it precludes reasonablematching (no less than 5um wide for resistors and100um2 for capacitors).
5.- Finally, choose the best interdigitation pattern.
E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 21
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Common-centroid in MOS transistors
Example of Interdigitated MOS transistor
A B B A
D S
Gate
SD D
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Common-centroid in MOS transistors
A
A
B
B
D DS
G
Example of cross-coupled MOS transistor
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E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 24
Rules for device matching
Construct matched resistors from a single material
Make matched resistors the same width
Make matched resistors sufficiently wide (minimum width ~ 5um)
Where practical, use identical geometries for resistors
Orient matched resistors in the same direction
Place matched resistors in close proximity
Interdigite arrayed resistors
Place dummies on either end of a resistors array
MATCHED RESISTORS
Segmented resistors are superior to serpentines
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E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 25
Rules for device matching
MATCHED RESISTORS (CONT.)
Use Poly resistors in preference to diffused ones
Place deposited resistors over field oxide
If leads cross resistors, they should cross all resistor segments inthe same manner
Place matched resistors well away from power devices
Avoid short resistor segments (Poly resistors must have a totallength no less than 50um to minimize nonlinearities)
Avoid excessive power dissipation in matched resistors
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E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 26
Rules for device matching
MATCHED CAPACITORSUse identical geometries for matched capacitors
Use square geometries for precisely matched capacitors
Make matched capacitors as large as practical
Place matched capacitors adjacent to another
Place matched capacitors over field oxide
Connect the upper electrode of a matched capacitor to the higher-impedance node
Place dummy capacitors around the outer edge of the array
Cross-couple arrayed capacitors
Consider the capacitance of leads connecting the capacitor
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E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 27
Rules for device matching
MATCHED CAPACITORS (Cont.)Do not run leads over matched capacitors unless they are
electrostatically shielded
Use thick oxide dielectrics in preference to thin oxide or compositedielectrics
Place matched capacitors well away from power devices.
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E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 28
Rules for device matching
MATCHED TRANSISTORSUse identical finger geometries
Use large active areas
For voltage matching, keep V gs small
For current matching keep V gs large
Orient transistors in the same direction
Place transistors in close proximity
Keep the layout of the matched transistors as compact as possible
Where practical use common-centroid layouts
Place dummy segments on the ends of arrayed transistors
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E. Martinez-Guerrero /Taller de Diseo Fsico /MDE_DESI_ITESO/Otoo 2005 29
Rules for device matching
MATCHED TRANSISTORS (Cont.)Place transistors well away from power devices
Do not place contacts on top of active gate area
Do not route metal across the active gate region
Keep all junctions of deep diffusions far away from active gate area
Connect gate fingers using metal straps
Use thin oxide devices in preference to thick oxide devices
Consider using NMOS transistors rather than PMOS transistors