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22/06/2011 ISSUE no:1 Revision no: 0

U5EEA23LINEAR AND DIGITALINTEGRATED CIRCUITS LABORATORY

Lab Mannual

B.Tech - EEE

Semester - 5

DEPARTMENT OF ELECTRICAL AND

ELECTRONICS ENGINEERING

Prepared by

G.ILANGOVAN, M.TECH

S.RAMAKRISHNAN, M.E

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LIST OF EXPERIMENTS:

1. Study of Basic Digital ICs.Verification of truth table for AND, OR, NOT, NAND, NOR, EXOR, JK FF,

RS FF, D FF)

2. Implementation of Boolean Functions, Adder/ Subtractor circuits.3. Code converters, Parity generator and parity checking, Excess 3, 2s

Complement, Binary to gray code using suitable ICs.

4. Shift Registers: Design and implementation of 4-bit shift registers in SISO,

SIPO, PISO, PIPO modes using suitable ICs.

5. Multiplexer/ De-multiplexer: Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8

demultiplexer

6. Timer IC application.Study of NE/SE 555 timer in Astable, Monostable operation.

7. Application of Op-AmpSlew rate verifications, inverting and non-inverting amplifier Adder,

8. Op Amp as comparator, Integrator and Differentiator.9. Study of Analog to Digital Converter and Digital to Analog Converter: Verification

of A/D conversion using dedicated ICs.

10. Study of VCO and PLL ICs

i. Voltage to frequency characteristics of NE/ SE 566 IC.

ii. Frequency multiplication using NE/SE 565 PLL IC.

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Ex. No.1a STUDY OF BASIC DIGITAL ICS

AIM:

To verify the truth table of basic digital ICsof AND, OR, NOT, NAND, NOR, EX-ORgates and JK flip flop, RS flip flop and D flip flop.

THEORY:

a. AND gate:An AND gate is the physical realization of logical multiplication operation. It is

an electronic circuit which generates an output signal of 1 only if all the inputsignals are 1.

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408:

CIRCUIT DIAGRAM:

TRUTH TABLE (AND Gate):

S.NoINPUT OUTPUT

A B Y = A. B

1. 0 0 0

2. 0 1 0

3. 1 0 0

4. 1 1 1

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b. OR gate:An OR gate is the physical realization of the logical addition operation. It is an

electronic circuit which generates an output signal of 1 if any of the input signalis 1.

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE (OR Gate):

S.NoINPUT OUTPUT

A B Y = A + B

1. 0 0 0

2. 0 1 1

3. 1 0 1

4. 1 1 1

c. NOT gate:A NOT gate is the physical realization of the complementation operation. It is an

electronic circuit which generates an output signal which is the reverse of the

input signal. A NOT gate is also known as an inverter because it inverts the

input.

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LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE (NOT Gate):

S.NoINPUT OUTPUT

A Y = A1. 0 1

2. 1 0

d. NAND gate:A NAND gate is a complemented AND gate. The output of the NAND gate will

be 0 if all the input signals are 1 and will be 1 if any one of the input signal is0.

LOGIC DIAGRAM:

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CIRCUIT DIARAM:

TRUTH TABLE (NAND Gate):

S.NoINPUT OUTPUT

A B Y = (A. B)1. 0 0 1

2. 0 1 1

3. 1 0 1

4. 1 1 0

e.

NOR gate:A NOR gate is a complemented OR gate. The output of the OR gate will be 1 ifall the inputs are 0 and will be 0 if any one of the input signal is 1.

LOGIC DIAGRAM:

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PIN DIAGRAM OF IC 7402

CIRCUIT DIAGRAM:

TRUTH TABLE (NOR Gate):

S.NoINPUT OUTPUT

A B Y = (A + B)1. 0 0 1

2. 0 1 0

3. 1 0 0

4. 1 1 0

f. EX-OR gate:An Ex-OR gate performs the following Boolean function,

A B = ( A . B ) + ( A . B )

It is similar to OR gate but excludes the combination of both A and B being

equal to one. The exclusive OR is a function that give an output signal 0 whenthe two input signals are equal either 0 or 1.

LOGIC DIAGRAM

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CIRCUIT DIAGRAM:

TRUTH TABLE (EX-OR Gate):

S.NoINPUT OUTPUT

A B Y = A B

1. 0 0 0

2. 0 1 1

3. 1 0 1

4. 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. To verify the truth table of basic digital Ics

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

2. AND gate IC 7408 1

3. OR gate IC 7432 1

4. NOT gate IC 7404 1

5. NAND gate IC 7400 1

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6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 1

8. Connecting wires As required

Result:

Thus verify the truth table of basic digital Ics of AND, OR, NOT, NAND, NOR,EX-OR gates.

Ex.NO:1b STUDY OF FLIP FLOPS

AIM:

To verify the characteristic table of RS, D, JK, and T Flip flops.

THEORY:

A Flip Flop is a sequential device that samples its input signals and changes its output

states only at times determined by clocking signal. Flip Flops may vary in the number

of inputs they possess and the manner in which the inputs affect the binary states.

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with

respect to the input on application of clock pulse. When the clock pulse is high the S

and R inputs reach the second level NAND gates in their complementary form. TheFlip Flop is reset when the R input high and S input is low. The Flip Flop is set when

the S input is high and R input is low. When both the inputs are high the output is in an

indeterminate state.

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

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CHARACTERISTIC TABLE:

CLOCK

PULSE

INPUT PRESENT

STATE (Q)

NEXT

STATE(Q+1)

STATUS

S R

1 0 0 NC NC NO CHANGE

2 0 0 NC NC

3 0 1 0 0 RESET4 0 1 1 0

5 1 0 0 1 SET

6 1 0 1 1

7 1 1 X X UNDEFINED

8 1 1 X X

-8-

D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when

both inputs are high at the same time, in the D Flip Flop the inputs are never madeequal at the same time. This is obtained by making the two inputs complement of each

other.

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

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CLOCK

PULSE

INPUT

D

PRESENT

STATE (Q)

NEXT

STATE(Q+1)

STATUS

1 0 0 02 0 1 0

3 1 0 1

4 1 1 1

JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs

behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with

K input and the clock pulse, similarly theoutput Q

is ANDed with J input and the

Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q

and Q output retain their previous values. When the clock pulse is high, the J and Kinputs reach the NOR gates. When both the inputs are high the output toggles

continuously. This is called Race around condition and this must be avoided.

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

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CLOCK

PULSE

INPUT PRESENT

STATE (Q)

NEXT

STATE(Q+1)

STATUS

J K

1 0 0 0 0 NO CHANGE

2 0 0 1 13 0 1 0 0 SET

4 0 1 1 0

5 1 0 0 1 RESET

6 1 0 1 1

7 1 1 0 1 TOGGLE

8 1 1 1 0

T FLIP FLOP:

This is a modification of JK Flip Flop, obtained by connecting both inputs J and Kinputs together. T Flip Flop is also called Toggle Flip Flop.

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

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CLOCK

PULSE

INPUT

T

PRESENT

STATE (Q)

NEXT

STATE(Q+1)

STATUS

1 0 0 02 0 1 0 TOGGLE

3 1 0 1

4 1 1 0

APPARATUS REQUIRED:


1. Digital IC trainer kit - 1

2. NOR gate IC 7402 13. NOT gate IC 7404 1

4. AND gate ( three input ) IC 7411 1


6. Connecting wires - As required

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and observe the status of all the flip flops.

RESULT:

The Characteristic tables of RS, D, JK, T flip flops were verified.

QUESTIONS:

1. What are the basic logic gates?2. What is mean by universal logic gates?3. How many bits a flip flop can store?4. What is mean by RS flip flop?5. What is the different between RS and JK flip flop?6. What will be the output of D-Flip flop if the input is zero?7. NAND gate is a combination of _____________________8. What is the use of flip-flops?9. How many OR gate and NOT gate needed for constructing a NOR gate?10.What is the different between a truth table and a characteristics table?11.Why are the gates used in manufacturing ICs?12.Why the digital circuit always represents 1s and 0s?

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Ex. No.2a IMPLEMENTATION OF BOOLEAN FUNCTIONS

AIM:

To design the logic circuit and verify the truth table of the given Booleanexpression: F (A, B, C, D) = (0, 1, 2, 5, 8, 9, 10)

[Design can be changed by changing the Boolean expression]

DESIGN:

Given , F (A,B,C,D) = (0,1,2,5,8,9,10)The output function F has four input variables hence a four variable Karnaugh Map is

used to obtain a simplified expression for the output as shown,

From the K-Map,

F = B C + D B + A C DSince we are using only two input logic gates the above expression can be re-written as,

F = C (B + A D) + D BNow the logic circuit for the above equation can be drawn.

CIRCUIT DIAGRAM:

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TRUTH TABLE:

S.NoINPUT OUTPUT

A B C D F=DB+C(B+AD)1 0 0 0 0 1

2 0 0 0 1 1

3 0 0 1 0 1

4 0 0 1 1 0

5 0 1 0 0 0

6 0 1 0 1 1

7 0 1 1 0 0

8 0 1 1 1 0

9 1 0 0 0 1

10 1 0 0 1 1

11 1 0 1 0 1

12 1 0 1 1 013 1 1 0 0 0

14 1 1 0 1 0

15 1 1 1 0 0

16 1 1 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagram2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the given Boolean expression.

APPARATUS REQUIRED:







6. NOR gate IC 7402 1

7. EX-OR gate IC 7486 18. Connecting wires As required

RESULT:

The truth table of the given Boolean expression was verified.

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Ex. No. 2b IMPLEMENTATION OF HALF ADDER & FULL ADDER

AIM:

To design and verify the truth table of the Half Adder & Full Adder circuits.

THEORY:

The most basic arithmetic operation is the addition of two binary digits. There

are four possible elementary operations, namely,

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 102

The first three operations produce a sum of whose length is one digit, but when

the last operation is performed the sum is two digits. The higher significant bit of this

result is called a carry and lower significant bit is called the sum.

HALF ADDER:

A combinational circuit which performs the addition of two bits is called half adder.

The input variables designate the augend and the addend bit, whereas the output

variables produce the sum and carry bits.

FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input bits is

called full adder. The three input bits include two significant bits and a previous carry

bit. A full adder circuit can be implemented with two half adders and one OR gate.

HALF ADDER

TRUTH TABLE(HALF ADDER):

S.NoINPUT OUTPUT

A B S C1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 0 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can be

obtained as,

Sum, S = A B

Carry, C = A . B

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CIRCUIT DIAGRAM (HALF ADDER):

FULL ADDER

TRUTH TABLE (FULL ADDER):

S.NoINPUT OUTPUT

A B C SUM CARRY

1. 0 0 0 0 02. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can beobtained as,

SUM = ABC + ABC + ABC + ABCCARRY = ABC + ABC + ABC +ABCUsing Karnaugh maps the reduced expression for the output bits can be obtained as,

SUM

SUM = ABC + ABC + ABC + ABC = A B CCARRY

CARRY = AB + AC + BC

CIRCUIT DIAGRAM (FULL ADDER):

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PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder

circuits.

APPARATUS REQUIRED:








RESULT:

The design of the half adder and full adder circuits was done and their truth tables were

verified.

Expt. No. 2c IMPLEMENTATION OF HALF SUBTRACTOR &

FULL SUBTRACTOR

AIM:

To design and verify the truth table of the Half Subtractor& Full Subtractor circuits.

THEORY:

The arithmetic operation, subtraction of two binary digits has four possible elementary

operations, namely,

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0 - 0 = 0

0 - 1 = 1 with 1 borrow

1 - 0 = 1

1 - 1 = 0

In all operations, each subtrahend bit is subtracted from the minuend bit. In case of thesecond operation the minuend bit is smaller than the subtrahend bit, hence 1 is

borrowed.

HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is called half

subtractor. The input variables designate the minuend and the subtrahend bit, whereas

the output variables produce the difference and borrow bits.

FULL SUBTRACTOR:

A combinational circuit which performs the subtraction of three input bits is called full

subtractor. The three input bits include two significant bits and a previous borrow bit.

A full subtractor circuit can be implemented with two halfsubtractor and one OR gate.

HALF SUBTRACTOR

TRUTH TABLE(HALF SUBTRACTOR):

S.NoINPUT OUTPUT

A B DIFF BORR

1. 0 0 0 02. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be

obtained as,

Difference, DIFF = A B

Borrow, BORR = A . B

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CIRCUIT DIAGRAM (HALF SUBTRACTOR):

FULL SUBTRACTOR

TRUTH TABLE (FULL SUBTRACTOR):

S.NoINPUT OUTPUT

A B C DIFF BORR

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be

obtained as,

Difference, DIFF= ABC + ABC + ABC + ABCBorrow, BORR = ABC + ABC + ABC +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as;

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DIFFERENCE

DIFF = ABC + ABC + ABC + ABC = A B C

BORROW

BORR = AB + AC + BC

CIRCUIT DIAGRAM (FULL SUBTRACTOR) :

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half subtractor and full

subtractor circuits.

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APPARATUS REQUIRED:








RESULT:

The design of the half subtractor and full subtractor circuits was done and their

truth tables were verified.

Questions:

1. What is meant by half and full adder?2. What is meant by half and full subtractor?3. What is meant by Karnaugh map?4. What are the ICs required for constructing adder and subtractor

circuit?

5. How many half adders are there in a full adder?6. What are the outputs produced at the end of full subtraction?7. What is mean by SOP and POS?8. List out the various types of k-maps.9. What is the maximum possible grouping in a four variable k-map?10.What are the various laws of Boolean algebra?

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Ex. No. 3a PARITY GENERATOR & CHECKER

AIM:

To design and verify the truth table of a three bit Odd Parity generator and checker.

THEORY:

A parity bit is used for the purpose of detecting errors during transmission of binary

information. A parity bit is an extra bit included with a binary message to make the

number of 1s either odd or even.

The message including the parity bit is transmitted and then checked at the receiving

end for errors. An error is detected if the checked parity does not correspond with the

one transmitted. The circuit that generates the parity bit in the transmitter is called a

parity generator and the circuit that checks the parity in the receiver is called a parity

checker.

In even parity the added parity bit will make the total number of 1s an even amountand in odd parity the added parity bit will make the total number of 1s an odd amount.In a three bit odd parity generator the three bits in the message together with the parity

bit are transmitted to their destination, where they are applied to the parity checker

circuit.

The parity checker circuit checks for possible errors in the transmission. Since the

information was transmitted with odd parity the four bits received must have an odd

number of 1s. An error occurs during the transmission if the four bits received havean even number of 1s, indicating that one bit has changed during transmission.

The output of the parity checker is denoted by PEC (parity error check) and it will be

equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1s.

CIRCUIT DIAGRAM:

ODD PARITY GENERATOR

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ODD PARITY GENERATOR

TRUTH TABLE (ODD PARITY GENERATOR):

S.NoINPUT

( Three bit message)OUTPUT

( Odd Parity bit)

A B C P

1 0 0 0 1

2 0 0 1 0

3 0 1 0 0

4 0 1 1 1

5 1 0 0 0

6 1 0 1 1

7 1 1 0 1

8 1 1 1 0

From the truth table the expression for the output parity bit is,

P( A, B, C) = (0, 3, 5, 6)

Also written as,

P = ABC + ABC + ABC + ABC = (A B C)

CIRCUIT DIAGRAM:

ODD PARITY CHECKER

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TRUTH TABLE (ODD PARITY CHECKER):

S.No

INPUT

( four bit message

Received )

OUTPUT

(Parity error

check)

A B C P X1. 0 0 0 0 1

2. 0 0 0 1 0

3. 0 0 1 0 0

4. 0 0 1 1 1

5. 0 1 0 0 0

6. 0 1 0 1 1

7. 0 1 1 0 1

8. 0 1 1 1 0

9. 1 0 0 0 0

10. 1 0 0 1 111. 1 0 1 0 1

12. 1 0 1 1 0

13. 1 1 0 0 1

14. 1 1 0 1 0

15. 1 1 1 0 0

16. 1 1 1 1 1

From the truth table the expression for the output parity checker bit is,

X (A, B, C, P) = (0, 3, 5, 6, 9, 10, 12, 15)

The above expression is reduced as,

This X = (A B C P)

APPARATUS REQUIRED:



2. EX-OR gate IC 7486

3. NOT gate IC 7404


PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the Parity generator and checker.

RESULT:

The design of the three bit odd Parity generator and checker circuits was done and theirtruth tables were verified.

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Ex. No. 3b EXCESS 3, 2S COMPLEMENT CONVERSION

AIM

To convert the given binary number in to its twos complement

Theory:

2s complement is the binary number that results when we add 1b to the 1scomplement of the number.

2s complement = 1s complement + 1bWhere 1s complement is obtained by converting all 1s to 0s and all 0s to 1s in

the given binary number.

7483 PIN Diagram:

B4 4 C4 C0 GND B1 A1 116 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

A4 3 A3 B3 Vcc 2 B2 A2Circuit Diagram:

Binary input B0 B1 B2 B3

7404

GND

10 8 3 1 11 7 4 16

Vcc

Vcc GND

C0

C4

9 6 2 15

S0 S1 S2 S3

7483

5

7483 1214

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Truth table:

Decimal

Binary code 2s ComplementB3 B2 B1 B0 S3 S2 S1 S0

0 0 0 0 0 0 0 0 01 0 0 0 1 1 1 1 1

2 0 0 1 0 1 1 1 0

3 0 0 1 1 1 1 0 1

4 0 1 0 0 1 1 0 0

5 0 1 0 1 1 0 1 1

6 0 1 1 0 1 0 1 0

7 0 1 1 1 1 0 0 1

8 1 0 0 0 1 0 0 0

9 1 0 0 1 0 1 1 1

10 1 0 1 0 0 1 1 011 1 0 1 1 0 1 0 1

12 1 1 0 0 0 1 0 0

13 1 1 0 1 0 0 1 1

14 1 1 1 0 0 0 1 0

15 1 1 1 1 0 0 0 1

Apparatus required:

1. Digital IC trainer kit2. IC 7483, IC 7404

Connecting wires

Procedure:

1. Verify the IC number IC for the respective logic gates2. Connections are made as shown in the circuit diagram3. Pin 14 is connected to +Vcc and pin 7 to ground4. Input binary code to B0, B1, B2, and B3 are given at respective pins and 2s

Complement outputs S0, S1, S2, S3 are taken for all the 16 combinations of the

input.

5. Connect the logic state output from the trainer kit to the input of the logic gateIC.

6. Connect the output from the logic gate IC to the output LED indicator of thetrainer kit.

7. Change the different logic states and note down the output.8. Verify the actual output with the given truth table for the respective logic gates.

Result:

Thus the truth table for binary code to twos complement converter is verified.

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Ex. No. 3c BINARY TO GRAY CODE CONVERTER

AIM:

To design and verify the truth table of a three bit binary to gray code converter.

THEORY:

Code converter is a circuit that makes two systems compatible even though each uses

different binary codes. There is a wide variety of binary codes used in digital systems.

Some of these codes are Binary Coded Decimal, Gray code, Excess- 3 code , ASCII code,

etc.

A combinational circuit performs the transformation of a three bit binary to gray code

converter by means of logic gates. The input variables are binary bits named as A,B,C

with A as the MSB and C as the LSB. The Gray code output bits are termed as X,Y,Zwith X as the MSB and Z as the LSB.

The Gray code is also called as reflective code. The gray coded number corresponding

to the decimal number 2n 1, for any n, differs from gray coded 0 (0000) in one bit

position only.

DESIGN:

TRUTH TABLE (3 BIT BINARY TO GRAY CODE CONVERTER):

S.NoINPUT - BINARY OUTPUT-GRAY

A B C X Y Z

1. 0 0 0 0 0 0

2. 0 0 1 0 0 1

3. 0 1 0 0 1 1

4. 0 1 1 0 1 0

5. 1 0 0 1 1 0

6. 1 0 1 1 1 1

7. 1 1 0 1 0 1

8. 1 1 1 1 0 0

From the truth table the expression for the output gray bits are,

X (A, B, C) = (4, 5, 6, 7)Y (A, B, C) = (2, 3, 4, 5)Z (A, B, C) = (1, 2, 5, 6)

Hence obtain the reduced SOP expression using Karnaugh maps as follows,

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For X:

X = A

For Y:

Y = A B

For Z:

Z = B C

CIRCUIT DIAGRAM (3 BIT BINARY TO GRAY CODE CONVERTER):

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PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the three bit binary to gray code

converter.

APPARATUS REQUIRED:



2. EX-OR gate IC 7486


RESULT:

The design of the three bit Binary to Gray code converter circuit was done and its truth

table was verified.

Questions:1. What is mean by parity generator?

2. What are the types of parity and where those are used?

3. What are types of binary codes used in digital system?

4. What is the use of parity checker?5. What is mean by 1s and 2s complement?

6. What is the difference between binary and BCD code?

7. What are the advantages of code converter?

8. Why gray code is called as reflective code?

9. What is the use of k-map?

10. Give some applications for code converters.

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Ex. No. 4 IMPLEMENTATION OF SHIFT REGISTERS

AIM:

To design and implement 4 bit shift registers in SISO, SIPO, PISO, PIPO modesusing suitable ICs.

THEORY:

A register capable of shifting its binary information either to the left or to the

right is called a shift register. The logical configuration of a shift register consists of a

chain of flip flops connected in cascade with the output of one flip flop connected to the

input of the next flip flop. All the flip flops receive a common clock pulse which causes

the shift from one stage to the next.

The Q output of a D flip flop is connected to the D input of the flip flop to theleft. Each clock pulse shifts the contents of the register one bit position to the right.

The serial input determines, what goes into the right most flip flop during the shift.

The serial output is taken from the output of the left most flip flop prior to the

application of a pulse. Although this register shifts its contents to its left, if we turn the

page upside down we find that the register shifts its contents to the right. Thus a

unidirectional shift register can function either as a shift right or a shift left register.


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CIRCUIT DIAGRAM:

TRUTH TABLE:

For a serial data input of 1101,

S.NO CLOCK

PULSE

INPUTS OUTPUTS

D1 D2 D3 D4 Q1 Q2 Q3 Q4

1 1 1 X X X 1 X X X

2 2 1 1 X X 1 1 X X

3 3 0 1 1 X 0 1 1 X

4 4 1 0 1 1 1 0 1 1

5 5 X 1 0 1 X 1 0 1

6 6 X X 1 0 1 X 1 0

7 7 X X X 1 0 X X 1

8 8 X X X X X X X X

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. Apply the input and verify the truth table of the counter

APPARATUS REQUIRED:



2. D Flip Flop IC 7474 23. Connecting wires As required

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RESULT:

The truth table of a serial in serial out left shift register was hence verified.

QUESTION PAPER

1. What is a shift register?2. List out the various types of shift register.3. What is meant by serial input and serial output?4. FIFO can also called as-------------------5. LIFO is possible only in ------------------------shift register6. What is the use of clock pulse in shift register?7. What is a register?8. How many flip flops can be used in an 8 bit shift registers?9. What is mean by a universal shift register?10.

Mention some of the uses of shift register.

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Expt. No. 5 MULTIPLEXER & DEMULTIPLEXER

AIM:

To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer.

THEORY:

Multiplexer is a digital switch which allows digital information from several

sources to be routed onto a single output line. The basic multiplexer has several data

input lines and a single output line.

The selection of a particular input line is controlled by a set of selection lines.

Normally, there are 2n

input lines and n selector lines whose bit combinations determine

which input is selected. Therefore, multiplexer is many into one and it provides thedigital equivalent of an analog selector switch.

A Demultiplexer is a circuit that receives information on a single line andtransmits this information on one of 2

npossible output lines. The selection of specific

output line is controlled by the values of n selection lines.

4 X 1 MULTIPLEXER

LOGIC SYMBOL:

TRUTH TABLE (4 X 1 MULTIPLEXER):

S.NoSELECTION INPUT OUTPUT

S1 S2 Y

1. 0 0 I0

2. 0 1 I1

3. 1 0 I2

4. 1 1 I3

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CIRCUIT DIAGRAM:

7408

7432

7408

7432

7408

7432

7408

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1X4 DEMULTIPLEXER

LOGIC SYMBOL:

TRUTH TABLE (1X4 DEMULTIPLEXER):

S.NoINPUT OUTPUT

S1 S2 Din Y0 Y1 Y2 Y3

1. 0 0 0 0 0 0 0

2. 0 0 1 1 0 0 0

3. 0 1 0 0 0 0 0

4. 0 1 1 0 1 0 0

5. 1 0 0 0 0 0 0

6. 1 0 1 0 0 1 0

7. 1 1 0 0 0 0 0

8. 1 1 1 0 0 0 1

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CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the multiplexer &Demultiplexer.

APPARATUS REQUIRED:





4. AND gate ( three input ) IC 7411 15. Connecting wires As required

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RESULT:

The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their

truth tables were verified.

QUESTIONS:

1. Why multiplexer is also called as data selector?2. How many select lines are needed for 4:1 multiplexer?3. What is mean by de-multiplexer?4. How many outputs will be produced for 4 inputs in a de-multiplexer?5. Why de-multiplexer is also called as decoder?6. What are the applications of mux and demux?7. What is mean by active high signal and active low signal?8. What is the different between an encoder and a multiplexer?9. When the output will be high in a de-multiplexer?10.What are the various combinations of multiplexer and de-multiplexer?

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Ex. No.6a STUDY OF NE555 TIMER IN ASTABLE MULTIVIBRATOR

AIM:

Todesign an astable multivibrator circuit for the given specifications using 555Timer IC.

THEORY:

An astable multivibrator, often called a free-running multivibrator, is a rectangular-

wave-generating circuit. This circuit does not require an external trigger to change the

state of the output. The time during which the output is either high or low is

determined by two resistors and a capacitor, which are connected externally to the 555

timer. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to

the time the output is high and is given by,

tc = 0.69 (R1 + R2) C

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal

to the time the output is low and is given by,

td = 0.69 (R2) C

Thus the total time period of the output waveform is,

T = tc + td = 0.69 (R1 + 2 R2) C

The term duty cycle is often used in conjunction with the astable multivibrator. The

duty cycle is the ratio of the time tc during which the output is high to the total time

period T. It is generally expressed in percentage. In equation form,

% duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100

PIN DIAGRAM:

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CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

DESIGN:

Given f= 4 KHz,

Therefore, Total time period, T = 1/f = ____________

We know, duty cycle = tc/ T

Therefore, tc = ------------------------

and td = ____________

We also know for an astable multivibrator

td = 0.69 (R2) C

Therefore, R2 = _____________

tc = 0.69 (R1 + R2) C

Therefore, R1 = _____________

PROCEDURE:

1. Connections are given as per the circuit diagram.2. + 5V supply is given to the + Vcc terminal of the timer IC.3. At pin 3 the output waveform is observed with the help of a CRO4. At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage

waveforms are plotted in a graph sheet.

OBSERVATIONS:

S.No Waveforms

Amplitude

( No. of div x

Volts per div )

Time period

( No. of div x

Time per div )

tc td

1. Output Voltage , Vo

2. Capacitor voltage , Vc

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APPARATUS REQUIRED:

S. No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1

2. CRO 30 MHz 13. Dual RPS 030 V 14. Timer IC IC 555 1

5. Bread Board 1

6. Resistors As required

7. Capacitors As required

8. Connecting wires and probes As required

RESULT:

The design of the Astable multivibrator circuit was done and the output voltage and

capacitor voltage waveforms were obtained.

Ex. No.6b STUDY OF NE555 TIMER IN MULTIVIBRATOR

MONOSTABLE OPERATION

AIM:

Todesign a monostable multivibrator for the given specifications using 555 timerIC.

THEORY:

A monostable multivibrator often called a one-shot multivibrator is a pulse generating

circuit in which the duration of the pulse is determined by the RC network connected

externally to the 555 timer. In a stable or stand-by state the output of the circuit is

approximately zero or at logic low level. When an external trigger pulse is applied, the

output is forced to go high (approx. Vcc). The time during which the output remains

high is given by,

tp = 1.1 R1 C

At the end of the timing interval, the output automatically reverts back to its logic low

state. The output stays low until a trigger pulse is applied again. Then the cycle repeats.

Thus the monostable state has only one stable state hence the name monostable.

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PIN DIAGRAM:

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

DESIGN:

Given tp = 0.616 ms = 1.1 R1 C

Therefore, R1 = _____________

PROCEDURE:

1. Connections are given as per the circuit diagram.2.

+ 5V supply is given to the + Vcc terminal of the timer IC.3. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC

4. At pin 3 the output waveform is observed with the help of a CRO5. At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage

waveforms are plotted in a graph sheet.

OBSERVATIONS:

S.No Observation

Amplitude

( No. of div x

Volts per div )

Time period

( No. of div x

Time per div )

ton toff

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1. Trigger input

2. Output Voltage , Vo

3. Capacitor voltage , Vc

APPARATUS REQUIRED:


1. Function Generator 3 MHz, Analog 1

2. CRO 30 MHz 1

3. Dual RPS 030 V 14. Timer IC IC 555 1

5. Bread Board 1




RESULT:

The design of the Monostable multivibrator circuit was done and the input and outputwaveforms were obtained.

Questions:

1. What is meant by astable multivibrator?2. In an astable multivibrator what type of wave form is generated?3. What is meant by duty cycle?4. What is meant by monostable multivibrator?5. Monostable multivibrator is also called as------------?6. Explain the differences between oscillations obtained from 555 and

digital IC.

7. What is meant by a trigger?8. How many stable states can be achieved in a monostable

multivibrator?

9. What are the applications of multivibrator?10.List out the applications of 555 timer IC.

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Ex. No.7a INVERTING AMPLIFIER

AIMTo design an Inverting Amplifier for the given specifications using Op-Amp IC 741.

THEORY:

The input signal Vi is applied to the inverting input terminal through R1 and the non-

inverting input terminal of the op-amp is grounded. The output voltage Vo is fed back

to the inverting input terminal through the Rf- R1 network, where Rf is the feedback

resistor. The output voltage is given as,

Vo = - ACL ViHere the negative sign indicates that the output voltage is 180

0out of phase with the

input signal.

PRECAUTIONS:

Output voltage will be saturated if it exceeds 15V.

PROCEDURE:

1. Connections are given as per the circuit diagram.2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.3. By adjusting the amplitude and frequency knobs of the function generator,

appropriate input voltage is applied to the inverting input terminal of the Op-

Amp.

4. The output voltage is obtained in the CRO and the input and output voltagewaveforms are plotted in a graph sheet.

PIN DIAGRAM:

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CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

DESIGN:

We know for an inverting Amplifier ACL = RF/ R1Assume R1 (approx. 10 K) and find RfHence Vo(theoretical) = - ACL Vi

OBSERVATIONS:

S.No. Amplitude

( No. of div x Volts per div )

Time period

( No. of div x Time per div )

Input

Output Theoretical -

Practical -

APPARATUS REQUIRED:



2. CRO 30 MHz 1

3. Dual RPS 030 V 1

4. Op-Amp IC 741 15. Bread Board 1



RESULT:

The design and testing of the inverting amplifier is done and the input and output

waveforms were drawn

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Ex. No.7b NON - INVERTING AMPLIFIER

AIM:

To design a Non-Inverting Amplifier for the given specifications using Op-Amp

IC 741.

THEORY:

The input signal Vi is applied to the non - inverting input terminal of the op-amp. This

circuit amplifies the signal without inverting the input signal. It is also called negative

feedback system since the output is feedback to the inverting input terminals. The

differential voltage Vd at the inverting input terminal of the op-amp is zero ideally and

the output voltage is given as,Vo = ACL Vi . Here the output voltage is in phase with the

input signal.

PRECAUTIONS:

Output voltage will be saturated if it exceeds 15V.

PROCEDURE:


appropriate input voltage is applied to the non - inverting input terminal of the

Op-Amp.


PIN DIAGRAM:

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CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

DESIGN:

We know for a Non-inverting Amplifier ACL = 1 + (RF/ R1)

Assume R1 ( approx. 10 K ) and find RfHence Vo = ACL ViOBSERVATIONS:

S.No. Amplitude


Time period


Input

Output Theoretical -

Practical -

APPARATUS REQUIRED:



2. CRO 30 MHz 1

3. Dual RPS (030) V 14. Op-Amp IC 741 1

5. Bread Board 1



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Expt. No.8a INTEGRATOR

Obtain the output of an Integrator circuit with component values R1Cf = 0.1ms, Rf = 10

R1 and Cf= 0.01 F , if 2 V peak to peak square wave at 1000Hz is applied as input.

AIM:

To design an Integrator circuit for the given specifications using Op-Amp IC 741.

THEORY:

A circuit in which the output voltage waveform is the integral of the input voltage

waveform is the integrator. Such a circuit is obtained by using a basic inverting

amplifier configuration if the feedback resistor Rf is replaced by a capacitor Cf . The

expression for the output voltage is given as,

Vo = - (1/RfC1) Vi dtHere the negative sign indicates that the output voltage is 180

0out of phase with the

input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the

value of fa < fb . The input signal will be integrated properly if the Time period T of the

signal is larger than or equal to RfCf. That is,

T RfCfThe integrator is most commonly used in analog computers and ADC and signal-wave

shaping circuits.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF INTEGRATOR:

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DESIGN:

We know the frequency at which the gain is 0 dB, fb = 1 / (2 R1 Cf)Therefore fb = _____

Since fb = 10 fa, and also the gain limiting frequency fa= 1 / (2 RfCf)We get, Rf= _______ and hence R1 = __________

PROCEDURE:



Amp.


OBSERVATIONS:

S.No. Amplitude


Time period


Input

Output

APPARATUS REQUIRED:



2. CRO 30 MHz 13. Dual RPS 030 V 14. Op-Amp IC 741 1

5. Bread Board 1




RESULT:

The design of the Integrator circuit was done and the input and output waveforms were

obtained.

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Expt. No.8b DIFFERENTIATOR

AIM:

To design a Differentiator circuit for the given specifications using Op-Amp IC 741.

THEORY:The differentiator circuit performs the mathematical operation of differentiation; that

is, the output waveform is the derivative of the input waveform. The differentiator may

be constructed from a basic inverting amplifier if an input resistor R 1 is replaced by a

capacitor C1. The expression for the output voltage is given as,

Vo = - RfC1 (dVi/dt)

Here the negative sign indicates that the output voltage is 1800

out of phase with the

input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input

terminal of the op-amp to compensate for the input bias current. A workable

differentiator can be designed by implementing the following steps:

1. Select fa equal to the highest frequency of the input signal to be differentiated.Then, assuming a value of C1 < 1 F, calculate the value of Rf.

2. Choose fb = 20 fa and calculate the values of R1 and Cfso that R1C1 = RfCf.The differentiator is most commonly used in waveshaping circuits to detect high

frequency components in an input signal and also as a rateofchange detector in FMmodulators.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

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DESIGN:

Given fa = ---------------

We know the frequency at which the gain is 0 dB, fa = 1 / (2 RfC1)Let us assume C1 = 0.1 F; then

Rf= _________

Since fb = 20 fa, fb = ---------------We know that the gain limiting frequency fb= 1 / (2 R1 C1)Hence R1 = _________

Also since R1C1 = RfCf ; Cf= _________

PROCEDURE:



Amp.


OBSERVATIONS:

Input - Sine wave

S.No. Amplitude


Time period


Input

Output

InputSquare waveS.No. Amplitude


Time period


Input

Output

APPARATUS REQUIRED:



2. CRO 30 MHz 13. Dual RPS 030 V 14. Op-Amp IC 741 1

5. Bread Board 1




RESULT:

The design of the Differentiator circuit was done and the input and output waveforms

were obtained.

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Questions:

1. What is mean by integrator?2. Where the integrator circuit is used?3. What is mean by differentiator?4. Where the differentiator circuit is used?5. What is the difference between integrator and differentiator?6. What are the applications of differentiator and integrator?7. Give the mathematical expiration for differentiation and integration.8. What is the use of feedback resistance and capacitance?9. Define delay time?10.What are the various types of wave forms obtained for integrator and

differentiator?

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Ex. No.9 STUDY OF ANALOG TO DIGITAL CONVERTER AND DIGITAL

TO ANALOG CONVERTER

AIM

To verify A/D conversion and D/A conversion using dedicated ICs

THEORY:

An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device

which converts a continuous quantity to a discrete timedigital representation. An ADC

may also provide an isolated measurement. The reverse operation is performed by a

digital-to-analog converter(DAC).

Typically, an ADC is an electronicdevice that converts an input analog voltage or

current to a digital number proportional to the magnitude of the voltage or current.However, some non-electronic or only partially electronic devices, such as rotary

encoders, can also be considered ADCs.

A digital-to-analog converter (DAC or D-to-A) is a device that converts a digital

(usually binary) code to an analog signal (current, voltage, or electric charge). An

analog-to-digital converter (ADC) performs the reverse operation.

DIGITAL TO ANALOG CONVERTER

Circuit Diagram: Digital to analog diagram

NC COMPENSATION

GND

MSB A1 AB LSB

A2 A7

A3 A6

A4 A4

1

16

2

15

3

144 DAC0808

13

5

12

6

11

7

10

8
http://en.wikipedia.org/wiki/Continuous_signalhttp://en.wikipedia.org/wiki/Discrete_signalhttp://en.wikipedia.org/wiki/Digital-to-analog_converterhttp://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Voltagehttp://en.wikipedia.org/wiki/Electric_currenthttp://en.wikipedia.org/wiki/Rotary_encoderhttp://en.wikipedia.org/wiki/Rotary_encoderhttp://en.wikipedia.org/wiki/Analog_signalhttp://en.wikipedia.org/wiki/Current_(electricity)http://en.wikipedia.org/wiki/Voltagehttp://en.wikipedia.org/wiki/Electric_chargehttp://en.wikipedia.org/wiki/Analog-to-digital_converterhttp://en.wikipedia.org/wiki/Analog-to-digital_converterhttp://en.wikipedia.org/wiki/Electric_chargehttp://en.wikipedia.org/wiki/Voltagehttp://en.wikipedia.org/wiki/Current_(electricity)http://en.wikipedia.org/wiki/Analog_signalhttp://en.wikipedia.org/wiki/Rotary_encoderhttp://en.wikipedia.org/wiki/Rotary_encoderhttp://en.wikipedia.org/wiki/Electric_currenthttp://en.wikipedia.org/wiki/Voltagehttp://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Digital-to-analog_converterhttp://en.wikipedia.org/wiki/Discrete_signalhttp://en.wikipedia.org/wiki/Discrete_signalhttp://en.wikipedia.org/wiki/Continuous_signal

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Circuit Diagram

Analog to digital converter

CLOCK INPUT OE ALE

CLK D0 LED1 A1 MSB

EOC D1 LED2 A2

SC D2 LED3 A3

ANALOG INPUT IN0 D3 LED4 A4

IN1

IN2 D4 LED5 A5

IN3 D5 LED6 A6

IN4 D6 LED7 A7

IN5

IN6 D7 LED8 A8 LSB

IN7

A B C GND

Procedure:

1. Connections are made as per the circuit diagram.2. Input analog voltage is applied to pin 6.3. The corresponding digital output is noted in the LED sequence.4. Input voltage is varied and the corresponding digital output is noted in the LED

sequence the bit batten is.

12 11 9

22

10

21

7

20

6

19

26

18

27 ADC

8

28 0808

15

1

14

2

3

174

5

16

25 24 23

13

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Tabular Column:

S.NO I/P

VOLTAGE

OUTPUT BIT PATTERN

A1

(MSB)

A2 A3 A4 A5 A6 A7 A8

(LSB)

+5V

A1 5K 10 V

A2

A3 5K

A4

A5 5K

A6 2 7 Output

A7 4 +15

A8 3 14 -15

0.1

135

14

6

7

15

8 DAC0808

2

9

10

4

1112

16

1

3

741

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DESIGN:

Output Voltage

VO=Vref=(A1/2+A2/4+A3/8+A4/16++A5/32+A6/64+A7/128+A8/256)

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Output from pin 4 is current signal and it is converted to proportional voltage by IC

741 op-amp.

3. Output voltage is measured using a voltmeter.

4. Output voltage for different input bit pattern is measured and tabulated.

Tabular column:

S.NO Input Bit Pattern Output

Voltage

A1

(MSB)

A2 A3 A4 A5 A6 A7 A8

(LSB)

Components required:

1. Analog ice trainer kit.

2. ADC 0808

3. DAC 0808

4. 741 op amp

5. Resistors

6. Capacitors.

7. Voltmeter (0-30v)

8. Connecting wires.

RESULT:

Thus the A/D conversion and D/A conversion using dedicated ICs is studied and

verified.

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QUESTIONS:

1. What is mean by ADC?2. Why flash type ADC is mostly used?3. What are the various types of inputs given to ADC?4. Why op-amp is used in ADC?5. What is the advantage of ADC?6. What is mean by DAC?7. What are the various other methods of DAC?8. What are the input sources given to a DAC?9. What is mean by reference voltage?10.Mention some of the applications of DAC?

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Ex.No.10 STUDY OF VCO AND PLL ICS

AIM:

To study voltage to frequency conversion characteristics of NE566 VCO IC and

frequency multiplication characteristics of NE565 PLL IC.

CIRCUIT DIAGRAM

VOLTAGE FREQUENCY CONVERSION CHARACTERISTICS OF NE566 IC

+6V

1K

1K

Triangular Wave Output

0.1

Square Wave Output

1K

0.1

DESIGN:

fo=2(Vcc-Vm)/(Vcc X Rt X Ct)

fo-output oscillation frequency

Vcc-supply voltage

Vm-modulating input voltage

PROCEDURE

1. connections are made as per the circuit diagram2. square wave output from pin 3 is observed in the CRO

CR0

6 8

4

NE 566 VCO IC

3

7

1

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3. modulating input voltage is varied and corresponding output frequency ismeasured and tabulated

OBSERVATION

Vcc=+5V

S.NO Vm (VOLTS) fo(Hz)

CIRCUIT DIAGRAM

FREQUENCY MULTIPLICATION CHARACTERISTICS OF NE565 IC

+6V

20 K 2K 0.001

VCO Output

0.01F

- 6V4.7 K

10 K

2N2222

FG

8

10

7

2 NE565 PLL

IC4

3

5 9 1

11

5

7490 1

2 3 6 7

CR

O

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DESIGN

Fo=Nfs

Fo-output oscillation frequency

Fs-input frequencyN-dividend of the divide by counter

PROCEDURE

1. connections are made as per the circuit diagram2. square wave input given to pin 23. output taken from pin 4 is observed in the CRO4. input frequency is varied and corresponding output frequency is measured and

tabulated

OBSERVATION

N=5

S.NO fs(Hz) fo(Hz)

APPARATUS REQUIRED

1. Analog IC trainer kit2. NE566 VCO IC3. NE 565 PLL IC4. Resistors5. Capacitors6. Voltmeter7. Function generator8. CRO9. Connecting wires

RESULT

Thus the voltage to frequency conversion and phase locked loop is studied.

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QUESTIONS:

1. What is mean by an oscillator?2. What is mean by VCO?3. Mention the applications of VCO.4. What are characteristics of VCO?5. What is mean by voltage multiplexer?6. What is mean by PLL?7. What are the various blocks of PLL?8. What is mean by frequency multiplexing?9. What are the ICs used for constructing a PLL?10.What is mean by filter and mention the various types of filters?

Documents

LDIC FINAL22.6.11