Lec 13Systems Architecture1 Systems Architecture Lecture 13: Integer Multiplication and Division Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan

Lec 13 Systems Architecture 1

Systems Architecture

Lecture 13: Integer Multiplication and Division

Jeremy R. JohnsonAnatole D. RuslanovWilliam M. Mongan

Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).


Introduction

• Objective: To provide hardware support for MIPS integer multiplication and divide instructions. To understand how to implement multiplication and division in hardware.

• Topics– Review MIPS ALU design– Review integer multiplication and division– MIPS integer multiply and divide instructions– Multiplication algorithms– Division algorithms– Multiply/Divide unit


Support for SLT and Overflow Detection

0

3

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b 2

Less

0

3

Result

Operation

a

1

CarryIn

0

1

Binvert

b 2

Less

Set

Overflowdetection

Overflow

a.

b.

0

3

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b 2

Less

0

3

Result

Operation

a

1

CarryIn

0

1

Binvert

b 2

Less

Set

Overflowdetection

Overflow

a.

b.


MIPS ALU

Seta31

0

Result0a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Bnegate

Zero

ALU0Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

ALU control lines Function000 and001 or010 add110 subtract111 set on less than

ALU ResultZero

Overflow

a

b

ALU operation

CarryOut


MIPS Integer Multiply and Divide

• Hi and Lo registers– mfhi– mflo

• Signed and unsigned multiply– mult– multu

• Divide instructions– div– divu– quotient is available in Lo and remainder in Hi

Lec 13 Systems Architecture

• More complicated than addition– accomplished via shifting and addition

• More time and more microchip area• We will look at 3 versions based on a simple algorithm

we learned in elementary school:

0010 (multiplicand)

__x_1011 (multiplier)

• Negative numbers: convert and multiply– there are better techniques, we won’t look at them

Multiplication in Hardware


Multiplication Hardware – Algorithm 1

DatapathControl

MultiplicandShift left

64 bits

64-bit ALU

ProductWrite

64 bits

Control test

MultiplierShift right

32 bits

32nd repetition?

1a. Add multiplicand to product and

place the result in Product register

Multiplier0 = 01. Test

Multiplier0

Start

Multiplier0 = 1

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

No: < 32 repetitions

Yes: 32 repetitions

Done

Lec 13 Systems Architecture 8http://www.cs.rpi.edu/~hollingd/comporg.2000/Notes/Mult.PDF



MultiplierShift right

Write

32 bits

64 bits

32 bits

Shift right

Multiplicand

32-bit ALU

Product Control test

Done

1. TestMultiplier0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1


Yes: 32 repetitionsDatapathControl



Multiplicand

32 bits

32-bit ALU

ProductWrite

64 bits

Controltest

Shift right

Note: Multiplier starts in right half of product.

Done

1. TestProduct0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

32nd repetition?

Start

Product0 = 0Product0 = 1


Yes: 32 repetitionsDatapathControl



Fast Multiplication Hardware

• Unroll the addition “loop”

• Use 32 32-bit adders• Each adder produces

32-bits and a carry-out• The least significant bit

of each intermediate sum is a bit of the product.

• The other 31 bits and the carry-out are passed along to the next adder.

April 19, 2023 Chapter 3 — Arithmetic for Computers

13

Faster Multiplier

• Uses multiple adders– Cost/performance tradeoff

Can be pipelinedSeveral multiplication performed in parallel


Division Hardware – Algorithm 1

64-bit ALU

Controltest

QuotientShift left

RemainderWrite

DivisorShift right

64 bits

64 bits

32 bits

Done

Test Remainder

2a. Shift the Quotient register to the left,setting the new rightmost bit to 1

3. Shift the Divisor register right 1 bit

33rd repetition?

Start

Remainder < 0


Yes: 33 repetitions

2b. Restore the original value by addingthe Divisor register to the Remainder

register and place the sum in theRemainder register. Also shift the

Quotient register to the left, setting thenew least significant bit to 0

1. Subtract the Divisor register from theRemainder register and place the result in the Remainder register

Remainder > 0–


Division Hardware – Algorithm 3

Write

32 bits

64 bits

Shift leftShift right

Remainder

32-bit ALU

Divisor

Controltest

Done. Shift left half of Remainder right 1 bit

Test Remainder

3a. Shift the Remainder register to the left, setting the new rightmost bit to 1

32nd repetition?

Start

Remainder < 0


Yes: 32 repetitions

3b. Restore the original value by addingthe Divisor register to the left half of theRemainder register and place the sum

in the left half of the Remainder register.Also shift the Remainder register to theleft, setting the new rightmost bit to 0

2. Subtract the Divisor register from theleft half of the Remainder register andplace the result in the left half of the

Remainder register

Remainder 0

1. Shift the Remainder register left 1 bit

–>


Documents

Lec 13Systems Architecture1 Systems Architecture Lecture 13: Integer Multiplication and Division Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan