Lec11-Digital System Testing_1

8/3/2019 Lec11-Digital System Testing_1

1/82

Digital System Testing


2/82

Why Testing..?

To determine the presence of faults, not theabsence of faults, in a given circuit. No amount of testing can guarantee that a circuit (chip,

board or system) is fault free. We carry out testing to increase our confidence in proper

working of the circuit.

Verification is an alternative to testing, used to

verify the correctness of a design. Simulation based methods.

Formal methods.


3/82

Testing basics

Verification:Predictive analysis to ensure that

the synthesized design, when manufactured,

will perform the given I/O function.

Test: A manufacturing step that ensures that

the physical device, manufactured from the

synthesized design, has no manufacturing

defect.


4/82

Testing vs. Verification

Testing

Verifies correctness ofmanufactured hardware.

Two-part process:

1. Test generation: softwareprocess executed once duringdesign

2. Test application: electricaltests applied to hardware

Test application performed onevery manufactured device.

Responsible for quality ofdevices.

Verification

Verifies correctness of design.

Performed by simulation,hardware emulation, or formalmethods.

Performed once prior tomanufacturing.

Responsible for quality ofdesign.


5/82

Levels of Testing

Testing can be carried out at the level of

Chip

Board

System

Cost :: Rule of 10

It costs 10 times more to test a device as we move

to the next higher level in the product

manufacturing process.


6/82


7/82

Costs of Testing

Design For Testability (DFT)

Chip area overhead and yield reduction

Performance overhead

Software processes of test Test generation and fault simulation

Test programming and debugging

Manufacturing testAutomatic test equipment(ATE) capital cost

Test center operational cost


8/82

Basic Testing Principle


9/82

Defects, Errors, and Faults

Defect: A defectin an electronic system is theunintended difference between the implemented

hardware and its intended design.

Error: A wrong output signal produced by adefective system is called an error. An error is an

effect whose cause is some defect.

Fault: A representation of a defect at theabstracted function level is called afault.


10/82

Example

Consider a digital system consisting of two inputs a and b, one output c,

and one two-input AND gate. The system is assembled by connecting a wire

between the terminal a and the first input of the AND gate. The output of

the gate is connected to c. But the connection between b and the gate is

incorrectly made b is left unconnected and the second input of the gate is

grounded. The functional output of this system, as implemented, is c=0,

instead of the correct output c=ab.

For this system, we have:

Defect: a short to ground.

Error: a=1,b=1 output c=0; correct output c=1.

Fault: signal b stuck at logic 0.


11/82

Some Real Defects in Chips

Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . .

Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) . . .

Time-dependent failures Dielectric breakdown

Electromigration . . .

Packaging failures Contact degradation Seal leaks . . .


12/82

Yield

A manufacturing defect is a finite chip areawith electrically malfunctioning circuitrycaused by errors in the fabrication process.

A chip with no manufacturing defect is called agood chip.

Fraction (or percentage) of good chipsproduced in a manufacturing process is calledtheyield..


13/82

Yield

Wafer

Defects

Faulty chips

Good chips

Unclustered defects

Wafer yield = 12/22 = 0.55

Clustered defects (VLSI)

Wafer yield = 17/22 = 0.77


14/82

Fault Modeling

I/O function tests inadequate for manufacturing(functionality versus component and interconnect testing)

Real defects (often mechanical) too numerous and often

not analyzable

A fault model identifies targets for testing

A fault model makes analysis possible

Effectiveness measurable by experiments


15/82


16/82

Stuck-at Faults

Some lines in the circuit are permanently stuck

at logic 0 or logic 1.

Two types

Single stuck-at faults

Multiple stuck-at faults


17/82

Single Stuck-at Fault

Simpler to handle computationally

Reasonably good fault coverage

A test set for detecting single stuck-at faults detects

a large percentage of multiple stuck-at faults aswell

Three properties define a single stuck-at fault

Only one line is faulty The faulty line is permanently set to 0 or 1

The fault can be at an input or output of a gate


18/82

Single Stuck-at Fault

For a circuit with k lines, the total number of

single stuck-at faults possible is 2k.

Most widely used fault model in the industry.


19/82

Example1 (No Fanout)

1

X

Stuck-at-1

0 (1)

0 (1)

True Response Faulty Response

1

1

0

0

Test Vector

This circuit has 7 fault sites and 14 single

stuck-at faults


20/82

Example2 (Fanout)

XOR circuit has 12 fault sites ( ) and 24 singlestuck-at faults

a

b

c

d

e

f

10

ghi

1

s-a-0

j

k

z

0(1)

1(0)

1

Test vector for h s-a-0 fault

Good circuit value

Faulty circuit value


21/82

Fault sites

Number of fault sites in a Boolean gate circuit

depends on number

Primary Inputs

Gates,

fanout branches.


22/82

Fault Equivalence

Fault equivalence: Two faults f1 and f2 are equivalentif all tests that detect f1 also detect f2.

If faults f1 and f2 are equivalent then the corresponding

faulty functions are identical.

Two faults of a Boolean circuit are called equivalent iffthey transform the circuit such that the two faulty

circuits have identical output functions. Equivalentfaults are also called indistinguishable and haveexactly the same set of tests.


23/82

Fault collapsing

All single faults of a logic circuit can be

divided into disjoint equivalence subsets,

where all faults in a subset are mutually

equivalent. A collapsed fault set contains onefault from each equivalence subset.

faultsallofSet

faultscollapsedofSetRatioCollapse


24/82


25/82


26/82

Equivalence Example

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

Faults in blue

removed by

equivalence

collapsing

20

Collapse ratio = ----- = 0.62532


27/82

Fault Dominance

If all tests of some fault F1 detect another fault

F2, then F2 is said to dominate F1.

Dominance fault collapsing:

If fault F2 dominates F1, then F2 is removed from

the fault list.

When dominance fault collapsing is used, it is

sufficient to consider only the input faults of

Boolean gates.


28/82

Fault Dominance

In a tree circuit (without fanouts) PI faults

form a dominance collapsed fault set.

If two faults dominate each other then they are

equivalent.


29/82

Dominance Example

s-a-1

F1

s-a-1F2

001

110 010

000

101 100 011

All tests of F2

Only test of F1s-a-1

s-a-1s-a-1

s-a-0

A dominance collapsed fault set


30/82

Dominance Collapsing

An n-input Boolean gate requires n + 1 single stuck-atfaults to be modeled.

To collapse faults of a gate, all faults from the output can be

eliminated retaining one type (s-a-1 for AND and NAND; s-a-0 for OR and NOR) of fault on each input and the othertype (s-a-0 for AND and NAND; s-a-1 for OR and NOR) onany one of the inputs.

The output faults of the NOT gate, the non-inverting buffer,and the wire can be removed as long as both faults on theinput are retained. No collapsing is possible for fanout.


31/82

Checkpoints

Primary inputs and fanout branches of a

combinational circuit are called checkpoints.

Checkpoint theorem: A test set that detects all

single (multiple) stuck-at faults on all

checkpoints of a combinational circuit, also

detects all single (multiple) stuck-at faults in

that circuit.


32/82

Checkpoints

Total fault sites = 16

Checkpoints ( ) = 10


33/82


34/82

Stuck-Open Example

Two-vector s-op test

can be constructed byordering two s-at testsA

B

VDD

C

pMOS

FETs

nMOS

FETs

Stuck-

open

1

0

0

0

0 1(Z)

Good circuit states

Faulty circuit states

Vector 1: test forA s-a-0

(Initialization vector)

Vector 2 (test forA s-a-1)


35/82

Stuck-Short Example

A

B

VDD

C

pMOS

FETs

nMOS

FETs

Stuck-short

1

0

0 (X)

Good circuit state

Faulty circuit state

Test vector forA s-a-0

IDDQ path in

faulty circuit


36/82

Automatic Test-Pattern Generator

ATPG algorithms inject a fault into a circuit,

and then use a variety of mechanisms to

activate the fault and cause its effect to

propagate through the hardware and manifestitself at a circuit output.


37/82

Random Pattern Generation

Start

Set input

probabilities

Generate a randomvector

Simulate Faults

Check

Coverage

Stop

Change

Probabilities

Adequate

Inadequate


38/82

Random Pattern Generation

Use to get tests for 60-80% of faults, then

switch to ATPG(Automatic Test Pattern

Generation) for rest.

No. of patterns

Fault

Coverage

100%

300


39/82

Functional ATPG programs generate a

complete set of test-patterns to completely

exercise the circuit function.

Structural test only exercises the minimal set

of stuck-at faults on each line of the circuit,

after discarding equivalent faults.

Functional vs Structural ATPG


40/82

Functional vs Structural ATPG

Example 64bit adder

Functional Block


41/82

Functional ATPG

Generate complete set of tests for circuit input-

output combinations. 129 inputs, 65 outputs

2129 = 680,564,733,841,876,926,926,749,214,863,536,422,912 inputpatterns required.

Fastest automatic test equipment(ATE), operating at 1GHZ

would take 2.1580566142x1022 years to apply all these

patterns.


42/82

Structural ATPG

Sum Circuit


43/82

Structural ATPG

Carry Circuit


44/82

Structural ATPG

In the adder

No redundant adder hardware, 64 bit slices.

Each with 27 faults

At most 64x27 = 1728 faults (tests) Takes 0.000001728 s on 1GHZ ATE.

In practice

Designer gives small set of functional tests. Augment with structural tests to boost coverage to

>98%


45/82

Design For Testability (DFT)


46/82

Definition

Design for testability(DFT) refers to those design techniques

that make test generation and test application cost-effective.

DFT methods for digital circuits:

Ad-hoc methods

Structured methods:

Scan

Partial Scan

Built-in self-test(BIST)

Boundary scan

DFT method for mixed-signal circuits:

Analog test bus


47/82

Ad-hoc methods


48/82

Ad-Hoc DFT Methods

Good design practices learnt through experience are used asguidelines:

Do-s and Donts

Avoid asynchronous (unclocked) feedback.

Avoid delay dependant logic. Avoid self resetting logic.

Avoid gated clocks.

Avoid redundant gates.

Avoid large fanin gates.

Make flip-flops initializable. Separate digital and analog circuits.

Provide test control for difficult-to-control signals.

Consider ATE requirements (tristates, etc.)


49/82

Design reviews conducted by experts or design auditing tools.

Disadvantages of ad-hoc DFT methods: Experts and tools not always available.

Test generation is often manual with no guarantee of high fault coverage.

Design iterations may be necessary.


50/82

Structured methods


51/82

1.Scan Design

Objectives

Simple read/write access to all subset of storage

elements in a design.

Direct control of storage elements to an arbitraryvalue (0 or 1)

Direct observation of the state of storage elements

and hence the internal state of the circuit. Enhanced controlability and observability


52/82


53/82

Scan Design

Use combinational ATPG to obtain tests for alltestable faults in the combinational logic.

Add shift register tests and convert ATPG tests intoscan sequences for use in manufacturing test.


54/82

Scan Design Rules

Use only clocked D-type of flip-flops for all

state variables.

At least one PI pin must be available for test;

more pins, if available, can be used.

All clocks must be controlled from PIs.

Clocks must not feed data inputs of flip-flops.


55/82

Correcting a Rule ViolationCorrecting a Rule Violation

All clocks must be controlled from PIs.

Comb.

logic

Comb.logic

D1

D2

CK

Q

FF

Comb.

logic

D1

D2

CK

Q

FF

Comb.

logic


56/82

Scan Flip-Flop (SFF)

D

TC

SD

CK

Q

QMUX

D flip-flop

Master latch Slave latch

CK

TC Normal mode, D selected Scan mode, SD selected

Master open Slave opent

t

Logic

overhead


57/82

Adding Scan Structure

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANIN

TC or TCK Not shown: CK orMCK/SCK feed all

SFFs.


58/82

Combinational Test Vectors

I2I1 O1 O2

S2S1 N2N1

Combinational

logic

PI

Present

state

PO

Next

state

SCANIN

TCSCANOUT


59/82

Testing Scan Register

Scan register must be tested prior to application of scan test sequences.

A shift sequence 00110011 . . . of length nsff+4 in scan mode (TC=0)produces 00, 01, 11 and 10 transitions in all flip-flops and observes theresult at SCANOUT output.

Total scan test length:= ((nsff+1)ncomb + nsff) + (nsff + 4) clock periods.

= (ncomb + 2) nsff+ ncomb + 4 clock periods.

Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~

106

clocks.

Multiple scan registers reduce test length.


60/82

Multiple Scan Registers

Scan flip-flops can be distributed among any number of shiftregisters, each having a separate scanin and scanoutpin.

Test sequence length is determined by the longest scan shiftregister.

Just one test control (TC) pin is essential.

SFFSFF

SFF

Combinational

logic

PI/SCANINM

U

X

CK

TC


61/82

Scan Overheads

IO pins: One pin necessary.

Area overhead: Gate overhead= [4 nsff/(ng+10nff)] x 100%,

where ng = comb. gates; nff=flip-flops; Example ng= 100k gates, nff= 2kflip-flops, overhead = 6.7%.

More accurate estimate must consider scan wiring andlayout area.

Performance overhead: Multiplexer delay added in combinational path; approx.

two gate-delays. Flip-flop output loading due to one additional fanout;

approx. 5-6%.


62/82


63/82

Scan Design - Summary

Scan is the most popular DFT technique: Rule-based design

Automated DFT hardware insertion

Combinational ATPG

Advantages: Design automation

High fault coverage; helpful in diagnosis

Hierarchicalscan-testable modules are easilycombined into large scan-testable systems

Moderate area (~10%) and speed (~5%) overheads


64/82

Scan Design - Summary

Disadvantages: Additional pin requirement.

Test hardware slows down the clock

Large test data volume and long test time

Basically a slow speed (DC) test


65/82

2.Partial-Scan Definition

A subset of flip-flops is scanned.

Objectives: Minimize area overhead and scan sequence length, yet

achieve required fault coverage Exclude selected flip-flops from scan:

Improve performance

Allow limited scan design rule violations

Allow automation:

In scan flip-flop selection In test generation

Shorter scan sequences


66/82

Partial-Scan Architecture

FF

FF

SFF

SFF

Combinational

circuit

PI PO

CK1

CK2 SCANOUT

TC


67/82

Partial-Scan -Summary

Partial-scan is a generalized scan method; scancan vary from 0 to 100%.

Partial-scan has lower overheads (area anddelay) and reduced test length.

Partial-scan allows limited violations of scandesign rules, e.g., a flip-flop on a critical pathmay not be scanned.


68/82

3.Built-In Self-Test (BIST)

Useful for field test and diagnosis (less expensivethan a local automatic test equipment)

Software tests for field test and diagnosis: Low hardware fault coverage

Low diagnostic resolution

Slow to operate

Hardware BIST benefits: Lower system test effort

Improved system maintenance and repair

Improved component repair

Better diagnosis


69/82

Test Problems Alleviated by BIST

Increasing chip logic-to-pin ratioharder observability Increasingly dense devices and faster clocks

Increasing test generation and application times

Increasing size of test vectors stored in ATE

Expensive ATE needed for 1 GHz clocking chips Hard testability insertiondesigners unfamiliar with

gate-level logic, since they design at behavioral level

In-circuit testing no longer technically feasible

Shortage of test engineers Circuit testing cannot be easily partitioned.


70/82

BIST Costs

Chip area overhead for: Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware

Pin overhead -- At least 1 pin needed to activate BIST operation

Performance overheadextra path delays due to BIST

Yield lossdue to increased chip area or more chips In system because ofBIST

Reliability reductiondue to increased area

Increased BIST hardware complexityhappens when BIST hardware ismade testable.


71/82

BIST Architecture

BILBO Built-in Logic Block


72/82

BILBOBuilt-in Logic Block

Observer

Programmable hardware block.

Can work as both a Test Pattern Generator(TPG)

and a Response Compactor(RC).

Four modes of operation:1. Flip-flop

2. LFSR pattern generator

3. LFSR response compacter4. Scan chain for flip-flops


73/82


74/82

LFSR


75/82

4.Boundary Scan

IEEE 1149.1 JTAG Boundary Scan Standard


76/82

System Test Logic


77/82


78/82

Serial Board / MCM Scan


79/82

Parallel Board / MCM Scan


80/82

Tap Controller

Boundary Scan Instructions

TESTING PORTIONS


81/82

TESTING -PORTIONS

ROTH-339 to 354 ,361 to 365

P 457 to461 p477 ,481 to 483,

P 1-8 ,p93 to 106

P 343 to 369


82/82

Thank You

All the Best

Documents

Lec11-Digital System Testing_1