Interrupts

CSC501 Operating Systems Principles

1

Last Lecture

q DeadlockQ Necessary ConditionsQ Solutions

q TodayQ Interrupts

2

Question: Why do we need

interrupts?

Introduction

q Interrupts provide an efficient way to handle unanticipated events and improve processor utilization

q Interrupts alter a program’s flow of controlQ Interrupt causes transfer of control to an

interrupt service routine (ISR)v ISR is also called a handler

Q When the ISR is completed, the original program resumes execution

Q Behavior is similar to a procedure callv Some significant differences between the two

3

Interrupts vs. ProceduresInterrupts

q Initiated by both softwareand hardware

q Can handle anticipated and unanticipated internal as well as external events

q ISRs or interrupt handlers are memory resident

q Use numbers to identify an interrupt service

q eflags register is saved automatically

Proceduresq Can only be initiated by

softwareq Can handle anticipated

events that are coded into the program

q Typically loaded along with the program

q Use meaningful names to indicate their function

q Do not save the eflagsregister

A Taxonomy of Pentium Interrupts

Difference:q Depending on the way they are reportedq Whether or not the interrupted instruction is

restarted

Difference:q Depending on the way they are reportedq Whether or not the interrupted instruction is

restarted

Interrupt Taxonomy

q ExceptionsQ Faults, Traps, and Aborts

q Software Interruptsq Hardware Interrupts

6

Exceptions: Faults, Traps, and Abortsq FaultsQ Instruction boundary before the instruction

during which the exception was detectedQ Restarts the instruction

q Examples:Q Page faultQ Segment-not-found fault

Exceptions: Faults, Traps, and Abortsq TrapsQ Instruction boundary immediately after the

instruction during which the exception was detected

Q No instruction restartq Examples:Q Overflow exception (interrupt 4) is a trapQ User defined interrupts are also examples of

traps

Exceptions: Faults, Traps, and Aborts

qAbortsQNo precise location of the instruction that

caused the exceptionQNo instruction restartingQ Reporting severe errors such as hardware

errors and inconsistent values in system tablesqExamples:QMachine checkQDouble fault

9

Dedicated Interrupts

q Several Pentium predefined interrupts ---called dedicated interrupts

q These include the first five interrupts:interrupt type Purpose

0 Divide error1 Single-step2 Non-maskable interrupt (NMI)3 Breakpoint4 Overflow

Dedicated Interrupts (cont’d)

qSingle-Step InterruptQUseful in debuggingQTo single step, Trap Flag (TF) should be setQCPU automatically generates a type 1 interrupt

after executing each instruction if TF is setQType 1 ISR can be used to present the system

state to the user

Dedicated Interrupts (cont’d)

qBreakpoint InterruptQUseful in debugging QCPU generates a type 3 interrupt QGenerated by executing a special single-byte

version of int 3 instruction (opcode CCH)

Interrupt Taxonomy

q Exceptionsq Software Interruptsq Hardware Interrupts

13

Software Interrupts

qInitiated by executing an int instruction, where the interrupt number is an integer between 0 and 255

qEach interrupt can be parameterized to provide several services.Q For example, Linux interrupt service int 0x80

provides a large number of services (more than 330 system calls!)vEAX register is used to identify the required

service under int 0x80

Hardware Interrupts

q Software interrupts are synchronous events Q Caused by executing the int instruction

q Hardware interrupts are asynchronous in natureQ Typically caused by applying an electrical signal

to the processor chipq Hardware interrupts can be Q MaskableQ Non-maskable

How Are Hardware Interrupts Triggered?

q Maskable interrupt is triggered by applying an electrical signal to the INTR (INTerrupt Request) pin of PentiumQ Processor recognizes this interrupt only if IF

(interrupt enable flag) is setQ Interrupts can be masked or disabled by clearing IF

q Non-maskable interrupt is triggered by applying an electrical signal to the NMI pin of processorQ Processor always responds to this signalQ Cannot be disabled under program control

How Does the CPU Know the Interrupt Type?

qInterrupt invocation process is common to all interruptsQWhether originated in software or hardware

qFor hardware interrupts, processor initiates an interrupt acknowledge sequenceQprocessor sends out interrupt acknowledge (INTA)

signalQIn response, interrupting device places interrupt

vector on the data busQProcessor uses this number to invoke the ISR that

should service the device (as in software interrupts)

How Can More Than One Device Interrupt?

q Processor has only one INTR pin to receive interrupt signal

q Typical system has more than one device that can interrupt --- keyboard, hard disk, floppy, etc.

q Use a special chip to prioritize the interrupts and forward only one interrupt to the CPUQ 8259 Programmable Interrupt Controller chip

performs this function

Interrupt Processing

q How many interrupts can be supported?Q Up to 256 interrupts

q Interrupt number is used as an index into the Interrupt Descriptor Table (IDT)Q This table stores the addresses of all ISRsQ Each descriptor entry is 8 bytes longv Interrupt number is multiplied by 8 to get byte

offset into IDTQ Location:v Protected mode: anywhere in memory IDTR

Detailed Steps in Interrupt Processing

q Step 1: Save the current machine stateq Step 2: Load the machine state for interrupt

handlingq Step 3: Invoke the corresponding ISRq Step 4: Resume the program execution

20

Question: Why do we need to save the current machine states?

Step 1: Save the Current Machine State

q Push the EFLAGS register onto the stackq Clear interrupt enable and trap flagsQ This disables further interruptsQ Use sti to enable interrupts

q Push CS and EIP registers onto the stack

Question: Where are these states saved?

Step 2: Load the Machine State for Interrupt Handling

q Load CS with the 16-bit segment selector from the interrupt gate

q Load EIP with the 32-bit offset value from the interrupt gate

Question: How to locate and load the machine states for

interrupt handling?

Protected Mode Interrupt Processing

Organization of the IDT

IDTR

Protected Mode Interrupt Processing

q IDTR contains the memory location of IDTq IDTR is a 48-bit registerQ 32 bits for IDT base addressQ 16 bits for IDT limit valuev IDT requires only 2048 (11 bits)v A system may have smaller number of descriptorsn Set the IDT limit to indicate the size in bytes

q Two special instructions to load (lidt) and store (sidt) IDTQ Both take the address of a 6-byte memory as the

operand

Protected Mode Interrupt Processing

Interrupt descriptor

Protected Mode Interrupt Processing

Interrupt invocation

Step 3: Invoke the ISR

q ISR: Interrupt-specific service routineq Examples:Q Single-stepQ BreakpointQ TimerQ Page faultQ …

27

Step 4: Resume the Program Execution

q What is the last instruction in an ISR:Q iret

q The actions taken on iret are:Q pop the 32-bit value on top of the stack into EIPQ pop the 16-bit value on top of the stack into CSQ pop the 32-bit value on top of the stack into the

EFLAGS registerq As in procedures, make sure that your ISR does

not leave any data on the stack Q Match your push and pop operations within the ISR

An Example:

q Timer interrupt handlerQ Related files: sys/clkint.S sys/clkinit.cQ Interrupt rate – based on clock timer v ctr1000: 1ms

Q Scheduling rate: v Interrupt rate * QUANTUM

q You will be familiar with page fault handler in Lab 3!

q Others: sys/evec.c

29

Next Lecture

q Midterm Review

30