Slide 1

LECC03, 9/30/2003 Richard Kass/OSU 1 Richard Kass Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector K.E. Arms, K.K. Gan, M. Johnson, H. Kagan, R. Kass, C. Rush, A. Rahimi, S. Smith, R. Ter-Antonian, M.M. Zoeller The Ohio State University A. Ciliox, M. Holder, S. Nderitu, M. Ziolkowski Universitaet Siegen, Germany l Introduction l Results from IBM 0.25 m Prototype Chips l Results from Proton Irradiations l Summary Outline

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LECC03, 9/30/2003 Richard Kass/OSU 2 ATLAS Pixel Detector l Inner most charged particle tracking detector l Pixel size: 50 m x 400 m l ~ 100 million channels l Dosage after 10 years: middle barrel layer: 50 Mrad or 10 15 1-MeV n eq /cm 2 optical link: 30 Mrad 2 disks/end 2 layers in barrel

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LECC03, 9/30/2003 Richard Kass/OSU 3 ATLAS Pixel Opto-link VCSEL: Vertical Cavity Surface Emitting Laser diode VDC: VCSEL Driver Circuit PIN: PiN diode DORIC: Digital Optical Receiver Integrated Circuit Opto-board: this board holds the VDCs, DORICs, PINs, VCSELS use BeO as substrate for heat management

Slide 4

LECC03, 9/30/2003 Richard Kass/OSU 4 Convert LVDS input signal into single-ended signal appropriate to drive the VCSEL diode lOutput (bright) current: 0 to 20 mA, controlled by external voltage lStanding (dim) current: ~ 1 mA to improve switching speed lRise & fall times: 1 ns nominal (80 MHz signals) lDuty cycle: (50 +/- 4)% lOn voltage of VCSEL: up to 2.3 V at 20 mA for 2.5 V supply l Constant current consumption! lCurrent design uses TRUELIGHT high power oxide VCSELs VCSEL Driver Circuit Specs

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LECC03, 9/30/2003 Richard Kass/OSU 5 l Decode Bi-Phase Mark encoded (BPM) clock and command signals from PIN diode l Input signal: 40-1100 A l Extract: 40 MHz clock l Duty cycle: (50 +/- 4)% l Total timing error: < 1 ns l Common Cathode PIN array l Bit Error Rate (BER): < 10 -11 at end of life Digital Optical Receiver IC Specs 40 MHz clock command BPM l Training period: ~1 ms of 20 MHz clock (BPM with no data) Input transitions leading edges Internal delays trailing edges

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LECC03, 9/30/2003 Richard Kass/OSU 6 Status of VDC and DORIC VDC and DORIC produced using IBM 0.25 m CMOS process Migrated ATLAS SCTs VDC & DORIC design in AMS 0.8 m Bipolar to DMILL DMILL (0.8 m CMOS) process met e-specs but was not rad hard enough VDC-I5e and DORIC-I5e: our fifth IBM submission Use CADENCE program 5 layers, enclosed layout transistors and guard rings 4 channels per chip ( VDC: 1.4mm 4mm DORIC: 2.3mm 4mm) engineering run, produced enough chips for production Received chips in June 2003 Electrical measurements performed on these chips: detailed measurements of many parameters: rise/fall time, duty cycle, bright/dim current VDC-I5e and DORIC-I5e are acceptable for use in pixel detector Need to certify that these chips are radiation hard previous VDC and DORIC version (I4) rad hard to > 50Mrad detailed plan to certify radiation hardness

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LECC03, 9/30/2003 Richard Kass/OSU 7 DORIC and VDC Layout Input Pads: Signal_in GndA Noise_in VddAmp VddA Preamp / Digital Test Pads Analog / Digital Bias, Resets Ch 1 Ch 2 Ch 3 Ch 4 Ch 1 Ch 2 Ch 3 Ch 4 DORIC-I5 ( 2.3 x 4mm) VDC-I5 ( 1.4 x 4mm)

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LECC03, 9/30/2003 Richard Kass/OSU 8 VDC-I5e Measurements Eight VDCI5e chips with four channels per chip were measured VDCI5e duty cycle bright dim Spec is 504%

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LECC03, 9/30/2003 Richard Kass/OSU 9 VDC-I5e Rise and Fall Times rise time fall time spec is