Lecture 1 Designing CMOS gates

Lecture outline

• CMOS design overview

• Skills developed and knowledge gained from the course • Tool handling skills: Cadence Electronic Design Automation (EDA) • Theoretical insights – estimations with pencil and paper

• The design flow – textbook MIPS example

• CMOS Fabrication

• Designing CMOS logic gates using MOSFET switches

• Iterative Logic Arrays (ILAs)

• Adder designs – custom design vs. synthesis from VHDL

• Summary

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Design flow

Simulation

Extraction

DRC

Schematic

Layout

LVS

Post Lay Mod

DRC = Design Rule Checker

LVS = Layout Versus Schematic

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Gajski Y-chart

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Block Diagram (Textbook MIPS example)

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Floor planning

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MIPS Layout

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Datapath layout

Bitslice 7

Bitslice 6

Bitslice 5

Bitslice 4

Bitslice 3

Bitslice 2

Bitslice 1

Flo

p w

ord

slic

e

add

er w

ord

slic

e

mu

x w

ord

slic

e

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Custom design vs. synthesis from VHDL • 8-bit implementations of MIPS from Patterson & Hennessy

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Standard cells, 130 nm CMOS, 7 metal layers Custom design, 0.6 um CMOS, 1.5x1.5 mm die

Example: synthesized 32-bit ALU layout

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CMOS Fabrication

• CMOS transistors are fabricated on silicon wafer

• Lithography process similar to printing press

• On each step, different materials are deposited or etched

• Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

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Inverter Cross-section

• Typically use p-type substrate for nMOS transistors

• Requires n-well for body of pMOS transistors

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n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

Well and substrate taps

• Substrate must be tied to GND and n-well to VDD

• Metal to lightly-doped semiconductor forms poor connection called Shottky Diode

• Use heavily doped well and substrate contacts/taps

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n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tapwell

tap

n+ p+

Inverter Mask Set

• Transistors and wires are defined by masks

• Cross-section taken along dashed line

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GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor

Inverter mask set and fabrication

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P-type silicon substrate

N-well

Active areas P+ select

Poly gate

Contact cuts

Metal wires

Fabrication

• Chips are built in huge factories called fabs

• Contain clean rooms as large as football fields

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Courtesy of IBM Corporation. Unauthorized use not permitted.

Back to the Y-chart

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Transistors

Designing gates with switches

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N-switch

A A

P-switch

A A

nMOSFET pMOSFET

ON when input A is HIGH ON when input A is LOW

Designing gates with switches

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N-switch

A A

P-switch

A A

nMOSFET pMOSFET

ON when input A is HIGH OFF when input A is HIGH

Designing gates with switches

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N-switch

A A

P-switch

A A

nMOSFET pMOSFET

OFF when input A is LOW ON when input A is LOW

Designing gates: AOI22

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Inputs: A, B, C, D

pMOS pull-up

network

nMOS pull-down network

VDD

VSS

Y

Y = AB + CD

&

&

≥1

AB

C D

Y = AB + CD

Designing gates: AOI22

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Y = AB + CDB

A

D

C

pMOS pull-up

network

Inputs: A, B, C, D

VDD

VSS

Y

&

&

≥1

AB

C D

Designing gates: AOI22

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B

A

D

C

pMOS pull-up

network

Inputs: A, B, C, D

VDD

VSS

Y

According to de Morgan´s theorem

Y = AB + CD

Y = A + B C + D

&

&

≥1

AB

C D

Designing gates: AOI22

Y = A + B C + D

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B

A

D

C

A

C

B

D

VDD

VSS

Y

Y = AB + CD

&

&

≥1

AB

C D

Designing gates: AOI22

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B

A

D

C

A

C

B

D

VDD

VSS

Y

Y = AB + CD

Y = A + B C + D

&

&

≥1

AB

C D

Simple CMOS gates

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Y A B A B Y AB A B

Exercise: AOI31, OAI22

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End of CMOS design lecture!

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Q & A?