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Lecture 11 Memory Design. Prith Banerjee ECE C03 Advanced Digital Design Spring 1998. Outline. Random Access Memories (RAMS) Static RAMs Dynamic RAMS Memory Organizations Read-Only Memories (ROMS) READING: Katz 7.6, 4.2.5. Memory. Need method for storing large amounts of data - PowerPoint PPT Presentation
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ECE C03 Lecture 11 1
Lecture 11Memory Design
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
ECE C03 Lecture 11 2
Outline
• Random Access Memories (RAMS)• Static RAMs• Dynamic RAMS• Memory Organizations• Read-Only Memories (ROMS)• READING: Katz 7.6, 4.2.5
ECE C03 Lecture 11 3
Memory• Need method for storing large amounts of data
– Computer programs, data, pictures, etc.
• RAM: Random Access Memory, Read/Write• ROM: Read-only Memory
Address Data000000 00111110000001 01101011000010 01011101000011 01100011000100 00111110000101 00000000000110 11111111000111 01010101001000 10101010001001 00100001001010 11011010
64x8 RAM
A3 D7A2 D6A1 D5A0 D4 D3 D2 D1Write D0
ECE C03 Lecture 11 4
8x4 RAM
Address Data
000
001
010
011
100
101
110
111
A2A1A0
Out3 Out2 Out1 Out0
ECE C03 Lecture 11 5
8x4 RAM
000
001
010
011
100
101
110
111
3:8Decoder
Enable
S2 S1 S0
A2A1A0
In3 In2 In1 In0
Out3 Out2 Out1 Out0
Write
ECE C03 Lecture 11 6
RAM Cell
• Requirements:– Store one bit of data
– Change data based on input when row is selected
S QR
Input
Row Select
ECE C03 Lecture 11 7
Static Random Access MemoriesTransistor efficient methods for implementing storage elements
Small RAM: 256 words by 4-bit
Large RAM: 4 million words by 1-bit
We will discuss a 1024 x 4 organization
Data Data
Word Enablei
j j
Static RAM Cell
Static RAM CellStatic RAM Cell
Words = Rows
Columns = Bits (Double Rail Encoded)
ECE C03 Lecture 11 8
Static RAM Organization
Chip Select Line (active lo)
Write Enable Line (active lo)
10 Address Lines
4 Bidirectional Data Lines
1024 x 4 SRAM
A0A1A2A3A4A5A6A7A8A9WECS
IO0IO1IO2IO3
ECE C03 Lecture 11 9
RAM OrganizationLong thin layouts are not the best organization for a RAM
Address Buffers
Row Decoders
A9
A8
A7
A6
A5
A4
Storage ArrayStorage Matrix
64 x 16 64 x 16 64 x 16 64 x 16
Sense Amplifiers
Address Buffers
Column Decoders
A3
A2
A1
A0
Data BuffersCS
WE
I/O0 I/O1 I/O2 I/O3
64 x 64SquareArray
Amplifers &Mux/Demux
Some Addrbits select
row
Some Addrbits selectwithin row
ECE C03 Lecture 11 10
RAM Timing
Simplified Read Timing
Simplified Write Timing
WE
CS
Address
Data Out Data Out
V alid Address
Access T ime
Input Data
V alid Address
Data In
Address
WE
CS
Memory Cycle T ime
ECE C03 Lecture 11 11
Dynamic Random Access Memories
Word Line
Bit Line
1 Transistor (+ capacitor) memory element
Read: Assert Word Line, Sense Bit Line
Write: Drive Bit Line, Assert Word Line
Destructive Read-Out
Need for Refresh Cycles: storage decay in ms
Internal circuits read word and write back
ECE C03 Lecture 11 12
DRAM Organization
Row Decoders
Storage Matrix
64 x 64
Column Latches, Multiplexers/Demultiplexers
Control Logic
A11
WE
. . .
A0
RAS
CAS
DIN
Row AddressColumn Address & Control Signals
DOUT
Long rows to simplify refresh
Two new signals: RAS, CAS
Row Address Strobe
Column Address Strobe
replace Chip Select
ECE C03 Lecture 11 13
RAM AddressingEven to read 1 bit, an entire 64-bit row is read!
Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits!
Address RAS CAS Dout Valid
Col AddressRow Address
Read Cycle
Read RowRow Address Latched
Read Bit Within RowColumn Address Latched
Tri-stateOutputs
ECE C03 Lecture 11 14
RAM Write TimingAddress RAS CAS WE Din Valid
Col AddressRow Address
(1) Latch Row Address Read Row
(2) WE low
(3) CAS low: replace data bit
(4) RAS high: write back the modified row
(5) CAS high to complete the memory cycle
ECE C03 Lecture 11 15
DRAM RefreshRefresh Frequency:
4096 word RAM -- refresh each word once every 4 ms
Assume 120ns memory access cycle
This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)!
But RAM is really organized into 64 rows
This is one refresh cycle every 62.5 µs (1 in 500 DRAM accesses)
Large capacity DRAMs have 256 rows, refresh once every 16 µs
RAS-only Refresh (RAS cycling, no CAS cycling)
External controller remembers last refreshed row
Some memory chips maintain refresh row pointer
CAS before RAS refresh: if CAS goes low before RAS, then refresh
ECE C03 Lecture 11 16
Variations of DRAMsPage Mode DRAM:
read/write bit within last accessed row without RAS cycle
RAS, CAS, CAS, . . ., CAS, RAS, CAS, ...
New column address for each CAS cycle
Static Column DRAM:
like page mode, except address bit changes signal new cyclesrather than CAS cycling
on writes, deselect chip or CAS while address lines are changing
Nibble Mode DRAM:
like page mode, except that CAS cycling implies next columnaddress in sequence -- no need to specify column address afterfirst CAS
Works for 4 bits at a time (hence "nibble")RAS, CAS, CAS, CAS, CAS, RAS, CAS, CAS, CAS, CAS, . . .
ECE C03 Lecture 11 17
RAM Expansion
• Implement a big RAM from multiple small RAMSD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Address
0000000
0010000
0100000
0110000
1000000
1010000
1100000
1110000
ECE C03 Lecture 11 18
RAM Expansion (cont)
• Build a 16x16 RAM from 16x4 RAMs
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
ECE C03 Lecture 11 19
RAM Expansion (cont)
• Build a 32x16 RAM from 16x4 RAMs
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
16x4 RAMA3 DinA2 A1 DoutA0
Write
ECE C03 Lecture 11 20
Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
Dec
0 n-1
Address
2 -1n
0
+5V +5V +5V +5V
Word Line 0011 Word Line 1010
Bit Lines
j
i
Internal Organization
This is another class of memory, which is read only, cannot write.
ECE C03 Lecture 11 21
ROMs vs PLAs
Not unlike a PLAstructure with afully decoded
AND array!
Not unlike a PLAstructure with afully decoded
AND array!
ROM vs. PLA:ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions
PAL problem: constrained fan-ins on OR planes
Memory array
2 n words by m bits
m output lines
n address lines
Decoder 2 n word lines
ECE C03 Lecture 11 22
Read-Only Memories2764 EPROM
8K x 8
16K x 16 Subsystem
2764
A0A1A2A3A4A5A6A7A8A9
O0O1O2O3O4O5O6O7
OECS
PGMVPP
A10A11A12
A0A1A2A3A4A5A6A7A8A9
O0O1O2O3O4O5O6O7
OECS
PGMVPP
A10A11A12
++2764
A0A1A2A3A4A5A6A7A8A9
O0O1O2O3O4O5O6O7
OECS
PGMVPP
A10A11A12
2764
A0A1A2A3A4A5A6A7A8A9
O0O1O2O3O4O5O6O7
OECS
PGMVPP
A10A11A12
2764
A0A1A2A3A4A5A6A7A8A9
O0O1O2O3O4O5O6O7
OECS
PGMVPP
A10A11A12
2764
A0A1A2A3A4A5A6A7A8A9
O0O1O2O3O4O5O6O7
OECS
PGMVPP
A10A11A12
+ +
A13/OE
A12:A0
D7:D0D15:D8
U3 U2
U1 U0
ECE C03 Lecture 11 23
Implementing Logic with ROMs
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
address outputs
ROM 8 w ords ¥
4 bits
A B C F 0 F 1 F 2 F 3
B 0 0 1 1 0 0 1 1
Address W ord Contents A 0 0 0 0 1 1 1 1
C 0 1 0 1 0 1 0 1
F 0 0 1 0 0 1 1 0 0
F 1 0 1 1 0 0 0 0 1
F 2 1 1 0 0 1 0 0 0
F 3 0 0 0 1 1 0 1 0
by
ECE C03 Lecture 11 24
Summary
• Random Access Memories (RAMS)• Static RAMs• Dynamic RAMS• Memory Organizations• Read-Only Memories (ROMS)• NEXT LECTURE: Finite State Machine Design• READING: Katz 8.1, 8.2, 8.4, 8.5, Dewey 9.1, 9.2