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EE 505
Lecture 14
String DACs
Current Steering DACs
DAC Performance Issues and Concerns
Glitch
Glitch
Incomplete Settling
Ringing
Review from Last Lecture
DAC Performance Issues and Concerns
IdealComplete
Linear Settling
Incomplete
Linear Settling
Complete Nonlinear
Settling
Incomplete
Nonlinear Settling Complete with glitch Incomplete with
glitchIncomplete with big
glitch
Review from Last Lecture
Switch Assignment
R
S1
R
S2
R
SN-2
R
SN-1
R
SN
VRFF
VOUT
n
XINChallenges:
n-channel region
p-channel region
Review from Last Lecture
Switch Parasitics
G DS
CBS
CGSOL CGDOL
CBD
CGB when offCGC when onφ
G DS
CBS
CGSOL
CGB when offCGC when on
CGDOL
CBD
CWELLSSUB
φ
• CBD and CBS can be significant and cause rise-fall times to be position dependent
• CGDOL can cause “kickback” or feed-forward
• CGS can slow turn-on and turn-off time of switch
Review from Last Lecture
R-String DAC
R
M1
R
M2
R
MN-2
R
MN-1
R
MN
VRFF
VOUT
n
XIN
Binary to
Thermometer
Decoder
2n
d1
d2
dN-2
dN-1
dN
CL
Capacitive loading due to switches
Review from Last Lecture
R-String DAC
Previous-Code Dependent Settling• Assume all C’s (except those on the R-string) were initially at 0V
• Red denotes V3, green denotes V6, black denotes 0V, Purple some other voltage
• Some capacitors may retain values from a previous input for many clock cycles
for some inputs resulting I previous-previous dependence of even longer
Transition from <010> to <101>
b3 b3 b2 b2 b1 b1
R-String
VREF
XIN
n
Decoder
VOUT
Tree Decoder
< 1 0 1 >
Example:
V3
V6
White boxes show capacitors dependent
upon previous code <010>
Review from Last Lecture
R-String DAC
Tree-Decoder in Digital Domain
b3 b3 b2 b2 b1 b1
Decoder
Tree Decoder
VDDVOUT
Do the resistors that form part of PTL dissipate any substantial power?
No because only one will be conducting for any DAC output
Single transistor used at each marked intersection for PTL AND gates
Dramatic reduction in capacitive loading at output
Will become more complicated if both p-channel and n-channel switches needed
Review from Last Lecture
R-String DAC
RF RF RF RF
RFRFRF RF
VREF
RF RF RF RF
RFRFRF RF
RF RF RF RF
RFRFRF RF
RF RF RF RF
RFRFRF RF
n1
XIN
n2
n
1 2n = n :n
Ro
w D
eco
de
r
VOUT
Column Decoder
String DAC with Row-Column Decoder
• Dramatic reduction in decoder
complexity
• Dramatic reduction of capacitive
loading on output
• Changes decoder from a one-
dimensional to a two-dimensional
solution (can be thought of as folding)
• Logic gates could be placed at each
node to eliminate analog row decoder
Challenges (most were present in earlier structures too)
• Some previous code dependence
• INL large
• Difficult to cancel gradient effects in layout
Switching sequencing can help a lot
• Switch impedances code dependent
• Settling times code dependent
R-String DAC
RF RF RF RF
RFRFRF RF
VREF
RF RF RF RF
RFRFRF RF
RF RF RF RF
RFRFRF RF
RF RF RF RF
RFRFRF RF
n1
XIN
n2
n
1 2n = n :n
Ro
w D
eco
de
r
VOUT
Column Decoder
Can this concept be extended further?
• Dramatic reduction in decoder
complexity
• Dramatic reduction of capacitive
loading on output
• Changes decoder from a one-
dimensional to a m-dimensional
solution (folding)
• Logic gates could be placed at each
node to eliminate analog row decoder
R-String DAC
What about this parallel R-string?
R
S1
R
S2
R
SN-2
R
SN-1
R
SN
VRFF
VOUT
n
XIN
R1
R1
Added two resistors tapped at middle
of original R-string
R-String DAC
What about this parallel R-string?
Added six resistors tapped at
middle of original R-string
S1
S2
R
SN-2
R
SN-1
R
SN
VRFF
VOUT
n
XIN
R2
R2
R1
R1
R1
R1
R
R RRR
R RRR
R RRR
R RRR
R RRR
R RRR
R RRR
R-String DAC
VOUT
n
2
n
2
MS
B R
ow
De
co
de
r
n1
n2LSB Analog MUX
VREF
R-String DAC
Note Dual Ladder is used !
RC
RF RF RF RF
RFRFRF RF
VREF
RC
RF RF RF RF
RFRFRF RF
RC
RF RF RF RF
RFRFRF RF
RC
RF RF RF RF
RFRFRF RF
n1
XIN
n2
n
1 2n = n :n
Column Decoder
Ro
w
De
cod
er
VOUT
R-String DAC
Note Dual Ladder is used !
32x32 Matrix
RC
RF RF RF RF
RFRFRF RF
VREF
RC
RF RF RF RF
RFRFRF RF
RC
RF RF RF RF
RFRFRF RF
RC
RF RF RF RF
RFRFRF RF
n1
XIN
n2
n
1 2n = n :n
Column Decoder
Ro
w
De
cod
er
VOUT
: AND pixel sensor gate
Cited by 51 (4/5/10)
Cited by 94 (4/6/14)
Cited by 109 (4/5/16)
Cited by 133 (3/8/21)
Pelgrom Paper Assessment
Pelgrom Paper Assessment
Pelgrom Paper Assessment
Pelgrom Paper Assessment
Pelgrom Paper Assessment
Pelgrom Paper Assessment
AB
R1_1
R1_2
R1_3
R1_4
R1_6
R1_5
R1_8
R1_7
R2_1
R2_2
R2_3
R2_4
R2_8
R2_7
R2_6
R2_5
AB
Common-Centroid Anti-Parallel Ladder Layout
Common-Centroid Anti-Parallel Ladder Layout
A
AB
B
R1_1
R2_1
R1_2
R1_3
R1_4
R1_6
R1_5
R1_8 R1_9
R1_10
R1_11
R1_12
R1_7
R2_2
R2_3
R2_4
R2_8
R2_7
R2_6
R2_5
R2_9
R2_10
R2_11
R2_12
Interconnects Not Shown
Pelgrom Paper Assessment
Pelgrom Paper Assessment
R-String DAC String DAC with Row-Column Decoder
• Dramatic reduction in decoder
complexity
• Dramatic reduction of capacitive
loading on output
• Changes decoder from a one-
dimensional to a two-dimensional
solution (can be thought of as folding)
• Logic gates could be placed at each
node to eliminate analog row decoder
Challenges (most were present in earlier structures too)
• Some previous code dependence
• INL large
• Difficult to cancel gradient effects in layout
Switching sequencing can help a lot
• Switch impedances code dependent
• Settling times code dependent
RF RF RF RF
RFRFRF RF
VREF
RF RF RF RF
RFRFRF RF
RF RF RF RF
RFRFRF RF
RF RF RF RF
RFRFRF RF
n1
XIN
n2
n
1 2n = n :n
Ro
w
De
cod
er
VOUT
Column Decoder
n1 n2
R-String DAC
R
R
R
R
VRFFn1
XIN
S1
S2
S3
RF
SN2
n2
n
1 2n = n :n
Sck
Sck
Sc1
R
Sc1
Sc2
Sc2
Sc3
Sc3
ScN1
ScN1
RF
RF
RF
RF
SN2-1
VOUT
Interpolator
Fine String Interpolator
R-String DAC
R
R
R
R
VRFFn1
XIN
S1
S2
S3
RF
SN2
VOUT
n2
n
1 2n = n :n
Sck
Sc(k-1)
Sc1
R
Sc2
Sc4
Sc3
ScN1
Sc(N1-1)
RF
RF
RF
RF
SN2-1
SN2+1
Sometimes termed sub-divider,
sub-range or dual-string DAC
Fine String Interpolator
R-String DAC
R
R
R
R
VRFF n1
XIN
S1
S2
S3
RF
SN2
VOUT
n2
n
1 2n = n :n
Sck
Sc(k-1)
Sc1
R
Sc2
Sc4
Sc3
ScN1
Sc(N1-1)
RF
RF
RF
RF
SN2-1
SN2+1
Buffered Fine String Interpolator
R-String DAC
R
R
R
VRFFn1
XIN
S1
S2
S3
RF
SN2
n2
n
1 2n = n :n
Sck
Sc1
R
Sc1
Sc2
Sc2
ScN1
ScN1
RF
RF
RF
SN2-1
VOUT
Sck
N2RF
N2RF
N2RF
N2RF Interpolator
Compensated Fine String Interpolator
2
2 2nN
Paralleling each R will be either the
interpolator or a resistor of value
N2RF
Area of N2RF resistors may be very
small
Tap voltages on coarse R-string should
not change with XIN
R-String DAC
R
R
R
VRFFn1
XIN
S1
S2
S3
RF
SN2
n2
n
1 2n = n :n
Sck
Sc1
R
Sc1
Sc2
Sc2
ScN1
ScN1
RF
RF
RF
SN2-1
VOUT
Sck
InterpolatorIINT
IINT
VDD
Compensated Fine String Interpolator
Current Sources have same
dc current as interpolator
Stay Safe and Stay Healthy !
End of Lecture 14
