Lecture 14 Memory Interfacelast

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Lecture XIV 8086 Memory

Interface

Wisam I Hasan


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Objectives:

Upon completion you will be able to:1. How to interface a memory device with p

2. How to access memory in READ or WRITE

3. Describe memory structure with all its type:

RAM, EPROM etc

4. Memory requirements

5. Address Decoding types

6. Interfacing examples


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Memory Structure and its requirements

As mentioned earlier,read/write memoriesconsist of an array ofregisters, in whicheach register has

unique address The size of the

memory is N x M asshown below where Nis the number of

registers and M is theword length, in numberof bits1

Input

data

A10

A0

WR

Input Buffer

R/W

Memory

2048 x 8

Output Buffer

Output

data

InternalDe

coder

RD

CS

Logic Diagram for RAM


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Example 1

If memory is having 12 address lines and 8data lines, then Number of registers/

memory locations (capacity) = 2N= 212

= 4096

Word length = M bit

= 8 bit

Example 2: if memory has 8192 memorylocations, then it has 13 address lines.

(How?)


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Table 14.1 summarizes capacity with

addressAddress lines

requiredMemory Capacity

101k = 1024 memory locations








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EPROM layout

A11

EPROM

4096 x 8

Output Buffer

InternalDe

coder

A0

Output

data

RD

CS

Shows the logicdiagram of typicalEPROM (ErasableProgrammableRead-Only Memory)

with 4096 (4k)registers

It has 12 addresslines (A0-A11), one

chip select (CS), oneRead control signal.

No WR signal, why?


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Basic Memory Interfacing with 8085

For interfacing memory devices to p 8085, keepthe following points in your mind:

p 8085 can access 64KB memory since addressbus is 16-bit.1

Generally EPROM (or EPROMs) is used as aprogram memory and RAM (or RAMs) as datamemory.2

The capacity of program memory and datamemory depends on the application.

Is is not always necessary to select 1 EPROMand 1 RAM. We can have multiple EPROMs andmultiple RAMs as per the rquirement ofapplication


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For Example

We have to implement 32 KB of program memory and 4KBEPROMs are available. In this case we can connect 8EPROMs in parallel.1

We can place EPROM/RAM anywhere in full 64 KB addressspace. But program memory (EPROM) should be located fromaddress 0000 H.2

It is not always necessary to locate EPROM and RAM inconsecutive memory address.3

The memory interfacing requires to:

Select the chip

Identify the register

Enable the appropriate buffer. p system includes memory and I/O devices.

It is important to note that p can communicate (read/write) withonly one device at a time, so address decoding needed.


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Address Decoding techniques

There are two main techniques:

Absolute decoding/ Full Decoding

Linear decoding / Partial Decoding

Absolute Decoding:

All the higher address lines are decoded to select the

memory chip, and the memory chip is selected only for

the specified logic level on these high-order address,

no other logic levels can select the chip.

The following figure shows the memory interface with

absolute decoding. This addressing technique is

normally used in large memory systems.


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Absolute Decoding Technique


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Memory map


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Linear Decoding

In small systems, h/w for the decoding logic canbe eliminated by using individual high-order

address lines to select memory chips.

This is referred to as linear decoding.

The figure below shows the addressing of RAM

with linear decoding technique.

This technique is also called partial decoding.

It reduces the cost of the decoding cct., but ithas a drawback of multiple address (shadow

addresses)


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Continued


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What about memory map?


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Interfacing example1:

Design memory system for 8085 p such that it should contain 8KB of EPROM and 8 KB of RAM.

Sol: the figure below shows the desired memory system using IC2764 (8K) EPROM and 6264 (8k) RAM. Memory requires 13address lines (A0-A12)1.

The remaining address lines (A13-A15) are decoded to generatechip select (CS) signals.

IC 74SL138 is used as decoder, when (A13-A15) address linesare 0 the Y0 output of decoder goes low and select the EPROM.other line to select the particular memory location.

When these lines are 001, the Y1 output of decoder goes lowand selects the RAM.


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Memory system


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Memory map


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Example 2

Design a p system for8085 such that it shouldcontain 16 KB of EPROM and 4 KB of RAM usingtwo 8 KB EPROMs (2764) and 2 KB RAMs (6116).

Sol: the following figure shows the desired memory

system using two (8K x 8) EPROM and two (2K x 8)RAMs.

EPROM memory is 8K, so it requires 13 addresslines (A12-A0) whereas RAM memory is 2K, so it

requires 11 address lines (A10-A0). The remainingaddress lines (A15-13) are used to generate chip-select (CS) signals. Also the memory map is shown


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Memory system solution


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Memory map


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Example 3:

Interface 2 KB RAM to 8085 using 2114 (1k x 4)chips, 74LS138 decoder and full address decodingand give the address map.

Sol: 2114 RAM is 1K x 4 i.e. it has 1K (1024)

memory locations, each of which is 4 bits. 8085 isan 8 bit processor. To interface byte RAM, werequire two nibble wide RAMs, connected togetherto form byte wide RAM.

To form 2K x 8 RAM we require two sets of 1Kx4 +

1Kx4 RAM chips. so in all we require four 1K x 4 RAM chips. the

figures below shows both the interface and map.


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Memory System using 2114 (1K x 4) chips


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Memory Map

AddressA0A1A9A14A15Mem IC

0000H00000000000000SA RAM1

03FFH11111111100000EA RAM1

0000H00000000000000SA RAM2

03FFH11111111100000EA RAM2

2000H00000000000100SA RAM3

23FFH11111111100100EA RAM3

2000H00000000000100SA RAM4

23FFH11111111100100EA RAM4


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Example 4

Design a p system for8085 p such that it shouldcontain 2 KB of EPROM and 2 KB of RAM withstarting address 0000H & 6000H.

Sol: the figure below shows the desired memory

system using 2 KB EPROM and 2 KB RAM. Bothare 2 KB so they need 11 lines (A0-A10) and theremaining higher addresses ( A15-A11) is used togenerate the chip select (CS).

Since EPROM starts from 0000H and RAM from6000H; EPROM selected when all higher address =0000 and RAM selected when ( A15-A11) =01100 B


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Memory system using 2K EPROM & RAM


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Memory map


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Decoding type comparison

Partial AddressDecoding

Full Address Decoding

Few higher address lines

are decoded

All higher lines are

decoded

H/W design is less oreliminated

More H/W is required

Less costHigher cost

It has multiple address

(shadow address)

No multiple addresses

Used in small systemUsed in large system


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Memory interface requirements

Select the chip Identify the register

Enable the appropriate buffer.

p system includes memory and I/O devices

p can communicate with only one device1

So decoding needed to communicate with memoryand I/O

So each device can be accessed independently.

Three type of decoding: Absolute

Linear

block


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Absolute decoding

The memory chip is selected only for the specifiedlogic level on address lines; no other logic level canselect the chip as shown below.

Two 8K EPROMs (2764) are used to provide even

and odd memory banks (16 bits). Control signals BHE and A0 are used to enable O/P

of odd and even memory banks.

13 address lines are required to address 8Klocations.(A1-A13)

All remaining address lines (A14-A19) to generatechip select

This technique is used in large memory system.


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Absolute addressing


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Linear Decoding (Partial Decoding)

In small system, H/W can be eliminated by using the

required addressing lines1.

The figure below shows the addressing of 16K RAM

(6264) with linear decoding BHE & A0 are used to enable odd & even banks.

A19 is used to select the RAM2.

A14 to A18 are not affect the chip selection

This method reduces cost

But it gives multiple (shadow) addresses


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Linear Decoding


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Block Decoding

In a p system the memory array is often

consists of several blocks of memory chips

Each block of memory requires decoding cct.

To avoid separate decoding for each memory

block special decoder IC is used to generate

chip select signal for each block.

The figure below shows the block decodingusing IC 74138 => 3:8 decoder


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Block Decoding


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Example 1: Design an 8086 based system with the following

specifications: 8086 in minimum mode

64 KB EPROM

64 KB RAM

Draw the complete schematic of the design

indicating address map. Sol: 8086 is 16 bit p so it is necessary to have odd

and even memory banks.

Two 32 KB EPROMs and two 32 KB RAMs1

For 32 KB RAM & EPROM need 15 address lines(A1-A15)

A0 & BHE are used to select even and odd banks


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Memory Map


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Interfacing 64 K RAM & 64 K EPROM


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Static RAM (SRAM)

Static RAM retains data as long as power is on

No action needed to retain data except power so that it is calledStatic1

The main difference between RAM and ROM; is that ROM writesunder special condition outside computer?

SRAM stores data and used for small memory amount (1 MBand less)

Slowest version has access time = 250 ns (fast enough toconnect to 8086)

62256 32K x 8 SRAM packaged in 28 pin has 120 or 150 nsaccess time

Other common SRAM are available in 8Kx8 and 128Kx8

10ns and less SRAM access time is used as cache memory


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4016 SRAM


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Dynamic RAM interface

DRAM needs refreshing after every 2 ms or 4ms

On the other hand, DRAM contains more memorycells as compared to SRAM per unit area.

DRAM is available in much larger sizes upto 16Mx1.

Let us see the pin configuration for a typical 64 K x 4DRAM (TMS4464).

To address 64 K we require 16 address lines.

But in DRAM the addresses is given in two phases

The low address is multiplexed with high address


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TMS4464 Pin

Has 8 address lines(A0-A7)

CAS (Column Address Strobe) islow CA

RAS (Row Address Strobe) is lowRA

Two phase A0-A7 placed onaddress bus and strobed byasserting RAS then A8-A15 withCAS


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Continued

16 bit address get latchedinto two internal 8-bit latch

The internally latched 16-bit access the content of

one of the 4-bit memorylocations.

Fig here shows the cct ofmultiplexing A0-A7 and A8-A15 address lines.RAS is

used to strobe row addressinto DRAM at low andcolumn address when itshigh


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DRAM controller

In most system, a DRAM controller integrated cct. Is used to doaddress multiplexing and the generation of DRAM controlsignals.

82C08 can control up to 1 MB of memory for 8086

It contains an address multiplexer that multiplexes an 18-bit

address onto 9 address connections. See fig below: AL0-AL8 & AH0-AH8 are the address inputs for

the controller and AQ0-AQ8 are the output

82C08 has internal cct. Which generates the CAS and RASsignals for the DRAM. (using CLK, S1, and S0)

Processor provides S1 and S0 signals as RD &WR inputs to

controller. The AACK/XACK signal of 82C08 is an acknowledge output that

is used to indicate the ready condition for p

This signal is connected to the READY input or clk-gtor READY


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Pin diagram of 82C08 DRAM controller


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Example:

Draw the interface of 1 MB DRAM to the 8086 withthe help of DRAM controller.

As DRAM controller accepts 18 address lines it canaddress up to 256 K memory locations.

So for 1 MB DRAM we should use a series of four256 K x 8 bit DRAM modules

The PAL 16L8 is used to generate bank selectsignals and other as shown in fig below

The A19 signal selects the upper bank or the lowerbank through the BS (Bank Select) input to the82C08 DRAM controller.


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The interface of 1 MB DRAM for 8086

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Lecture 14 Memory Interfacelast