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ECE 301 – Digital Electronics
Sequential Logic Circuits:
FSM Design
(Lecture #18)
ECE 301 - Digital Electronics 2
FSM Design: Procedure• Understand specifications
• Derive state diagram
• Create state table
• Perform state minimization (if necessary)
• Encode states (state assignment)
• Create state-assigned table
• Select type of Flip-Flop to use
• Determine Flip-Flop input equations and FSM output equation(s)
• Draw logic diagram
ECE 301 - Digital Electronics 3
Moore Machines
FSM Design
ECE 301 - Digital Electronics 4
Example:
Design a FSM that detects a sequence of three or more consecutive ones on an input bit stream.
The FSM should output a 1 when the sequence is detected, and a 0 otherwise.
A circuit that detects the occurrence of a particular pattern on its input is referred to as a sequence detector.
FSM Design (Moore)
ECE 301 - Digital Electronics 5
FSM Design: Example (Moore)
Input: 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 …
Output: 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 …
ECE 301 - Digital Electronics 6
FSM Design: Example (Moore)
StateDiagram
ECE 301 - Digital Electronics 7
FSM Design: Example (Moore)
QA
QB
QA+ Q
B+
State Table
ECE 301 - Digital Electronics 8
FSM Design: Example (Moore)
The choice of Flip-Flop determines the complexity of the combinational logic required in the design of the state machine.
Each type of Flip-Flop has a unique characteristic equation.
SR Flip-Flop
Q+ = S + R'.Q
D Flip-Flop
Q+ = D
JK Flip-Flop
Q+ = J.Q' + K'.Q
T Flip-Flop
Q+ = T '.Q + T.Q'
ECE 301 - Digital Electronics 9
Synthesis using D Flip-Flops
(Q+ = D)
FSM Design (Moore)
ECE 301 - Digital Electronics 10
FSM Design: Example (Moore)
Flip-Flop Input
DA D
B
Q+ = Dnext state flip-flop input
QA
QB
QA+ Q
B+
ECE 301 - Digital Electronics 11
FSM Design: Example (Moore)
ECE 301 - Digital Electronics 12
FSM Design: Example (Moore)
QA
QB
Q'B
ECE 301 - Digital Electronics 13
Synthesis using JK Flip-Flops
(Q+ = J.Q' + K'.Q)
FSM Design (Moore)
ECE 301 - Digital Electronics 14
FSM Design: Example (Moore)
+
Excitation Table
ECE 301 - Digital Electronics 15
FSM Design: Example (Moore)
Q+ = J.Q' + K'.Qnext state flip-flop inputs
QA
QB
QA+ Q
B+
ECE 301 - Digital Electronics 16
FSM Design: Example (Moore)
ECE 301 - Digital Electronics 17
FSM Design: Example (Moore)
QA
QB
Q'B
Q'A
ECE 301 - Digital Electronics 18
Example:
Design a Finite State Machine (FSM) that meets the following specifications:
This is another example of a sequence detector.
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of the clock.
3. The output z is equal to 1 if the pattern 101 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should not be detected.
FSM Design (Moore)
ECE 301 - Digital Electronics 19
FSM Design: Example (Moore)
Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 …
Output (z): 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 …
ECE 301 - Digital Electronics 20
FSM Design: Example (Moore)Start State
End State
StateDiagram
ECE 301 - Digital Electronics 21
Example:
Design a Finite State Machine (FSM) that meets the following specifications:
This is another example of a sequence detector.
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of the clock.
3. The output z is equal to 1 if the pattern 101 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
FSM Design (Moore)
ECE 301 - Digital Electronics 22
FSM Design: Example (Moore)
Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 …
Output (z): 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 …
ECE 301 - Digital Electronics 23
FSM Design: Example (Moore)Start State
End State
StateDiagram
ECE 301 - Digital Electronics 24
Example:
Design a Finite State Machine (FSM) that meets the following specifications:
This is example of a sequence detector that can detect 2 sequences.
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of the clock.
3. The output z is equal to 1 if the pattern 110 or the pattern 010 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
FSM Design (Moore)
ECE 301 - Digital Electronics 25
FSM Design: Example (Moore)
Input (w): 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 …
Output (z): 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 …
ECE 301 - Digital Electronics 26
FSM Design: Example (Moore)
StateDiagram
ECE 301 - Digital Electronics 27
Acknowledgments
The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for
Digital Design (4th Edition).
They are the property of and are copyrighted by Pearson Education.