Lecture 23 OUTLINE The MOSFET (cont’d) Source/drain structure CMOS fabrication process The CMOS power crisis Reading: Pierret 19.2; Hu 6.10 Optional Reading:

Lecture 23

OUTLINE

The MOSFET (cont’d) • Source/drain structure• CMOS fabrication process• The CMOS power crisis

Reading: Pierret 19.2; Hu 6.10Optional Reading: Pierret 4; Hu 3

Source and Drain (S/D) Structure• To minimize the short channel effect and DIBL, we want

shallow (small rj) S/D regions but the parasitic resistance of these regions increases when rj is reduced.

where = resistivity of the S/D regions

• Shallow S/D “extensions” may be used to effectively reduce rj with a relatively small increase in parasitic resistance

jdrainsource WrRR /,

Lecture 23, Slide 2EE130/230A Fall 2013

E-Field Distribution Along the Channel• The lateral electric field peaks at

the drain end of the channel.Epeak can be as high as 106 V/cm

• High E-field causes problems:–Damage to oxide interface & bulk (trapped oxide charge VT shift)

–substrate current due to impact ionization:


Lightly Doped Drain (LDD) Structure• Lower pn junction doping results in lower peak E-field

“Hot-carrier” effects are reduced Parasitic resistance is increased


R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.9

Parasitic Source-Drain Resistance

)(1 0

0

TGS

sDsat

DsatDsat

VVRI

II

• For short-channel MOSFET, IDsat0 VGS – VT , so that

IDsat is reduced by ~15% in a 0.1 m MOSFET.

• VDsat is increased to VDsat0 + IDsat (RS + RD)

G

S D

Lecture 23, Slide 5

RS RD

EE130/230A Fall 2013 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 7-10

Summary: MOSFET OFF State vs. ON State• OFF state (VGS < VT):– IDS is limited by the rate at which carriers diffuse across

the source pn junction– Minimum subthreshold swing S, and DIBL are issues

• ON state (VGS > VT):– IDS is limited by the rate at which carriers drift across

the channel– Punchthrough is of concern at high drain bias

• IDsat increases rapidly with VDS

– Parasitic resistances reduce drive current• source resistance RS reduces effective VGS

• source & drain resistances RS & RD reduce effective VDSLecture 23, Slide 6EE130/230A Fall 2013

CMOS Technology

p-substrate

(ND)n-well

(ND)n-well

(NA)p-well

Single-well technology• n-well must be deep enough to avoid vertical punch-through

Need p-type regions (for NMOS) and n-type regions (for PMOS)on the wafer surface, e.g.:

(NA)

p- or n-substrate(lightly doped)

Twin-well technology• Wells must be deep enough to avoid vertical punch-through


Sub-Micron CMOS Fabrication Process

• A series of lithography, etch, and fill steps are used to create silicon mesas isolated by silicon-dioxide

• Lithography and implant steps are used to form the NMOS and PMOS wells and the channel/body doping profiles

p-type Silicon Substrate


Shallow Trench Isolation (STI) - oxide



• The thin gate dielectric layer is formed

• Poly-Si is deposited and patterned to form gate electrodes

• Lithography and implantation are used to form NLDD and PLDD regions





• A series of steps is used to form the deep source / drain regions as well as body contacts

• A series of steps is used to encapsulate the devices and form metal interconnections between them.




CMOS Technology Advancement

• Gate length has not scaled proportionately with device pitch (0.7x per generation) in recent generations.– Transistor performance has been boosted by other means.

90 nm node 65 nm node 45 nm node 32 nm node

T. Ghani et al.,IEDM 2003

K. Mistry et al.,IEDM 2007

P. Packan et al.,IEDM 2009

XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.)

(after S. Tyagi et al., IEDM 2005)


Performance Boosters

P. Packan et al., IEDM Technical Digest, pp. 659-662, 2009

• Strained channel regions eff

• High-k gate dielectric and metal gate electrodes CoxeCross-sectional TEM views of Intel’s 32nm CMOS devices

EE130/230A Fall 2013 Lecture 23, Slide 12

Historical Voltage Scaling• Since VT cannot be scaled down aggressively, the supply

voltage (VDD) has not been scaled down in proportion to the MOSFET gate length:

Source: P. Packan (Intel), 2007 IEDM Short Course

VDD

VDD – VT


Power Density Scaling – NOT!Po

wer

Den

sity

(W

/cm

2 )

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

1E+01

1E+02

1E+03

0.01 0.1 1

Gate Length (μm)

Passive Power Density

Active Power Density

Source: B. Meyerson (IBM) Semico Conf.,January 2004

Power Density Trend

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010

YearPo

wer

Den

sity

(W/c

m2 )

Hot Plate

Nuclear Reactor

Rocket Nozzle

Source: S. Borkar (Intel )

Sun’s Surface

Power Density Prediction circa 2000


Parallelism• Computing performance is now limited by power dissipation.

This has forced the move to parallelism as the principal means of increasing system performance.

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

Nuclear Reactor

Rocket Nozzle

Sun’s Surface

Core 2

Source: S. Borkar (Intel )10

010

110

210

310

40

20

40

60

80

100

Nor

mal

ized

Ene

rgy/

op

1/throughput (ps/op)

Operate at a lower energy point (lower VDD)

Run in parallel to recoup performance

singlecore

dualcore

Energy vs. Delay per operation


Key to VDD Reduction: Gate Control

• The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential.

lower VDD to achieve target ION/IOFF

reduced short-channel effect (SCE) and drain-induced barrier lowering (DIBL)

log ID

VGSVDD

ION

Body

Gate

Drain

Cox

Cdep

Source

ox

total

C

CS


Intel Ivy Bridge Processor


Documents

Lecture 23 OUTLINE The MOSFET (cont’d) Source/drain structure CMOS fabrication process The CMOS power crisis Reading: Pierret 19.2; Hu 6.10 Optional Reading: