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7/31/2019 Lecture 3 Power Estimation
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Dr. Tezaswi Raja
Apr 2012
7/31/2019 Lecture 3 Power Estimation
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Dr. Tezaswi Raja
n n
Source Drain
p
Gate
IGIDL
Large electric field exists on the gate-drain overlap region Minority carriers are injected into the substrate causing GIDL
GIDL can be decreased by increasing Gate Oxide thickness
GateDrain
overlap
ELEN601: Intro to Low Power Design 2
Leakage
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Why do we need to estimate Power?
Transistor level power estimation techniques
Spice based power estimation
Gate level power estimation techniques Vector based power estimation
Probabilistic power estimation
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 3
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Accurate System Specifications Individual power estimates determine overall system
specifications Does the overall system meet power requirements?
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 4
2W
7.1W
0.1W
3.2W
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Optimization Trade-offs Accurate power will determine the various design
choices.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 5
Design Optimization Space
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Reliability and Thermal design Accurate power will determine the package, board and
thermal envelope design.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 6
7/31/2019 Lecture 3 Power Estimation
7/48Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 7
System Level
Architecture Level
Gate Level
Transistor Level
Physical Level
SimulationTime
Highest
Least
Accuracy
Highest
Least
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Why do we need to estimate Power?
Transistor level power estimation techniques
Spice based power estimation
Gate level power estimation techniques Vector based power estimation
Probabilistic power estimation
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 8
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Spice is a transistor level simulator for analyzing the circuit behavior.
Golden industry standard for accurate modeling of transistor behavior. Circuit is modeled as a network of resistors, capacitors and Inductors. Voltage at each node is recursively solved for using Kirchoffs voltage
laws and matrix reduction.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 9
Transistor Modelsfrom Foundry
Circuit Netlist
Simulationconditions
Spice Engine Time based nodal voltages Waveforms Measurements
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Power for any path can be measured in Spice using a dummy voltage source.
Spice measurements are very accurate.
Spice measurements are very expensive in terms of computing resources and time.
Fast-Spice simulators exist but also have capacitylimitations.
How do we estimate power for large circuits?
Hierarchically!!
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 10
Circuit Under Test
Vdd
Vss
Circuit Under Test
Vdd
Vss
+ -
Vdummy= 0
.MEAS TRAN POWER AVG I(Vdummy)
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Power is measured for each gate at different input conditionsusing Spice
Each gate is represented by a model in the power analysis tool.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 11
Simulation
Conditions
Spice Based Analysisof each gate
Gate Level Netlist(.v)
Gate Models(.lib)
Event DrivenSimulator
PowerConsumed
Characterization
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Characterization Find Pinttables for each gate in library
Find Pleak tables for each gate in library
Find Delay tables for each gate in library
Pre-simulation Find CL for each gate(and node) in the circuit
Find delay for each gate in circuit
Find delay of each wire in circuit(Elmore delay model)
Event Driven Simulation Given a set of input vectors, find time discrete events at each node in
circuit
Compute the total transitions at each node in circuit.
Compute Pdyn at each gate
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 12
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Characterizationis the process of creating timing andpower models for each gate in the library.
Gate model(.lib) for a gate contains: Input capacitance of each input
Gate delay vs Input transition vs Output load
Output slew vs Input transition vs Output load
Internal switching power Input transition vs Output load
Leakage per each input combination of the gate
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 13
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Input Slew/CL 0.1 fF 0.5fF 1.0fF 3.0fF0.01ns 10ps 15ps 20ps 40ps
0.1ns 14ps 20ps 24ps 48ps
0.5ns 18ps 24ps 28ps 56ps
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 14
Delay vs Input Slew and Output Load (for each input)
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Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 15
Input Slew/CL 0.1 fF 0.5fF 1.0fF 3.0fF0.01ns 10pJ 15pJ 20pJ 40pJ
0.1ns 14pJ 20pJ 24pJ 48pJ
0.5ns 18pJ 24pJ 28pJ 56pJ
Input Power vs Input Slew and Output Load (for each input)
Case Leakage
A=0, B=0 1.0pA
A=0, B=1 1.4pA
A=1, B=0 1.8pA
Leakage Power for each input combination
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Characterization Find Pinttables for each gate in library
Find Pleak tables for each gate in library
Find Delay tables for each gate in library
Pre-simulation Find CL for each gate(and node) in the circuit
Find delay for each gate in circuit
Find delay of each wire in circuit(Elmore delay model)
Event Driven Simulation Given a set of input vectors, find time discrete events at each node in
circuit
Compute the total transitions at each node in circuit.
Compute Pdyn at each gate
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 16
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Copyright Agrawal, 2007
17
Circuit partitioned into channel-connected components for Spice characterization.
Usually one CCC is one logic gate.
Internal nodes of a CCC are not needed for logic computation.
G1
G2
G3
Internal
switchingnodes notseen bylogicsimulator
R. E. Bryant, A Switch-Level Model and Simulator for MOS Digital Systems,IEEE Trans. Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984.
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Input capacitance Cinof each gate is read from
gate models.
Wire capacitance Cw
can be estimated using
wire-load models(inaccurate) or
extracted from layout(accurate)
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 18
CL = Cin +CW
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For each gate in the circuit: Given the load capacitance CLread gate delay from gate
models.
Note that the exact CLmay not be present in themodels.
Extrapolation introduces inaccuracy in the delayestimation.
Wider ranges for CLare recommended for accurateestimates.
How about wire delay?
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 19
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20
For all caps in circuit, trace back to input and find allcommon resistors to delay path.
N
Delay at node k = 0.69 Cj Rjkj=1
where N =number of capacitive nodes in the network
W. Elmore, The Transient Response of Damped Linear Networks with ParticularRegard to Wideband Amplifiers,J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948.
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Copyright Agrawal, 2007
21
s 1
2
3
4
5
R1
R2
R3
R4
R5
C1
C2
C3
C5
C4
Example:
Delay at node 5 = 0.69[R1 C1 + R1 C2 + (R1+R3)C3+ (R1+R3)C4 + (R1+R3+R5)C5]
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Characterization Find Pinttables for each gate in library
Find Pleak tables for each gate in library
Find Delay tables for each gate in library
Pre-simulation Find CL for each gate(and node) in the circuit
Find delay for each gate in circuit
Find delay of each wire in circuit(Elmore delay model)
Event Driven Simulation Given a set of input vectors, find time discrete events at each node in
circuit
Compute the total transitions at each node in circuit.
Compute Pdyn at each gate
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 22
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23
b
a
c (Spice )
Time units0 3
Inputs
Logicsimulation
Trigger Event
Transient region
c (zero delay) Result event
c (unit delay) X Result event
c (multiple delay) X Result event
Output
Spice response of a NAND gate can be modeled as a switching event.
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Copyright Agrawal, 2007
24
2
2
4
2
a=1
b=1
c=10
d= 0
e=1
f=0
g=1
Time, t04 8
g
t = 012
34567
8
ActivityList
c= 0
d= 1, e= 0
g= 0
f= 1
g= 1
Scheduledevents
d, e
g
f
g
Timestack
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Copyright Agrawal, 2007
25
t=0
1
2
3
4
5
6
7
maxCurrenttimepointer Event link-list
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Where: Ckis the total node capacitance being switched, as determined by the
simulator. Vis the supply voltage. fis the clock frequency, i.e., the number of vectors applied per unit time
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 26
Pdyn = Ck V2fall nodes k
Event DrivenSimulator
InputVectors
Toggle Countsat each node
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Where: E(g,e) = energy of event eof gateg, pre-computed short-circuit
power from Spice. f(g,e) = occurrence frequency of the event eat gateg, observed
by logic simulation.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 27
Pint = E(g,e) f(g,e)gates g events e
Event DrivenSimulator
InputVectors
Internal Eventsat each gate
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Where: P(g,s) = static power dissipation of gateg for states, obtained from
Spice.
T(g,s) = duration of states at gateg, obtained from logic simulation.
T= number of vectors vector period.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 28
Pstat = P(g,s) T(g,s)/Tgates g states s
Event DrivenSimulator
InputVectors
Internal Vectorstates at each gate
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Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 29
Total Power = Pdyn + Pint +Pstat
A. Deng, Power Analysis for CMOS/BiCMOS Circuits, Proc. International Workshop LowPower Design, 1994.J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, Simulation Algorithms, PowerEstimation and Diagnostics in PowerMill, Proc. PATMOS, 1995.C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, The Design and Implementation ofPowerMill, Proc. International Symp. Low Power Design, 1995, pp. 105-109.
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Computationally expensive for large circuits
Results are very dependent on input vector set.
How can we estimate power without vectors?
Probabilistic Analysis
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 30
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Every signal is modeled as a set of probabilities.
P1(x) : Probability of a signal x being 1 P0(x) : Probability of a signal x being 0
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 31
Signal Probabilities
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Observe signal for interval t0 + t1 Signal is 1 for duration t1
Signal is 0 for duration t0
Signal probabilities:
p1 = t1 /(t0 + t1 )
p0 = t0/(t0 + t1 ) = 1 p1
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 32
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33
p1
p2
p1 p2
p1
p2
1 (1 - p1)(1 - p2)
p1 1 - p1
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34
x1
x2x3
x1 x2
y =1 - (1 - x1x2) x3=1 - x3 + x1x2x3=0.625= 5/8 (from truth table)
X1 X2 X3 Y0 0 0 10 0 1 00 1 0 10 1 1 0
1 0 0 11 0 1 01 1 0 11 1 1 1
0.5
0.5
0.5
0.25 0.625
Ref:K. P. Parker and E. J. McCluskey,
Probabilistic Treatment of GeneralCombinational Networks, IEEE Trans.on Computers, vol. C-24, no. 6, pp. 668-670, June 1975.
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35
x1
x2
x1 x2
y =1 - (1 - x1x2) x2=1 x2 + x1x2x2
=0.625X1 X2 Y0 0 10 1 0
1 0 11 1 1
0.5
0.5 0.25 0.625
Why the difference?
=0.75
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36
x1
x2
x1 x2
y =1 - (1 - x1x2) x2=1 x2 + x1x2x2=1 x2 + x1x2=0.75 (correct value)
X1 X2 Y0 0 10 1 0
1 0 11 1 1
0.5
0.5 0.25 0.625?
Signal Probability propagation is dependent on input correlationInputs are correlated in circuits with reconvergent fanout
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Identify reconvergent fanout nodes in thecircuit
For these nodes, calculate probabilities with
full expansion of terms Remove any exponents of variables
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 37
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38
x1
x2
x1 + x2 x1x2
y = (x1 + x2 x1x2) x2= x1x2 +x2x2 x1x2x2= x1x2 + x2 x1x2= x2
=0.5 (correct value)
X1 X2 Y0 0 00 1 1
1 0 01 1 1
0.5
0.5 0.75 0.375?
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Transition probability is defined as the probability of atransition happening on x.
P01(x) is defined as the probability of x going from 0 to 1.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 39
Transition Probabilities
Is this true?P(0->1) = p1(x)*p0(x)
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Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 40
1/fck
p0 = 0.5p1 = 0.5
p0 = 0.5p1 = 0.5
p0 = 0.5
p1 = 0.5
P01 = 2/8P01 = p0 * p1
P01 = 3/8
P01 = 1/8
P(0->1) = p1(x)*p0(x)is not always correct!
How do we combine signal and transition probabilities?
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Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 41
p1 = p01
p10 + p01
p1 =p1 *p11 + (1-p1) *p01
p0 p1
p11p01
p10
p00
What has this got to do with Power?
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Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 42
Pdyn = f * CL V2
= T(x) * CL V2
Transition density T(x) is defined as number of transitionsper unit time.
If we know the transition density of a signal, we can
calculate its power.
F. Najm, Transition Density: A New Measure of Activity in Digital Circuits,IEEE Trans. CAD, vol. 12, pp. 310-323, Feb. 1993.
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Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 43
Transition Density = 2 * p0 *p01 = 2 * p1 * p10
Transition Density = p1 *p10 + p0 *p01= 2 * p01 * p10
p10 + p01
p0 p1
p11p01
p10
p00
Power consumed
Power consumed
No PowerNo Power
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44
p1, T1
p2, T2
p1 * T2 + p2 * T1
p1, T1
p2, T2
(1 - p1)* T2 + (1 - p2) *T1
p1, T1 T1
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Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 45
Pdyn = f * CL V2
= T(x) * CL V2
Transition density at each node can be determined by:
Signal probability at each node Transition density at each node
Stages for estimating Power Assign Signal Probability at primary inputs
Assign Transition Density at primary inputs Propagate Signal Probabilities to all nets in circuit Propagate Transition Density to all nets in circuit Calculate Power consumed at each net in the circuit.
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46
X1
X2
X3
0.2, 1
0.3, 2
0.4, 3
0.06
0.436
Transition density
Y
Ci
CY
Power = 0.5 V 2 (0.7Ci + 3.24CY)
Stages for estimating Power
Assign Signal Probability at primary inputs Assign Transition Density at primary inputs
Propagate Signal Probabilities to all nets in circuit
Propagate Transition Density to all nets in circuit
Calculate Power consumed at each net in the circuit.
Signal probability
, 0.7
, 3.24
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Split reconvergent portion into super-gates For each super-gate, expand the terms using
Shannons expansion theorem
Obtain Transition density using Booleandifference.
Dr. Tezaswi Raja ELEN601: Intro to Low Power Design 47
C. E. Shannon, A Symbolic Analysis of Relay and Switching Circuits, Trans. AIEE, vol. 57,pp. 713-723, 1938.
S. C. Seth and V. D. Agrawal, A New Model for Computation of Probabilistic Testability inCombinational Circuits,Integration, the VLSI Journal, vol. 7, no. 1, pp. 49-75, April 1989.
F. Najm, Transition Density: A New Measure of Activity in Digital Circuits,IEEE Trans.CAD, vol. 12, pp. 310-323, Feb. 1993.
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Power estimation in Spice is accurate butexpensive
Gate level power estimation can be donehierarchically to improve performance.
Vector based simulators are used to estimate logicactivity
Probabilistic estimation of power can be used for
quick vector-less power estimate.