General Information

Today’s Agenda Scintillator Review Signals, noise, jitter Nuclear electronics Oscilloscopes Hands-On demo

Time dependence of emitted light Non-radiative transfer of energy from vibrational states to fluorescent state

Typical time: 0.2 – 0.4 ns

Decay of fluorescent stateTypical time: 1 – 3 ns

Rise with time constant r

Fall with time constant f

Total pulse shape

Note: the rise time is usually increased substantially by subsequent components in the system and variations in path length in large scintillators

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Scintillation Counter Plateau

Low voltage: very few countsWith increasing voltage (gain) the number of counts rises sharply once the signalPulses are above the discriminator thresholdRegeneration effects (after pulsing etc) at higher voltages

Scintillation counters are typically operated in the middle of the plateau

Exercise 1 Learn how to use the HV power supply Connect Scintillator/PM to HV and to Oscilloscope Adjust HV and oscilloscope until you see signals Explore basic oscilloscope functions

Horizontal settingsVertical settingsCouplingTrigger

Bandwidth

Example:A rectangular pulse of period Ttransmitted through systems witha bandwidth of 0.1/T, 0.5/T, 1/T and5/T, respectively

Bandwidth of a system is defined as thepoint where the frequency response dropsby 3 dB.

Decibel dB: log. unit of measurement thatspecifies a quantity (usual power) relativeto a reference level

G = 10 log10 V1/V03 dB = 103/10 corresponds to a factor ~2

Scintillator and PMT Signals Non-radiative transfer of energy from vibrational states to fluorescent state

Typical time: 0.2 – 0.4 ns

Decay of fluorescent stateTypical time: 1 – 3 ns

Rise with time constant r

Fall with time constant f

Total pulse shape

Note: the rise time is usually increased substantially by subsequent components in the system and variations in path length in large scintillators

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Definitions:

PM Signals (cont’d)

A PMT maybe considered as an ideal currentsource in parallel with a certain resistance andcapacitance. Equivalent circuit:

This leads to the equation

With the solution:

Typical values:G = 106, N = 100, s = 5nsR = k, C = 10 pF= RCFor s small signal but original shapeFor s larger amplitude but shape dominated by RC of output circuit

dtdVC

tVtI

Signal (Pre-Amplifier)

Charge Sensitive Amplifier

The signal charge Qs will be distributed between sensor capacitance Cd and the pre-amp input capacitance Ci

=> Ci must be large compared to the detector capacitanceidid

i

id

i

s

i

CCCCC

QQQ

QQ

11

Qs

Pulse ShapingTwo conflicting objectives

Limit bandwidth to match measurement time(transform a narrow sensor pulse into a broader pulsewith a gradually rounded maximum)

Constrain pulse width to avoid overlap (pile-up) Ultimate measure:

Signal to Noise Ratio (SNR) Throughput, maximum rate

Characteristic shaping or peaking time TP

CR-RC Shaper

Extracting InformationOnce the sensor signal is acquired we can extract the information we are trying to measure:

Count pulses (Discriminator) Measure energy, energy loss, charge (Analog to Digital Conversion) Measure time (Time to Digital Conversion, time measurement techniques)

Typically we have more than one sensor Combine signals (Basic coincidence techniques)

Discriminator

A discriminator is a device which respondsonly to input signals with a pulse height greater than a (adjustable) threshold.

If this criterion is met the discriminator issues a standard logic signal.

The width of the output signal is usually adjustable.

Typical Disciminator NIM Modules

LeCroy 8-channel discriminatorInput threshold adjustable from -30 mV to -1 VOutput width adjustable from 5 ns to 600 ns

Testpoint to measure threshold voltage with DVM

(Common) Veto (aka Inhibit) Input

Access for (tiny) screwdriver to adjust width and threshold

NIM Standard

Nuclear Instruments and Methods - 1964 (DOE/ER-0457)

Common “backplane” power distribution, detachable supply delivering +6 V, -6 V, +12 V, -12 V, +24 V, and -24 V

No computer interface Standardized modules

Height of 8.75” (1.35” single, 2.70” double width)

For details see

www.esd.fnal.gov/esd/catalog/intronim.htm

Standardized Electronics NIM, CAMAC, VME, Fastbus, PCI….

Custom electronics (FPGA, ASICS) common for modern experiments Standards encompass a wide range of mechanical and

electrical definitions - provides cost and convenience advantages

flexibility and interchangeabilityEasily configurableUpdate with a few modules

Status:CAMAC is very much past its prime. Still lot’s of modules aroundFastbus is obsoleteNIM frequently used for test standsVME, Compact PCI, PCI (PCIe) add-on modules, USB are in

widespread use.

Logic Levels NIM standard specifies logic levels by currents through

50 resistor:voltages of 0 V and -0.8 V for logic 0 and 1, respectively

ECL, Emitter-Coupled Logic” "0" = -1.75 V = LOW = False "1" = -0.9 V = HIGH = TrueFast, high power consumption

TTL, Transistor–Transistor Logic1962, Texas instruments “0” < 0.8V “1”>2.0 V

LVDS (twisted pair, differential)Low-voltage differential signaling (LVDS) uses high-speed analog circuit techniques to provide multigigabit data transfers on copper interconnects and is a generic interface standard for high-speed data transmission

“0” = 1.0 V “1” = 1.4 V

Connections BNC

For coaxial cable Whatsit?50 and 75 versions

LEMOminiature push-pull coaxial, with a 50

ohm impedance (to replace BNC) HV - should be on red cable, SHV Ribbon, Twisted Pair (110 ) Cable - careful of impedance!

Analyzing the Pulse Shape A lot of information can be extracted from the pulse shape

Charge/energy from integrating the pulse or the peak amplitude of well-shaped pulses.

Timing from the rise time, peaking time, fit of standard pulse to pulse shape Pile up and overlapping pulses …

An Analog to Digital Converter (ADC) converts the information contained in the analog signal to an equivalent digital form. Peak sensing

Digitize the peak voltage Charge sensitive

Digitize total integrated current (charge) Flash

Digitize each signal several times (=> reconstruct waveform)

Analog to digital conversion

FlashA discriminator for each of the 2n codesNew sample every clock cycleFast, large, lots of power, limited to <10 bits

RampLinear analog ramp and count clock cyclesTakes 2n clock cycles for a n bit converterSlow, small, low power, can be made with

large resolution

1

2

3

2n

Linear to binary encoder

Vref

1 Counter

Start Clock

Start Stop

RampVin

I

Vin

Vin

100 010 011DAC code

DAC voltage

DACAprox reg.

Vin

ADC code

More ADC Architectures

Successive approximation Binary search via a DAC and single discriminator Takes n clock cycles Relatively slow, small, low power, medium to

large resolution

Pipelined Input to each stage is fed to both a sample and

hold and a 3-bit flash ADC S&H maintains signal level; ADC converts signal

with 3 bit accuracy. ADC output is send to a DAC Signal is subtracted from original signal and is

passed on to next stage. Now dominating ADC architecture in modern

CMOS technologies and impressive improvements in the last 10 years: speed, bits, power, size

Commercially available: 1 GS/s conversion rate with 8-bit resolution and a power dissipation ofabout 1.5 W

ADC Imperfections Quantization (static)

Bin size: Least significant bit (LSB) =Vmax/2n

Quantization error: RMS error/resolution:

Integral non linearity (INL): Deviation from ideal conversion curve (static) Max: Maximum deviation from ideal RMS: Root mean square of deviations from ideal

curve

Differential non linearity (DNL): Deviation of quantization steps (static) Min: Minimum value of quantization step Max: Maximum value of quantization step RMS: Root mean square of deviations from ideal

quantization step

Missing codes (static) Some binary codes never present in digitized output

Non-Monotonic (static) Non monotonic conversion can be quite unfortunate

in some applications. A given output code can correspond to several input values.

12LSB IdealIdeal

INL:Variation from ideal curve

INL:Variation from ideal curve

DNL: Variations fromideal LSB

DNL: Variations fromideal LSB

Missing codeMissing code

Non monotonicNon monotonic

Digital to Analog Conversion (DAC)The digital to analog converter or DAC is the opposite of the ADC.Several implementations, one simple example:A binary word is passed to a networkof branches, one for each bit.A different resistors provide different weights(R, 2R, 4R, …)

rn

nnno VaaaaV

2...222 0

33

22

11

Time Measurement Time measurements are important in many detector applications

Identification of bunch crossing (LHC: 25ns) Distinguish among individual collisions (events) in continuous beam like experiments (or very

short bunch interval like CLIC: ~250ps) Drift time

Position in drift tubes ( binary detectors with limited time resolution: ~1ns) Time projection chamber (both good time and amplitude)

Time Of Flight (TOF) detectors (very high time resolution: 10-100ps)

p < 1.2 GeV

Time resolution 90 – 100 ps

Time to digital conversion

Charge integration (start – stop) Limited dynamic range High resolution: ~1-100 ps Sensitive analog circuit needing ADC for final

conversion. Sensitive to temperature, etc. so often needs in-

system calibration Can be combined with time counter for large

dynamic range

Counter Large dynamic range Good and cheap time references available as

crystal oscillators Synchronous to system clock so good for time

tagging Limited resolution: ~1ns

Counter plus delay locked delay elements Delay elements time locked to master counter

clock Resolution: 25 – 100ps

Start Stop

ADC

Start

Stop

CounterClock

RegisterHit

Reset

Time tagging type

CounterClock

Start Stop

Start-stop type

Register

PhaseClock

Hit

Delay Locked Loop

Time walk and Jitter Time walk: Time dependency on amplitude

Jitter: Variation in time caused by signal noise

Improved Timing

Constant Fraction Discriminator

Zero-Crossing Disciminator

Basic Coincidence TechniquesA coincidence unit determines if two or more (logic) signals are coincident in time generates a standard logic signal if true and no signal if false.

Think “logical And”

Majority Logic Units are standard modules that can implement more sophisticated logic conditions.

A minimum overlap is required.

Adjusting the system/delay: Coincidence Curve

Accidental (random) coincidencesrandom rate = 2 n1n2 pulse

Gate / Delay Generator, Logic UnitsGate Generator Provides precise delays for triggering,

syncing, delaying and gating events Typical range from 100 ns to seconds Also operates as latch Gating allows regions of interest to be

processed and stored while ignoring the bulk of unwanted data

Can also delay signals by selected time

LeCroy Dual Logic Unit• These logic units offer the functions of fan-in, coincidence, and majority logic.

• Four logic inputs and one common veto input.

• All inputs are terminated in 50 Ohm.

Additional Exercises Explore the discriminator module; adjust output width Measure the signal transmission speed in RG58 Setup two scintillation counters in coincidence