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EE141
1
EE141 EECS141 1 Lecture #22
EE141 EECS141 2 Lecture #22
Some Project Adjustments:
Group 2: Minimize power while ensuring that the delay should be
no more than 1200 ps.Be aware that this obviously leads to a
higher clock frequency. Use a clock frequency of 800 MHz to
compute the power.
Minimize the delay, while ensuring that the power should be no
more than 75 uW. REVISED DEFINITION: Minimize the delay,
while ensuring that the average energy per cycle is no more than
750 fJ. The length of a cycle is defined as the length of your
critical path + 2.5% timing margin.
Hw 7 due next Monday
Hardware Lab next week
Graded Midterm 2 and Phase 1to be returned today
EE141
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EE141 EECS141 3 Lecture #22
Last lecture
Latches and registers
Today’s lecture:
Timing
Reading
Chapter 7
EE141 EECS141 4 Lecture #22
0
2
4
6
8
10
12
14
16
18
10-14 14-18 18-22 22-26 26-30 30-34 34-38 38-42
MT2
EE141
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EE141 EECS141 5 Lecture #22
0
2
4
6
8
10
12
14
16
6-9 9-12 12-15 15-18 18-21 21-24 24-27
Combined
EE141 EECS141 6 Lecture #22
EE141
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EE141 EECS141 7 Lecture #22
D
CLK
CLK
Q
Dynamic Static
EE141 EECS141 8 Lecture #22
Keepers can be added to “staticize”
EE141
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EE141 EECS141 9 Lecture #22
Negative latch
(transparent when CLK= 0)
Positive latch
(transparent when CLK= 1)
EE141 EECS141 10 Lecture #22
AND latch Example: logic inside the latch
EE141
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EE141 EECS141 11 Lecture #22
EE141 EECS141 12 Lecture #22
Master-Slave
Latches
D Clk
Q D Clk
Q
Clk
Data D Clk
Q Clk
Data
Pulse-Triggered
Latch
L1 L2 L
Ways to design an edge-triggered sequential cell:
EE141
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EE141 EECS141 13 Lecture #22
EE141 EECS141 14 Lecture #22
EE141
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EE141 EECS141 15 Lecture #22
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
EE141 EECS141 16 Lecture #22
EE141
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EE141 EECS141 17 Lecture #22
EE141 EECS141 18 Lecture #22
D Clk
Q
D
Q
Clk
tclk-q thold
PWm tsetup
td-q
Delays can be different for rising and falling data transitions
T
EE141
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EE141 EECS141 19 Lecture #22
D Clk
Q
D
Q
Clk
tclk-q
thold
T
tsetup
Delays can be different for rising and falling data transitions
EE141 EECS141 20 Lecture #22
Cycle time (max): TClk > tclk-q + tlogic + tsetup
Race margin (min): thold < tclk-q,min + tlogic,min
tclk-q
tclk-q,min
tlogic
tlogic,min tsetup, thold
EE141
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EE141 EECS141 21 Lecture #22
Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
Clock jitter
Temporal variations in consecutive edges of the clock signal; modulation + random noise
Cycle-to-cycle (short-term) tJS
Long term tJL
Variation of the pulse width
Important for level sensitive clocking
EE141 EECS141 22 Lecture #22
Sources of clock uncertainty
Variation
EE141
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EE141 EECS141 23 Lecture #22
Both skew and jitter affect the effective cycle time
Only skew affects the race margin (usually)
Clk
Clk
tSK
tJS
EE141 EECS141 24 Lecture #22
# of registers
Clk delay Insertion delay
Max Clk skew
Earliest occurrence
of Clk edge
Nominal – /2
Latest occurrence
of Clk edge
Nominal + /2
EE141
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EE141 EECS141 25 Lecture #22
EE141 EECS141 26 Lecture #22
Launching edge arrives before the receiving edge
EE141
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EE141 EECS141 27 Lecture #22
Receiving edge arrives before the launching edge
CLK1
CLK2
T CLK
T CLK -
2
1
4
3
EE141 EECS141 28 Lecture #22
Minimum cycle time:
Tclk + = tclk-q + tsetup + tlogic
Worst case is when receiving edge arrives early (negative )
tclk-q
tclk-q,min
tlogic
tlogic,min tsetup, thold
EE141
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EE141 EECS141 29 Lecture #22
Hold time constraint:
t(clk-q,min) + t(logic,min) > thold +
Worst case is when receiving edge arrives late
Race between data and clock
tclk-q
tclk-q,min
tlogic
tlogic,min tsetup, thold
EE141 EECS141 30 Lecture #22
Clk
TCLK
tsetup
tclk-Q tlogic
Latest point
of launching Earliest arrival
of next cycle
tJS +
EE141
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EE141 EECS141 31 Lecture #22
If launching edge is late and receiving edge is early, the data will not be too late if:
Minimum cycle time is determined by the maximum delays through the logic
tclk-q + tlogic + tsetup < TCLK – tJS,1 – tJS,2 +
tclk-q + tlogic + tsetup - + 2tJS < TCLK
Skew can be either positive or negative
EE141 EECS141 32 Lecture #22
Clk tclk-q,min
tlogic,min
Earliest point
of launching
Data must not arrive
before this time
Clk thold
Nominal
clock edge
EE141
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EE141 EECS141 33 Lecture #22
Minimum logic delay
If launching edge is early and receiving edge is late:
tclk-q,min + tlogic,min – tJS,1 > thold + tJS,2 +
tclk-q,min + tlogic,min > thold + 2tJS+
(This assumes jitter at launching and receiving clocks are
independent – which usually is not true)
EE141 EECS141 34 Lecture #22
Pipelining
Wires (introduction)