The Stack, Subroutines, Interrupts and Resets

In many computers, memory is divided into three distinct areas:

program areadata areastack

The stack is an area of memory used for the temporary storage of information. Subroutines and interrupts make use of the stack.

The stack pointer (SP) is a register within the P that contains the address of the next location available for the stack.

The P’s internal logic causes the SP to decrement automatically when data is stored in the stack and to automatically increment when it is removed. Therefore, the SP must initially be set to the highest address in the stack area (called the top of the stack initially).

e.g., if the stack is to occupy locations $0200 to $02FF then use LDS #$02FF instruction as initialization before using the stack.

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SP instructions are:

- DES SP - 1 SP- INS SP + 1 SP- LDS M:M + 1 SP (in immediate, direct, extended

and indexed modes)- STS SP M:M + 1 (in direct, extended and

indexed modes)- TXS IX - 1 SP - TSX SP + 1 IX - TYS IY - 1 SP - TSY SP + 1 IY

PUSH and PULL Instructions

The push (PSH) and pull (PUL) instructions store and load data to and from the stack.

A PSHA (or B or X or Y) writes the contents of the specified register in the stack at the SP location and then decrements the SP once (for PSHA and PSHB) or twice (for PSHX and PSHY) because the original stack location is no longer vacant but contains the pushed data.

A PULA (or B or X or Y) first increments the SP once to point to the last item that has been inserted into the stack and then transfers the contents of the stack appropriately to the specified register.

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Note that the stack acts as a Last-In-First-Out (LIFO) structure. A PULL retrives the information that was last PUSHed onto the stack.

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Subroutines

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When the same function is required more than one in a program, it is frequently written as a subroutine,

A subroutine can be used any number of times by the main program.

This capability is provided by the following three instructions;

o JSR (jump to subroutine)o BSR (branch to subroutine)o RTS (return from subroutine)

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JSR instruction has both indexed and extended modes.

With the complete exucution of JSR, the address of the next instruction to be executed (the one following the JSR) is stored automatically in the stack

Then the PC is changed appropriately according to the addressing mode used for JSR

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BSR (branch to subroutine) has only the relative addressing mode and the subroutine start address is calculated by the CPU by using the offset. Each subroutine must have RTS (return from subroutine) as the last insatruction of the subroutine.

With the execution of the RTS, the CPU restores the PC from the stack again automatically and therefore the program returns back to the instruction where it has left before the jump or branch to the subroutine. The following example is for the extended case in the above figure:

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[n+3] H[n+3] L

Nested subroutines: Since PC saving and recovery is automatic by the use of stack, it is possible to execute nested subroutines as follows.

If the stack is used for register savings in a subroutine, the recovery should be done in the reverse order and in a balanced fashion

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Example: If a subroutine uses accumulators A and B and the CCR, how can the main program preserve the contents of these registers ?

The first four instruction of the subroutine may be Opcode Mnemonic

36 PSHA37 PSHB07 TPA36 PSHA

which puts A, B and CCR on the stack as follows:

Restore order before the RTS:Opcode Mnemonic 32 PULA06 TAP33 PULB32 PULA39 RTS

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Contents of the stack after entering the subroutineand executing the first four instructions

Example: Solve example 9 (square from a lookup table) as a subroutine and use it in a main program to calculate the squre of two numbers. Also pass the input parameter and the output parameter using accumulator A only. Do not use loc. $40 and $41 any more.

label mnemonic comment SQR LDX #SQTAB load base of table

TSTA check input numberBEQ FOUND if it is zero, stop

searching and goto FOUND

CONT INX point to the next table entry

DECA decrement ABNE CONT and repeat for a

number of timesFOUND LDAA $00,X get the

corresponding table entry

RTSMAIN LDAA #$05 get the input data

JSR SQRSTAA $41 store the first resultLDAA #$06JSR SQRSTAA $42 store the second

resultEND BRA END

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Example: Write an M68HC11 program, which performs the following task:

data array starts in memory location $0500 length of the array is in memory location $0040.

Some of the elements of the given array will be placed to another area in the memory starting at location $0900.

Each element of the original array will be checked whether it is a 2-digit valid BCD number or not and will be placed in the new array by reversing its bit order if it is valid,

i.e,

if the content of the memory location $0500, for example, is a valid 2-digit BCD number X7X6X5X4X3X2X1X0 then X0X1X2X3X4X5X6X7 will be stored to the memory location $0900. If the number is not a valid 2-digit BCD number, then it will not be stored.

At the end, the memory location $0041 will hold the total number of bytes in the new array.

Write the BCD checking part of your code as a subroutine.

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Solution: (write comments for the program as an exercise)

MAINLDS #$STACKBASELDX #$0500LDAB $40STAB BYTECOUNTLDY #$0900

CONTLDAA $00,XJSR CHKBCDBNE CONT2

VALIDLDAB #$08STAB BITCOUNT no need

CONTSHIFTLSLAROR $00,YDECBBNE CONTSHIFTINY

CONT2INXDEC BYTECOUNT BNE CONT

ENDBRA END

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CHKBCDPSHACLRATAPPULA

TABDAACBARTS

Interrupts and ResetsAn interrupt is an hardware (sometimes software) initiated subroutine call

Depending on the type of the interrupt and the logic state of the I bit in the condition code register, the CPU may suspend its normal operation and service the interrupt.

The software used in response to the interrupt signal is called an interrupt service subroutine.

After the interrupt service subroutine is executed, the CPU returns to the original program and resumes execution as if no interrupt occurred.

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This requires the CPU’s registers to be saved when CPU services an interrupt and returned unaltered when the routine is finished.

An interrupt service subroutine ends with an RTI instruction which automatically returns the CPU registers.

Interrupt vectors

All resets and interrupts use vectors indicating the start address of reset or interrupt routines.

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Example:

$FFF2 00$FFF3 EE

$00EE 7E$00EF 00$00F0 30

$0030 B6$0031 11$0032 A2

Interrupt masks and enables

An interrupt signal may or may not be recognized under programmer’s control by mostly setting the interrupt mask bit (I bit) in the CPU’s CCR.

If I = 1, CPU does not recognize interrupt signals => Interrupts are masked.

I bit can be set by using the SEI instruction and cleared by using the CEI instruction.

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Fixed by the system

Vector jump tableCan be initialized asLDAA #$7ESTAA $EELDX #$0030STX $EF

Interrupt service subroutine

When an interrupt request occurs CPU pushes all CPU register values to stack in the order: PC, IY, IX, ACCA, ACCBA, CCR (pushing low byte first for 16-bit registers).

When RTI is executed the data is pulled from the stack and the registers are restored.

For RESET: No stacking of the registers.

Hardware interrupts and resets

RESET: Executed whenever the chip is powered up, whenever the external pin is activated. Highest priority.

Other processor resets: Computer Operating Properly (COP) failure reset, COP clock monitor fail reset,

Nonmaskable interrupt (XIRQ): is used to handle the highest priority interrupts.

When you power up or RESET 68HC11, XIRQ is masked, i.e. X bit in CCR is set.

To clear X, TAP (Transfer from ACCA to CCR) instruction should be used.

Interrupt Request (IRQ): is maskable by setting bit I in the CCR.

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IRQ versus XIRQ

1. CPU can ignore the IRQ input if the I flag is 1; it can ignore XIRQ if the X flag is 1. However I flag can be set and cleared any time by software. X flag can be cleared only once, then it remains at 0.

2. IRQ can be programmed as a level-sensitive or edge-sensitive input via the IRQE bit in the OPTION (at $1039) register. XIRQ is always level sensitive.

3. XIRQ input has higher priority over IRQ input. When they are activated simultaneously (while X=I=0), CPU will respond to XIRQ first.

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68HC11IRQ

XIRQ

Software and CPU control interrupts

Software interrupt (SWI): Forces the CPU to respond the same as it does to an externally generated interrupt. Useful in helping to debug the programs. Not maskable by either I or X bits in CCR.

Wait for Interrupt (WAI): 68HC11 reduces its power while waiting to be woken up. All registers are stacked. Only an unmasked interrupt will wake up the controller.

STOP: If S bit in CCR is set, STOP performs like a NOP. If S bit is reset, all internal clocks halt, thus halting execution. To wake up the controller, RESET, XIRQ or IRQ (when I=0) must be used.

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