LEMBAR KERJA PRAKTIKAN EKS. EMBEDDED SYSTEM PERTEMUAN 1:PENGENALAN Nama Handito NIM 12/331317/PA/14587 Kelompok Kelas A Hari/ Tanggal Selasa, 3 Maret 2015 LISTING Test Bench VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Pert1VHDL is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end Pert1VHDL; architecture Behavioral of Pert1VHDL is begin SUM <= A XOR B XOR C; CARRY <= (A OR B)OR (A OR C) OR (B OR
