Let's Build a Computer - zenspider.comryan/presentations/2014_gogaruco_lets_build… · Sous-Chef 3. Sous-Chef 3 Assistant. 4. ISS Icarus 4. 5. Unfortunate Accident 5. 6. Phase Matter

1

Year3014

1

2

After aseries ofdemotions

2

3

Sous-Chef3

Sous-Chef3

Assistant

4

ISSIcarus

4

5

UnfortunateAccident

5

6

PhaseMatter Array

6

7

7

Dark MatterCephalopod

8

Killing8

9

TheCaptain

9

10

ScienceOfficer

10

11

Engineer11

12

and, ofcourse

12

13

TheComputer

13

14

I’mstranded!

14

15

All IHave

15

16

PowerSupply

16

17

A Bucket ofNAND gates

17

18

andthisbook

18

19

I am...19

20

Lost In Space

20

Ryan Davis, Seattle.rbLet’s Build a Computer!

@the_zenspiderGoGaRuCo 3014

Let’s Build a Computer!

21



Setting ExpectationsHighly Technical Talk

(I hope) Highly Approachable Talk

200 Slides ≅ 6 ⅔ spm

I have to go incredibly fast.

Not my field of expertise at all. I’m terrified.22



Nand to Tetris

23



I !

this book24

♥


@the_zenspiderGoGaRuCo 3014 25

High Level Language & OS

Virtual Machine

Assembly Language

Machine Language

Hardware Platform

Chips & Logic Gates

Physics




Virtual Machine

Assembly Language

Machine Language

Hardware Platform

Chips & Logic Gates

Physics


Virtual Machine

Assembly Language

Machine Language

Hardware Platform

Chips & Logic Gates

Physics


@the_zenspiderGoGaRuCo 3014 26statement of the system’s abstraction—namely, the various services that it isexpected to deliver. Having presented the what, each chapter proceeds to discuss howthe abstraction can be implemented, leading to a (proposed) Implementation section.The next section is always Perspective, in which we highlight noteworthy issues leftout from the chapter. Each chapter ends with a Project section that provides step-by-step building instructions, testing materials, and software tools for actually buildingand unit-testing the system described in the chapter.

Projects

The computer system described in the book is for real—it can actually be built, andit works! A reader who takes the time and effort to gradually build this computer willgain a level of intimate understanding unmatched by mere reading. Hence, the bookis geared toward active readers who are willing to roll up their sleeves and build acomputer from the ground up.

Each chapter includes a complete description of a stand-alone hardware or soft-ware development project. The four projects that construct the computer platformare built using a simple Hardware Description Language (HDL) and simulated on ahardware simulator supplied with the book. Five of the subsequent software projects

c3

c10

c7

c9

c6

c5

c11

c1

c2

c12

c8

c4

Typicalsoftwarehierarchy

Typicalhardwareplatform

High-Level Language / Applications (∞)

Operating System

Compiler

Virtual Machine

Assembler

Computer Architecture

Machine Language

ALU Memory Elements

Boolean Arithmetic

Boolean Logic

Sequential Logic

Figure P.1 Book and proposed course map, with chapter numbers in circles.

xii Preface

From “Elements of Computing Systems”



Projects



c3

c10

c7

c9

c6

c5

c11

c1

c2

c12

c8

c4




Operating System

Compiler

Virtual Machine

Assembler


Machine Language

ALU Memory Elements

Boolean Arithmetic

Boolean Logic

Sequential Logic


xii Preface




Projects



c3

c10

c7

c9

c6

c5

c11

c1

c2

c12

c8

c4




Operating System

Compiler

Virtual Machine

Assembler


Machine Language

ALU Memory Elements

Boolean Arithmetic

Boolean Logic

Sequential Logic


xii Preface




Complexity builds from Simplicity

27

Boolean Logic

Boolean Arithmetic

Sequential Logic

Computer Logic



Very Important:

28



This is NOT comic sans!

29




29

ttttt




29

ttttt Hand-drawn font called Sketchnote!



Boolean Logic

30



NAND



WTF is a

Nand?!?32



Not-And

33

NAND



Not-And

33

NAND

Not



Not-And

33

NAND

And

Not



Nand34

NAND

a b nand

T T F

T F T

F T T

F F T



Rubydef nand a, b ! (a && b) end

35



Rubyclass Object def ⅋⅋ other ! (self && other) end end

36



Rubyclass Object def ⅋⅋ other ! (self && other) end end

36

So Cool!



Universal Gates

37

NAND

NOR




38

Nand

Not

And

Or

Xor / Mux / Dmux



NOT



Only using ?

40

NAND



not41

a not

T F

F T

NOT



Nand →

Not?42

NAND

a b nand

T T F

T F T

F T T

F F T



Nand →

Not43

a b nand

T T F

T F T

F T T

F F T

NAND



Not44

NAND

a b nand

T T F

F F T



AND



Only using & ?

46

NOT NAND



and47

a b and

T T T

T F F

F T F

F F F

AND



nand →

and?48

NAND

a b nand

T T F

T F T

F T T

F F T



and =

not nand

49

NAND

a b nand

T T F

T F T

F T T

F F T



and =

not not and

50

NAND

a b nand

T T F

T F T

F T T

F F T



and =

not not and

51

NAND

a b nand

T T F

T F T

F T T

F F T



NAND NOT nand-not

52

a b and

T T T

T F F

F T F

F F F



NAND NAND

and53

a b and

T T T

T F F

F T F

F F F



OR



Only using , , & ?

55

NOT

NAND

AND



or56

OR

a b or

T T T

T F T

F T T

F F F



De Morgan’s Law!

57



Venn Diagrams??!!

58


@the_zenspiderGoGaRuCo 3014http://en.wikipedia.org/wiki/Venn_diagram

Venn Diagrams??!!

58



Venn Diagrams!

59



Venn Diagrams!

59

http://thisisindexed.com/



Venn Diagrams!

60

A B



A | B

61

A B



A B

!(A | B)

62



!(A | B)

63

A B



(!A & !B)

64

A B



!(!A & !B)

65

A B



!(!A & !B) = A | B

66

A B



a | b67

OR

a b or

T T T

T F T

F T T

F F F



!(!a & !b)

68

a b or

T T T

T F T

F T T

F F F

NOT

NOT

AND NOT



not(and( not(a), not(b)))

69

a b or

T T T

T F T

F T T

F F F

NOT

NOT

AND NOT



not(and( not(a), not(b)))

70

a b or

T T T

T F T

F T T

F F F

NOT

NOT

AND NOT



NAND

NOT

NOT nand( not(a), not(b))

71

a b or

T T T

T F T

F T T

F F F



NAND

NOT

NOT nand( not(a), not(b))

72

a b or

T T T

T F T

F T T

F F F



nand( nand(a,a), nand(b,b))

73

a b or

T T T

T F T

F T T

F F F

NANDNAND

NAND



XOR



Only using , ,

& ?75

NOT NAND

ANDOR



a b xor

T T F

T F T

F T T

F F F

xor76

XOR



a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

77

AND

ANDOR



a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

77

AND

ANDOR



AND

ANDOR

NAND

NAND

a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

78



AND

ANDOR

NAND

NAND

a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

78



a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

79

OR

NAND

NAND

NAND NAND

NAND NAND



a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

79

OR

NAND

NAND

NAND NAND

NAND NAND



a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

80

NAND

NAND

NAND NAND

NAND NAND

NAND

NAND

NAND



NAND

NAND

NAND NAND

NAND NAND

NAND

NAND

NAND

a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

81



NAND

NAND

NAND

NAND

NAND

a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

82



NAND

NAND

NAND

NAND

NAND

a b xor

T T F

T F T

F T T

F F F

!

a & !b | !a & b

83



xor84

a b xor

T T F

T F T

F T T

F F F

NAND

NAND

NAND

NAND



mux

85



Muxes are Easy!mux = if sel then b else a end

86



Muxes are Easy!mux = if sel then b else a end

86

Just an if

stateme

nt!



mux87

mux

sel a b xorT T T TT T F FT F T TT F F FF T T TF T F TF F T FF F F F



mux88


mux



mux89


mux



mux90

AND

AND

OR




mux91

NAND

NAND

NAND




dmux



DMuxes are easy, kindaif sel then a = in else b = in end

93



dmux

dmux94

sel in a b

T T T F

T F F F

F T F T

F F F F



AND

AND

dmux95

sel in a b

T T T F

T F F F

F T F T

F F F F



dmux96

NAND NAND

NAND NAND

sel in a b

T T T F

T F F F

F T F T

F F F F



N-way Gates

97



or8way

98



or8waydef or8way a,b,c,d,e,f,g,h a || b || c || d || e || f || g || h end

99



OR

OR

OR

OR

OR

OR

OR



OR

OR

OR

OR

OR

OR

OR

ab

c

d

e

f

g

h

inpu

ts



OR

OR

OR

OR

OR

OR

OR

ab

c

d

e

f

g

h 1 output

inpu

ts



OR

OR

OR

OR

OR

OR

OR

ab

c

d

e

f

g

h 1 output

1

2

3

4

5

6

inpu

tsdepth/tim

e



OR

OR

OR

OR

OR

OR

OR



OR

OR

OR

OR

OR

OR

OR

ab

cd

ef

gh

inpu

ts



OR

OR

OR

OR

OR

OR

OR

ab

cd

ef

gh

1 output

inpu

ts



OR

OR

OR

OR

OR

OR

OR

ab

cd

ef

gh

1 output

inpu

ts1

2

depth/time



Muxes

102



mux4way

mux4way

103

2 bit selector



mux8way

3 bit selector

mux8way

104



dmux4way

dmux4way

105

2 bit selector



dmux8way

dmux8way

3 bit selector



“Trivial”107



Exercise for the

“Reader”108



Just Remember

109




110



16 Bit Logic & More

111



NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT

NOT



AND

AND

AND

AND

AND

AND

AND

AND

AND

AND

AND

AND

AND

AND

AND

AND



OR

OR

OR

OR

OR

OR

OR

OR

OR

OR

OR

OR

OR

OR

OR

OR



mux

mux

mux

mux

mux

mux

mux

mux

mux

mux

mux

mux

mux

mux

mux

mux



“Trivial”116



Exercise for the Reader

117



Boolean Arithmetic

118



Adders!

119



Not these Adders

120

https://www.flickr.com/photos/79818573@N04/14226945188



Nor Black Adder

121



Just Good, Simple,

Arithmetic!122



Adders, Elementary-School Style

123

11 +012




123

11 +01

A

2




123

11 +01

A

B2




123

11 +01

A

B

02




123

11 +01

A

B

Sum0

2




123

11 +01

1

A

B

Sum0

2




123

11 +01

1

A

B

Sum

Carry

02




123

11 +01

1

A

B

Sum

Carry

002




123

11 +01

11

A

B

Sum

Carry

002




123

11 +01

11

A

B

Sum

Carry

1 002



Adders

124

11 +01

11

A

B

Sum

Carry

1 00

half adder

2



11 +01

Adders

125

11

A

B

Sum

Cin

1 00

Carry

full adder

2



Half Adder

126

AND

XOR Sum

Carry

A

B



Full Adder

127

XOR XOR

AND

AND

OR

Sum

Carry

A

B

Cin



16-bit Adder

128



add16

129

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

FullAdder

0

x0

y0

x1

y1

s13

s14

s15

x2

y2

...

…



But Ryan!130



Doesn’t this have the same problem as or8way?

131



Why, Yes!132



Yes, it does!

133



What they don’t teach you in grade school…

134



Full Adder

135

XOR XOR

AND

AND

OR

Sum

Carry

A

B

Cin



XOR XOR

AND

AND

OR

Sum

Carry

A

B

Cin

Full Adder?

136



XOR XOR

AND

Sum

A

B

Cin

Propagate

Generate

OR

Partial Full Adder

137



S0S1S2S3P0P1P2P3

G0G1G2G3PFA

CLA

C0

A0 B0

PFA

A1 B1

PFA

A2 B2

PFA

A3 B3

C4

Add4

138



Add16

139

S0-3S4-7S8-11S12-15P0P1P2P3

G0G1G2G3add4

CLA

C0

A0-3 B0-3

add4

A4-7 B4-7

add4

A8-11 B8-11

add4

A12-15 B12-15

C4



Carry Lookahead Monster

140

cla2 (1

of 1)

c1x1

p3x1

p1x1g2x1

c3x1c2x1

p0x1g0x1

p2x1c0x1

c4x1

g3x1g1x1



Slightly Less Scary? (define (cla g0 g1 g2 g3 p0 p1 p2 p3 cin c1 c2 c3 pout gout) (let-values ([(w1c0 w1c1 w1c2) (wires w 3)] [(w2c1 w2c2) (wires w 2)] [(w3c2) (w)] [(w1g w2g w3g) (wires w 3)]) (append (list (comment (comment-cla))) (And p0 cin w1c0) (Or g0 w1c0 c1) ! (And p1 g0 w1c1) (and3 p1 p0 cin w2c1) (or3 g1 w1c1 w2c1 c2) ! (And p2 g1 w1c2) (and3 p2 p1 g0 w2c2) (and4 p2 p1 p0 cin w3c2) (or4 g2 w1c2 w2c2 w3c2 c3) ! (And p3 g2 w1g) (and3 p3 p2 g1 w2g) (and4 p3 p2 p1 g0 w3g) ! (or4 g3 w1g w2g w3g gout) (and4 p3 p2 p1 p0 pout))))

141



Slightly Less Scary? (define (cla g0 g1 g2 g3 p0 p1 p2 p3 cin c1 c2 c3 pout gout) (let-values ([(w1c0 w1c1 w1c2) (wires w 3)] [(w2c1 w2c2) (wires w 2)] [(w3c2) (w)] [(w1g w2g w3g) (wires w 3)]) (append (list (comment (comment-cla))) (And p0 cin w1c0) (Or g0 w1c0 c1) ! (And p1 g0 w1c1) (and3 p1 p0 cin w2c1) (or3 g1 w1c1 w2c1 c2) ! (And p2 g1 w1c2) (and3 p2 p1 g0 w2c2) (and4 p2 p1 p0 cin w3c2) (or4 g2 w1c2 w2c2 w3c2 c3) ! (And p3 g2 w1g) (and3 p3 p2 g1 w2g) (and4 p3 p2 p1 g0 w3g) ! (or4 g3 w1g w2g w3g gout) (and4 p3 p2 p1 p0 pout))))

141

No, not really.



Least Scary, Most Abstract

142

Ci = Gi + PiCi-1 Gi = AiBi Pi = Ai + Bi



Least Scary, Most Abstract

142

Ci = Gi + PiCi-1 Gi = AiBi Pi = Ai + Bi



Least Scary, Most Concrete

143

C1 = G0 + P0C0 C2 = G1 + P1G0 + P1P0C0 C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0



Least Scary, Most Concrete

143

C1 = G0 + P0C0 C2 = G1 + P1G0 + P1P0C0 C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

I can handle that…



Just Details

144



Incrementers

145



Inc16

146

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

Half Adder

1

i1

i2

i3

i4

o15

o14

o13

o12…

…



Faster, but Scarier

147

��

��

��

��

��

��

��

��

��

��

��

��

��

��

�

��

http://www.righto.com/2013/11/the-z-80s-16-bit-incrementdecrement.html



ALU

148



Arithmetic Logic Unit

149

f(x,y)ALU

zx zynx ny f no

zr ng

x

y

out




149

f(x,y)ALU

zx zynx ny f no

zr ng

x

y

out




149

f(x,y)ALU

zx zynx ny f no

zr ng

x

y

out




149

f(x,y)ALU

zx zynx ny f no

zr ng

x

y

out




149

f(x,y)ALU

zx zynx ny f no

zr ng

x

y

out



Arithmetic Logic UnitIN x[16], y[16], // 16-bit inputs zx, // zero the x input? nx, // negate the x input? zy, // zero the y input? ny, // negate the y input? f, // compute out = x+y (f=1) else x&y no; // negate the out output? !OUT out[16], // 16-bit output zr, // 1 if (out == 0), 0 otherwise ng; // 1 if (out < 0), 0 otherwise

150



Arithmetic Logic UnitIN x[16], y[16], // 16-bit inputs zx, // zero the x input? nx, // negate the x input? zy, // zero the y input? ny, // negate the y input? f, // compute out = x+y (f=1) else x&y no; // negate the out output? !OUT out[16], // 16-bit output zr, // 1 if (out == 0), 0 otherwise ng; // 1 if (out < 0), 0 otherwise

150

YUCK!



Arithmetic Logic UnitMux16(a=x, b=false, sel=zx, out=x2); Mux16(a=y, b=false, sel=zy, out=y2); !Not16(in=x2, out=notx2); // if (zx==1) set x = 0 Not16(in=y2, out=noty2); // if (zy==1) set y = 0 !Mux16(a=x2, b=notx2, sel=nx, out=x3); // if (nx==1) set x = ~x Mux16(a=y2, b=noty2, sel=ny, out=y3); // if (ny==1) set y = ~y !Add16(a=x3, b=y3, out=add16); // if (f==1) set out = x + y And16(a=x3, b=y3, out=and16); // if (f==0) set out = x & y Mux16(a=and16, b=add16, sel=f, out=out1); !Not16(in=out1, out=notout); Mux16(a=out1, b=notout, sel=no, out=out, // if (no==1) set out = ~out out[0..7]=out2a, out[8..15]=out2b, out[15]=ng); // if (out<0) set ng = 1 !Or8Way(in=out2a, out=outa); Or8Way(in=out2b, out=outb); Or(a=outa, b=outb, out=nzr); !Not(in=nzr, out=zr); // if (out==0) set zr = 1




YUCK!Mux16(a=x, b=false, sel=zx, out=x2);

Mux16(a=y, b=false, sel=zy, out=y2); !Not16(in=x2, out=notx2); // if (zx==1) set x = 0 Not16(in=y2, out=noty2); // if (zy==1) set y = 0 !Mux16(a=x2, b=notx2, sel=nx, out=x3); // if (nx==1) set x = ~x Mux16(a=y2, b=noty2, sel=ny, out=y3); // if (ny==1) set y = ~y !Add16(a=x3, b=y3, out=add16); // if (f==1) set out = x + y And16(a=x3, b=y3, out=and16); // if (f==0) set out = x & y Mux16(a=and16, b=add16, sel=f, out=out1); !Not16(in=out1, out=notout); Mux16(a=out1, b=notout, sel=no, out=out, // if (no==1) set out = ~out out[0..7]=out2a, out[8..15]=out2b, out[15]=ng); // if (out<0) set ng = 1 !Or8Way(in=out2a, out=outa); Or8Way(in=out2b, out=outb); Or(a=outa, b=outb, out=nzr); !Not(in=nzr, out=zr); // if (out==0) set zr = 1









My Mind,

She Asplodes!





Mux16(a=y2, b=noty2, sel=ny, out=y3); // if (ny==1) set y = ~y !Add16(a=x3, b=y3, out=add16); // if (f==1) set out = x + y And16(a=x3, b=y3, out=and16); // if (f==0) set out = x & y Mux16(a=and16, b=add16, sel=f, out=out1); !Not16(in=out1, out=notout); Mux16(a=out1, b=notout, sel=no, out=out, // if (no==1) set out = ~out out[0..7]=out2a, out[8..15]=out2b, out[15]=ng); // if (out<0) set ng = 1 !Or8Way(in=out2a, out=outa); Or8Way(in=out2b, out=outb); Or(a=outa, b=outb, out=nzr); !Not(in=nzr, out=zr); // if (out==0) set zr = 1152

My Mind,

She Asplodes!



b0-7

b8-15

mux

mux

mux mux

mux muxNOT

NOT

NOT AND

add16

OR8

OR8

OR

out

zr

0

zy

0

y

x

zx

nx

ny

fno

ng

b15


153



b0-7

b8-15

mux

mux

mux mux

mux muxNOT

NOT

NOT AND

add16

OR8

OR8

OR

out

zr

0

zy

0

y

x

zx

nx

ny

fno

ng

b15


153



b0-7

b8-15

mux

mux

mux mux

mux muxNOT

NOT

NOT AND

add16

OR8

OR8

OR

out

zr

0

zy

0

y

x

zx

nx

ny

fno

ng

b15


153

Always

Both



b0-7

b8-15

mux

mux

mux mux

mux muxNOT

NOT

NOT AND

add16

OR8

OR8

OR

out

zr

0

zy

0

y

x

zx

nx

ny

fno

ng

b15


153

Always

Both



b0-7

b8-15

mux

mux

mux mux

mux muxNOT

NOT

NOT AND

add16

OR8

OR8

OR

out

zr

0

zy

0

y

x

zx

nx

ny

fno

ng

b15


153

Always

Both Multiple &

Partial!!



f(x,y)

zx zynx ny f no

zr ng

x

y

out


154

b0-7

b8-15

mux

mux

mux mux

mux muxNOT

NOT

NOT AND

add16

OR8

OR8

OR

out

zr

0

zy

0

y

x

zx

nx

ny

fno

ng

b15



6 little flags = Instruction set

155

01 -1x y

!x !y-x -y

x+1 y+1x-1 y-1x+yx-y y-xx&y x|y



ALU in 440 NAND Gates By Mark Armbrust w/ Koen Simmons’ optimizations.

via forums for nand2tetris

156





156





156





156



Sequential Logic

157



Combinational vs

Sequential158



SomeLogicin out

Combinational Chips

159



InputLogic

OutputLogicMemoryin out

Sequential Chips

160



InputLogic


Sequential Chips

160Clock Input



DFF

161



DFF “Magic” Logic:

out(t) = in(t-1)

162



Atomic in nand2tetris

163



Can be created with nands!

164



Building a DFF using the TECS Hardware Simulator, by Mark Armbrust.

http://www.marksmath.com/tecs/dff/

From NAND to DFF

165






From NAND to DFF

165

NAND

NAND






From NAND to DFF

165

NAND

NAND

NAND

NAND

NAND

NAND






From NAND to DFF

165

NAND

NAND

NAND

NAND

NAND

NAND

NAND

NAND

NAND

NAND

NAND

NAND

NAND

NAND

NOT




!

Details166

Just



!

Details166

Interesting



bit

load

in out

167



bitbit(t) = if load then in else bit(t-1) end !return bit(t)

168

bit

load

in out



dff(t) = if load then in else dff(t-1) end !return dff(t)

bit

load

in outdff

bit

169



dff(t) = if load then in else dff(t-1) end !return dff(t)

load

inout mux dff

bit

170



register

load

in out



load

in outbit0 bit1 bit15…

register

172



bit0

load

in0 out0

bit1in1 out1

bit2in2 out2

…inN outN

bit15in15 out15

Simple Linear Layout

173



RAMn

in

load

addr

out



in

load

addr

out

register

load

in out

register

load

in out

register

load

in out

register

load

in out

…

175



InputLogic


Sequential Logic

176

register

load

in out

register

load

in out

register

load

in out

register

load

in out

…Addressing Addressing



InputLogic


RAM8

177

register

load

in out

register

load

in out

register

load

in out

register

load

in out

…dmux8way mux8way



DFFBit

RegisterRam8Ram64Ram512Ram4KRam16K


178



DFFBit

RegisterRam8Ram64Ram512Ram4KRam16K


178

×8

×8

×8

×8

×4

1bit×16



RAM64+?179



Again180



Exercise for the

“Reader”181



outcounter

load

in

resetincr

182



AKA Program Counter

183



Addresses current instruction

in ROM184



RegisterInc16

Mux16

reset load inc

0

in

outMux16AND

AND

OR

OR

Mux16

185



RegisterInc16

Mux16

reset load inc

0

in

outMux16AND

AND

OR

OR

Mux16

185

Blah Blah Logic



RegisterInc16

Mux16

reset load inc

0

in

outMux16AND

AND

OR

OR

Mux16

185

The Magic

Blah Blah Logic




186



Memory

code&

data

CPUInput

Output

ALU

Registers

Control



cpu

188

CPU

outM

writeM

addressM

pc

inM

instruction

reset



CPU Guts

?189



address outROM32K

rom32k

190



outKeyboard

keyboard

191



screen

192

load outScreen8K words

in

address



keyboard

addr

in

RAM

Screen

Keyboard

out

screen

Memory

193



Memory

code&

data

CPUInput

Output

ALU

Registers

Control



computer

195

address outROM32K

CPU

outM

writeM

addressM

pc

inM

instruction

reset

keyboard

addr

in

RAM

Screen

Keyboard

out

screen



Let’s Go Home!

196



apollo guidance computer197



Julian Simioni, MWRC 2014Software Development Lessons from the

Apollo Program

16-bit words.

Most software in ROM

Never had an error in flight.

http://www.ibiblio.org/apollo/ to fly your own.

198

http://www.ibiblio.org/apollo/



2,800 dual 3-input

NOR ICs!!199

http://upload.wikimedia.org/wikipedia/commons/1/13/Agc_flatp.jpg



Thank You200

Documents

Let's Build a Computer - zenspider.comryan/presentations/2014_gogaruco_lets_build… · Sous-Chef 3. Sous-Chef 3 Assistant. 4. ISS Icarus 4. 5. Unfortunate Accident 5. 6. Phase Matter