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LHC Detector Upgrades
Su Dong
SLAC Summer Institute Aug/2/2012
1 LHC Detector Upgrades
LHC is exceeding expectations in many ways
2 LHC Detector Upgrades
Rapid increase in luminosity Even more dramatic pileup challenge
Z->µµ event with 25 pileup vertices
Design lumi 1x1034
Design pileup <µ>~24
LHC Roadmap
3 LHC Detector Upgrades
The Path to High Luminosity
4 LHC Detector Upgrades
LHC reached today’s performance at a much faster pace than anyone could have anticipated.
LHC took a somewhat different path to reach today’s performance with a somewhat different configuration compared to the original design.
LHC detectors performed remarkably well to survive the challenge of rapid luminosity increase (and the even more rapid pileup growth).
Are we going to be as lucky for the next phase of luminosity challenge ?
Do we have solutions for the upcoming challenges ? Current LHC detectors took >10 years to build. Do we have
a timely strategy ?
LHC Configuration Scenarios
Config year
Bunch/spacing
Bunch /Beam
Protons /bunch
εn (µm)
Xing angle
(µRad)
β* (m)
Peak L (cm-2 s-1)
Mean Pileup Events
design 25ns 2808 1×1011 3.75 280 0.55 1.0x1034 25.5
`Phase-0’ 50ns 1404 1.7×1011 2.5 270 0.5 1.7x1034 86
+LINAC4 50ns 1404 2.5×1011 3.75 320 0.5 2.5x1034 125
`Phase-2’ 25ns 2808 2.0×1011 2.5 420 0.2 6.9x1034 173
`Phase-2’ 50ns 1408 3.3×1011 3.75 520 0.2 6.2x1034 311
5
Phase-2 Based on Oliver Bruning’s Charmonix-2011 projections
Some Known Limitations
Degraded performance of silicon sensors close to interactions point due to radiation damage.
Data bandwidth bottlenecks at various stages of data pipeline due to the nonlinear Luminosity*Occupancy growth.
L1 calorimeter trigger segmentation granularity limiting background suppression performance.
L1 muon trigger fake suppression capability. L1 muon Pt resolution preventing raising Pt threshold
beyond ~40 GeV. Tracking pattern recognition fake rate at high occupancy.
6 LHC Detector Upgrades
Phase 0/1 Pixel Detectors
Insertable B-Layer (IBL) to be installed in 2014 inside present pixel detector
ATLAS IBL (phase-0) CMS new Pixel (phase-1)
7 LHC Detector Upgrades
Complete replacement of pixel system in 2018
ATLAS Pixel Insertable B-Layer (IBL)
First hit at R=33mm (Present B-layer at R=55mm) Pixel size 100x250µm (Present pixel 100x400µm) IBL later material ~1.5% (Present pixel ~3%/layer)
8 LHC Detector Upgrades
d0 z0
1 GeV trk 1 GeV trk
ATLAS IBL
9 LHC Detector Upgrades
64cm
Source test
3D Silicon Sensors
Original proposal by Sherwood Parker
10 LHC Detector Upgrade
Initial pioneering R&D at Stanford Nanofabrication Facility. 3D sensors on IBL is the first HEP application.
IBL stave
Primary candidate sensor pixel upgrade innermost layer Radiation hard, active edge
pixel cell
n+ p+
75o
90o
Pixel Upgrade b-tag performance
11 DOE Lab Energy Frontier Comparative Review 2012
4-Layer Pixel with IBL
3-Layer Pixel
ATLAS IBL CMS new pixel
CMS Phase-1 Pixel
12 LHC Detector Upgrades
HL-LHC Tracking Upgrade
13 LHC Detector Upgrades
L = 1x1033
Tracking at HL-LHC
14 LHC Detector Upgrades
L = 5x1034
HL-LHC Tracker
15 LHC Detector Upgrades
ATLAS Phase-2 Tracker Layout Study
All silicon tracking: typically 10 double-sided Si strip hits + 4 pixel hits; |η|<2.5
Tracker Implementation Desires
Would like to have infinitesimal granularity for best resolution
Should only consume minimal power Should be extremely light in material It should be very radiation hard Has infinite bandwidth for shipping data There should be just a few cables to connect It’s better to only cost pocket change
16 LHC Detector Upgrades
The R&D Work for Reality
17 LHC Detector Upgrades
CMS strip tracker end cap Just before for installation...
CO2 cooling
DC-DC
2mm
Data Transmission
ATLAS Phase-1 Muon Small Wheel
18 LHC Detector Upgrades
New small wheel MicroMegas + sTGC For precision Pt and trigger
nSW
CMS Phase-1 Muon Trigger
19 LHC Detector Upgrades
Complete instrumentation of the staged ME4 chambers
L1 Muon Pt Threshold Problem
L1 rate at HL-LHC forces the raise of L1 muon Pt threshold, but resolution limitation would result in random removal of all high Pt muons if threshold exceeds ~30 GeV.
L1 track (+mu) trigger to improve Pt resolution (CMS, ATLAS)
L1 muon trigger with MDT (ATLAS) 20 LHC Detector Upgrades
ATLAS is similar with RPC,TGC only L1 trigger
CMS
L1 Track Trigger for HL-LHC
Many possible different topologies but implementations all very difficult.
21 LHC Detector Upgrades
Phase-2 Trigger Strategy
22 LHC Detector Upgrade
Time (µs)
Much less demanding than self-seeded L1 track trigger working 40Mhz => more versatile L1 track trigger
L0 ~500 Khz L1 ~200 Khz L1 algorithm only using data from ROIs in L0 trigger
ATLAS L1 Muon Trigger with MDT
23 LHC Detector Upgrades
xTCA platform for Trigger & DAQ
24 LHC Detector Upgrades
CMS current trigger plant CMS µTCA trigger shelf
ATCA = Advanced Telecommunication Computing Architecture
25
Reconfigurable Cluster Element Concept
Resources per RCE
Xilinx Virtex 5 FX70 FPGA with built-in crossbar & user firmware application space
4 GByte memory
6 channels of data I/O up to 12.5 Gb/s per channel.
40 Gb/s Ethernet network output
128 DSP tiles
LHC Detector Upgrades
DPM2DPM2 DPM3DPM1
RTM
IPMCfront panel
RCE5 RCE6RCE3 RCE4 RCE7 RCE8RCE1 RCE2
front panel
DTM
RCE switch
baseclock fabric P1
Shelf Back-Plane
1-40 GE
1-40 GE 1-12.5 gbits/sec
1-40 GE
1 GE
26
Cluster On Board (COB) V4
4 Data Processing Modules (DPM) Dual RCE (6 MGT), or Single RCE (6 MGT),
or Single RCE (30 slow
I/O ports) 1 Data Transport Module (DTM) 1 control RCE 24 port x 40G
switching capacity 2x40Gb/s Ethernet
port Front TTC interface
(FTM) Rear Transition Module (RTM): User interface via P3
P3
P2
LHC Detector Upgrades
24-port 10-GE switch
IPMI controller
PICMG 3.8 P3 with 120 pairs of user I/O
FTM (to be built) for TTC interface
1 of 4 DPMs (with GEN-I RCEs)
COB (V4) with Gen-I Mezzanine
27
DTM
Power/ J-tag/ I2C
LHC Detector Upgrades
28
Ethernet topology in a 14-slot ATCA shelf
f r ont panel
DPM2
RCE 5
RCE 6DPM2
RCE 3
RCE 4
DPM3
RCE 7
RCE 8
DPM1
RCE 1
RCE 2
DTM
RTM
f ront panel
DPM 2
RCE5
RCE6
DPM 2
RCE3
RCE4
DPM 3
RCE7
RCE8
DPM 1
RCE1
RCE2 DT
M
RTM
f ron
t pan
el
DPM 2
RCE 5
RCE 6
DPM 2
RCE 3
RCE 4
DPM 3
RCE 7
RCE 8
DPM 1
RCE 1
RCE 2
DTM
RTM
f r ont panel
DPM2
RCE5 RCE
6
DPM2
RCE3 RCE
4
DPM3
RCE7 RCE
8
DPM1
RCE1 RCE
2
DTM
RTM
f ront panel
DPM2
RCE5
RCE6
DPM2
RCE3
RCE4
DPM3
RCE7
RCE8
DPM1
RCE1
RCE2
DTM
RTM
f ront panel
DPM2
RCE5
RCE6
DPM2
RCE3
RCE4
DPM3
RCE7
RCE8
DPM1
RCE1
RCE2
DTM
RTM
f ront panel
DPM2
RCE5
RCE6
DPM2
RCE3
RCE4
DPM3
RCE7
RCE8
DPM1
RCE1
RCE2
DTM
RTM
front panel
DPM2
RCE5
RCE6 DPM2
RCE3
RCE4
DPM3
RCE7
RCE8
DPM1
RCE1
RCE2
DTM
RTM
f ron
t pan
el
DPM
2
RCE 5
RCE 6
DPM
2
RCE 3
RCE 4
DPM
3
RCE 7
RCE 8
DPM
1
RCE 1
RCE 2
DTM
RTM
fron
t pan
el
DPM
2
RCE5
RCE6
DPM
2
RCE3
RCE4
DPM
3
RCE7
RCE8
DPM
1
RCE1
RCE2
DTM
RTM
front panel
DPM2
RCE5
RCE6
DPM2
RCE3
RCE4
DPM3
RCE7
RCE8
DPM1
RCE1
RCE2
DTM
RTM
front panel
DPM2
RCE5RCE6
DPM2
RCE3RCE4
DPM3
RCE7RCE8
DPM1
RCE1RCE2
DTM
RTM
front panel
DPM2
RCE5
RCE6
DPM2
RCE3
RCE4
DPM3
RCE7
RCE8
DPM1
RCE1
RCE2
DTM
RTM
front panel
DPM2
RCE5
RCE6
DPM2
RCE3
RCE4
DPM3
RCE7
RCE8
DPM1
RCE1
RCE2DTM
RTM
1-40 GE x 28 40 GE
The full mesh ATCA backplane: Any slot has 40Gb/s bandwidth with each other slot in the shelf simultaneously. Compare to VME as single bus of 40MB/s
LHC Detector Upgrades