Lic Manual

Department of Electronics and Communication Engineering

Lab Manual

EE6311 LINEAR AND DIGITAL INTEGRATED CIRCUITSLABORATORY

Page 1

Exp No. 1a STUDY OF LOGIC GATES

AIM:

To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. AND gate IC 7408 13. OR gate IC 7432 14. NOT gate IC 7404 15. NAND gate IC 7400 16. NOR gate IC 7402 17. EX-OR gate IC 7486 18. Connecting wires As required

THEORY:

a. AND gate:

An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of ‘1’ only if all the input signals are ‘1’.

b. OR gate:

An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.

c. NOT gate:

A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input.

Page 2

AND GATE

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408 :

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = A . B1. 0 0 02. 0 1 0

Page 3

3. 1 0 04. 1 1 1

OR GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = A + B

Page 4

1. 0 0 02. 0 1 13. 1 0 14. 1 1 1

NOT GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A Y = A’

Page 5

1. 0 12. 1 0

NAND GATE

LOGIC DIAGRAM:


CIRCUIT DIARAM:

Page 6

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = (A . B)’1. 0 0 12. 0 1 13. 1 0 14. 1 1 0

NOR GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

Page 7

TRUTH TABLE:

S.No INPUT OUTPUTA B Y = (A + B)’

1. 0 0 12. 0 1 03. 1 0 04. 1 1 0

EX-OR GATE

LOGIC DIAGRAM


CIRCUIT DIAGRAM:

Page 8

TRUTH TABLE:

S.NoINPUT OUTPUT

A B Y = AB1. 0 0 02. 0 1 13. 1 0 14. 1 1 0

d. NAND gate:

A NAND gate is a complemented AND gate. The output of the NAND gate will be ‘0’ if all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.

e. NOR gate:

A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all the inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.

f. EX-OR gate:

An Ex-OR gate performs the following Boolean function,

A B = ( A . B’ ) + ( A’ . B )

It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal ‘0’ when the two input signals are equal either ‘0’ or ‘1’.

PROCEDURE:

1. Connections are given as per the circuit diagram1. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 2. Apply the inputs and verify the truth table for all gates.

Page 9

RESULT:

The truth table of all the basic digital ICs were verified.

Exp No. 2a HALF ADDER & FULL ADDER

AIM:

To design and verify the truth table of the Half Adder & Full Adder circuits.

APPARATUS REQUIRED:

Page 13

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. AND gate IC 74083. OR gate IC 74324. NOT gate IC 74045. EX-OR gate IC 74866. Connecting wires As required

THEORY:

The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely,

0 + 0 = 00 + 1 = 11 + 0 = 11 + 1 = 102

The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum.

HALF ADDER:

A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate.

HALF ADDER

TRUTH TABLE:

S.NoINPUT OUTPUT

A B S C1. 0 0 0 02. 0 1 1 03. 1 0 1 04. 1 1 0 1

Page 14

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum, S = A BCarry, C = A . B

CIRCUIT DIAGRAM:

FULL ADDER

TRUTH TABLE:

S.No INPUT OUTPUTA B C SUM CARRY

1. 0 0 0 0 02. 0 0 1 1 03. 0 1 0 1 04. 0 1 1 0 15. 1 0 0 1 06. 1 0 1 0 17. 1 1 0 0 18. 1 1 1 1 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,

SUM = A’B’C + A’BC’ + AB’C’ + ABCCARRY = A’BC + AB’C + ABC’ +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

Page 15

SUM

SUM = A’B’C + A’BC’ + AB’C’ + ABC = A B C

CARRY

CARRY = AB + AC + BC

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

Page 16

RESULT:

The design of the half adder and full adder circuits was done and their truth tables were verified.

2.b. HALF SUBTRACTOR & FULL SUBTRACTOR

Page 17

AIM:

To design and verify the truth table of the Half Subtractor & Full Subtractor circuits.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. AND gate IC 74083. OR gate IC 74324. NOT gate IC 74045. EX-OR gate IC 74866. Connecting wires As required

THEORY:

The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely,

0 - 0 = 00 - 1 = 1 with 1 borrow1 - 0 = 11 - 1 = 0

In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.

HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits.

FULL SUBTRACTOR:

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.

HALF SUBTRACTOR

Page 18

TRUTH TABLE:

S.NoINPUT OUTPUT

A B DIFF BORR1. 0 0 0 02. 0 1 1 13. 1 0 1 04. 1 1 0 0

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF = A BBorrow, BORR = A’ . B

CIRCUIT DIAGRAM:

FULL SUBTRACTORTRUTH TABLE:

S.NoINPUT OUTPUT

A B C DIFF BORR1. 0 0 0 0 02. 0 0 1 1 13. 0 1 0 1 14. 0 1 1 0 15. 1 0 0 1 06. 1 0 1 0 07. 1 1 0 0 08. 1 1 1 1 1

Page 19

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be obtained as,

Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABCBorrow, BORR = A’BC + AB’C + ABC’ +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

DIFFERENCE

DIFF = A’B’C + A’BC’ + AB’C’ + ABC = A B C

BORROW

BORR = A’B + A’C + BC

Page 20

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half subtractor and full subtractor

circuits.

RESULT:

The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.

Page 21

2.c. IMPLEMENTATION OF BOOLEAN FUNCTIONS

AIM:

To design the logic circuit and verify the truth table of the given Boolean expression, F (A,B,C,D) = Σ (0,1,2,5,8,9,10)

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. AND gate IC 74083. OR gate IC 74324. NOT gate IC 74045. NAND gate IC 74006. NOR gate IC 74027. EX-OR gate IC 74868. Connecting wires As required

DESIGN:

Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10)

The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a simplified expression for the output as shown,

From the K-Map,

Page 22

F = B’ C’ + D’ B’ + A’ C’ DSince we are using only two input logic gates the above expression can be re-written as, F = C’ (B’ + A’ D) + D’ B’Now the logic circuit for the above equation can be drawn.

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.NoINPUT OUTPUT

A B C D F=D’B’+C’(B’+A’D)1. 0 0 0 0 12. 0 0 0 1 13. 0 0 1 0 14. 0 0 1 1 05. 0 1 0 0 06. 0 1 0 1 17. 0 1 1 0 08. 0 1 1 1 0

Page 23

9. 1 0 0 0 110. 1 0 0 1 111. 1 0 1 0 112. 1 0 1 1 013. 1 1 0 0 014. 1 1 0 1 015. 1 1 1 0 016. 1 1 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagram 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the given Boolean expression.

RESULT:

The truth table of the given Boolean expression was verified.

Page 24

Exp No.3 CODE CONVERTERS

AIM :

To construct and verify the truth table of Binary to Gray code, Gray to Binary Code, BCD to Excess-3 code converter circuits.

APPARATUS REQUIRED:

S.NO Particular Name SPECIFICATION QUANTITY1 Digital IC trainer kit ---- 12 IC 7486 QUAD 33 IC 7404 QUAD 14 Connecting Wires

PROCEDURE:

1. Give connections as per the circuit diagram 2. Inputs are given to the circuit making high ‘1’ i.e. +5 V or

+ Vcc supply to the 14th pin and for low ‘0’ i.e. GND to the 7th

pin of gate IC 3. Verify the truth table as given for all the code converter

Page 25

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUTS(Binary Code) OUTPUTS (Gray Code)

B3 B2 B1 B0 G3 G2 G1 G00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

Page 26

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUTS(Gray Code) OUTPUTS(Binary Code)G3 G2 G1 G0 B3 B2 B1 B00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 0

Page 27

1 1 0 11 1 1 01 1 1 1

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUTS(BCD Code) OUTPUTS(Binary Code)A B C D B3 B2 B1 B00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 0

Page 28

RESULT:The code converter circuits are all constructed and truth table is verified.

3.b. PARITY GENERATOR & CHECKER

AIM:

To design and verify the truth table of a three bit Odd Parity generator and checker.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 1

Page 29

2. EX-OR gate IC 74863. NOT gate IC 74044. Connecting wires As required

THEORY:

A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker.

In even parity the added parity bit will make the total number of 1’s an even amount and in odd parity the added parity bit will make the total number of 1’s an odd amount.In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission.

Since the information was transmitted with odd parity the four bits received must have an odd number of 1’s. An error occurs during the transmission if the four bits received have an even number of 1’s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1’s.

ODD PARITY GENERATOR

TRUTH TABLE:

INPUT OUTPUTS.No ( Three bit message) ( Odd Parity bit)

A B C P

Page 30

1. 0 0 0 12. 0 0 1 03. 0 1 0 04. 0 1 1 15. 1 0 0 06. 1 0 1 17. 1 1 0 18. 1 1 1 0

From the truth table the expression for the output parity bit is,

P( A, B, C) = Σ (0, 3, 5, 6)

Also written as,

P = A’B’C’ + A’BC + AB’C + ABC’ = (A B C) ‘

CIRCUIT DIAGRAM:

ODD PARITY GENERATOR

Page 31

ODD PARITY CHECKER

TRUTH TABLE:

INPUTOUTPUT

( four bit messageS.No (Parity error check)

Received )A B C P X

1. 0 0 0 0 12. 0 0 0 1 03. 0 0 1 0 04. 0 0 1 1 15. 0 1 0 0 06. 0 1 0 1 17. 0 1 1 0 18. 0 1 1 1 09. 1 0 0 0 010. 1 0 0 1 111. 1 0 1 0 112. 1 0 1 1 013. 1 1 0 0 114. 1 1 0 1 015. 1 1 1 0 016. 1 1 1 1 1

From the truth table the expression for the output parity checker bit is,

X (A, B, C, P) = Σ (0, 3, 5, 6, 9, 10, 12, 15)

The above expression is reduced as,

X = (A B C P) ‘

Page 32

CIRCUIT DIAGRAM:

ODD PARITY CHECKER

PROCEDURE:

1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the Parity generator and checker.

RESULT:

The design of the three bit odd Parity generator and checker circuits was done and their truth tables were verified.

Page 33

Expt. No. 4 MULTIPLEXER & DEMULTIPLEXER

AIM:

To design and verify the truth table of a 4X1 Multiplexer & 1X4

Demultiplexer. APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. OR gate IC 74323. NOT gate IC 74044. AND gate ( three input ) IC 74115. Connecting wires As required

THEORY:

Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine which input is selected. Therefore, multiplexer is ‘many into one’ and it provides the digital equivalent of an analog selector switch.

A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines.

Page 34

DESIGN:4 X 1 MULTIPLEXER

LOGIC SYMBOL:

TRUTH TABLE:

S.No SELECTION INPUT OUTPUTS1 S2 Y

1. 0 0 I0

2. 0 1 I1

3. 1 0 I2

4. 1 1 I3

PIN DIAGRAM OF IC 7411:

Page 35

CIRCUIT DIAGRAM:

1X4 DEMULTIPLEXER

LOGIC SYMBOL:

Page 36

TRUTH TABLE:

S.NoINPUT OUTPUT

S1 S2 Din Y0 Y1 Y2 Y31. 0 0 0 0 0 0 02. 0 0 1 1 0 0 03. 0 1 0 0 0 0 04. 0 1 1 0 1 0 05. 1 0 0 0 0 0 06. 1 0 1 0 0 1 07. 1 1 0 0 0 0 08. 1 1 1 0 0 0 1

CIRCUIT DIAGRAM:

Page 37

PROCEDURE:

1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer.

RESULT:

The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables were verified.

Page 38

Expt. No. 5 ASYNCHRONOUS DECADE COUNTER

AIM:

To implement and verify the truth table of an asynchronous decade counter.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

Page 39

1. Digital IC trainer kit 12. JK Flip Flop IC 7473 24. NAND gate IC 7400 15. Connecting wires As required

THEORY:

Asynchronous decade counter is also called as ripple counter. In a ripple counter the flip flop output transition serves as a source for triggering other flip flops. In other words the clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the transition that occurs in other flip flops. The term asynchronous refers to the events that do not occur at the same time. With respect to the counter operation, asynchronous means that the flip flop within the counter are not made to change states at exactly the same time, they do not because the clock pulses are not connected directly to the clock input of each flip flop in the counter.


CIRCUIT DIAGRAM:

Page 40

TRUTH TABLE:

S.NoCLOCK OUTPUTPULSE D(MSB) C B A(LSB)

1 - 0 0 0 02 1 0 0 0 13 2 0 0 1 04 3 0 0 1 15 4 0 1 0 06 5 0 1 0 17 6 0 1 1 08 7 0 1 1 19 8 1 0 0 010 9 1 0 1 011 10 0 0 0 0

PROCEDURE:1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter.

RESULT:The truth table of the Asynchronous decade counter was hence verified.

Page 41

6. DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM:

To design and implement encoder and decoder using logic gates and study of IC

7445 and IC 74147.

APPARATUS REQUIRED:

SL.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2

2. OR GATE IC 7432 3

3. NOT GATE IC 7404 1

4. IC TRAINER KIT - 1

5. PATCH CORDS - 27

THEORY:ENCODER:

An encoder is a digital circuit that performs inverse operation of a decoder. An

encoder has 2n input lines and n output lines. In encoder the output lines generates the binary

code corresponding to the input value. In octal to binary encoder it has eight inputs, one for

each octal digit and three output that generate the corresponding binary code. In encoder it is

assumed that only one input has a value of one at any given time otherwise the circuit is

meaningless. It has an ambiguity that when all inputs are zero the outputs are zero. The zero

outputs can also be generated when D0 = 1.

DECODER:

A decoder is a multiple input multiple output logic circuits which converts coded

input into coded output where input and output codes are different. The input code generally

has fewer bits than the output code. Each input code word produces a different output code

word i.e there is one to one mapping can be expressed in truth table. In the block diagram of

decoder circuit the encoded information is present as n input producing 2n possible outputs.

2n output values are from 0 through out 2n – 1.

PIN DIAGRAM FOR IC 7445:

BCD TO DECIMAL DECODER:

Page 42

PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:

Page 43

TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

Page 44

TRUTH TABLE:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Page 45

Thus design and implementation of encoder and decoder circuits were performed

using logic gates and IC 7445 and IC 74147 were studied.

Expt. No. 6a IMPLEMENTATION OF SHIFT REGISTERS

AIM:

To implement and verify the truth table of a serial in serial out shift register.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Digital IC trainer kit 12. D Flip Flop IC 7474 23. Connecting wires As required

THEORY:

A register capable of shifting its binary information either to the left or to the right is called a shift register. The logical configuration of a shift register consists of a chain of flip flops connected in cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse which causes the shift from one stage to the next.

The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines, what goes into the right most flip flop during the shift. The serial output is taken from the output of the left most flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift register can function either as a shift right or a shift left register.


Page 46

CIRCUIT DIAGRAM:

Page 47

TRUTH TABLE:

For a serial data input of 1101,

S.NO CLOCK INPUTS OUTPUTSPULSE D1 D2 D3 D4 Q1 Q2 Q3 Q4

1 1 1 X X X 1 X X X2 2 1 1 X X 1 1 X X3 3 0 1 1 X 0 1 1 X4 4 1 0 1 1 1 0 1 15 5 X 1 0 1 X 1 0 16 6 X X 1 0 1 X 1 07 7 X X X 1 0 X X 18 8 X X X X X X X X

PROCEDURE:

1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter.

RESULT:

The truth table of a serial in serial out left shift register was hence verified.

6b. DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM:To design and implement(i) Serial in serial out (ii) Serial in parallel out (iii) Parallel in serial out (iv) Parallel in parallel out.

APPARATUS REQUIRED:

SL.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

Page 48

4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-Flip flop

cascaded with output of one flip flop connected to input of next flip flop. All flip flops

receive common clock pulses which causes the shift in the output of the flip flop. The

simplest possible shift register is one that uses only flip flop. The output of a given flip flop

is connected to the input of next flip flop of the register. Each clock pulse shifts the content

of register one bit position to right.

PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

Page 49

TRUTH TABLE:

Serial in Serial out

CLK

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1

LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE:

OUTPUT

CLK DATA QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

Page 50

3 0 0 0 1 1

4 1 1 0 0 1

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

Page 51

TRUTH TABLE:

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus the various types of Shift Registers were designed and implemented using IC7474.

Page 52

Expt. No.7 Op-amp Applications

a. INVERTING AMPLIFIER

AIM:

To design an Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Op-Amp IC 741 15. Bread Board 16. Resistors As required7. Connecting wires and probes As required

THEORY:

The input signal Vi is applied to the inverting input terminal through R1 and the non-inverting input terminal of the op-amp is grounded. The output voltage Vo is fed back to the inverting input terminal through the Rf - R1 network, where Rf is the feedback resistor. The output voltage is given as,

Page 53

Vo = - ACL Vi

Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal.

PROCEDURE:

1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator,

appropriate input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage

waveforms are plotted in a graph sheet.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

Page 54

DESIGN:

We know for an inverting Amplifier ACL = RF / R1

Assume R1 ( approx. 10 KΩ ) and find RfHence Vo = - ACL Vi

OBSERVATIONS:

S.No InputOutput

Practical Theoretical

1.Amplitude( No. of div x Volts per div )

2.Time period( No. of div x Time per div )

MODEL GRAPH:

Inverting amp

Vin

(V)t(sec)

Vo

(V)

t(sec)

Page 55

RESULT:

The design and testing of the inverting amplifier is done and the input and output waveforms were drawn.

b. NON - INVERTING AMPLIFIER

AIM:

To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Op-Amp IC 741 15. Bread Board 16. Resistors As required7. Connecting wires and probes As required

THEORY:

The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies the signal without inverting the input signal. It is also called negative feedback system since the output is feedback to the inverting input terminals. The differential voltage Vd at the inverting input terminal of the op-amp is zero ideally and the output voltage is given as,

Vo = ACL Vi

Here the output voltage is in phase with the input signal.

PROCEDURE:

1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.

Page 56

3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the non - inverting input terminal of the Op-Amp.

4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

DESIGN:

We know for a Non-inverting Amplifier ACL = 1 + ( RF / R1)Assume R1 ( approx. 10 KΩ ) and find RfHence Vo = ACL Vi

OBSERVATIONS:

Page 57

S.No InputOutput

Practical Theoretical



MODEL GRAPH:

Non-Inverting amp

Vin

(V)

Vo

t(sec)

(V)

t(sec)

RESULT:

The design and testing of the Non-inverting amplifier is done and the input and output waveforms were drawn.

c. DIFFERENTIATOR

AIM:

To design a Differentiator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Op-Amp IC 741 15. Bread Board 1

Page 58

6. Resistors7. Capacitors8. Connecting wires and probes As required

THEORY:

The differentiator circuit performs the mathematical operation of differentiation; that is, the output waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor C1 . The expression for the output voltage is given as,

Vo = - Rf C1 ( dVi /dt )

Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for the input bias current. A workable differentiator can be designed by implementing the following steps:

1. Select fa equal to the highest frequency of the input signal to be differentiated. Then, assuming a value of C1 < 1 µF, calculate the value of Rf.

2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.

The differentiator is most commonly used in waveshaping circuits to detect high frequency components in an input signal and also as a rate–of–change detector in FM modulators.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

Page 59

DESIGN :

[ To design a differentiator circuit to differentiate an input signal that varies in frequency from 10 Hz to about 1 KHz. If a sine wave of 1 V peak at 1000Hz is applied to the differentiator , draw its output waveform.]

Given fa = 1 KHzWe know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1)Let us assume C1 = 0.1 µF ; thenRf = _________Since fb = 20 fa , fb = 20 KHzWe know that the gain limiting frequency fb = 1 / (2π R1 C1)Hence R1 = _________Also since R1C1 = Rf Cf ; Cf = _________

Given Vp = 1 V and f = 1000 Hz, the input voltage is Vi = Vp sin ωtWe know ω = 2πf

Hence Vo = - Rf C1 ( dVi /dt ) = - 0.94 cos ωt

PROCEDURE:

1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.

Page 60

3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp.

4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

OBSERVATIONS:

S.No Input Output



MODEL GRAPH:

VinModel graph

IV

t

-IV

Vo

2V

t

-2V

RESULT:

The design of the Differentiator circuit was done and the input and output waveforms were obtained.

d. INTEGRATOR

AIM:

To design an Integrator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

Page 61

1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Op-Amp IC 741 15. Bread Board 16. Resistors7. Capacitors8. Connecting wires and probes As required

THEORY:

A circuit in which the output voltage waveform is the integral of the input voltage waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the output voltage is given as,

Vo = - (1/Rf C1 ) ∫ Vi dt

Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < fb . The input signal will be integrated properly if the Time period T of the signal is larger than or equal to Rf Cf . That is,

T ≥ Rf Cf

The integrator is most commonly used in analog computers and ADC and signal-wave shaping circuits.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF INTEGRATOR:

Page 62

DESIGN:

[ To obtain the output of an Integrator circuit with component values R1Cf = 0.1ms , Rf = 10 R1 and Cf = 0.01 µF and also if 1 V peak square wave at 1000Hz is applied as input.]

We know the frequency at which the gain is 0 dB, fb = 1 / (2π R1 Cf)Therefore fb = _____Since fb = 10 fa , and also the gain limiting frequency fa = 1 / (2π Rf Cf)We get , R1 = _______ and hence Rf = __________

PROCEDURE:

1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate

input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms

are plotted in a graph sheet.

OBSERVATIONS:

S.No Input Output



MODEL GRAPH:

Page 63

Model graphVin

T t

Vo

T

t

RESULT:

The design of the Integrator circuit was done and the input and output waveforms were obtained.

e. Summing Amplifier: [Inverting]

Design: R1=R2=R3=R & R = Rf = 4.7KΩ; RL = 10 KΩ; RCOMP = R1 || R2 || R3 || Rf

VO = - Rf / R [V1+V2+V3]

Circuit Diagram

V1R1

V2 R2

V3 R3

RCOMP

Rf

+12V

7

2 VO = - RF/R [V1+V2+V3]-6

3 +IC 741

4

RL

-12V

0

Page 64

f. Schmitt Trigger (comparator):

Design : VCC = 12 V; VSAT = 0.9 VCC; R1= 47KΩ; R2 = 120Ω

VUT = + [VSAT R2] / [R1+R2] & VLT = - [VSAT R2] / [R1+R2] & HYSTERSIS [H] = VUT - VLT

Circuit Diagram

+12V

7

2 -6

3 +

4

Vin -12V

R1

R2 RL = 10K

Model Graph0

g. Voltage Follower (Slew rate

verifications):

Design:

Vin = Vout [Unity Gain] & Rin = ∞ & Rf = 0

Circuit Diagram

+12V

7 U1

2 -6 VO

3 +IC 741

I1

4

1V/1KHz -12V

0Page 65

Procedure

1. Connect the circuit as shown in the circuit

2. Set the input voltage as 5V (p-p) at 1KHz. (Input should be always less than Vcc)

3. Note down the output voltage at CRO

4. To observe the phase difference between the input and the output, set the CRO in dual

Mode and switch the trigger source in CRO to CHI.

5. Plot the input and output waveforms on the graph.

Observation:

Peak to peak amplitude of the output = Volts.

Frequency = Hz.

Upper threshold voltage = Volts.

Lower threshold voltage = Volts.

ResultThus Applications of op-amp were studied.

Expt. 8 TIMER IC APPLICATIONS

a. ASTABLE MULTIVIBRATOR

AIM:

To design an Astable multivibrator circuit for the given specifications using 555 Timer IC.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Timer IC IC 555 15. Bread Board 1

Page 66

6. Resistors7. Capacitors8. Connecting wires and probes As required

THEORY:

An Astable multivibrator, often called a free-running multivibrator, is a rectangular-wave-generating circuit. This circuit do not require an external trigger to change the state of the output. The time during which the output is either high or low is determined by two resistors and a capacitor, which are connected externally to the 555 timer. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by,

tc = 0.69 (R1 + R2) C

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by,

td = 0.69 (R2) C

Thus the total time period of the output waveform is,T = tc + td = 0.69 (R1 + 2 R2) C

The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed in percentage. In equation form,

% duty cycle = [( R1 + R2) / (R1 + 2 R2)] x 100

PIN DIAGRAM:

Page 67

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR

DESIGN:

[ To design an astable multivibrator with 65% duty cycle at 4 KHz frequency, assume C= 0.01 µF]

Given f= 4 KHz,Therefore, Total time period, T = 1/f = ____________We know, duty cycle = tc / TTherefore, tc = ------------------------

and td = ____________

We also know for an astable multivibrator td = 0.69 (R2) CTherefore, R2 = _____________

tc = 0.69 (R1 + R2) CTherefore, R1 = _____________

PROCEDURE:

1. Connections are given as per the circuit diagram. 2. + 5V supply is given to the + Vcc terminal of the timer IC. 3. At pin 3 the output waveform is observed with the help of a CRO 4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage


Page 68

OBSERVATIONS:

AmplitudeTime period

( No. of div x( No. of div x

S.No Time per div )Volts per div )

tc td

1. Output Voltage , Vo

2. Capacitor voltage , Vc

MODEL GRAPH:Voltage in volts

vo

Voltage across the capacitor

t(mse)

RESULT:

The design of the Astable multivibrator circuit was done and the output voltage and capacitor voltage waveforms were obtained.

b. MONOSTABLE MULTIVIBRATOR

AIM:

To design a monostable multivibrator for the given specifications using 555 Timer IC.

APPARATUS REQUIRED:

Page 69

S.No Name of the Apparatus Range Quantity1. Function Generator 3 MHz, Analog 12. CRO 30 MHz 13. Dual RPS 0 – 30 V 14. Timer IC IC 555 15. Bread Board 16. Resistors7. Capacitors8. Connecting wires and probes As required

THEORY:

A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand-by state the output of the circuit is approximately zero or at logic low level. When an external trigger pulse is applied, the output is forced to go high (approx. Vcc). The time during which the output remains high is given by,

tp = 1.1 R1 C

At the end of the timing interval, the output automatically reverts back to its logic low state. The output stays low until a trigger pulse is applied again. Then the cycle repeats.Thus the monostable state has only one stable state hence the name monostable.

PIN DIAGRAM:

Page 70

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

DESIGN:

[ To design a monostable multivibrator with tp = 0.616 ms , assume C = 0.01 µF ]

Given tp = 0.616 ms = 1.1 R1 CTherefore, R1 = _____________

PROCEDURE:

1. Connections are given as per the circuit diagram. 2. + 5V supply is given to the + Vcc terminal of the timer IC. 3. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC

Page 71

4. At pin 3 the output waveform is observed with the help of a CRO 5. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage


OBSERVATIONS:

AmplitudeTime period( No. of div x

( No. of div xS.No Time per div )

Volts per div )

ton toff

1. Trigger input

2. Output Voltage , Vo

3. Capacitor voltage , Vc

T

VIN

TP

VD

VC T

VβSAT

VSAT

circuitT

VO –V SAT T

andobtained.

MODEL GRAPH:

RESULT:The design of the Monostable multivibrator was done and the input output waveforms were

EX.No. 9 DAC and ADC Converters

a. DAC CONVERTERS

Page 72

Aim:-

To design R-2R ladder type DAC using op-amp.

Components Required:-

S.No Components Range Quantity1. Op-amp IC 741 12. Resistors 10KΩ,20KΩ 13. DPDT(switch) 14. Dual Tracking Supply (0-30)V 15. Voltage Source (0-30)V 1

Theory:-In R-2R ladder type D to A converter, only two values of resistor is used (i.e. R and

2R). Hence it is suitable for integrated circuit fabrication. The typical values of R are from 2.5KΩ to 10KΩ. In this output voltage is a weighted sum of digital inputs. Since the resistive ladder is a linear network, the principle of super position can be used to find the total analog output voltage for a particular digital input by adding the output voltages caused by the individual digital inputs.

Circuit Diagram: 4-Bit R/2R Ladder DAC:

VR

Rf =12k

2R 2R 2R 2R45

R

2 -2R R R R 6

3 L M7 4 1 C

+

71

VO

Design:-R B B B B

Output voltage, VO −VRF 1 2 3 4

1R 2 3 4

2 2 2 2Binary value=1000(given)Output voltage=6v (given)

Page 73

Reference resistor =10KΩ (given)Reference Voltage, VR=10V (given)

∴ Rf =12kΩ

Resolution,

V 1 V

R R2

NFR

V 1 10V 12KΩ42 10KΩ

V 0.75

Procedure:-1. Connections are given as per the circuit diagram. 2. The power supply is switched on. 3. Reference voltage is set as 10V. 4. Binary values are applied according to the binary input values. 5. The output voltage is noted down. 6. The output voltage obtained is compared with the given output voltage.

Result:-Thus the R-2R ladder type DAC was designed using Op-amp.

b. ADC CONVERTORS

Aim:-

To design Flash type ADC and Successive approximation type ADC using op-amp.

Components Required:-

S.No Components Range Quantity1. Op-amp IC 741 12. Resistors 10KΩ,20KΩ 13. DPDT(switch) 14. Dual Tracking Supply (0-30)V 15. Voltage Source (0-30)V 1

Circuit diagram: Flash ADC

Page 74

Theory:

Illustrated is a 3-bit flash ADC with resolution 1 volt (after Tocci). The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output.

Circuit diagram: Successive approximation ADC

Theory:

Page 75

Normally analogue-to-digital con-verter (ADC) needs interfacing through a microprocessor to convert analogue data into digital format. This requires hardware and necessary software, resulting in increased complexity and hence the total cost.The circuit of A-to-D converter shown here is configured around ADC 0808, avoiding the use of a microprocessor. The ADC 0808 is an 8-bit A-to-D converter, having data lines D0-D7. It works on the principle of successive approximation. It has a total of eight analogue input channels, out of which any one can be selected using address lines A, B and C. Here, in this case, input channel IN0 is selected by grounding A, B and C address lines.Usually the control signals EOC (end of conversion), SC (start conversion), ALE (address latch enable) and OE (output enable) are interfaced by means of a microprocessor. However, the circuit shown here is built to operate in its continuous mode without using any microprocessor. Therefore the input control signals ALE and OE, being active-high, are tied to Vcc (+5 volts). The input control signal SC, being active-low, initiates start of conversion at falling edge of the pulse, whereas the output signal EOC becomes high after completion of digitisation. This EOC output is coupled to SC input, where falling edge of EOC output acts as SC input to direct the ADC to start the conversion.As the conversion starts, EOC signal goes high. At next clock pulse EOC output again goes low, and hence SC is enabled to start the next conversion. Thus, it provides continuous 8-bit digital output corresponding to instantaneous value of analogue input. The maximum level of analogue input voltage should be appropriately scaled down below positive reference (+5V) level.The ADC 0808 IC requires clock signal of typically 550 kHz, which can be easily derived from an astable multivibrator constructed using 7404 inverter gates. In order to visualise the digital output, the row of eight LEDs (LED1 through LED8) have been used, wherein each LED is connected to respective data lines D0 through D7. Since ADC works in the continuous mode, it displays digital output as soon as analogue input is applied. The decimal equivalent digital output value D for a given analogue input voltage Vin can be calculated from the relationship

Procedure:-1. Connections are given as per the circuit diagram. 2. The power supply is switched on. 3. Reference voltage is set as 10V. 4. Binary values are applied according to the binary input values. 5. The output voltage is noted down. 6. The output voltage obtained is compared with the given output voltage.

Result:-Thus the ADC circuits were designed using Op-amp.

Page 76

EX.No. 10 Study of PLL and VCO characteristics

a. Voltage to frequency characteristics of VCO

Aim:To study the voltage to frequency characteristics of VCO

Circuit diagram

In most cases, the frequency of an oscillator is determined by the time constant RC. However, in cases or applications such as FM, tone generators, and frequency-shift keying (FSK), the frequency is to be controlled by means of an input voltage, called the control voltage. This can be achieved in a voltage-controlled oscillator (VCO). A VCO is a circuit that provides an oscillating output signal (typically of square-wave or triangular waveform) whose frequency can be adjusted over a range by a dc voltage. An example of a VCO is the 566 IC unit, that provides simultaneously the square-wave and triangular-wave outputs as a function of input voltage. The frequency of oscillation is set by an external resistor R1 and a capacitor C1 and

the voltage Vc applied to the control terminals. Figure shows that the 566 IC unit contains current

sources to charge and discharge an external capacitor Cv at a rate set by an external resistor R1 and the modulating dc input voltage. A Schmitt trigger circuit is employed to switch the current sources between charging and discharging the capacitor, and the triangular voltage produced across the capacitor and square-wave from the Schmitt trigger are provided as outputs through buffer amplifiers. Both the output waveforms are buffered so that the output impedance of each is 50 f2. The typical magnitude of the triangular wave and the square wave are 2.4 Vpeak.to-peak

and 5.4Vpeak.to.peak.

Page 77

The frequency of the output waveforms is approximated by

fout = 2(V+ - Vc)/R1C1V+

Figure shows the pin connection of the 566 unit. The VCO can be programmed over a 10-to-l frequency range by proper selection of an external resistor and capacitor, and then modulated over a 10-to-l frequency range by a control voltage, Vc (The voltage controlled oscillators

(VCOs) are commonly used in converting low-frequency signals such as EEG (electro-encephalograms) or ECG (electro-cardiograms)

into an audiofrequency (AF range).)

b. Frequency multiplication Of PLL IC

Aim: To study the Frequency multiplication of PLL IC.

Circuit diagram

Page 78

The block diagram of a frequency muliplier (or synthesizer) is shown in figure. In this circuit, a frequency divider is inserted between the output of the VCO and the phase comparator (PC) so that the loop signal to the PC is at frequency fOUT while the output of VCO is N fOUT. This output is a multiple of the input frequency as long as the loop is in lock. The desired amount of multiplication can be obtained by selecting a proper divide- by N network where N is an integer. Figure shows this function performed by a 7490 configured as a divide-by-4 circuit.

In this case the input Vin at frequency /in is compared with the output frequency fOUT at pin 5. An output at N fOUT (4 fOUT in this case) is connected through an inverter circuit to give an input at pin 14 of the 7490, which varies between 0 and + 5 V. Using the output at pin 9, which is one-fourth of that at the input to the 7490, the signal at pin 4 of the PLL is four times the input frequency as long as the loop remains in lock.

Since the VCO can be adjusted over a limited range from its centre frequency, it may become necessary to change the VCO frequency whenever the divider value is changed.

Page 79

For verification of the circuit operation, one must determine the input frequency range and then adjust the free

running fOUT of the VCO by means of R1 and C1 so that the output frequency of the 7490 divider is midway within the predetermined input frequency range.

The output of VCO should now be equal to 4

Result:Thus the PLL and VCO characteristics were studied.

Page 80

FIN.

Documents

Lic Manual