Linear and Digital Ic Lab 2011-12 (Ktm & Ns)

LABORATORY MANUAL
LABORATORY
http://annauniversitystudymaterials.blogspot.in/ Page 2
1.a STUDY OF LOGIC GATES 03
1.b STUDY OF FLIP FLOPS 07
2. ADDERS, SUBTRACTORS AND REDUCTION OF A BOOLEAN
EXPRESSION USING KARNAUGH MAP 12
3.a CODE CONVERTERS, ODD PARITY GENERATOR AND ODD
PARITY CHECKER 18
COUNTERS 27
REGISTERS 34
6. STUDY AND DESIGN OF 4 :1 & 8 :1 MULTIPLEXER AND
DEMULTIPLEXER 54
TIMER 59
10.a
NE/SE 566 IC 94

Aim:
To study the truth tables of various logic gates and verify them experimentally
using appropriate integrated circuits.
1. AND Gate IC 7408 1
2. OR Gate IC 7432 1
3. NOT Gate IC 7404 1
4. NAND Gate IC 7400 1
5. NOR Gate IC 7402 1
6. EXOR Gate IC 7486 1
7. EXNOR Gate IC 4077 1
8. Bread Board - 1
10. Connecting wires - As Req.
11. Regulated Power supply (0-30V) 1
12 Current Limiting Resistor 330 ohm As Req.
Theory:
The logic gates are the basic building blocks of digital systems. A logic gate
produces an output level depending upon the input levels present at that instant. The
functionality of any logic gate can be explained by the corresponding truth table and
logical expression. Both NAND and NOR gates can perform all the three basic logic
functions (AND, OR and NOT), so they are called as Universal gates.
AND Gate Truth Table IC7408 AND Gate



1. Connections are made as shown in the wiring diagram.
2. The input logic levels are applied from D.C. power supply and the corresponding
output logic level is checked through an LED.
3. All possible input combinations and their corresponding outputs as per the truth
table, are verified.
Aim:
To study the truth tables of various flip flops and verify them experimentally
using appropriate integrated circuits.
5. Bread Board - 1
9. Current Limiting Resistor 330 ohm As Req.
Theory:
The output Q is called the state of the flip-flop
S=1, R=0 Sets the state to 1
S=0, R=1 Resets (or Clears) the state to 0
S=0, R=0 is the Hold state
S=1, R=1 is not allowed
SR Flip-Flop- Excitation Table Truth Table

Because the 11 input will not be allowed, the result is a don’t care, and Q = S + R’q. This
is the characteristic equation for an S-R flip-flop.
D Flip-flop:
0 0 0
0 1 0
1 0 1
1 1 1

J-K Flip-flop
If J and K are different then the output Q takes the value of J at the next clock
edge.
If J and K are both low then no change occurs. If J and K are both high at the
clock edge then the output will toggle from one state to the other.
Characteristic Equation
Truth Table:
T Flip-flop:
The T or "toggle" flip-flop changes its output on each clock edge, giving an

Characteristic Equation
1. Connections are made as shown in the logic diagram.
2. The input clock pulse are applied from digital trainer and the corresponding output
logic levels are checked through LEDs.
3. The workings of flip-flops are verified using truth table.
Inference:
Result:

3. What is mean by edge triggered and level triggered flipflop? 4. What is the characteristic equation for JKFF?
5. What is mean by setup time and hold time? 6. What are the applications of flip flops?
7. What is the 1's and 2's complement of the decimal number 25? 8. What types of flip-flops can be used to implement the memory elements of a
counter? 9. How is a J-K flip-flop made to toggle?
10. The term hold always means ________.
Experiment: 2
USING KARNAUGH MAP
1. Half-adder
2. Full-adder
3. Half-subtractor
4. Full-subtractor and to reduce the given Boolean expression using a Karnaugh
map, implement the reduced expression and test the same.
Apparatus Required:
5. Bread Board - 1
9. Current Limiting Resistor 330 ohm As Req.
Theory:
Adders and subtractors are part of digital arithmetic circuits that perform
arithmetic operations. An adder is a digital circuit that adds two bits and a carry and
outputs a sum bit and carry bit. A subtractor, subtracts the subtrahend bit from the
minuend bit, considering the borrow due to previous subtraction and outputs difference

sed
only for LSB subtraction, since the borrow obtained from preceding subtraction is not
considered.
Design Methodology:
The required circuits are designed using appropriate truth tables. Each output is
expressed as a Boolean algebraic function of all the inputs. The obtained logical
expressions for each of the outputs are reduced using either Karnaugh maps or Boolean
laws.
Karnaugh map:
Karnaugh map is a chart, composed of an arrangement of adjacent cells, each
representing a particular combination of variables in sum or product form. K-map
provides a simple, systematic method of simplifying a Boolean expression, without
changing the functionality of the expression. The simplification leads to reduction in
number of gate inputs during implementation.
Half Adder:
S=X'Y+XY'
SUM(X,Y,Z) = X'Y'Z + XY'Z' + X'YZ' + XYZ
S= X
CARRY= XY + XZ + YZ

K MAP
Half Subtractor:
K MAP
Full Subtractor
K MAP
output logic levels are checked through LEDs.
3. For adders and subtractors, all possible input combinations and their corresponding
outputs as per their truth tables are verified.
4. The given Boolean expression is entered in an appropriate K-map. Groups are formed
such that all the entries are covered. Equivalent terms representing each group is written
to obtain the simplified expression.
5. Step 4 operations are repeated for the canonical form representation of the given
expression and the simplified expression is obtained.

Viva Questions:
1. What is mean by half adder? 2. What is mean by full adder?
3. What is mean by parallel adder? 4. What is mean by carry lookahead adder?
5. What is mean by ripple carry adder? 6. What is mean by parallel binary adder?
7. What are the different types of adder implementation? 8. Realize the functions of NOT, AND, OR and NAND gates only with NOR
gates. 9. Reduce the following using tabulation method.
F = m2 + m3 + m4 + m6 + m7 +m9 + m11 + m13. 10. List out the differences between half adder and full adder.
Experiment: 3(a)
CHECKER
Aim:
1. Gray to Binary code converter
2. Binary to gray code converter
3. 4-Bit Odd Parity Generator and
4. 4-Bit Odd Parity Checker
Apparatus Required
1. Not Gate IC 7404 1
3. Bread Board - 1

7. Current Limiting Resister 330 ohm As Req.
Theory:
Code Converter:
Code converters are logic circuits whose inputs are bit patterns representing
numbers or characters in one code and whose outputs are their corresponding
representations in a different code.
Gray Code:
It is a non-weighted code used in instrumentation and data acquisition systems,
where linear or angular displacement is measured and converted into equivalent digital
values. Gray code is an unit-distance code because successive code words in this code
differ by only one bit position.
Parity Generator and Parity Checker:
When binary data is transmitted, it is susceptible to noise that can alter or distort
its contents. The simplest technique for detecting single-bit errors is that of adding an
extra bit, known as the parity bit, to each word being transmitted. There are two types of
parity – odd parity and even parity. For odd parity, the parity bit is set to a ‘1’ at the
transmitter such that the total number of ‘1’ bits in the word including the parity bit is an
odd number. When the digital data is received, the parity checking circuit generates an
error signal if the total number of ‘1’ bits is even in an odd-parity system.
Design Methodology:
The required circuits are designed using appropriate truth tables. Each output is
expressed as a Boolean algebraic function of all the inputs. The obtained logical
expressions for each of the outputs are reduced using either Karnaugh maps or Boolean
laws.


output logic levels are checked through LEDs.
3. For the first three circuits all possible input combinations and their corresponding
outputs as per their truth tables are verified.
4. For a 4-bit odd parity checker, the error conditions are simulated and appropriate
observations are made for three different cases.
Experiment: 3(b)
Aim:
6. Bread Board - 1
Theory:
Encoder:
An encoder is a digital circuit that performs the inverse operation of a decoder.
An encoder has 2 n input lines and n output lines. The output lines generate the binary
equivalent of the input line whose value is 1.At any one time, only one input line has a
value of 1. The figure below shows the truth table of an 8:3 encoder. It has got 8 inputs
and 3 outputs.
Decoder:
It is a logic circuit that converts an ‘n’ bit binary input code into ‘m’ bit output
line activated such that any one is selected for each one of possible combination of
inputs.
2. The input clock pulse are applied from digital trainer and the corresponding output
logic levels are checked through LEDs.
3. The working of decoding and encoding are verified for proper operation.
Inference:
Result:
Viva Questions:
1. What is mean by encoder? 2. What is mean by decoder?
3. How does an encoder differ from decoder? 4. What is mean by odd and even parity? Is mean by counter?
5. What are the applications of decoder? 6. What is mean by priority encoder?
7. Convert the decimal 65 to BCD, Excess-3 and Gray code. 8. What are codes? List the different codes with examples.

Aim:
To design, construct and test the following types of counters
1. Synchronous counter – Mod 6
2. Synchronous 4-Bit Binary Counter
3. Asynchronous 4 Bit Binary Counter
4. Asynchronous Decade Counters
Theory:
A counter is a sequential machine that produces a specified count sequence. The
count changes whenever the input clock is asserted. There is a great variety of counter
based on its construction.
2. Clock Trigger: Positive edged or Negative edged
3. Counts: Binary, Decade
4. Count Direction: Up, Down, or Up/Down
5. Flip-flops: JK or T or D
A counter can be constructed by a synchronous circuit or by an asynchronous
circuit. With a synchronous circuit, all the bits in the count change synchronously with
S.No Component Name Part No/Range Quantity in Nos
6. Flip Flop IC74LS73 2
7. Trainer kit - 1
8. Bread Board - 1

the assertion of the clock. With an asynchronous circuit, all the bits in the count do not all
change at the same time.
A counter may count up or count down or count up and down depending on the
input control. Because of limited word length, the count sequence is limited. For an n-bit
counter, the range of the count is [0, 2n-1]. The complement of the count sequence counts
in reverse direction. If the uncomplemented output counts up, the complemented output
counts down. If the uncomplemented output counts down, the complemented output
counts up. The natural count sequence is to run through all possible combinations of the
bit patterns before repeating itself. External logic can be used to arbitrary cause the
counter to start at any count and terminate at any count. A binary counter produces a
count sequence similar to the binary numbers. A decade counter counts from 0 to 9, thus
making it suitable for human interface. Other counters count to 12 making them suitable
for clocks.
• Synchronous Counters
Asynchronous: The events do not have a fixed time relationship with each other and do
not occur at the same time.
Synchronous: The events have a fixed time relationship with each other and do occur at
the same time.
Counters are classified according to the way they are clocked. In asynchronous
counters, the first flip-flop is clocked by the external clock pulse and then each
successive flip-flop is by clocked the output of the preceding flip-flop. In synchronous
counters, the clock input is connected to all of the flip-flop so that they are clocked
simultaneously. It is used to count how many clock pulses just have entered. Number of
flip-flops are combined together in order to count the input clock pulses. The count exists
in the form of binary and it is called the state of the counter. If the counter has ‘n’ flip-
flops, it can have a maximum of 2n states or unique states; it is called the modulus of the
counter. The number of unique states passed by the counter before coming back to its
initial state is called the module of a counter. If a counter does not utilize all possible

The change in state of flip-flop will ripple from LSB to MSB which represents
flip-flop and hence called as ripple counter.
For designing a shortened modulus counter, an appropriate reset signal to clear
inputs of all the flip-flops present is given.
Synchronous Counters:
In synchronous counters, the clock inputs of all the flip-flops are connected
together and are triggered by the input pulses. Thus, all the flip-flops change state
simultaneously (in parallel).

Determination of the minimal-sum expressions for a synchronous mod-6 counter
using clocked JK flip-flops.
Synchronous 4-Bit Binary Counter:
Asynchronous Counters:
An asynchronous counter is one in which the flip-flop within the counter do not
change states at exactly the same time because they do not have a common clock pulse.
The main characteristic of an asynchronous counter is each flip-flop derives its
own clock from other flip-flops and is therefore independent of the input clock.
Consequently, the output of each flip-flop may change at different time, hence the term
asynchronous. From the asynchronous counter diagram above, we observed that the
output of the first flip-flop becomes the clock input for the second flip-flop, and the
output of the second flip-flop becomes the clock input for the third flip-flop etc. For the
first flip-flop, the output changes whenever there is a negative transition in the clock
input. This means that the output of the first flip-flop produces a series of square waves
that is half the frequency of the clock input. Since the output of the first flip-flop becomes
the clock of the second flip-flop, the output of the second flip-flop is half the frequency
of its clock, i.e. the output of the first flip-flop that in turn is half the frequency of the
clock input. This behavior, in essence is captured by the binary bit pattern in the counting
sequence

Asynchronous Decade Counters:
The binary counters previously introduced have two to the power n states. But
counters with states less than this number are also possible. They are designed to have the
number of states in their sequences, which are called truncated sequences. These
sequences are achieved by forcing the counter to recycle before going through all of its
normal states. A common modulus for counters with truncated sequences is ten. A
counter with ten states in its sequence is called a decade counter.
Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice
that only Q1 and Q3 are used to decode the count of ten. This is called partial decoding,

2. The input clock pulse is applied from digital trainer and the corresponding output is
checked through LEDs.
Viva Questions:
1. What is mean by counter? 2. What is mean by synchronous and asynchronous counter?
3. What is mean by decade counter? 4. What is mean by binary counter?
5. What is the difference between the counting sequences of up and down counter? 6. Give the advantages and disadvantages of a synchronous counter over an
asynchronous counter? 7. What is the difference between combinational logic and sequential logic?
8. How many flip-flops are required to construct a decade counter? 9. The terminal count of a typical modulus-10 binary counter is ________.
10. To operate correctly, starting a ring counter requires ______________.

Aim:
To design, construct and test the following types of shift registers
1. 4 bit Serial in Serial out Shift Register
2. 4 bit Serial in Parallel out Shift Register
3. 4 bit Parallel in Parallel out Shift Register
4. 4 bit Parallel in Serial out Shift Register
Apparatus Required:
Theory:
Shift registers, like counters, are a form of sequential logic. Sequential logic,
unlike combinational logic is not only affected by the present inputs, but also, by the
prior history. In other words, sequential logic remembers past events. Shift registers
produce a discrete delay of a digital signal or waveform. A waveform synchronized to a
clock , a repeating square wave, is delayed by "n" discrete clock times, where "n" is the
number of shift register stages. Thus, a four stage shift register delays "data in" by four
clocks to "data out". The stages in a shift register are delay stages, typically type "D"
Flip-Flops or type "JK" Flip-flops.
6. Flip Flop IC 7474 2
7. Trainer kit - 1
8. Bread Board - 1

Formerly, very long (several hundred stages) shift registers served as digital
memory. This obsolete application is reminiscent of the acoustic mercury delay lines
used as early computer memory. Serial data transmission, over a distance of meters to
kilometers, uses shift registers to convert parallel data to serial form. Serial data
communications replaces many slow parallel data wires with a single serial high speed
circuit.
Serial data over shorter distances of tens of centimeters, uses shift registers to get
data into and out of microprocessors. Numerous peripherals, including analog to digital
converters, digital to analog converters, display drivers, and memory, use shift registers
to reduce the amount of wiring in circuit boards. Some specialized counter circuits
actually use shift registers to generate repeating waveforms. Longer shift registers, with
the help of feedback generate patterns so long that they look like random noise, pseudo-
noise.
Basic shift registers are classified by structure according to the following types:
Serial-in/serial-out
Parallel-in/serial-out
Serial-in/parallel-out
Universal parallel-in/parallel-out
Above we show a block diagram of a serial-in/serial-out shift register, which is 4-
stages long. Data at the input will be delayed by four clock periods from the input to the
output of the shift register. Data at "data in", above, will be present at the Stage A output

output, and "data in" is transfered to stage A output. After the third clock, stage C is
replaced by stage B; stage B is replaced by stage A; and stage A is replaced by "data in".
After the fourth clock, the data originally present at "data in" is at stage D, "output". The
"first in" data is "first out" as it is shifted from "data in" to "data out".
Data is loaded into all stages at once of a parallel-in/serial-out shift register. The
data is then shifted out via "data out" by clock pulses. Since a 4- stage shift register is
shown above, four clock pulses are required to shift out all of the data. In the diagram
above, stage D data will be present at the "data out" up until the first clock pulse; stage C
data will be present at "data out" between the first clock and the second clock pulse; stage
B data will be present between the second clock and the third clock; and stage A data will
be present between the third and the fourth clock. After the fourth clock pulse and
thereafter, successive bits of "data in" should appear at "data out" of the shift register
after a delay of four clock pulses.
If four switches were connected to DA through DD, the status could be read into a
microprocessor using only one data pin and a clock pin. Since adding more switches

Above, four data bits will be shifted in from "data in" by four clock pulses and be
available at QA through QD for driving external circuitry such as LEDs, lamps, relay
drivers, and horns. After the first clock, the data at "data in" appears at QA. After the
second clock, The old QA data appears at QB; QA receives next data from "data in". After
the third clock, QB data is at QC. After the fourth clock, QC data is at QD. This stage
contains the data first present at "data in". The shift register should now contain four data
bits.
A parallel-in/parallel-out shift register combines the function of the parallel-in,
serial-out shift register with the function of the serial-in, parallel-out shift register to
yields the universal shift register. The "do anything" shifter comes at a price– the
increased number of I/O (Input/Output) pins may reduce the number of stages which can
be packaged. Data presented at DA through DD is parallel loaded into the registers. This
data at QA through QD may be shifted by the number of pulses presented at the clock
input. The shifted data is available at QA through QD. The "mode" input, which may be
more than one input, controls parallel loading of data from DA through DD, shifting of
data, and the direction of shifting. There are shift registers which will shift data either left
or right.
Serial-in/serial-out shift register:
Serial-in, serial-out shift registers delay data by one clock time for each stage.
They will store a bit of data for each register. A serial-in, serial-out shift register may be
one to 64 bits in length, longer if registers or packages are cascaded. Below is a single
stage shift register receiving data which is not synchronized to the register clock. The
"data in" at the D pin of the type D FF (Flip-Flop) does not change levels when the clock
changes for low to high. We may want to synchronize the data to a system wide clock in
a circuit board to improve the reliability of a digital logic circuit.
The obvious point (as compared to the figure below) illustrated above is that
whatever "data in" is present at the D pin of a type D FF is transfered from D to output Q
at clock time. Since our example shift register uses positive edge sensitive storage
elements, the output Q follows the D input when the clock transitions from low to high as
shown by the up arrows on the diagram above. There is no doubt what logic level is
present at clock time because the data is stable well before and after the clock edge. This
is seldom the case in multi-stage shift registers. But, this was an easy example to start
with. We are only concerned with the positive, low to high, clock edge. The falling edge
can be ignored. It is very easy to see Q follow D at clock time above. Compare this to the

Since "data in" appears to changes at clock time t1 above, what does the type D
FF see at clock time? The short over simplified answer is that it sees the data that was
present at D prior to the clock. That is what transfered to Q at clock time t1 is. The
correct waveform is QC. At t1 Q goes to a zero if it is not already zero. The D register
does not see a one until time t2, at which time Q goes high.
Since data, above, present at D is clocked to Q at clock time, and Q cannot
change until the next clock time, the D FF delays data by one clock period, provided that
the data is already synchronized to the clock. The QA waveform is the same as "data in"
with a one clock period delay. A more detailed look at what the input of the type D Flip-
Flop sees at clock time follows. Refer to the figure below. Since "data in" appears to
changes at clock time (above), we need further information to determine what the D FF
sees. If the "data in" is from another shift register stage, another same type D FF, we can
draw some conclusions based on data sheet information. Manufacturers of digital logic
make available information about their parts in data sheets, formerly only available in a
collection called a data book . Data books are still available; though, the manufacturer's
web site is the modern source.

Three type D Flip-Flops are cascaded Q to D and the clocks paralleled to form a
three stage shift register above.
Type JK FFs cascaded Q to J, Q' to K with clocks in parallel to yield an alternate
form of the shift register above. A serial-in/serial-out shift register has a clock input, a
data input, and a data output from the last stage. In general, the other stage outputs are not
available otherwise; it would be a serial-in, parallel-out shift register. The waveforms
below are applicable to either one of the preceding two versions of the serial-in, serial-out
shift register. The three pairs of arrows show that a three stage shift register temporarily

At clock time t1 a "data in" of 0 is clocked from D to Q of all three stages. In
particular, D of stage A sees a logic 0, which is clocked to QA where it remains until time
t2. At clock time t2 a "data in" of 1 is clocked from D to QA. At stages B and C, a 0, fed
from preceding stages is clocked to QB and QC. At clock time t3 a "data in" of 0 is
clocked from D to QA. QA goes low and stays low for the remaining clocks due to "data
in" being 0. QB goes high at t3 due to a 1 from the previous stage. QC is still low after t3
due to a low from the previous stage. QC finally goes high at clock t4 due to the high fed
to D from the previous stage QB. All earlier stages have 0s shifted into them. And, after
the next clock pulse at t5, all logic 1s will have been shifted out, replaced by 0s
Parallel-in, Serial-out Shift Register:
Parallel-in/ serial-out shift registers do everything that the previous serial-in/
serial-out shift registers do plus input data to all stages simultaneously. The parallel-in/
serial-out shift register stores data, shifts it on a clock by clock basis, and delays it by the
number of stages times the clock period. In addition, parallel-in/ serial-out really means
that we can load data in parallel into all stages before any shifting ever begins. This is a
way to convert data from a parallel format to a serial format. By parallel format we mean
that the data bits are present simultaneously on individual wires, one for each data bit as
shown below. By serial format we mean that the data bits are presented sequentially in
time on a single wire or circuit as in the case of the "data out" on the block diagram
below.
Below we take a close look at the internal details of a 3-stage parallel-in/ serial-

selector to determine whether data will load in parallel, or shift stored data to the right. In
general, these elements will be replicated for the number of stages required. We show
three stages due to space limitations. Four, eight or sixteen bits is normal for real parts.
Above we show the parallel load path when SHIFT/LD' is logic low. The upper
NAND gates serving DA DB DC are enabled, passing data to the D inputs of type D Flip-
Flops QA QB DC respectively. At the next positive going clock edge, the data will be
clocked from D to Q of the three FFs. Three bits of data will load into QA QB DC at the
same time. The type of parallel load just described, where the data loads on a clock pulse
is known as synchronous load because the loading of data is synchronized to the clock.
This needs to be differentiated from asynchronous load where loading is controlled by
the preset and clear pins of the Flip-Flops which does not require the clock. Only one of
these load methods is used within an individual device, the synchronous load being more
common in newer devices.
The shift path is shown above when SHIFT/LD' is logic high. The lower AND
gates of the pairs feeding the OR gate are enabled giving us a shift register connection of
SI to DA , QA to DB , QB to DC , QC to SO. Clock pulses will cause data to be right shifted
out to So on successive pulses. The waveforms below show both parallel loading of three
bits of data and serial shifting of this data. Parallel data at DA DB DC is converted to serial
data at SO.
What we previously described with words for parallel loading and shifting is now
set down as waveforms above. As an example we present 101 to the parallel inputs DAA
DBB DCC. Next, the SHIFT/LD' goes low enabling loading of data as opposed to shifting
of data. It needs to be low a short time before and after the clock pulse due to setup and
hold requirements. It is considerably wider than it has to be. Though, with synchronous
logic it is convenient to make it wide. We could have made the active low SHIFT/LD'
almost two clocks wide, low almost a clock before t1 and back high just before t3. The
important factor is that it needs to be low around clock time t1 to enable parallel loading
of the data by the clock. Note that at t1 the data 101 at DA DB DC is clocked from D to Q
of the Flip-Flops as shown at QA QB QC at time t1. This is the parallel loading of the data
synchronous with the clock.
Now that the data is loaded, we may shift it provided that SHIFT/LD' is high to
enable shifting, which it is prior to t2. At t2 the data 0 at QC is shifted out of SO which is
the same as the QC waveform. It is either shifted into another integrated circuit, or lost if
there is nothing connected to SO. The data at QB, a 0 is shifted to QC. The 1 at QA is
shifted into QB. With "data in" a 0, QA becomes 0. After t2, QA QB QC = 010. After t3, QA
QB QC = 001. This 1, which was originally present at QA after t1, is now present at SO
and QC. The last data bit is shifted out to an external integrated circuit if it exists. After t 4
all data from the parallel load is gone. At clock t5 we show the shifting in of a data 1
present on the SI, serial input. Why provide SI and SO pins on a shift register? These
connections allow us to cascade shift register stages to provide large shifters than
available in a single IC (Integrated Circuit) package. They also allow serial connections
to and from other ICs like microprocessors.
Serial-in, Parallel-out Shift Register:
A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift
register in that it shifts data into internal storage elements and shifts data out at the serial-
out, data-out, pin. It is different in that it makes all the internal stages available as
outputs. Therefore, a serial-in/parallel-out shift register converts data from serial format
to parallel format. If four data bits are shifted in by four clock pulses via a single wire at
data-in, below, the data becomes available simultaneously on the four Outputs QA to QD
after the fourth clock pulse.

The practical application of the serial-in/parallel-out shift register is to convert data from
serial format on a single wire to parallel format on multiple wires. Perhaps, we will
illuminate four LEDs (Light Emitting Diodes) with the four outputs (QA QB QC QD ).
The above details of the serial-in/parallel-out shift register are fairly simple. It
looks like a serial-in/ serial-out shift register with taps added to each stage output. Serial
data shifts in at SI (Serial Input). After a number of clocks equal to the number of stages,
the first data bit in appears at SO (QD) in the above figure. In general, there is no SO pin.
The last stage (QD above) serves as SO and is cascaded to the next package if it exists.
If a serial-in/parallel-out shift register is so similar to a serial-in/ serial-out shift
register, why do manufacturers bother to offer both types? Why not just offer the serial-
in/parallel-out shift register? They actually only offer the serial-in/parallel-out shift
register, as long as it has no more than 8-bits. Note that serial-in/ serial-out shift registers

for above shift register.
The shift register has been cleared prior to any data by CLR', an active low
signal, which clears all type D Flip-Flops within the shift register. Note the serial data
1011 pattern presented at the SI input. This data is synchronized with the clock CLK.
This would be the case if it is being shifted in from something like another shift register,
for example, a parallel-in/ serial-out shift register (not shown here). On the first clock at
t1, the data 1 at SI is shifted from D to Q of the first shift register stage. After t2 this first
data bit is at QB. After t3 it is at QC. After t4 it is at QD. Four clock pulses have shifted
the first data bit all the way to the last stage QD. The second data bit a 0 is at QC after the
4th clock. The third data bit a 1 is at QB. The fourth data bit another 1 is at QA. Thus, the

four outputs. It will available on the four outputs from just after clock t4 to just before t5.
This parallel data must be used or stored between these two times, or it will be lost due to
shifting out the QD stage on following clocks t5 to t8 as shown above.
Parallel-in, Parallel-out or Universal Shift Register:
The purpose of the parallel-in/ parallel-out shift register is to take in parallel data,
shift it, then output it as shown below. A universal shift register is a do-everything device
in addition to the parallel-in/ parallel-out function.
Above we apply four bit of data to a parallel-in/ parallel-out shift register at DA
DB DC DD. The mode control, which may be multiple inputs, controls parallel loading vs.
shifting. The mode control may also control the direction of shifting in some real devices.
The data will be shifted one bit position for each clock pulse. The shifted data is available
at the outputs QA QB QC QD . The "data in" and "data out" are provided for cascading of
multiple stages. Though, above, we can only cascade data for right shifting. We could
accommodate cascading of left-shift data by adding a pair of left pointing signals, "data
in" and "data out", above. The internal details of a right shifting parallel-in/ parallel-out
shift register are shown below. The tri-state buffers are not strictly necessary to the

The 74LS395 so closely matches our concept of a hypothetical right shifting
parallel-in/ parallel-out shift register that we use an overly simplified version of the data
sheet details above. See the link to the full data sheet more more details, later in this
chapter. LD/SH' controls the AND-OR multiplexer at the data input to the FF's. If
LD/SH'=1, the upper four AND gates are enabled allowing application of parallel inputs
DA DB DC DD to the four FF data inputs. Note the inverter bubble at the clock input of the
four FFs. This indicates that the 74LS395 clocks data on the negative going clock, which
is the high to low transition. The four bits of data will be clocked in parallel from DA DB
DC DD to QA QB QC QD at the next negative going clock. In this "real part", OC' must be
low if the data needs to be available at the actual output pins as opposed to only on the
internal FFs.The previously loaded data may be shifted right by one bit position if
LD/SH'=0 for the succeeding negative going clock edges. Four clocks would shift the
data entirely out of our 4-bit shift register. The data would be lost unless our device was
cascaded from QD' to SER of another device.

Above, a data pattern is presented to inputs DA DB DC DD. The pattern is loaded to
QA QB QC QD . Then it is shifted one bit to the right. The incoming data is indicated by
X, meaning the we do no know what it is. If the input (SER) were grounded, for
example, we would know what data (0) was shifted in. Also shown, is right shifting by
two positions, requiring two clocks.
The above figure serves as a reference for the hardware involved in right shifting of data.
It is too simple to even bother with this figure, except for comparison to more complex
figures to follow.
Right shifting of data is provided above for reference to the previous right shifter.
If we need to shift left, the FFs need to be rewired. Compare to the previous right
shifter. Also, SI and SO have been reversed. SI shifts to QC. QC shifts to QB. QB shifts to
QA. QA leaves on the SO connection, where it could cascade to another shifter SI. This

Above we shift the same data pattern left by one bit. There is one problem with the "shift
left" figure above. There is no market for it. Nobody manufactures a shift-left part. A
"real device" which shifts one direction can be wired externally to shift the other
direction. Or, should we say there is no left or right in the context of a device which shifts
in only one direction. However, there is a market for a device which will shift left or right
on command by a control line. Of course, left and right are valid in that context.
What we have above is a hypothetical shift register capable of shifting either
direction under the control of L'/R. It is setup with L'/R=1 to shift the normal direction,
right. L'/R=1 enables the multiplexer AND gates labeled R. This allows data to follow
the path illustrated by the arrows, when a clock is applied. The connection path is the
same as the” too simple" "shift right" figure above. Data shifts in at SR, to QA, to QB, to
QC, where it leaves at SR cascade. This pin could drive SR of another device to the right.
What if we change L'/R to L'/R=0?

With L'/R=0, the multiplexer AND gates labeled L are enabled, yielding a path, shown
by the arrows, the same as the above "shift left" figure. Data shifts in at SL, to QC, to QB,
to QA, where it leaves at SL cascade. This pin could drive SL of another device to the
left. The prime virtue of the above two figures illustrating the "shift left/ right register" is
simplicity. The operation of the left right control L'/R=0 is easy to follow. A commercial
part needs the parallel data loading implied by the section title. This appears in the figure
below.
Now that we can shift both left and right via L'/R, let us add SH/LD', shift/ load,
and the AND gates labeled "load" to provide for parallel loading of data from inputs DA

enabled to pass data DA DB DC to the FF data inputs. the next clock CLK will clock the
data to QA QB QC. As long as the same data is present it will be re-loaded on succeeding
clocks. However, data present for only one clock will be lost from the outputs when it is
no longer present on the data inputs. One solution is to load the data on one clock, then
proceed to shift on the next four clocks. This problem is remedied in the 74ALS299 by
the addition of another AND gate to the multiplexer. If SH/LD' is changed to SH/LD'=1,
the AND gates labeled "load" are disabled, allowing the left/ right control L'/R to set the
direction of shift on the L or R AND gates. Shifting is as in the previous figures.
The only thing needed to produce a viable integrated device is to add the fourth AND
gate to the multiplexer as alluded for the 74ALS299. This is shown in the next section for
that part.
PIN Diagram
2. The input clock pulses are applied from digital trainer and the corresponding output is
checked through LED’s.
1. What is mean by shift register?
2. What are the qualitative differences between parallel loading and serial loading shift register?
3. How can a serial in / parallel out register be used as a serial in/ serial out register?
4. What is mean by parallel in/ parallel out register? 5. What is mean by serial in /serial out register?
6. What is mean by parallel data transfer? 7. What is a shift register that will accept a parallel input, or a bidirectional
serial load and internal shift features, called? 8. What is meant by parallel load of a shift register?
9. What is the difference between a ring shift counter and a Johnson shift counter?

Experiment: 6
STUDY AND DESIGN OF 4 :1 & 8 :1 MULTIPLEXER AND DEMULTIPLEXER
Aim:
Apparatus Required:
5. Bread Board - 1
Theory:
Multiplexer:
Multiplexing is defined as the process of feeding several independent signals to a
common load, one at a time. The device or switching circuitry used to select and connect
one of these several signals to the load at any one time is known as a multiplexer.
A multiplexer is a combinatorial circuit that is given a certain number (usually a
power of two) data inputs, let us say 2n, and n address inputs used as a binary number to
select one of the data inputs. The multiplexer has a single output, which has the same
value as the selected data input. The multiplexer works like the input selector of a home
music system. Only one input is selected at a time, and the selected input is transmitted to
the single output. Here is such an abbreviated truth table for n = 3. The full truth table
would have 2(3 + 23) = 2048 rows.

The process of feeding several independent loads with signals coming
from a common signal source, one at a time. A device used for de-multiplexing is known
as a de-multiplexer the de-multiplexer circuit takes a single data input and one or more
address inputs, and selects which of multiple outputs will receive the input signal. The
address input determine which data output is going to have the same value as the data

2. The input clock pulses are applied from digital trainer and the corresponding output is
checked through LEDs.
Viva Questions:
1. What is mean by multiplexer? 2. What is the another name of multiplexer and why we are calling it as like that?
3. What are the applications of multiplexer? 4. Write the truth table for 4 input multiplexer
5. What is meant by multiplexing? 6. What is meant by demultiplexer?
7. What is the another name of demultiplexer? 8. What are the applications of Demultiplexer?
9. What is mean by clock demultiplexer? 10. How can we construct 2
n to 1 multiplexer from an n to 2
n decoder?
Aim:
1.To study and testing of Astable Multivibrator operation using NE/SE 555 Timer
2.To study and testing of Monostable Multivibrator operation using NE/SE 555 Timer
Apparatus Required:
555 Timer IC
The 555 timer IC was first introduced around 1971 by the Signetics Corporation
as the SE555/NE555 and was called "The IC Time Machine" and was also the very first
and only commercial timer IC available. It provided circuit designers with a relatively
cheap, stable, and user-friendly integrated circuit for both monostable and astable
applications. The 555 contains more than 28 transistors and it is basically a chip
containing a number of building blocks that end up very similar to an oscillator without
the TIMING COMPONENTS. It needs two or three external components to produce an
oscillator capable of operating at a frequency from 1Hz to 500 kHz. When it oscillates at
a frequency less than 1Hz, the circuit is called a Timer or Delay. . It can be used with any
power supply in the range 5-18 volts, thus it is useful in many analog circuits. When
connected to a 5-volt supply, the circuit is directly compatible with TTL or CMOS digital
devices.
1. Timer IC NE/SE 555 1
3. Bread Board - 1
5. DRB 1
6. DCB 1
9. Function Generator - 1
Description of Functional Block Diagram:
Referring to the functional diagram (Fig. 2.2), three 5kΩ resistors act as a voltage
divider, providing bias voltage of 2/3 Vcc to the upper comparator and 1/3 Vcc to the
lower comparator, where Vcc is the activation supply voltage to the 555 timer. These two
voltages are used to fix the threshold voltage for the two comparators and aid to

‘control voltage’ terminal, a capacitor (0.01µF) will be connected between control
voltage terminal (pin 5) and ground to bypass noise or ripple from the supply.
In standby (stable state), the output Q of the control flip flop (FF) is at logic one
(HIGH). This makes the output (pin 3) logic zero (LOW) because the power
amplifier is basically an inverting amplifier.
Triggering is accomplished by taking the pin 2 from above to below a voltage
level of 1/3 Vcc. The action of the trigger input is level-sensitive, allowing slow
rate-of-change waveforms, as well as pulses, to be used as trigger sources. The
trigger pulse must be of shorter duration than the time interval determined by the
external R and C.
When the trigger input is slightly lower than 1/3 Vcc, the lower comparator
output goes to positive saturation which in turn it sets the control flip flop. The
flip flop will be in set state i.e. Q= logic one (HIGH) and Q =logic zero (LOW).
Then the output of timer will be at logic one(HIGH)
Applying a positive trigger at the Threshold terminal (pin 6), when the voltage is
slightly higher than 2/3 Vcc, the upper comparator goes to positive saturation
which in turn resets the control flip flop. The flip flop goes to reset state i.e. Q=
logic zero (LOW) and Q = logic one (HIGH). Then the output of timer will be
logic zero (LOW)
The reset input (pin 4) provides a mechanism to reset the Control flip flop in a
manner which overrides the effect of any instruction coming to control flip flop from
lower comparator. This overriding reset is effective when the reset input is less than
about 0.4V. When this reset is not used, it is returned to Vcc. the transistor T2 serves as a
buffer to isolate the reset input from the control flip flop and transistor T1. The transistor

Monostable Operation:
In the standby (stable) state, control flip flop holds transistor T1 ON, thus
clamping the external timing capacitor C to ground. The output remains at
ground potential, i.e., LOW.
As the trigger in Fig. 2.3(a) passes through Vcc/3(i.e. trigger input is slightly
lesser than 1/3 Vcc), the lower comparator is triggered to positive saturation and
the control flip flop is set, i.e. Q= logic one (HIGH) and Q =logic zero (LOW).
This makes the transistor T1 OFF and the short circuit across the timing capacitor
C is released.
As Q is LOW, output (pin 3) goes HIGH (=Vcc). The timing cycle now begins.
Since C is unclamped, voltage across it rises exponentially through R towards
Vcc with a time constant RC as in Fig. 2.3(b)
After a time period T, the capacitor voltage is just greater than 2/3Vcc (which is
applied in pin 6) and the upper comparator is triggered to positive saturation,

logic one (HIGH)(assuming very small trigger pulse width). This makes
transistor T1 go ON (i.e. saturates), thereby discharging the capacitor C rapidly to
ground potential. The output returns to the standby state or ground potential as
shown in Fig. 2.3(c) .
The voltage across the capacitor as in Fig is given by
)1( RC
2

From the above equation it is evident that timing interval is independent of the
supply voltage. It may also be noted that once triggered, the output remains in the HIGH
state until time T elapses, which depends only upon R and C. Any additional trigger pulse
coming during this time will not change the output state.
However, if a negative going reset pulse as in Fig. 2.4(d) is applied to the reset terminal
(pin-4) during the timing cycle, transistor T2 goes OFF, T1 becomes ON and the external
timing capacitor C is immediately discharged. The output now will be as in Fig. 2.4(c)
with doted lines. It may be seen that the output of T2 is connected directly to the input of
T1 so as to turn ON T1 immediately and thereby avoid the propagation delay through the
FF. Now, even if the reset is released, the output will still remain LOW until a negative
going trigger pulse is again applied at pin2.
Astable Operation:
The timing resistor is split into two sections R a and R b. Pin 7 of discharging
transistor T1 is connected to the junction of R a and R b.
When the power supply Vcc is connected, the external timing capacitor C charges
towards Vcc with a time constant (R a + R b)C. During this time, the lower
comparator will be in positive saturation which in tern sets the control flip flop
(i.e. Reset R=0, Set S=1), this makes Q =0 Output (pin 3) goes high (equals Vcc),
which has unclamped the timing capacitor C.

When the capacitor voltage is just greater than (2/3)Vcc the upper comparator
triggers to positive saturation and resets the control flip flop(i.e. Reset R=1, Set
S=0) so that Q =1. This in turn, makes transistor T1 on and capacitor C starts
discharging towards ground through R b and transistor T1 with a time constant R bC
(neglecting the forward resistance of T1).
Current also flows into transistor T1 through R a. Resistors R a and R b must be
large enough to limit this current and prevent damage to the discharge transistor
T1.
The minimum value of R a is approximately equal to Vcc/0.2 where 0.2A is the
maximum current through the on transistor T1.
During the discharge of the timing capacitor C, as it reaches just less than) Vcc/3,
the lower comparator is triggered and sets the control flip flop (i.e. Reset R=0,
Set S=1), which turns Q =0.
Now Q =0 unclamps the external timing capacitor C.
The capacitor C is thus periodically charged and discharged between (2/3) Vcc and
(1/3) Vcc respectively.
Fig. 2.6 shows the timing sequence and capacitor voltage waveform. The time duration
for which the output remains HIGH is the time taken by the capacitor to charge from
(1/3) Vcc to (2/3) Vcc. This may be calculated as follows:
Let R a+R b=R
The capacitor voltage for a low pass RC circuit subjected to a step input of Vcc volts is
given by
)1( RC

The time ta taken by the circuit to charge from 0 to 2/3 Vcc is
)1( 3
2 RC
RC t a
09.1
and time t b is to change from 0 to 1/3Vcc is,
)1( 3
1 RC
Or, t b=0.405RC.
So the time to change from 1/3 Vcc to 2/3 Vcc is
t1 = ta-t b
C Rb )0.69(R 0.69RC0.405RC-1.09RCt a1
The output is low while capacitor is discharging from (2/3)Vcc to (1/3)Vcc through the
resistor R b and the voltage across the capacitor is given by
)1( 3
By solving we get C0.69R t b2
The charging path of the capacitor is through R a and R b and discharging is only through
R b. Therefore total time,
T = t1+t2
45.1 f

The duty cycle defined here as the ratio of the time the output is low as compared to the
total time period
Duty cycle = ba
R
ba
b

The duty cycle is always less than 50% in other words, the off time t2 is always
less than the ON time t1. Thus the output of the 555 astable circuit is asymmetric. By
making Rb large compared to Ra,(i.e. R a=minimum) the waveform becomes more
symmetric and the 555 output approaches a square wave. If R a is very small, the pin 7 will

when it is ON. This may damage the transistor T1 and hence the timer. To avoid this, a
diode can be connected across the resistance R b in forward bias.
Procedure:
1. The connections are given as per the given circuit diagrams (Fig. 2.3 and Fig 2.5)
drawn as per the design values.
2. The values of Vcc = 5V, R =5kΩ (use decade resistance box) and C=0.1μF (use
decade capacitance box) are set.
3. Appropriate Trigger input (400 Hz, 5V p-p, square wave) is applied from the
signal generator for monostable operation.
4. The output signals from Pin no.3 and pin no.6 (voltage across the capacitor) are
observed using a CRO and the frequency and amplitude (p-p) of the output
waveforms are recorded.
Inference:
Result:
Viva Questions:
1. What is mean by astable multivibrator? 2. What is mean by duty cycle?
3. What are the types of astable multivibrator? 4. Write the equation for time intervals present in an astable multivibrator.
5. What is the another name of astable multivibrator? 6. What is mean by monostable multivibrator?
7. What is the difference between an astable multivibrator and a monostable multivibrator?
8. What is the another name of monostable multivibrator? 9. What are the types of monostable multivibrator?
10. What is mean by quasi-stable state?

Experiment No: 8
(a) Inverting Amplifier
(b) Non-inverting Amplifier
1. Op amp IC IC 741 1
4. Bread Board - 1
6. Resister 10K 3
7. Resister 1K 2

Inverting Amplifier:
The op-amp is connected using two resistors R 1 and R f such that the input signal
is applied in series with R 1 and the output is connected back to the inverting input
through R f . The non-inverting input is connected to the ground or the center tap of the
dual polarity power supply. In operation, as the input signal moves positive, the output
will move negative and vice versa. The amount of voltage change at the output relative to
the input depends on the ratio of the two resistors R 1 and R f .
Since the input resistance is infinite, current through R 1 will be equal to the current
through R f . Assuming that the op-amp is an ideal one, then Vd = 0 and node ‘a’ is at
ground potential.
Current through R 1 and R f is given by 1
1 R
in f out
Hence the closed loop gain of the inverting amplifier is, 1 R
R
V

V V
Where Va is the voltage at node ‘a’. Since node ‘a’ is at virtual ground, Va=0. Therefore
by rearranging the above equation the closed loop gain can be written as
1 R
R V V
The negative sign indicates a Phase shift of 180 between Vin and Vout. Also inverting
input is at virtual ground, the effective input impedance is R 1.
Non-inverting Amplifier:
The non-inverting amplifier is connected so that the input signal goes directly to
the non-inverting input (+) and the input resistor R 1 is grounded. In this configuration, the
input impedance as seen by the signal is much greater since the input will be following
the applied signal and not held constant by the feedback current. As the signal moves in
either direction, the output will follow in phase to maintain the inverting input at the same
voltage as the input (+). The voltage gain is always more than unity.
Analysis:
As the difference voltage Vd is zero, the voltage at node ‘A’ is Vin, same as the iput
voltage applied to non-inverting terminal. Now, R f and R 1 forms a potential divider.
Hence 1
cl
11
1 1 . Where Acl is closed loop voltage gain of the non-inverting
operational amplifier. Hence output voltage in
f
Inverting Summing Amplifier:
Operational amplifiers are used to design a circuit whose output is sum of several
inputs. Such a circuit is called Summing amplifier or Adder Circuit or summer.
Analysis:
Assume the op-amp is ideal one (Fig.8.3) i.e. a virtual ground exists at the
inverting input, Input resistance R i is infinite and input current is zero. Hence current
through R f can be obtained by applying KCL at node ‘A’
0 32

R . Thus the output is an
inverted, weighted sum of the input the inputs. When R 1= R 2= R 3, we have Vout=-
(V1+V2) in this case the output Vo is the inverted sum of the input signal.
Let R 1= R 2= 2R 3 then the output voltage Vout is the average of two input signals
(inverted) i.e.
Non-Inverting Summing Amplifier:
The summer that gives a non-inverting sum is the non-inverting summing
amplifier (Fig. 8.4). Let the voltage at the inverting input terminal is Va. The voltage at
non-inverting input terminal will also be Va. By applying KCL at node ‘a’ we get
0 2
21
2
2
1
1
11
amplifier with aout V R
R V

R V out
which is non-inverted weighted sum of inputs. Let R 1= R 2=
R=R 3/2, then Vout=V1+V2.
Comparator
Since the gain of the open loop amplifier is extremely high, the output of an op-
amp will be saturated fully positive, if the non-inverting input is more positive than the
inverting input, and saturated fully negative if the non-inverting input is less positive than

voltages. It compares two voltages and when one input exceeds the other in magnitude,
the states of output voltage will change.
In the circuit shown in the Fig. 8.7, we have an op-amp connected as a
comparator, comparing the input voltage with a reference voltage set by the
potentiometer (R 2). If Vin drops below the reference voltage set by R 2, the op-amp's
output will saturate to +V. Otherwise, if Vin is above the reference voltage, the op-amp's
output will saturate to -V. The output voltage would transition between opposing states of
saturation whenever the input voltage was equal to the reference voltage produced by the
potentiometer. The result would be a square wave. Fig. 8.8 and Fig. 8.9 show the output
of cooperator for positive and negative reference voltages.
Fig 3: Comparator
Differentiator and Integrator
By introducing electrical reactance into the feedback loops of op-amp amplifier
circuits, we can cause the output to respond to changes in the input voltage over time.
Drawing their names from their respective calculus functions, the integrator produces a
voltage output proportional to the product (multiplication) of the input voltage and time;
and the differentiator (not to be confused with differential) produces a voltage output
proportional to the input voltage's rate of change. Capacitance can be defined as the
measure of a capacitor's opposition to changes in voltage. Capacitors oppose voltage its
ge change across it. dt
dv C i . Capacitors oppose voltage change by creating current in
the circuit: that is, they either charge or discharge in response to a change in applied
voltage. So, the more capacitance a capacitor has, the greater its charge or discharge
current will be for any given rate of voltage change across it. dt
dv C i
Differentiator:
We can build an op-amp circuit (Fig. 1.5) which measures change in voltage by
measuring current through a capacitor, and outputs a voltage proportional to that current:
By referring the fig.1.5, the right-hand side of the capacitor is held to a voltage of
0 volts, due to the "virtual ground" effect. Therefore, current "through" the
capacitor is solely due to change in the input voltage.
A steady input voltage won't cause a current through C, but a changing input
voltage will.
Capacitor current moves through the feedback resistor, producing a drop across it,
which is the same as the output voltage.
A linear, positive rate of input voltage change will result in a steady negative
voltage at the output of the op-amp. Conversely, a linear, negative rate of input
voltage change will result in a steady positive voltage at the output of the op-amp.
This polarity inversion from input to output is due to the fact that the input signal

Analysis:
In the differentiator circuit (Fig. 1.5) node ‘a’ is at virtual ground potential i.e.
Va=0the current ic through the capacitor is dt
dv C vv
d C i in
ainc . The current if
through the feed back resistor is vout/R and there is no current into op-amp. Therefore
current at node ‘a’ can be described by 0 R
v
dt
dv RC v in
out . Thus the output voltage vout is a constant(-RC) times the derivative of
the input voltage vin. the negative sign indicates a 180 0 phase shift of the output
waveform with respect to input signal.
By taking laplace transform the output equation can be written as Vout(s)= -RCsVin(s).
substitute s=jω and ω =2πf then gain ain
out
f
2

Differentiator Wave Forms:

Integrator:
The op-amp circuit would generate an output voltage proportional to the
magnitude and duration that an input voltage signal has deviated from 0 volts. Stated
differently, a constant input signal would generate a certain rate of change in the output
voltage: differentiation in reverse i.e. integration. To do this a capacitor is connected in
feedback path along with an input resistor R 1. The integrator circuit is shown in the Fig.
The negative feedback of the op-amp ensures that the inverting input will be held at 0
volts (the virtual ground).
If the input voltage is exactly 0 volts, there will be no current through the resistor,
therefore no charging of the capacitor, and therefore the output voltage will not
change.
We cannot guarantee what voltage will be at the output with respect to ground in
this condition, but we can say that the output voltage will be constant .
By applying a constant, positive voltage to the input, the op-amp output will fall
negative at a linear rate, in an attempt to produce the changing voltage across the
capacitor necessary to maintain the current established by the voltage difference
across the resistor. Conversely, a constant, negative voltage at the input results in
a linear, rising (positive) voltage at the output.
The output voltage rate-of-change will be proportional to the value of the input
voltage.
Analysis:
In the circuit of Fig.1.6, nodal equation at node ‘a’ is 0 dt
dv C
v
dt
in
t
t v .
Where v0(0) is the initial output voltage. The output is -1/RC times the integral of input
and RC is the time constant of the integrator.
By taking laplace transform, the output equation becomes )( 1
)( sV sRC
sV inout (assume
Initial voltage V0(0)=0). Substitute s=jω and ω =2πf and get the magnitude of the gain of
the integrator is fRC RC j jV
jV A
Integrator Wave Forms:
Procedure:
Inverting Amplifier:
1. Connections are made as per the circuit diagram drawn as per the design values.
2. The input sinusoidal signal with a particular frequency and amplitude (p-p) is
applied from a signal generator. Input signal frequency and amplitude (p-p) are
noted.
3. The output signal is observed using a CRO and the frequency and amplitude (p-p)
of the same are noted.
4. The gain for which the circuit is designed is verified by comparing the input and
output signals.
5. The input and output signals are plotted with same scale.
Non-inverting Amplifier:
2. The input sinusoidal signal with a particular frequency and amplitude (p-p) is
applied from a signal generator. Input signal frequency and amplitude (p-p) are
noted.
3. The output signal is observed using a CRO and the frequency and amplitude (p-p)
of the same are noted.
4. The gain for which the circuit is designed is verified by comparing the input and
output signals.
5. The input and output signals are plotted with same scale.
Summing Amplifier:
2. The input D.C. voltages of appropriate values are applied from a D.C. power
supply and the values are also noted.
3. The output voltage is measured using a voltmeter / multi-meter and it is noted.
4. The output voltage is verified for validity by comparing the gain for which the
circuit is designed and input voltages
Comparator:
1. Connections are made as per the circuit diagram drawn.
2. The positive and negative reference voltages are applied to the non-inverting
terminal of the op-amp by adjusting the potentiometer.
3. A sinusoidal signal with a particular frequency and amplitude (p-p) is applied to
the inverting terminal of the op-amp from a signal generator. Input signal
frequency and amplitude (p-p) are noted.
4. The output signals are observed using a CRO and the frequency and amplitude
(p-p) of the output waveforms are recorded.
Differentiator and Integrator:
2. The input square wave with a particular frequency and amplitude (p-p) is applied
from a signal generator. Input signal frequency and amplitude (p-p) are noted.
3. The output signals are observed using a CRO and the frequency and amplitude (p-
p) of the output waveforms are recorded.
4. The output voltage is verified for validity.

Viva Questions:
1. What is an op-amp? 2. What are the characteristics of an ideal opamp?
3. What is mean by open loop and closed loop operation of an opamp? 4. What is the input impedance of a non-inverting op-amp amplifier?
5. Define common mode rejection ratio. 6. What is mean by slew rate?
7. What are the limitations of an ordinary op-amp differentiator? 8. What is the difference between the integrator and differentiator?

Experiment No: 9.a
Aim:
To design the following digital to analog converters and test their functionality by
conducting an experiment;
Apparatus Required:
Theory:
Digital to Analog converters (DACs) are circuits that convert digital signal into
analog electrical quantities directly related to the digitally encoded input number. DACs
allow computer to communicate with analog world. The digital output from a process
computer cannot be used to directly to operate a valve that controls gas flow to a furnace.
But the output of a digital system might be changed to operate a servo motor which
drives the arm of a plotter.
Conversion of n digital voltage levels into one equivalent analog voltage can be
achieved by designing a resistive network. The resistive network changes each digital
level into an equivalent binary weighted voltage or current, which can be added using a
summing circuit to get the equivalent analog signal.
1. Bread Board - 1
3. Resistor 8K 1
5. CRO - 1

Weighted resistor digital to analog converter:
The weighted binary resistive summing network is shown in the Fig. 3.1. The
input signals are applied to the inverting terminal of the op-amp. The magnitude of
current proportional to the value of each bit in the digital input word is generated by the
reference voltage, Vref , divided by the weighed binary resistor (i1=Vref /1kΩ). The input
impedance of the op-amp is infinity, and almost no current can enter into the input
terminals. So the current from weighted binary resistors ‘I’ has to go through R f . the
output Vout is the product of current I and feedback resistor R f . The weightings of the
resistors are that of straight binary coding (8, 4, 2, 1 for 4-bit DAC), with the most
significant bit (MSB) in a 4-bit DAC having a weighting resistance one-eighth that of the
least significant bit (LSB).
Let all the switches D0 to D3 are open, the current through the R f will be
A0 8k
V0k 10R IV f out
If the switch D0 and D3 are connected with Vref and the other two switches are open (the
digital word is 1 0 0 1) the current through the R f will be
mA9 8k
output 9V1K 9mAR IV f out
Since the input is connected in the inverting terminal of the op-amp, the polarity of the

Disadvantage:
Weighted binary resistance DACs with more number of bits requires large range
of resistance values. The resistance tolerances that must exist in DACs to achieve
accurate conversions are difficult to maintain over large value of resistance. In addition,
the power requirement varies inversely with the resistance value. In a 4 bit DAC circuit,
this means that if 1/8-W resistor is used for the LSB, a 1-W resistor is needed for MSB.
R-2R Ladder digital to analog converter
Ladder Resistive network (R-2R ladder) is shown in the Fig. 3.2. Only two
resistance values are required, making this circuit ideal for integrated circuit
manufacturing.
Analysis using superposition theorem:
This is done by assuming that an input signal Vref (Fig. 3.2) is applied to only one
input at a time and all other inputs are at zero. The output current is calculated by
applying each of these individual input. Finally all of these outputs are added to get the
total output.
Consider a current that flows into any single input. Whenever such a current
reaches a node, it divides into half, since an equivalent resistance of 2R is exhibited in
both branches. This is shown in the Fig. 3.3 and Fig. 3.4. The current flowing through the
feedback resistor R f due to the LSB is 1/8 of the current due to the MSB.
The Fig. 3.3 shows, the reference voltage Vref is connected only to MSB,(the
digital word is 1 0 0 0) then current i= 2R
VV aref ref ref a V R
iV R
R V
3
1 ;
3
connected only to LSB,(the digital word is 0 0 0 1) then current i= 2R
VV aref

1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1 0 1 0
12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1
MSB
LSB
R-2R Ladder Network:
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1 0 1 0
12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1
Design:
Vo = - 51 2
Procedure:
1. The connections are given as per the given circuit diagrams (Fig. 2.3 and Fig 2.5) drawn as per the design values.
2. Output voltages for various digital inputs are measured using an analog voltmeter and they are recorded

ANALOG TO DIGITAL CONVERTER
Aim: To convert an analog signal into an equivalent Digital signal using IC ADC0808
Apparatus Required:
The ADC0808, ADC0809 data acquisition component is a monolithic CMOS
device with an 8-bit analog-to-digital converter, 8-channel multiplexer and
microprocessor compatible control logic (Fig. 4.1). The 8-bit A/D converter uses
successive approximation as the conversion technique. The converter features a high
impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree
and a successive approximation register. The 8-channel multiplexer can directly access
any of 8-single-ended analog signals. The device eliminates the need for external zero
and full scale adjustments. Easy interfacing to microprocessors is provided by the latched
and decoded multiplexer address inputs and latched TTL TRI-STATE outputs.
The design of the ADC0808, ADC0809 has been optimized by incorporating the
most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809
offers high speed, high accuracy, minimal temperature dependence, excellent long-term
accuracy and repeatability, and consumes minimal power. These features make this
device ideally suited to applications from process and machine control to consumer and
automotive applications.
1. ADC IC IC ADC0808 1
2. Trainer kit - 1
3. Bread Board - 1

MULTIPLEXER
The device contains an 8-channel single-ended analog signal multiplexer. A particular input channel is selected by using the address decoder. Table 4.1 shows the
input states for the address lines to select any channel. The address is latched into the decoder on the low-to-high transition of the address latch enable signal.
Table 4.1
CONVERTER CHARACTERISTICS
The heart of this single chip data acquisition system is its 8-bit analog-to-digital
converter. The converter is designed to give fast, accurate, and repeatable conversions
over a wide range of temperatures.
The basic block diagram of the converter is shown in the Fig. 4.1 with doted lines.
The converter is partitioned into three major sections: the 256R ladder network,
the successive approximation register, and the comparator. The converter’s digital
outputs are positive true.
The 256R ladder network approach was chosen over the conventional R/2R
ladder because of its inherent monotonic, which guarantees no missing digital
codes. The 256R network does not cause load variations on the reference voltage.
When the start pulse signal activates the control circuit, the successive
approximation register (SAR) is cleared.
The output of the SAR is 00000000. Vout of the D/A converter is 0. Now, if
Vin>Vout the comparator output is positive. During the first clock pulse, the

This initial setting of the register causes the output of the D/A converter (256R ladder with tree switch) to be half the reference voltage, i.e. ½Vref .
This converter output is compared to the unknown input Vin by the comparator. If the input voltage Vin is greater than the converter reference voltage, the
comparator produces a positive output, that causes the control register to retain the 1 setting in its MSB and the converter continues to supply its reference output
voltage of ½Vref . The SAR output is 10000000
The switch tree sets 1 in the second MSB of the control register and its reading becomes 11000000. This causes the D/A converter to increase its reference output

In this case the total reference voltage exceeds the unknown

Documents

Linear and Digital Ic Lab 2011-12 (Ktm & Ns)