Author / Company / Division / Rev. / Date

Lithography

Challenges

Moore’s Law Rising Costs and

Challenges of Advanced

Patterning

SEMI Texas Spring Forum

May 21, 2013

Austin, Texas

“A smartphone today has more computing

power than all of NASA did when it put a

man on the moon in 1969” – Paul Otellini –

CES 2012

Moore’s Law

Number of transistors

doubles every 2 years

Wavelength

Extensions

Process

Innovations

Novel

Materials

Patterning

Advances

Lithography Roadmap

EUV

248

193

193i

DPT

200

8

80

2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016

Hal

f P

itch

re

solu

tio

n (

nm

)

Logic

NAND

DRAM

Resolution = NA

k1 • λ

Wavelength Extensions

John William Strutt

aka

Lord Rayleigh

Process factor

Wavelength 248nm

193nm

157nm

13.5nm (EUV)

Numerical Aperture Lens property

Immersion

Why EUV (13.5nm)?

40nm HP 193i EUV

3x footprint Vacuum-based

Complex components

Old vs. New

EUV Optics

40 layers of Mo / Si

~70% transmission

Key EUV Challenges

Resist

EUV Source

Mask

193nm Source

Excimer laser EUV Source

Old vs. New Source

Creating 13.5nm Radiation

30um Tin droplets

80kW CO2 Laser

Debris Generator

EUV Utilities

Electrical Power (kW)

Water (l/min)

193i EUV

49

75

532

1600

Wavelength

Extensions

Novel

Materials

Patterning

Advances

Process

Innovations

Double Patterning

40nm to 20nm

Double Patterning

Deposition

Double Patterning

Etchback

Double Patterning

Etchback

Double Patterning

20nm Features

0

1

2

3

4

5

6

193193i

193i + DPT193i + QPT

EUV - 180 wphEUV - 100 wph

EUV - 10 wph

Co

st

per

Layer

(a.u

.)

Cost per Layer

Wavelength

Extensions

Process

Innovations

Novel

Materials

Patterning

Advances

Directed Self-Assembly (DSA)

Polymer A Polymer B

Two different property

polymers are connected

with covalent bond Coating and

＆Bake

A with A and B with B

approach each other

A and B are separated

Disordered state Ordered State

DSA is realized by separation of the different polymer blocks

DSAL is a lithography to make patterns using lithographically directed self-

assembly (DSA) of block copolymer

Pattern Scaling Theory A B A B A

A B B

A B

Cylinder Lamellar

B A

B

𝐿0 ∝ 𝑎𝑁2/3𝜒1/6

𝐿0 𝐿0

𝑎

Statistical monomer

segment length

𝑁 Total degree of

polymerization

𝜒𝐴𝐵 Interaction strength

(Flory-Huggins

parameter)

A. N. Semenov, Sov. Phys. JETP 61, 733 (1985)

Self-Aligned Hole

or Pitch Shrink

Line/ Space Pitch

Shrink

CDU/ LWR

Healing

Complementary Lithography

Novel capability

Line Pattern

Collapse Prevention

Process Window

Improvement

(Dose, Focus)

Resolution

Customer Applications and Design

Rules

Directed Self-Assembly Opportunities

Small size pattern

Y. S. Jung, J.B. Chang, E. Verploegen, K. K. Berggren, C. A. Ross, Nano Lett, 10, 1000 (2010)

Pattern shrink

PS-PDMS

SEM pictures by Tokyo Electron Ltd.

Applicability

M. P. Stoykovich, H. Kang, K. C. Daoulas, G. Liu, C. C. Liu, J. J. de Pablo, M. Muller, P. F. Nealey, ACS Nano, 1 (3), 168 (2007)

90nm hole 30nm hole

DSA

DSA Pre-pattern

~35 nm LN/ 100 nm pitch

Wet resist

strip

Trim etch

~15 nm

After 4x DSA process

12.5 nm line/spaces

Etch Guide Chemo-Epitaxy

RIE Etch

14 nm HP DSA pattern

PS-b-PMMA Grapho-Epitaxy

DSA Pre-pattern

~35 nm LN/ 112 nm pitch

Neutral Layer

Coat

Develop

Liftoff

After 4x DSA anneal

14 nm line/spaces

PS-PMMA Chemo-Epitaxy (Lift off)

Line/ Space DSA (SPIE 2012)

B. Rathsack, et. Al., “Pattern Scaling with Directed Self Assembly Through Lithography

and Etch Process Integration”, SPIE 8323-10 (2012)

High Chi L/S Demonstration

9 nm HP

Ellipse Hole

Hole Split (two 16nm holes)

Ellipse Hole

Slit hole

Trench

16nm 1:1 holes

Graphoepitaxy Hole Application

B. Rathsack, et. Al., “Advances in DSA integration

and manufacturability at 300 mm”, SPIE 8323-10 (2013)

Device Integration

Through collaborative process development, DSA patterns have been

etch transferred into device relevant substrate (silicon substrate)

Schmid, et. al., “Fabrication of 28nm pitch Si fins with DSA

lithography, ” SPIE 8680-51, (2013)

DSA Patterning Etched SOI substrates

with DSA process (PS-PMMA on neutralization layer)

LER ~1.5 nm with post etch annealing

Hsin-Yu Tsai, et al., J. Vac. Sci. Technol. B 30, 06F205 (2012)

29 nm Pitch

DSA Line with Cut for FIN FET Devices after etch transfer into a silicon-on-insulator (SOI) substrate

HsinYu Tsai , et al., IBM 5 April 2013, SPIE Newsroom

29 nm Pitch

Summary

Cost will drive which option is adopted by industry

Wavelength

Extensions

EUV

Novel

Materials

Direct Self Assembly

Process

Innovations

Double Pattern

Multi Pattern