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Logic Design Lab
Manual 10ESL38 3rdsem 2013Ratings: (0)|Views:15,364|Likes:140Published byvishvakiranaL.D. LAB (10ESL38)For III Semester B.E. Electronics and Communication Engineering(As per VTUSyllabus),Prepared...See more
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ECE -
10ESL38Dept.of Electronics and
CommunicationsEngg.CITY
ENGINEERING
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COLLEGEBANG
ALORE
62.
Manual
Prepared
by:Mr.
Vishvakiran
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RC, Asst.Prof., CEC
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Logic Design Lab2013 10ESL383rd
Sem, E&C Dept. 1VK
TABLE OFCONTENT
SExperime
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nts Page No.IC Pin Config
urations 21.
Boolean Expression realizat
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ion using Logic gates 42.
Half/Full Add
er and Subtractor 73.
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a. Parallel Adder/ Subtracto
r 10 b. BCDto Excess-3
and Vice-
versa 144.
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Binary to Gray Conversion
and vice versa165.
MUX/DEMU
X for arithmet
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ic circuits 216.
Comparators
277.
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Decoder Chipfor LED Displ
ay 318.
Priority Encoder 339.
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Flip-Flop verificati
on 3510.
Counters3811.
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Shift Registers 5012.
Ring Counter/
Johnson Counter 5513.
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Sequence Generator 57
Logic DesignLab Syllabus
10ESL38
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59Possible Viva Questions
60
Logic Design Lab2013 10ESL383rd
Sem, E&C Dept. 2
VK
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IC Pinconfiguration
sInverter (NOT
Gate) -7404LS 2-
Input AND Gate- 7408LS2-
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Input OR Gate -
7432LS 2-
Input NAND Ga
te - 7400LS2-
Input NOR Gat
e - 7402LS 2-
Input EX-OR Gate -
7486LS3-
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Input NAND G
ate - 7410LS 4-
bit Binary Full
Adder74LS83
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Logic Design Lab
2013 10ESL383rdSem, E&C Dept. 3
VK
Dual 4-
Input NAND Gate -
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7420LS Dual 4-
input Multiplex
er741534-Bit
Magnitude
Comparator-
7485 Decoders/Demultiplexer 7
4139
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Shift Register -
7495 Synchron
ous Up/Down C
ounter
74192Decimalscalar-
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7490DualJKFli
p-flop
7476
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