Logic Cricuit Design Lab2

8/8/2019 Logic Cricuit Design Lab2

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Logic Cricuit Design Lab

LAB3: Study Level of Abstraction in Fig 1

and design flow diagram in Fig 2, focus on

RTP Simulation using Testbench. In Fig 3,

write VHDL to create register and Testbench

for simulation. What is the difference between

asynchrounous reset and synchronous reset? In

Fig 4, write VHDL and Testbench?

Figure 1 Levels of Abstraction


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Figure 2 Design flow diagram

Figure 3 Register


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Figure 4 asynchrounous reset vs synchronous

reset Register


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LAB4:1. Design 4 bit register using input name and

output name as following in Fig 4, create

the4 bit register Package and simulation.

2. Use Seg7_decorder Package in Lab 2

connect output of the 4 bit register

Package, shown in Fig 5


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Figure 4. The 4 bit register

Figure 5. The 7-segment

3. Use Testbench as shown Fig 6 for

simulation, describe each process of

Testbench.


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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_seg7_decoder_vhd IS

END tb_seg7_decoder_vhd;

ARCHITECTURE test OF tb_seg7_decoder_vhd IS

COMPONENT seg7_decoder

Port ( clk :in std_logic;

rst :in std_logic;

in_en :in std_logic;

bin_in : in std_logic_vector(3 downto 0);

seg7_out : out std_logic_vector(7 downto 0));

END COMPONENT;

SIGNAL bin_in : std_logic_vector(3 downto 0) := (others=>'0');

SIGNAL seg7_out : std_logic_vector(7 downto 0);

signal clk :std_logic:= '0';

signal rst :std_logic;

signal in_en :std_Logic;

BEGIN

uut: seg7_decoder PORT MAP( clk => clk,

rst => rst,

in_en => in_en,


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bin_in => bin_in,

seg7_out => seg7_out

);

clk


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in_en


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wait for 500 ns;

bin_in


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Example LAB

Write VHDL using Package.


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TEST LAB

TEST LAB. Design counter which can count

from 0 to 99 and recount again, write

Testbench for simulation

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Logic Cricuit Design Lab2