Logical Effort Anitha

8/3/2019 Logical Effort Anitha

1/40

logical effort-Anitha R.


2/40

Introduction Delay in a Logic Gate Multistage Logic Networks

Choosing the Best Number of Stages Example Summary



3/40

Chip designers face a bewildering array of choices

What is the best circuit topology for a function?

How many stages of logic give least delay?

How wide should the transistors be?

Logical effort is a method to make these decisions

Uses a simple model of delay

Allows back-of-the-envelope calculations

Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries

? ? ?



4/40

Ben Bitdiddle is the memory designer for the Motoroil68W86, an embedded automotive processor. Help Bendesign the decoder for a register file.

Decoder specifications:

16 word register file Each word is 32 bits wide

Each bit presents load of 3 unit-sized transistors

True and complementary address inputs A[3:0]

Each input may drive 10 unit-sized transistors Ben needs to decide:

How many stages to use? How large should each gate be?

How fast can decoder operate?

A[ : ]33 A[ : ]33

33

bits33

word

s

33

:

De

coder

333

Register File



5/40

Express delays in process-independent unit

absdd

= = 3RC

12 ps in 180 nmprocess

40 ps in 0.6 mprocess



6/40


Delay has two components

absdd

=

d f p= +



7/40



Effort delayf= gh (a.k.a. stage effort) Again has two components

absdd

=

d pf= +



8/40



Effort delay f = gh (a.k.a. stage effort)

Again has two components g: logical effort

Measures relative ability of gate to delivercurrent

g 1 for inverter

absdd

=

d f p= +



9/40



Effort delay f = gh (a.k.a. stage effort)

Again has two components

h: electrical effort= Cout

/ Cin

Ratio of output to input capacitance

Sometimes called fanout

absdd

=

d f p= +



10/40



Parasitic delayp Represents delay of gate driving no load

Set by internal parasitic capacitance

absdd

=

d pf= +



11/40

d = f+p

= gh +p

ElectricalEffort:h = C

out/ C

in

Normalized

Delay:d

Inverter

-input3

NAND

g =

p =d =

g =

p =d =

3 3 3 3 3 3

3

3

3

3

3

3

3



12/40

d = f+p

= gh +p

What aboutNOR2?

ElectricalEffort:h = C

out/ C

in

Normalized

Delay:d

Inverter

-input3

NAND

g = 3

p = 3d = h + 3

g = /33

p = 3d = ( / )h +33 3

EffortDelay:f

Parasitic Delay: p

3 3 3 3 3 3

3

3

3

3

3

3

3



13/40

DEF: Logical effort is the ratio of the inputcapacitance of a gate to the input capacitance ofan inverter delivering the same output current.

Measure from delay vs. fanout plots

Or estimate by counting transistor widths

A YA

B

YA

BY

3

3

3 3

3 3

3

3

3

3

Cin

= 3

g = /33

Cin

= 3

g = /33

Cin

= 3

g = /33



14/40

Gate type Number of inputs

1 2 3 4 nInverter 1

NAND 4/3 5/3 6/3 (n+2)/3

NOR 5/3 7/3 9/3 (2n+1)/3

Tristate / mux 2 2 2 2 2

XOR, XNOR 4, 4 6, 12, 6 8, 16, 16,8

Logical effort of common gates



15/40

Gate type Number of inputs

1 2 3 4 nInverter 1

NAND 2 3 4 n

NOR 2 3 4 n

Tristate / mux 2 4 6 8 2n

XOR, XNOR 4 6 8

Parasitic delay of common gates

In multiples of pinv ( 1)



16/40

Estimate the frequency of an N-stage ring oscillator

Logical Effort: g =

Electrical Effort: h =

Parasitic Delay: p =

Stage Delay: d =

Frequency: fosc =



17/40

Estimate the frequency of an N-stage ring oscillator

Logical Effort: g = 1

Electrical Effort: h = 1

Parasitic Delay: p = 1

Stage Delay: d = 2

Frequency: fosc = 1/(2*N*d) = 1/4N

31 stage ring oscillatorin 0.6 m process hasfrequency of ~ 200

MHz



18/40

Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g =

Electrical Effort: h =

Parasitic Delay: p =

Stage Delay: d =

d



19/40

Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g = 1

Electrical Effort: h = 4

Parasitic Delay: p = 1

Stage Delay: d = 5

d

The FO4 delay is about

200 ps in 0.6 mprocess

60 ps in a 180 nmprocess

f/3 ns in an fm

processlogical effort-Anitha R.


20/40

Logical effort generalizes to multistage networks Path Logical Effort

Path Electrical Effort

Path Effort

iG g= out-path

in-path

C

H C=

i i iF f g h= =

33x

y z33

g3

= 3h

3= x/33

g3

= /33h

3= y/x

g3

= /33h

3= z/y

g3

= 3h

3= /z33



21/40

Logical effort generalizes to multistage networks Path Logical Effort

Path Electrical Effort

Path Effort

Can we write F = GH?

iG g= out path

in path

C

H C

=

i i iF f g h= =



22/40

No! Consider paths that branch:

G =

H =GH =

h1 =

h2 =

F = GH?

3

33

3333

33



23/40

No! Consider paths that branch:

G = 1

H = 90 / 5 = 18GH = 18

h1 = (15 +15) / 5 = 6

h2 = 90 / 15 = 6

F = g1g2h1h2 = 36 = 2GH

3

33

3333

33



24/40

Introduce branching effort Accounts for branching between stages in path

Now we compute the path effort F = GBH

on path off path

on path

C C

b C

+

=

iB b= ih BH=

Note:



25/40

Path Effort Delay

Path Parasitic Delay

Path Delay

F iD f= iP p=

i FD d D P= = +



26/40

Delay is smallest when each stage bears sameeffort

Thus minimum delay of N stage path is

This is a key result of logical effort Find fastest possible delay Doesnt require calculating gate sizes

i FD d D P= = +

3

N

i if g h F= =

3

ND NF P= +



27/40

How wide should the gates be for least delay?

Working backward, apply capacitancetransformation to find input capacitance of each

gate given load it drives. Check work by verifying input cap spec is met.

out

in

i

i

C

C

i out in

f gh g

g CCf

= =

=



28/40

Select gate sizes x and y for least delay fromA to B

3x

x

x

y

y

33

33

A

B



29/40

Logical Effort G =

Electrical Effort H =

Branching Effort B =

Path Effort F =

Best Stage Effort

Parasitic Delay P =

Delay D =

3x

x

x

y

y

33

33

A

B

f=



30/40

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8

Branching Effort B = 3 * 2 = 6

Path Effort F = GBH = 125

Best Stage Effort

Parasitic Delay P = 2 + 3 + 2 = 7

Delay D = 3*5 + 7 = 22 = 4.4 FO4

3x

x

x

y

y

33

33

A

B

3 3f F= =



31/40

Work backward for sizesy =

x =

3x

x

x

y

y

33

33

A

B



32/40

Work backward for sizesy = 45 * (5/3) / 5 = 15

x = (15*2) * (5/3) / 5 = 10

P: 3

N: 3

33

33

A

BP: 3N: 3P: 33

N: 3



33/40

Compare many alternatives with a spreadsheet

Design N G P D

NAND4-INV 2 2 5 29.8

NAND2-NOR2 2 20/9 4 30.1INV-NAND4-INV 3 2 6 22.1

NAND4-INV-INV-INV 4 2 7 21.1

NAND2-NOR2-INV-INV 4 20/9 6 20.5

NAND2-INV-NAND2-INV 4 16/9 6 19.7INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4

NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6



34/40

Term Stage Pathnumber of stages

logical effort

electrical effort

branching effort

effort

effort delay

parasitic delay

delay

iG g=

out-path

in-path

C

CH =

N

iB b= F GBH=

F iD f=

iP p=

i FD d D P= = +

out

in

C

Ch =on-path off-path

on-path

C C

Cb

+=

f gh=

f

p

d f p= +

g

3



35/40

1) Compute path effort2) Estimate best number of stages

3) Sketch path with N stages

4) Estimate least delay5) Determine best stage effort

6) Find gate sizes

F GBH=

3logN F=

3

ND NF P= +3 Nf F=

i

i

i out

in

g CC

f=



36/40


Dynamic Power Static Power


37/40


Power is drawn from a voltage sourceattached to the VDD pin(s) of a chip.

Instantaneous Power:

Energy:

Average Power:

( ) ( ) ( )P t I t V t=

3

( )

T

E P t dt=

avg

3

3

( )

TE

P P t dtT T= =


38/40


( ) ( )VDD DD DDP t I t V=

( ) ( ) ( )3

3R

R R

V tP t I t R

R= =

( ) ( ) ( )

( )

3 3

33

3

3

C

C

V

C

dV

E I t V t dt C V t dtdt

C V t dV CV

= =

= =


39/40


When the gate output rises

Energy stored in capacitor is

But energy drawn from the supply is

Half the energy from VDD is dissipated in the pMOS

transistor as heat, other half stored in capacitor When the gate output falls

Energy in capacitor is dumped to GND

Dissipated as heat in the nMOS transistor

33

3C L DDE C V=

( )3 3

3

3

DD

VDD DD L DD

V

L DD L DD

dVE I t V dt C V dtdt

C V dV C V

= =

= =


40/40

Power DissipationPower Dissipation

SourcesSources Ptotal = Pdynamic + Pstatic Dynamic power: Pdynamic = Pswitching + Pshortcircuit

Switching load capacitances

Short-circuit current

Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD

Subthreshold leakage

Gate leakage

Junction leakage

C t ti t

Documents

Logical Effort Anitha