LogiCORE™ FIFO Generator v2 - pudn.comread.pudn.com/downloads94/doc/372131/fifo_generator_ug175.pdf · FIFO Generator v2.1 User Guide UG175 April 28, 2005 ... Figure 5-21: Programmable

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LogiCORE FIFO Generator v2.1

User GuideUG175 April 28, 2005

FIFO Generator v2.1 User Guide www.xilinx.com UG175 April 28, 2005

Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (High-Risk Applications). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

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Date Version Revision

04/28/05 1.1 Initial Xilinx release.

http://www.xilinx.com

FIFO Generator v2.1 User Guide www.xilinx.com 3UG175 April 28, 2005

Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 1: IntroductionAbout the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

FIFO Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 2: Installing the CoreSystem Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Installing the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CORE Generator IP Updates Installer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Manual Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Chapter 3: Core ArchitectureSystem Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Clock Implementation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Built-in FIFO Support in Virtex-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21First-Word Fall-Through (FWFT) - new in v2.1 release . . . . . . . . . . . . . . . . . . . . . . . . . 21Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Non-Symmetric Aspect Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Core Configurations/Implementations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Independent Clocks: Block RAM and Distributed RAM . . . . . . . . . . . . . . . . . . . . . 23Independent Clocks: Virtex-4 Built-in FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Common Clock: Block RAM, Distributed RAM, Shift Register . . . . . . . . . . . . . . . 23Common Clock: Virtex-4 Built-in FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23FIFO Generator Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Interface Signals: FIFOs With Independent Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Interface Signals: FIFOs with Common Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 4: Generating the CoreCORE Generator Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31FIFO Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Component Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table of Contents


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FIFO Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Common Clock (CLK), Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Common Clock (CLK), Distributed RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Common Clock (CLK), Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Common Clock (CLK), Built-in FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Independent Clocks (RD_CLK, WR_CLK), Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . 33Independent Clocks (RD_CLK, WR_CLK), Distributed RAM . . . . . . . . . . . . . . . . . . . . 33Independent Clocks (RD_CLK, WR_CLK), Built-in FIFO. . . . . . . . . . . . . . . . . . . . . . . . 33

Performance Options and Data Port Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Performance Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Register Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Read Latency (clock cycles). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Data Port Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Input Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Input Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Output Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Output Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Primitive Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Optional Flags and Handshaking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Optional Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Almost Full Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Almost Empty Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Write Port Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Write Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Overflow (Write Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read Port Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Valid (Read Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Underflow (Read Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Programmable Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Programmable Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Programmable Full Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Programmable Empty Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Data Count and Reset Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Data Count Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Summary Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Chapter 5: Designing with the CoreGeneral Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Know the Degree of Difficulty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Understand Signal Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Initializing the FIFO Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Independent Clocks: Block RAM and Distributed RAM . . . . . . . . . . . . . . . . . . . . . 42

Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ALMOST_FULL and FULL Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Example Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44ALMOST_EMPTY and EMPTY Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Modes of Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Handshaking Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Underflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46



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Write Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Example Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Programmable Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Programmable Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Programmable Empty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Data Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Read Data Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Write Data Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52First-Word Fall-Through (FWFT) Data Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Example Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Non-symmetric Aspect Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Independent Clocks: Built-in FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

FULL Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Example Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58EMPTY Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Example Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Handshaking Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Underflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Write Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Example Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60


Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Synchronization Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Common Clock FIFO: Block RAM, Distributed RAM, Shift Register . . . . . . . . . 67

Common Clock FIFO: Block RAM and Distributed RAM . . . . . . . . . . . . . . . . . . . . . . . 67Common Clock FIFO: Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Write and Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68ALMOST_FULL and FULL Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69ALMOST_EMPTY and EMPTY Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Example Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Handshaking Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Underflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Write Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Example Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70


Data Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Common Clock: Built-in FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77



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Chapter 6: Special Design ConsiderationsResetting the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Continuous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Pessimistic Full and Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Programmable Full and Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Write Data Count and Read Data Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Setup and Hold Time Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Chapter 7: Simulating Your DesignSimulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Appendix A: Performance InformationResource Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Appendix B: Core Parameters



Preface: About This Guide

Chapter 1: Introduction

Chapter 2: Installing the Core

Chapter 3: Core ArchitectureFigure 3-1: FIFO with Independent Clocks: Interface Signals . . . . . . . . . . . . . . . . . . . . . . 25

Chapter 4: Generating the CoreFigure 4-1: FIFO Generator Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 4-2: Performance Options and Data Port Parameters . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 4-3: Optional Flags and Handshaking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 4-4: Programmable/Optional Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 4-5: Data Count and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 4-6: Summary Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Chapter 5: Designing with the CoreFigure 5-1: Functional Implementation of a FIFO with Independent Clock Domains . 42Figure 5-2: Write Operation for a FIFO with Independent Clocks. . . . . . . . . . . . . . . . . . . 44Figure 5-3: Standard Read Operation for a FIFO with Independent Clocks . . . . . . . . . . 45Figure 5-4: FWFT Read Operation for a FIFO with Independent Clocks . . . . . . . . . . . . . 45Figure 5-5: Handshaking Signals for a FIFO with Independent Clocks . . . . . . . . . . . . . . 47Figure 5-6: Programmable Full Single Threshold: Threshold Set to 7. . . . . . . . . . . . . . . . 48Figure 5-7: Programmable Full with Assert and Negate Thresholds:

Assert Set to 10 and Negate Set to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Figure 5-8: Programmable Empty with Single Threshold: Threshold Set to 4 . . . . . . . . 50Figure 5-9: Programmable Empty with Assert and Negate Thresholds:

Assert Set to 7 and Negate Set to 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 5-10: Write and Read Data Counts for FIFO with Independent Clocks . . . . . . . . 53Figure 5-11: 1:4 Aspect Ratio: Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 5-12: 1:4 Aspect Ratio: Status Flag Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 5-13: 4:1 Aspect Ratio: Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 5-14: 4:1 Aspect Ratio: Status Flag Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 5-15: Reset Behavior for FIFO with Independent Clocks . . . . . . . . . . . . . . . . . . . . 56Figure 5-16: Functional Implementation of Built-in FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 5-17: Write Operation for a FIFO with Independent Clocks. . . . . . . . . . . . . . . . . . 58Figure 5-18: Read Operation for a FIFO with Independent Clocks . . . . . . . . . . . . . . . . . . 59

Schedule of Figures



R

Figure 5-19: Handshaking Signals for a FIFO with Independent Clocks . . . . . . . . . . . . . 60Figure 5-20: Programmable Full Single Threshold: Threshold Set to 7. . . . . . . . . . . . . . . 62Figure 5-21: Programmable Full with Assert and Negate Thresholds:

Assert Set to 10 and Negate Set to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 5-22: Programmable Empty with Single Threshold: Threshold Set to 4 . . . . . . . 63Figure 5-23: Programmable Empty with Assert and Negate Thresholds:

Assert Set to 4 and Negate Set to 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Figure 5-24: Reset Behavior for Built-In FIFO Implementations

with Independent Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Figure 5-25: FIFO with Independent Clocks: Write and Read Clock Domains . . . . . . . . 66Figure 5-26: Functional Implementation of a Common Clock FIFO

using Block RAM or Distributed RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 5-27: Functional Implementation of a Common Clock FIFOusing Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 5-28: Write and Read Operation for a FIFO with Common Clocks . . . . . . . . . . . . 69Figure 5-29: Handshaking Signals for a FIFO with Common Clocks . . . . . . . . . . . . . . . . 71Figure 5-30: Programmable Full Single Threshold: Threshold Set to 7. . . . . . . . . . . . . . . 72Figure 5-31: Programmable Full with Assert and Negate Thresholds:

Assert Set to 10 and Negate Set to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Figure 5-32: Programmable Empty with Single Threshold: Threshold Set to 4 . . . . . . . 74Figure 5-33: Programmable Empty with Assert and Negate Thresholds:

Assert Set to 7 and Negate Set to 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 5-34: Write and Read Data Counts for FIFO with Common Clocks . . . . . . . . . . . 75Figure 5-35: FIFO Reset Behavior for FIFO with Common Clocks . . . . . . . . . . . . . . . . . . 76

Chapter 6: Special Design Considerations

Chapter 7: Simulating Your Design

Appendix A: Performance Information

Appendix B: Core Parameters



Preface: About This Guide

Chapter 1: Introduction

Chapter 2: Installing the Core

Chapter 3: Core ArchitectureTable 3-1: Memory Configuration Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 3-2: FIFO Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 3-3: FIFO Configurations Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Table 3-4: Reset Signal for FIFOs with Independent Clocks . . . . . . . . . . . . . . . . . . . . . . . . 25Table 3-5: Write Interface Signals for FIFOs with Independent Clocks . . . . . . . . . . . . . . 26Table 3-6: Read Interface Signals for FIFOs with Independent Clocks. . . . . . . . . . . . . . . 27Table 3-7: Interface Signals for FIFOs with a Common Clock . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 4: Generating the Core

Chapter 5: Designing with the CoreTable 5-1: Interface Signals and Corresponding Clock Domains . . . . . . . . . . . . . . . . . . . . 43Table 5-2: Independent Clock FIFO Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 5-3: Interface Signals and Corresponding Clock Domains . . . . . . . . . . . . . . . . . . . . 57Table 5-4: Built-In FIFO Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Table 5-5: Common Clock FIFO Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Chapter 6: Special Design Considerations

Chapter 7: Simulating Your Design

Appendix A: Performance InformationTable A-1: Benchmarks: FIFO Configured without Optional Features . . . . . . . . . . . . . . . 83Table A-2: FIFO Benchmarks: Configured with Multiple Programmable Thresholds . 84Table A-3: Benchmarks: FIFO Configured with Virtex-4 Built-in FIFO Resources. . . . . 85

Appendix B: Core ParametersTable B-1: FIFO Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Schedule of Tables



R



R

Preface

About This Guide

This user guide describes the function and operation of the LogiCORE FIFO Generator, as well as information about designing, customizing, and implementing the core.

Guide ContentsThe following chapters are included:

Preface, About this Guide describes how the user guide is organized, the conventions used in the guide, and provides information about additional resources.

Chapter 1, Introduction, describes the core and related information, including recommended design experience, additional resources, technical support, and submitting feedback to Xilinx.

Chapter 2, Installing the Core, provides information about installing the core. Chapter 3, Core Architecture, describes the core configuration options and their

interfaces.

Chapter 4, Generating the Core, describes how to generate the core using the Xilinx CORE Generator GUI.

Chapter 5, Designing with the Core, discusses how to use the core in a user application.

Chapter 6, Special Design Considerations, discusses specific design features that must be considered when using with the core.

Chapter 7, Simulating Your Design, provides instructions for simulating the design with either behavioral or structural simulation models.

Appendix A, Performance Information, provides a summary of the cores performance data.

Appendix B, Core Parameters, provides a comprehensive list of the parameters set by in the CORE Generator GUI for the FIFO Generator.



Chapter : About This GuideR

Additional ResourcesFor additional information, go to http://www.xilinx.com/support. The following table lists some of the resources you can access from this website or by using the provided URLs.

ConventionsThis document uses the following conventions. An example illustrates each convention.

TypographicalThe following typographical conventions are used in this document:

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry to verification and debugging

http://www.xilinx.com/support/techsup/tutorials/index.htm

Answer Browser Database of Xilinx solution records

http://www.xilinx.com/xlnx/xil_ans_browser.jsp

Data Sheets Device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

Problem Solvers Interactive tools that allow you to troubleshoot your design issues

http://www.xilinx.com/support/troubleshoot/psolvers.htm

Tech Tips Latest news, design tips, and patch information for the Xilinx design environment

http://www.xilinx.com/xlnx/xil_tt_home.jsp

Convention Meaning or Use Example

Courier fontMessages, prompts, and program files that the system displays

speed grade: - 100

Courier boldLiteral commands you enter in a syntactical statement ngdbuild design_name

Italic font

Variables in a syntax statement for which you must supply values

See the Development System Reference Guide for more information.

References to other manuals See the User Guide for details.

Emphasis in textIf a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

Dark Shading Items that are not supported or reserved This feature is not supported

http://www.xilinx.com/supporthttp://www.xilinx.com/support/techsup/tutorials/index.htmhttp://www.xilinx.com/xlnx/xil_ans_browser.jsphttp://www.xilinx.com/xlnx/xweb/xil_publications_index.jsphttp://www.xilinx.com/support/troubleshoot/psolvers.htmhttp://www.xilinx.com/xlnx/xil_tt_home.jsphttp://www.xilinx.com


ConventionsR

Online DocumentThe following linking conventions are used in this document:

Square brackets [ ]

An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required.

ngdbuild [option_name] design_name

Braces { } A list of items from which you must choose one or more lowpwr ={on|off}

Vertical bar | Separates items in a list of choices lowpwr ={on|off}

Vertical ellipsis...

Repetitive material that has been omitted

IOB #1: Name = QOUT IOB #2: Name = CLKIN...

Horizontal ellipsis . . . Omitted repetitive material allow block block_name loc1 loc2 ... locn;

Notations

The prefix 0x or the suffix h indicate hexadecimal notation

A read of address 0x00112975 returned 45524943h.

An _n means the signal is active low usr_teof_n is active low.



Blue textCross-reference link to a location in the current document

See the section Additional Resources for details.

Refer to Title Formats in Chapter 1 for details.

Red text Cross-reference link to a location in another document See Figure 2-5 in the Virtex-II Handbook.

Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files.



Chapter : About This GuideR



R

Chapter 1

Introduction

The Xilinx LogiCORE FIFO Generator, a fully verified first-in first-out memory queue for use in any application requiring in-order storage and retrieval, enables high-performance and area-optimized designs. This core is customizable using the Xilinx CORE Generator system as a complete solution with preimplemented control logic, including management of the read and write pointers and the generation of status flags.

This chapter introduces the FIFO Generator and provides related information, including recommended design experience, additional resources, technical support, and submitting feedback to Xilinx.

About the Core The FIFO Generator is a Xilinx CORE Generator IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=FIFO_Generator.

For information about system requirements and installation, see Chapter 2, Installing the Core..

Recommended Design ExperienceThe FIFO Generator is a fully verified solution, and can be used by all levels of design engineers. When implementing a FIFO with independent write and read clocks, special care must be taken to ensure the FIFO Generator is correctly used. For details, see Synchronization Considerations, page 66.

Technical SupportFor technical support, visit http://support.xilinx.com/. Questions are routed to a team of engineers with FIFO Generator expertise.

Xilinx will provide technical support for use of this product as described in the FIFO Generator User Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=FIFO_Generatorhttp://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=FIFO_Generatorhttp://www.xilinx.comhttp://support.xilinx.com/


Chapter 1: IntroductionR

FeedbackXilinx welcomes comments and suggestions about the FIFO Generator and the documentation supplied with the core.

FIFO Generator For comments or suggestions about the FIFO Generator, please submit a webcase from http://support.xilinx.com/. Be sure to include the following information:

Product name Core version number Explanation of your comments

Document For comments or suggestions about this document, please submit a webcase from http://support.xilinx.com/. Be sure to include the following information:

Document title Document number Page number(s) to which your comments refer Explanation of your comments

http://www.xilinx.comhttp://support.xilinx.com/http://support.xilinx.com/


R

Chapter 2

Installing the Core

This chapter provides instructions for installing the FIFO Generator. The FIFO Generator is provided under the terms of the Xilinx LogiCORE Site License Agreement, which conforms to the terms of the SignOnce IP License standard defined by the Common License Consortium.

System Requirements

Windows

Windows 2000 Professional (Service Pack 2-4) Windows XP Professional (Service Pack 1)

Solaris/Linux

Sun Solaris 8/9 Red Hat Enterprise Linux 3.0 (32-bit and 64-bit)

Software

ISE 7.1i with Service Pack 1 or higher

If necessary, ISE 7.1i Service Packs can be downloaded from http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?software=7.1i.

Installing the CoreYou can install the core in two ways: from the CORE Generator IP Updates Installer, which displays a list of compatible updates from which you select the desired core or core update, or by performing a manual installation after downloading the core from the web.

CORE Generator IP Updates Installer 1. From the CORE Generator main GUI, choose Tools > Updates Installer to start the

Updates Installer.

2. If prompted for a proxy host, contact your administrator to determine the proxy host address and port number you need to get through your firewall.

3. Select 7.1i_ip_update1 from the list of updates in the Available Packages panel.

4. Click Add To Install Queue to add the update ZIP file to the install queue.

5. Do one of the following:

http://www.xilinx.com/ipcenter/doc/xilinx_click_core_site_license.pdfhttp://www.xilinx.comhttp://www.xilinx.com/ipcenter/signonce.htmhttp://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?software=7.1i


Chapter 2: Installing the CoreR

If prompted to enter a log-in name and password, enter your Xilinx log-in and password.

If you are new to Xilinx, click Create an Account and follow the instructions to create an account. (After creating an account, you will be redirected to the page to download the core.)

6. Click Install All Packages from Queue to download the update.

After downloading the update, the Updates Installer terminates the CORE Generator session and installs the downloaded archive. After the download is complete, you can restart the CORE Generator.

7. To confirm the installation, check the following file: C:\Xilinx\coregen\install\install_history. Note: This step assumes your Xilinx software is installed in C:\Xilinx.

Manual Installation1. Close the CORE Generator application if it is running.

2. Download the IP Update ZIP file (Windows) or tar.gz file (UNIX) from the following location and save it to a temporary directory: http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=ip&software=7.1i

If prompted to enter a log-in name and password, enter your Xilinx log-in and password.

If you are new to Xilinx, click Create an Account and follow the instructions to create an account.

3. Do one of the following:

For Windows, unpack the ZIP file using WinZip 7.0 SR-1 or later.

For UNIX, Xilinx recommends that you unpack the tar.gz file using the UNIX command line utilities gunzip and tar. WinZip and GNU tar are not recommended due to differences in the way they handle files with long path names. Please see Xilinx Answer 11162 for details.

4. Extract the ZIP file (ise_71i_ip_update1.zip) or tar.gz (ise_71i_ip_update1.tar.gz) archive to the root directory of your Xilinx software installation. Allow the extractor utility you use to overwrite all existing files and maintain the directory structure defined in the archive.

5. To verify the root directory of your Xilinx installation, do one of the following:

For Windows: Type echo %XILINX% from a DOS prompt.

For Unix: If you have already installed the Xilinx ISE software, the Xilinx variable defined by your set-up script identifies the location of the Xilinx installation directory. After sourcing the Xilinx set-up script, type echo $XILINX to determine the location of the Xilinx installation. Note that you may need system administrator privileges to install the update.

6. Confirm the directory structure in one of the following ways: For Windows:

\coregen\ip\xilinx\primary_ip1_h\com\xilinx\ip

For UNIX: /coregen/ip/xilinx/primary_ip1_h/com/xilinx/ip

If you do not see this directory structure, recheck the directory to which you extracted the archive and try again.

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=ip&software=7.1ihttp://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=11162http://www.xilinx.com


Installing the CoreR

7. Restart the CORE Generator. During start-up, the CORE Generator automatically detects new versions of IP available in your installation and lets you specify which IP customizers (cores) will be visible in your current CORE Generator project.

8. Choose one of the following options:

Display only the latest versions for all cores in the catalog

Update the catalog view to add only new cores to the display

Make a Custom selection of visible cores in your current project

9. Determine if the installation was successful by verifying that the new cores are visible in the CORE Generator GUI.

10. If the new cores arent visible, return to Step 6 to verify the directory structure. If the directory structure is incorrect, return Step 4 to verify that the directory was extracted to the correct location.

For additional assistance installing the IP Update, contact the Xilinx Hotline.



Chapter 2: Installing the CoreR



R

Chapter 3

Core Architecture

This chapter describes the FIFO Generator configuration options and their interfaces.

System Overview

Clock Implementation OperationThe FIFO Generator enables FIFOs to be configured with either independent or common clock domains for write and read operations. The independent clock configuration of the FIFO Generator enables the user to implement unique clock domains on the write and read ports. The FIFO Generator handles the synchronization between clock domains, placing no requirements on phase and frequency. When data buffering in a single clock domain is required, the FIFO Generator can be used to generate a core optimized for that clock.

Built-in FIFO Support in Virtex-4The FIFO Generator supports the Virtex-4 built-in FIFO modules, enabling large FIFOs to be created by cascading the built-in FIFOs in both width and depth. The core expands the capabilities of the built-in FIFOs by utilizing the FPGA fabric to create optional status flags not implemented in the built-in FIFO macro.

First-Word Fall-Through (FWFT) - new in v2.1 releaseThe first-word fall-through (FWFT) feature provides the ability to look-ahead to the next word available from the FIFO without issuing a read operation. When data is available in the FIFO, the first word falls through the FIFO and appears automatically on the output bus (DOUT). FWFT is useful in applications that require low latency access to data and to applications that require throttling based on the contents of the data that are read. FWFT support is included in independent clock FIFOs created with either block RAM or distributed RAM.

Memory TypesThe FIFO Generator implements FIFOs built from block RAM, distributed RAM, shift registers, or the Virtex-4 built-in FIFOs. The core combines memory primitives in an optimal configuration based on the selected width and depth of the FIFO. Table 3-1 provides best-use recommendations for specific design requirements.



Chapter 3: Core ArchitectureR

Non-Symmetric Aspect RatioThe core supports generating FIFOs whose write and read ports have different widths, enabling automatic width conversion of the data width. Non-symmetric aspect ratios ranging from 1:8 to 8:1 are supported for the write and read port widths. This feature is available for FIFOs implemented with block RAM that are configured to have independent write and read clocks.

Core Configurations/ImplementationsTable 3-2 provides a summary of the supported memory and clock configurations.

Table 3-1: Memory Configuration Benefits

Independent Clocks

Common Clock

Small Buffering

Medium-Large

Buffering

High Performance

Minimal Resources

Built-in FIFO

Block RAM

Shift Register

Distributed RAM

Table 3-2: FIFO Configurations

Clock Domain Memory TypeSupported

ConfigurationNon-symmetricAspect Ratios

First-WordFall-Through

Common Block RAM

Common Distributed RAM

Common Shift Register

Common Built-in FIFO 1

1. The built-in FIFO primitive is only available in the Virtex-4 architecture.

Independent Block RAM

Independent Distributed RAM

Independent Built-in FIFO1 2

2. For non-symmetric aspect ratios, use the block RAM implementation (feature not support-ed in Virtex-4 built-in FIFO primitive).

3

3. FWFT for the built-in FIFO will be supported by the FIFO Generator in a future release.Contact your Xilinx representative for more details.



Independent Clocks: Block RAM and Distributed RAMR

Independent Clocks: Block RAM and Distributed RAMThis implementation category allows the user to select block RAM or distributed RAM and supports independent clock domains for write and read data accesses. Operations in the read domain are synchronous to the read clock and operations in the write domain are synchronous to the write clock.

The feature set supported for this type of FIFO includes non-symmetric aspect ratios (different write and read port widths), status flags (full, almost full, empty, and almost empty), as well as programmable full and empty flags generated with user-defined thresholds. Optional read data count and write data count indicators provide the number of words in the FIFO relative to their respective clock domains. In addition, optional handshaking and error flags are available (write acknowledge, overflow, valid, and underflow).

Independent Clocks: Virtex-4 Built-in FIFOThis implementation category allows the user to select the built-in FIFO available in the Virtex-4 architecture. Operations in the read domain are synchronous to the read clock and operations in the write domain are synchronous to the write clock.

The feature set supported for this configuration includes status flags (full and empty) and programmable full and empty flags generated with user-defined thresholds. In addition, optional handshaking and error flags are available (write acknowledge, overflow, valid, and underflow).

Common Clock: Block RAM, Distributed RAM, Shift RegisterThis implementation category allows the user to select block RAM, distributed RAM, or shift register and supports a common clock for write and read data accesses.

The feature set supported for this configuration includes status flags (full, almost full, empty, and almost empty) and programmable empty and full flags generated with user-defined thresholds. In addition, optional handshaking and error flags are supported (write acknowledge, overflow, valid, and underflow), and an optional data count provides the number of words in the FIFO.

Common Clock: Virtex-4 Built-in FIFOThis implementation category allows the user to select the built-in FIFO available in the Virtex-4 architecture and supports a common clock for write and read data accesses.

The feature set supported for this configuration includes status flags (full and empty) and optional programmable full and empty flags with user-defined thresholds. In addition, optional handshaking and error flags are available (write acknowledge, overflow, valid, and underflow).




FIFO Generator FeaturesTable 3-3 summarizes the FIFO Generator features supported for each clock configurationand memory type.

Table 3-3: FIFO Configurations Summary

FIFO Feature

Independent Clocks Common Clock

Block RAM

DistributedRAM

Built-in FIFO

Block RAM

Distributed RAM, Shift Register

Built-in FIFO

Non-symmetric Aspect Ratios

1

1. For applications with a single clock that require non-symmetric ports, use the independentclock configuration and connect the write and read clocks to the same source. A dedicatedsolution for common clocks will be available in a future release. Contact your Xilinx repre-sentative for more details.

Symmetric Aspect Ratios

Almost Full

Almost Empty

Handshaking

Data Count

Programmable Empty/Full Thresholds

First-Word Fall-Through

2

2. To enable First-Word Fall-Through, select Registered Outputs with Read Latency 0 onpage 2 of the GUI.

2

DOUT Reset Value

3

3. All architectures except for Virtex, Virtex-E, Spartan-II, and Spartan-IIE.

3



FIFO Generator FeaturesR

FIFO InterfacesThe following two sections provide definitions for the FIFO interface signals. Figure 3-1illustrates these signals (both the standard and optional ports) for a FIFO core that sup-ports independent write and read clocks.

Figure 3-1: FIFO with Independent Clocks: Interface Signals

Note: Optional Ports are in italics

DOUT[M:0]

EMPTY

RST

RD_EN

RD_CLK

PROG_FULL_THRESH_ASSERT

PROG_FULL_THRESH_NEGATE

PROG_FULL_THRESH

Write ClockDomain

Read ClockDomain

FULL

WR_EN

DIN[N:0]

WR_CLK

ALMOST_FULL

PROG_FULL

WR_ACK

OVERFLOW

ALMOST_EMPTY

PROG_EMPTY

VALID

UNDERFLOW

PROG_EMPTY_THRESH_ASSERT

PROG_EMPTY_THRESH_NEGATE

PROG_EMPTY_THRESH




Interface Signals: FIFOs With Independent ClocksThe signal (RST) causes a reset of the entire core logic (both write and read clock domains) and is defined in Table 3-4. It is an asynchronous input which is synchronized internally in the core before being used. The initial hardware reset should be generated by the user.

Table 3-5 defines the signals for the write interface for FIFOs with independent clocks. Thewrite interface signals are divided into required and optional signals and all signals aresynchronous to the write clock (WR_CLK).

Table 3-4: Reset Signal for FIFOs with Independent Clocks

Name Direction Description

RST Input Reset: This signal is an asynchronous reset that initializes all internal pointers and output registers.

Table 3-5: Write Interface Signals for FIFOs with Independent Clocks


Required

WR_CLK Input Write Clock: All signals on the write domain are synchronous to this clock.

DIN[N:0] Input Data Input: The input data bus used when writing the FIFO.

WR_EN Input Write Enable: If the FIFO is not full, asserting this signal causes data (on DIN) to be written to the FIFO.

FULL Output Full Flag: When asserted, this signal indicates that the FIFO is full. Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is non-destructive to the contents of the FIFO.

Optional

ALMOST_FULL Output Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.

PROG_FULL Output Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold. It is deasserted when the number of words in the FIFO is less than the negate threshold.

WR_DATA_COUNT [D:0] Output Write Data Count: This bus indicates the number of words stored in the FIFO. The count is guaranteed to never under-report the number of words in the FIFO, to ensure the user never overflows the FIFO.

WR_ACK Output Write Acknowledge: This signal indicates that a write request (WR_EN) during the prior clock cycle succeeded.

OVERFLOW Output Overflow: This signal indicates that a write request (WR_EN) during the prior clock cycle was rejected, because the FIFO is full. Overflowing the FIFO is non-destructive to the contents of the FIFO.




Table 3-6 defines the signals on the read interface of a FIFO with independent clocks. The read interface signals are divided into required signals and optional signals, and all signals are synchronous to the read clock (RD_CLK).

PROG_FULL_THRESH Input Programmable Full Threshold: This signal is used to input the threshold value for the assertion and de-assertion of the programmable full (PROG_FULL) flag. The threshold can be dynamically set in-circuit during reset.

The user can either choose to set the assert and negate threshold to the same value (using PROG_FULL_THRESH), or the user can control these values independently (using PROG_FULL_THRESH_ASSERT and PROG_FULL_THRESH_NEGATE).

PROG_FULL_THRESH_ASSERT Input Programmable Full Threshold Assert: This signal is used to set the upper threshold value for the programmable full flag, which defines when the signal is asserted. The threshold can be dynamically set in-circuit during reset.

PROG_FULL_THRESH_NEGATE Input Programmable Full Threshold Negate: This signal is used to set the lower threshold value for the programmable full flag, which defines when the signal is de-asserted. The threshold can be dynamically set in-circuit during reset.

Table 3-5: Write Interface Signals for FIFOs with Independent Clocks (Continued)


Table 3-6: Read Interface Signals for FIFOs with Independent Clocks


Required

RD_CLK Input Read Clock: All signals on the read domain are synchronous to this clock.

DOUT[M:0] Output Data Output: The output data bus is driven when reading the FIFO.

RD_EN Input Read Enable: If the FIFO is not empty, asserting this signal causes data to be read from the FIFO (output on DOUT).

EMPTY Output Empty Flag: When asserted, this signal indicates that the FIFO is empty. Read requests are ignored when the FIFO is empty, initiating a read while empty is non-destructive to the FIFO.

Optional

ALMOST_EMPTY Output Almost Empty Flag: When asserted, this signal indicates that the FIFO is almost empty and one word remains in the FIFO.

PROG_EMPTY Output Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable threshold. It is de-asserted when the number of words in the FIFO exceeds the programmable threshold.

RD_DATA_COUNT [C:0] Output Read Data Count: This bus indicates the number of words available for reading in the FIFO. The count is guaranteed to never over-report the number of words available for reading, to ensure that the user does not underflow the FIFO.

VALID Output Valid: This signal indicates that valid data is available on the output bus (DOUT).




Interface Signals: FIFOs with Common ClockTable 3-7 defines the interface signals of a FIFO with a common write and read clock. The table is divided into standard and optional interface signals, and all signals (except reset) are synchronous to the common clock (CLK).

UNDERFLOW Output Underflow: Indicates that the read request (RD_EN) during the previous clock cycle was rejected because the FIFO is empty. Underflowing the FIFO is non-destructive to the FIFO.

PROG_EMPTY_THRESH Input Programmable Empty Threshold: This signal is used to input the threshold value for the assertion and de-assertion of the programmable empty (PROG_EMPTY) flag. The threshold can be dynamically set in-circuit during reset.

The user can either choose to set the assert and negate threshold to the same value (using PROG_EMPTY_THRESH), or the user can control these values independently (using PROG_EMPTY_THRESH_ASSERT and PROG_EMPTY_THRESH_NEGATE).

PROG_EMPTY_THRESH_ASSERT Input Programmable Empty Threshold Assert: This signal is used to set the lower threshold value for the programmable empty flag, which defines when the signal is asserted. The threshold can be dynamically set in-circuit during reset.

PROG_EMPTY_THRESH_NEGATE Input Programmable Empty Threshold Negate: This signal is used to set the upper threshold value for the programmable empty flag, which defines when the signal is de-asserted. The threshold can be dynamically set in-circuit during reset.

Table 3-6: Read Interface Signals for FIFOs with Independent Clocks (Continued)


Table 3-7: Interface Signals for FIFOs with a Common Clock


Required

RST Input Reset: This signal is an asynchronous reset that initializes all internal pointers and output registers.

CLK Input Clock: All signals on the write and read domains are synchronous to this clock.

DIN[N:0] Input Data Input: The input data bus used when writing the FIFO.

WR_EN Input Write Enable: If the FIFO is not full, asserting this signal causes data (on DIN) to be written to the FIFO.

FULL Output Full Flag: When asserted, this signal indicates that the FIFO is full. Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is non-destructive to the contents of the FIFO.

DOUT[M:0] Output Data Output: The output data bus driven when reading the FIFO.

RD_EN Input Read Enable: If the FIFO is not empty, asserting this signal causes data to be read from the FIFO (output on DOUT).

EMPTY Output Empty Flag: When asserted, this signal indicates that the FIFO is empty. Read requests are ingnored when the FIFO is empty, initiating a read while empty is non-destructive to the FIFO.




Optional

DATA_COUNT [C:0] Output Data Count: This bus indicates the number of words stored in the FIFO.

ALMOST_FULL Output Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.

PROG_FULL Output Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold. It is deasserted when the number of words in the FIFO is less than the negate threshold.

WR_ACK Output Write Acknowledge: This signal indicates that a write request (WR_EN) during the prior clock cycle succeeded.

OVERFLOW Output Overflow: This signal indicates that a write request (WR_EN) during the prior clock cycle was rejected, because the FIFO is full. Overflowing the FIFO is non-destructive to the contents of the FIFO.

PROG_FULL_THRESH Input Programmable Full Threshold: This signal is used to set the threshold value for the assertion and de-assertion of the programmable full flag (PROG_FULL). The threshold can be dynamically set in-circuit during reset.

The user can either choose to set the assert and negate threshold to the same value (using PROG_FULL_THRESH), or the user can control these values independently (using PROG_FULL_THRESH_ASSERT and PROG_FULL_THRESH_NEGATE).

PROG_FULL_THRESH_ASSERT Input Programmable Full Threshold Assert: This signal is used to set the upper threshold value for the programmable full flag, which defines when the signal is asserted. The threshold can be dynamically set in-circuit during reset.

PROG_FULL_THRESH_NEGATE Input Programmable Full Threshold Negate: This signal is used to set the lower threshold value for the programmable full flag, which defines when the signal is de-asserted. The threshold can be dynamically set in-circuit during reset.

ALMOST_EMPTY Output Almost Empty Flag: When asserted, this signal indicates that the FIFO is almost empty and one word remains in the FIFO.

PROG_EMPTY Output Programmable Empty: This signal is asserted after the number of words in the FIFO is less than or equal to the programmable threshold. It is de-asserted when the number of words in the FIFO exceeds the programmable threshold.

VALID Output Valid: This signal indicates that valid data is available on the output bus (DOUT).

UNDERFLOW Output Underflow: Indicates that read request (RD_EN) during the previous clock cycle was rejected because the FIFO is empty. Underflowing the FIFO is non-destructive to the FIFO.

Table 3-7: Interface Signals for FIFOs with a Common Clock (Continued)





PROG_EMPTY_THRESH Input Programmable Empty Threshold: This signal is used to set the threshold value for the assertion and de-assertion of the programmable empty flag (PROG_EMPTY). The threshold can be dynamically set in-circuit during reset.

The user can either choose to set the assert and negate threshold to the same value (using PROG_EMPTY_THRESH), or the user can control these values independently (using PROG_EMPTY_THRESH_ASSERT and PROG_EMPTY_THRESH_NEGATE).

PROG_EMPTY_THRESH_ASSERT Input Programmable Empty Threshold Assert: This signal is used to set the lower threshold value for the programmable empty flag, which defines when the signal is asserted. The threshold can be dynamically set in-circuit during reset.

PROG_EMPTY_THRESH_NEGATE Input Programmable Empty Threshold Negate: This signal is used to set the upper threshold value for the programmable empty flag, which defines when the signal is de-asserted. The threshold can be dynamically set in-circuit during reset.

Table 3-7: Interface Signals for FIFOs with a Common Clock (Continued)




R

Chapter 4

Generating the Core

The FIFO Generator is fully customizable using the Xilinx CORE Generator system.

CORE Generator Graphical User InterfaceThe FIFO Generator graphical user interface (GUI) provides 6 windows for configuring a FIFO. The six GUI windows are:

FIFO Implementation Performance Options and Data Port Parameters Optional Flags and Handshaking Options Programmable Flags Data Count and Reset Summary



Chapter 4: Generating the CoreR

FIFO ImplementationThe main FIFO Generator window defines the component name and provides configuration options for the core.

Component NameBase name of the output files generated for this core. The name must begin with a letter and be composed of the following characters: a to z, 0 to 9, and _.

FIFO ImplementationThis section of the GUI allows the user to select from a set of available FIFO implementations and supported features. The key supported features which are only available for certain implementations are highlighted by the checks in the right-margin. The available options are listed below, with cross-references to additional information.

Common Clock (CLK), Block RAM

For more information, see section Common Clock FIFO: Block RAM and Distributed RAM, page 67.

Figure 4-1: FIFO Generator Main Window



FIFO ImplementationR

Common Clock (CLK), Distributed RAM

For more information, see section Common Clock FIFO: Block RAM and Distributed RAM, page 67.

Common Clock (CLK), Shift Register

For more information, see section Common Clock FIFO: Shift Registers, page 68. This implementation is only available in Virtex-II and newer architectures.

Common Clock (CLK), Built-in FIFO

For more information, see section Common Clock: Built-in FIFO, page 77. This implementation is only available when using the Virtex-4 architecture.

Independent Clocks (RD_CLK, WR_CLK), Block RAM

For more information, see section Independent Clocks: Block RAM and Distributed RAM, page 42. This implementation optionally supports asymmetric read/write ports and first-word fall-through (selectable in the second window of the GUI as shown in Figure 4-2).

Independent Clocks (RD_CLK, WR_CLK), Distributed RAM

For more information, see section Independent Clocks: Block RAM and Distributed RAM, page 42. This implementation optionally supports first-word fall-through (selectable in the second window of the GUI as shown in Figure 4-2).

Independent Clocks (RD_CLK, WR_CLK), Built-in FIFO

For more information, see section Independent Clocks: Built-in FIFO, page 57. This implementation is only available when using the Virtex-4 architecture.




Performance Options and Data Port ParametersThis window enables users to set performance options and data port parameters for the core.

Performance OptionsOnly available when an independent clock FIFO with block RAM or distributed RAM is selected. For more information, see Read Operation, page 44.

Register Outputs

Implements a FIFO with registered outputs. When selected, a first-word fall-through FIFO will be implemented.

Read Latency (clock cycles)

Indicates the latency of a read operation on the FIFO in clock cycles. A latency of 0 indicates that a first-word fall-through FIFO will be implemented; otherwise, a standard FIFO will be implemented.

Data Port Parameters

Input Data Width

Valid range is 1 to 256.

Figure 4-2: Performance Options and Data Port Parameters



Optional Flags and Handshaking OptionsR

Input Depth

Valid range is 16 to 4194394. Only depths with powers of 2 are allowed.

Output Data Width

Available if independent clocks configuration with block RAM is selected. Valid range must comply with asymmetric port rules. See Non-symmetric Aspect Ratios, page 53.

Output Depth

Automatically calculated based on Input Data Width, Input Depth, and Output Data Width.

Primitive Depth

The primitive depth is the configuration of the built-in FIFO primitive used to generate the core. The valid options are: 512, 1024, 2048, and 4096. The default primitive selection will use the minimum number of primitives required, but can be over-written by the user if required. This option is available only if independent clocks or common clock configuration with built-in FIFO is selected.

Optional Flags and Handshaking OptionsThis window allows the user to select the optional status flags and set the handshaking options.

Figure 4-3: Optional Flags and Handshaking Options




Optional Flags

Almost Full Flag

Available in all FIFO implementations except those using built-in FIFOs. Generates an output port that indicates the FIFO is almost full (only one more word can be written).

Almost Empty Flag

Available in all FIFO implementations except in those using built-in FIFOs. Generates an output port that indicates the FIFO is almost empty (only one more word can be read).

Write Port Handshaking

Write Acknowledge

Generates write acknowledge flag which reports the status of a write operation. This signal can be configured to be active high or low (default active high).

Overflow (Write Error)

Generates overflow flag which indicates when the previous write operation was not successful. This signal can be configured to be active high or low (default active high).

Read Port Handshaking

Valid (Read Acknowledge)

Generates valid flag which indicates when the data on the output bus is valid. This signal can be configured to be active high or low (default active high).

Underflow (Read Error)

Generates underflow flag which indicates that the previous read request was not successful. This signal can be configured to be active high or low (default active high).



Programmable FlagsR

Programmable FlagsIn this window, the user can select the programmable flag type when generating a specific FIFO Generator configuration.

Programmable Flags

Programmable Full Type

Select a programmable full threshold type from the drop-down menu. The valid range for each threshold will be displayed, and will vary depending on options selected elsewhere in the GUI.

Full Threshold Assert Value: Available if Programmable Full with Single or Multiple Threshold Constants is selected. Enter a user-defined value, or select a preset value from the drop-down menu. The valid range for this threshold is provided in the GUI. When using a single threshold constant, only the assert threshold value is used.

Full Threshold Negate Value: Available if Programmable Full with Multiple Threshold Constants is selected. Enter a user-defined value, or select a preset value from the drop-down menu. The valid range for this threshold is provided in the GUI.

Programmable Empty Type

Select a programmable empty threshold type from the drop-down menu. The valid range for each threshold will be displayed, and will vary depending on options selected elsewhere in the GUI.

Figure 4-4: Programmable/Optional Flags




Empty Threshold Assert Value: Available if Programmable Empty with Single or Multiple Threshold Constants is selected. Enter a user-defined value, or select a preset value from the drop-down menu. The valid range for this threshold is provided in the GUI. When using a single threshold constant, only the assert value is used.

Empty Threshold Negate Value: Available if Programmable Empty with Multiple Threshold Constants is selected. Enter a user-defined value, or select a preset value from the drop-down menu. The valid range for this threshold is provided in the GUI.

Data Count and Reset WindowThis window lets the user set data count and reset parameters.

Data Count OptionsUse extra logic for more accurate Data Counts: This checkbox is only available for independent clocks FIFO with block RAM or distributed RAM, and when using first-word fall-through. This option uses additional external logic to generate a more accurate data count. See First-Word Fall-Through (FWFT) Data Count, page 52 for additional details.

Write Data Count: Available if an independent clocks FIFO with block RAM or distributed RAM is selected. Valid range is from 1 to log2 (write depth).

Read Data Count: Available if an independent clocks FIFO with block RAM or distributed RAM is selected. Valid range is from 1 to log2 (read depth).

Figure 4-5: Data Count and Reset



Summary WindowR

Data Count: Available if a common clock FIFO with block RAM, distributed RAM or shift registers is selected. Valid range is from 1 to log2 of input depth.

Resets

Dout Reset Value: Available in Virtex-II and newer architectures for all implementations using block RAM, distributed RAM, or shift register memory. This text box indicates the hexidecimal value which is asserted on the output of the FIFO when RST is asserted.

Summary WindowThis window summarizes the FIFO type, dimensions, and additional features selected by the user. In the Additional Features section, most features display either Not Selected (if the feature is not used), or Selected (if the feature is used).

Note: Write depth and read depth provide the actual FIFO depths for the selected configuration. These depths may differ slightly from the depth selected on page 2 of the FIFO GUI.

Figure 4-6: Summary Window



R

Chapter 5

Designing with the Core

This chapter describes the steps required to turn a FIFO Generator core into a fully-functioning design integrated with the users application logic. This chapter is divided into sections that describe the design steps required for each features implementation. It is important to note that depending on the configuration of the FIFO core, only a subset of the implementation details provided are applicable. For successful use of a FIFO core, the design guidelines discussed in this chapter must be observed.

General Design Guidelines

Know the Degree of DifficultyA fully compliant and feature rich FIFO design is challenging to implement in any technology. In addition, the degree of difficulty is significantly influenced by the following:

Maximum system clock frequency Targeted device architecture Specific user application

The user should ensure design techniques are used to facilitate implementation, including pipelining and use of constraints (timing constraints as well as placement and/or area constraints).

Understand Signal PipeliningTo understand the nature of FIFO designs, it is important to understand how pipelining is used to maximize performance and implement synchronization logic for clock-domain crossing. Data written into the write interface may take multiple clock cycles before it can be accessed on the read interface. Refer to the selected implementation below for details on the latency of a particular FIFO configuration.

Initializing the FIFO GeneratorThe FIFO Generator must be reset after the FPGA is configured and before operation begins. A reset pin (RST) is provided, and is an asynchronous reset that clears the internal counters and output registers. Internal to the core, RST is synchronized to the clock domain in which it is used, to ensure that the FIFO initializes to a known state. This synchronization logic allows for proper reset timing of the core logic, avoiding glitches and metastable behavior. Refer to the selected implementation below for details on the reset behavior for a specific FIFO configuration.



Chapter 5: Designing with the CoreR

Independent Clocks: Block RAM and Distributed RAMFigure 5-1 illustrates the functional implementation of a FIFO configured with independent clocks. This implementation uses block RAM or distributed RAM for memory, counters for write and read pointers, conversions between binary and Gray code for synchronization across clock domains, and logic for calculating the status flags.

This FIFO is designed to support an independent read clock (RD_CLK) and write clock (WR_CLK); in other words, there is no required relationship between RD_CLK and

Figure Top x-ref 1

Figure 5-1: Functional Implementation of a FIFO with Independent Clock Domains

Write FlagLogic

Read Counter

Gray to BinaryConverters

Read FlagLogic

Binary to GrayConverters

OPTIONAL:First Word FallThrough Logic

Write Counter

Binary to GrayConverter

Gray to BinaryConverter

WR_EN

DIN

DOUT

RD_EN

FULL

ALMOST_FULL

PROG_FULL

WR_DATA_COUNT

WRITE CLOCK DOMAIN READ CLOCK DOMAIN

WRITE PORT READ PORT

ADDRB

DOUTADDRA

DIN

WE

MEMORY

RD_DATA_COUNT

PROG_EMPTY

ALMOST_EMPTY

EMPTY

Write Counter

Read Counter




WR_CLK with regard to frequency or phase. The FIFO interface signals are only valid in their respective clock domains and are summarize in Table 5-1.

For FIFO cores using independent clocks, the timing relationship between the write and read operations and the status flags is affected by the relationship of the two clocks. For example, the timing between writing to an empty FIFO and the de-assertion of EMPTY is determined by the phase and frequency relationship between the write and read clocks. For additional information refer to the Synchronization Considerations, page 66.

Write OperationThis section describes the behavior of a FIFO write operation and the associated status flags. When write enable is asserted and the FIFO is not full, data is added to the FIFO from the input bus (DIN) and write acknowledge (WR_ACK) is asserted. If the FIFO is continuously written to without being read, it fills with data. Write operations are only successful when the FIFO is not full. When the FIFO is full and a write is initiated, the request is ignored, the overflow flag is asserted and there is no change in the state of the FIFO (i.e. overflowing the FIFO is non-destructive).

ALMOST_FULL and FULL Flags

The almost full flag (ALMOST_FULL) indicates that only one more write can be performed before FULL is asserted. This flag is active high and synchronous to the write clock (WR_CLK).

The full flag (FULL) indicates that the FIFO is full and no more writes can be performed until data is read out. This flag is active high and synchronous to the write clock (WR_CLK). If a write is initiated when FULL is asserted, the write request is ignored and OVERFLOW is asserted.

Example Operation

A typical write operation is illustrated in Figure 5-2. The user asserts WR_EN, causing a write operation to occur on the next rising edge of the WR_CLK. Since the FIFO is not full, WR_ACK is asserted, acknowledging a successful write operation. When only one additional word can be written into the FIFO, the FIFO asserts the ALMOST_FULL flag. When the ALMOST_FULL flag is asserted, one additional write causes the FIFO to assert FULL. When a write occurs after FULL is asserted, WR_ACK is de-asserted and

Table 5-1: Interface Signals and Corresponding Clock Domains

WR_CLK RD_CLK

DIN DOUT

WR_EN RD_EN

FULL EMPTY

ALMOST_FULL ALMOST_EMPTY

PROG_FULL PROG_EMPTY

WR_ACK VALID

OVERFLOW UNDERFLOW

WR_DATA_COUNT RD_DATA_COUNT




OVERFLOW is asserted, indicating an overflow condition. Once the user performs one or more read operations, the FIFO de-asserts FULL, and data can successfully be written to the FIFO, as is indicated by the assertion of WR_ACK and de-assertion of OVERFLOW.

Read OperationThis section describes the behavior of a FIFO read operation and the associated status flags. When read enable is asserted and the FIFO is not empty, data is read from the FIFO on the output bus (DOUT), and the valid flag (VALID) is asserted. If the FIFO is continuously read without being written, the FIFO empties. Read operations are successful when the FIFO is not empty. When the FIFO is empty and a read is requested, the read operation is ignored, the underflow flag is asserted and there is no change in the state of the FIFO (i.e. underflowing the FIFO is non-destructive).

ALMOST_EMPTY and EMPTY Flags

The almost empty flag (ALMOST_EMPTY) indicates that the FIFO will be empty after one more read operation. This flag is active high and synchronous to RD_CLK. This flag is asserted when the FIFO has one remaining word that can be read.

The empty flag (EMPTY) indicates that the FIFO is empty and no more reads can be performed until data is written into the FIFO. This flag is active high and synchronous to the read clock (RD_CLK). If a read is initiated when EMPTY is asserted, the request is ignored and UNDERFLOW is asserted.

Modes of Read Operation

The FIFO Generator supports two modes of read options, standard read operation and first-word fall-through (FWFT) read operation. The standard read operation provides the user data on the cycle after it was requested. The FWFT read operation provides the user data on the same cycle in which it is requested.

Standard FIFO Read Operation

For a standard FIFO read operation, after read enable is asserted and if the FIFO is not empty, the next data stored in the FIFO is driven on the output bus (DOUT) and the valid flag (VALID) is asserted.

A standard read access is illustrated in Figure 5-3. Once the user writes at least one word into the FIFO, EMPTY is de-asserted indicating data is available to be read. The user asserts RD_EN, causing a read operation to occur on the next rising edge of RD_CLK. The FIFO outputs the next available word on DOUT and asserts VALID, indicating a successful read

Figure 5-2: Write Operation for a FIFO with Independent Clocks

WR_CLK

WR_EN

FULL

ALMOST_FULL

WR_ACK

OVERFLOW

DIN D1 D2 D3 D4 D5 D12 D13




operation. When the last data word is read from the FIFO, the FIFO asserts EMPTY. If the user continues to assert RD_EN while EMPTY is asserted, the read request is ignored, VALID is de-asserted, and UNDERFLOW is asserted. Once the user performs a write operation, the FIFO de-asserts EMPTY, allowing the user to resume valid read operations, as indicated by the assertion of VALID and de-assertion of UNDERFLOW.

First-Word Fall-Through FIFO Read Operation

The first-word fall-through (FWFT) feature provides the ability to look-ahead to the next word available from the FIFO without issuing a read operation. When data is available in the FIFO, the first word falls through the FIFO and appears automatically on the output bus (DOUT). Once the first word appears on DOUT, EMPTY is de-asserted indicating one or more readable words in the FIFO, and VALID is asserted, indicating a valid word is present on DOUT.

A FWFT read access is illustrated in Figure 5-4. Initially, the FIFO is not empty, the next available data word is placed on the output bus (DOUT), and VALID is asserted. When the user asserts RD_EN, the next rising clock edge of RD_CLK places the next data word onto DOUT. After the last data word has been placed on DOUT, an additional read request by the user causes the data on DOUT to become invalid, as indicated by the de-assertion of VALID and the assertion of EMPTY. Any further attempts to read from the FIFO results in an underflow condition.

Figure 5-3: Standard Read Operation for a FIFO with Independent Clocks

Figure 5-4: FWFT Read Operation for a FIFO with Independent Clocks

RD_CLK

DOUT

VALID

UNDERFLOW

RD_EN

EMPTY

D D D D

ALMOST_EMPTY

RD_CLK

DOUT

VALID

UNDERFLOW

RD_EN

EMPTY

D D D D

ALMOST_EMPTY




Handshaking FlagsHandshaking flags (valid, underflow, write acknowledge and overflow) are supported to provide additional information regarding the status of the write and read operations. The handshaking flags are optional, and can be configured as active high or active low through the CORE Generator GUI (see Handshaking Options in Chapter 4 for more information). These flags (configured as active high) are illustrated in Figure 5-5.

Valid

The operation of the valid flag (VALID) is dependent on the read mode of the FIFO. This flag is synchronous to the read clock (RD_CLK).

Standard FIFO Read Operation

For standard read operation, the VALID flag is asserted at the rising edge of RD_CLK for each successful read operation, and indicates that the data on the DOUT bus is valid. When a read request is unsuccessful (when the FIFO is empty), VALID is not asserted.

FWFT FIFO Read Operation

For FWFT read operation, the VALID flag indicates the data on the output bus (DOUT) is valid for the current cycle. A read request

Documents

LogiCORE™ FIFO Generator v2 - pudn.comread.pudn.com/downloads94/doc/372131/fifo_generator_ug175.pdf · FIFO Generator v2.1 User Guide UG175 April 28, 2005 ... Figure 5-21: Programmable