Upload
others
View
3
Download
0
Embed Size (px)
Citation preview
Low energy and HighLow energy and High performanceperformanceLow energy and HighLow energy and High--performance performance Embedded Systems Design and Embedded Systems Design and R fi bl A hiR fi bl A hiReconfigurable ArchitecturesReconfigurable Architectures
Ass. Professor Dimitrios SoudrisAss. Professor Dimitrios Soudris
Dept. of Electrical and Computer Eng., Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace, GreeceDemocritus Univ. of Thrace, Greece
11
Democritus Univ. of Thrace, GreeceDemocritus Univ. of Thrace, [email protected], [email protected]@ee.duth.gr, [email protected]
Embedded systems definitions Embedded systems definitions HiPEAC Roadmap http:HiPEAC Roadmap http: www hipeac netwww hipeac netHiPEAC Roadmap http: HiPEAC Roadmap http: www.hipeac.netwww.hipeac.net
Embedded systems (ES) = informationEmbedded systems (ES) information processing systems embedded into a larger producta larger product
55
Embedded Systems:Embedded Systems:Memory managementMemory managementMemory managementMemory management
S
PROC
D
SRAM
SR
AM
EXTERNALMEMORY
EXTERNALMEMORY
DP
EmbeddedDRAMMMU
MEMORYMEMORY
P(External Access) = 30 x P(Arithmetic Operations)
77P(Internal Memory) = typ. 40 % - 60 % P(Chip)( ) ( p )
Embedded Systems: Embedded Systems: Dynamic ApplicationsDynamic Applicationsy a c pp cat o sy a c pp cat o s
Graphical ProcessingVirtual Games Platforms
Current multimedia and wireless network applications:Current multimedia and wireless network applications:-- Very complex => designed with highVery complex => designed with high--level languages level languages
Graphical ProcessingVirtual Games Platforms
y p g gy p g g g gg g(e.g. C++) (e.g. C++)
-- Dynamic Memory (DM) required => several sources of Dynamic Memory (DM) required => several sources of unpredictability: user movements? image features?unpredictability: user movements? image features?gg
-- Multiple subMultiple sub--algorithms => different DM access patternsalgorithms => different DM access patternsFinal platforms:Final platforms:-- Portables: limited Resources (e g memory cpu power)Portables: limited Resources (e g memory cpu power)
88
-- Portables: limited Resources (e.g. memory, cpu, power)Portables: limited Resources (e.g. memory, cpu, power)-- Low power and high performanceLow power and high performance
Methodology for Dynamic Data Type Methodology for Dynamic Data Type Refinement ManagementRefinement ManagementRefinement ManagementRefinement Management
Multimedia and Multimedia and NetworkNetworkNetwork Network ApplicationsApplications
Significant Significant improvementsimprovementsimprovements improvements in energy in energy consumption consumption >80%>80%
TradeTrade--offs of offs of memory memory footprint, footprint, p ,p ,performance, performance, energy energy consumed in consumed in DDT DDT
99
Refinement Refinement are possibleare possible
Customized Dynamic Memory Manager: Customized Dynamic Memory Manager: Reduced Power ConsumptionReduced Power ConsumptionReduced Power ConsumptionReduced Power Consumption
SingleSingle--functionedfunctionedSingleSingle--functionedfunctioned–– Executes a single program, repeatedlyExecutes a single program, repeatedly
Ti htlTi htl t i dt i dTightlyTightly--constrainedconstrained–– Low cost, low power, small, fast, etc.Low cost, low power, small, fast, etc.
Reactive and realReactive and real--timetime–– Continually reacts to changes in the Continually reacts to changes in the 84% more
thansystem’s environmentsystem’s environment
–– Must compute certain results in realMust compute certain results in real--time time
AMDREL25% more
than
1010
without delaywithout delay AMDREL
Results for Infenion EasyPortResults for Infenion EasyPortResults for Infenion EasyPortResults for Infenion EasyPort
Lower fragmentation level than Lea 2.7.2Lower fragmentation level than Lea 2.7.2Higher performance than the WinXPHigher performance than the WinXP
1111
Higher performance than the WinXP Higher performance than the WinXP allocator modelallocator model
AMDREL: Architecture of a fullAMDREL: Architecture of a full--custom designed FPGA Hardwarecustom designed FPGA Hardwarecustom designed FPGA Hardwarecustom designed FPGA Hardware
• The “island style”The island style
• Uniform routing channel architecture
• The I/O pads are evenly• The I/O pads are evenly distributed around the perimeter
1212
FPGA layout (8X8 array)FPGA layout (8X8 array)y ( y)y ( y)
Fine-grain Specs8X8-8X8 array
-Area: 5.8 X 6.1mm^2-Up to 330MHz(register-to-register delay)0 18 um CMOS STM-0.18 um CMOS STM
-6 metal layers-Core Power Supply: 1.8V-LSE configuration time: 42nsFull Configuration time: 2 9us-Full Configuration time: 2.9us
-20 tracks on routing channels
I/O PINS96 Data I/Os-96 Data I/Os
-1 Global Reset -1 Global Clock-12-bit Configuration Address Bus
1313
Bus-16-bit Configuration Data Bus- Power/Ground pinsFull-custom design by AUTH,
Subcontractor in AMDREL
Design 3D FPGA architecturesDesign 3D FPGA architecturesDesign 3D FPGA architecturesDesign 3D FPGA architectures
A hit t l lA hit t l lArchitecture level Architecture level exploration of FPGAsexploration of FPGAs
–– Design an interconnectionDesign an interconnection–– Design an interconnection Design an interconnection network based on the network based on the connectivity demandsconnectivity demands
–– Temperature/Power Temperature/Power ––Aware Placement and Aware Placement and RoutingRouting 3D stack:Routing Routing
–– Alternative interconnection Alternative interconnection schemes for 3D viasschemes for 3D vias
3D stack:Reduced system sizeShort interconnectsReduced packaging
1414
Reduced packaging costLower power
Energy RequirementsEnergy RequirementsEnergy RequirementsEnergy Requirements
0,82
0,76
0,78
0,80
lized
en
ergy Energy
by 37%
Energy Savings by 37%
0,70
0,72
0,74
Nor
mal
0,64
0,66
0,68
0,62
,
100% 90% 80% 70% 60% 50% 40% 30% 20% 10%
2 Layers 3 Layers 4 Layers 5 Layers 6 Layers
% fabricated vias
1515
15
2 Layers 3 Layers 4 Layers 5 Layers 6 Layers
7 Layers 8 Layers 9 Layers 10 Layers
CAD Tools for 2D and 3D reconfigurable CAD Tools for 2D and 3D reconfigurable architectures:architectures:MEANDER Design FrameworkMEANDER Design Framework
Application description in HDL
Synthesis
Technology Mapping2D Flow 3D Flow
2D or 3DArchitecture?
EX-VPR
2D P&RPowerModel
2D architecture library
3DPRO
3DPower
3D architecture library
3D P&R
Bitstream generation
2D P&R 3D P&R
1616
Bitstream generation
Available for on-line execution at http://vlsi.ee.duth.gr/amdrel
Current and Future research Current and Future research trendstrends New marketsNew marketstrends trends -- New marketsNew markets
Dynamic multimedia and network Dynamic multimedia and network applicationsapplicationsapplicationsapplications
System Level modeling, exploration and System Level modeling, exploration and ti i titi i tioptimizationoptimization
RTOS RTOS –– realreal--time operating systems. Runtime operating systems. Run--time managementtime management
MultiMulti--core architecturecore architectureNetworkNetwork--onon--chip interconnectionschip interconnectionsNetworkNetwork onon chip interconnectionschip interconnections
⇒⇒ 3D 3D –– integrated circuitsintegrated circuits
1717
VLSI Design and Testing Center ActivitiesActivities
Personnel: 1 Professor, 2 PhDs, 4 G d d 4 M S dGraduate students, 4 M.Sc. studentsIt consists of: (a) Low Power Design Group and (b) Embedded SystemsGroup and (b) Embedded Systems GroupCooperation with leading universities, Cooperation with leading universities, institutes and industryinstitutes and industryinstitutes and industryinstitutes and industry
Funding from National and EUFunding from National and EUFunding from National and EU Funding from National and EU projects. More 20 projects (>1.2 mil. projects. More 20 projects (>1.2 mil. euros, the last 8 years)euros, the last 8 years)New projects in 7New projects in 7thth IST frameworkIST framework
1818
⇒⇒New projects in 7New projects in 7thth IST frameworkIST framework
VLSI Design and Testing Center Activities: AWARDSActivities: AWARDS
Award of 2,000$ VLSI 2005sponsored by Intel and
IBM, Arizona, USAVLSI 2005
1919
4-th Position for AMDREL project