Low Noise GaAs FET/BJT VCO

8/17/2019 Low Noise GaAs FET/BJT VCO

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A LOW PHASE-NOISE GaAs FET/BJT VOLTAGE-CONTROLLED OSCILLATORFOR MICROWAVE APPLICATIONS

1Vladimir Ulansky and

2Sally Faisal Ben Suleiman

1Department of Electronics, National Aviation University

Kosmonavta Komarova 1, Kiev, 03058, UkraineE-mail: [email protected]

2Department of Electronics, Carleton University1125 Colonel by Drive, Ottawa, Ontario, K1S5B6, Canada,

E-mail: [email protected]

Abstract - This paper presents a novel negative differential resistance (NDR) voltage-controlled oscillator (VCO)

for microwave applications. The VCO circuit comprises a GaAs field-effect transistor (FET) and a bipolar

junction transistor (BJT) current mirror. The VCO has an N -type I-V characteristic with controllable slope of the

NDR region. The mathematical models of the I-V characteristic are developed using three the most frequently

used models of GaAs FET drain current: Curtice, Statz and TOM. The designed VCO uses an n-channel GaAs

metal semiconductor field effect transistor (MESFET) NE722S01 and four p-n-p bipolar junction transistors

(BJTs) MRFC521. The VCO covers a frequency band between 1.233 GHz and 1.679 GHz with maximumin-band phase-noise of -146 dBc/Hz at 100-kHz offset over the tuning range. Power consumption of the VCO

core is 53 mW from a 6.5 V supply. The implemented prototype of the proposed oscillator draws 4 mA from a

3.2V power supply and generates low-noise low-distortion signal.

Keywords - metal semiconductor field effect transistor, varactor, current mirror, power consumption

1. INTRODUCTION

The VCOs are critical building blocks in all modern microwave communications systems and satellitetransceivers. The rapid growth of such systems has created a great demand for low phase-noise low powerconsumption VCOs. Modern microwave oscillators use the hetero-junction BJTs or low-noise high-electron

mobility transistors (HEMTs) as active devices for achieving low phase-noise performance [1], [2]. Aconsiderable amount of publications has been devoted to the MESFET oscillators [3] – [5]. All above mentioned

oscillators are related to the class of negative impedance oscillators having negative real part in the inputimpedance [6]. Another class of microwave oscillators is based on the Gunn and tunnel diodes [7], [8], which havean NDR region in the N -type current-voltage (I-V) characteristic. Locating the operating point in the NDR regionresults in creating a negative resistance induced into the tank circuit for compensating its losses. The N -type I-V

characteristic can be obtained artificially by using an electronic circuit, which generally consists of a FET withnegative gate-to-source voltage and a current mirror [9].

In this paper a GaAs FET VCO with a BJT improved Wilson current mirror (IWCM) is analysed anddesigned. The VCO performance characteristics are investigated by SPICE simulation.

2. ARCHITECTURE

The VCO circuit is shown in Fig. 1. The resistors R1 and R2, transistor Q1, and improved Wilson current

mirror (IWCM) transistors M1-M4 provide an N -type characteristic of the current I t versus voltage V CC .

Transistor Q1 can be a MESFET, HEMT or pseudomorphic HEMT. The VCO tank circuit consists of a radio

frequency coil L and two contrary connected varactor diodes VD 1 and VD 2. Resistor Rctrl isolates the dc control

voltage line, V ctrl , from the VCO tank. Capacitors C 1 and C 2 are used for reducing the phase-noise and harmonic

distortions. The current mirror supplies almost equal currents I IN and I OUT to the drain of FET Q 1 and to ground.

In the circuit of Fig. 1, the current mirror input voltage V IN =2V EB, where V EB is the emitter-base junction voltage

of transistors M1M4. For the IWCM the input ( I IN ) and output ( I OUT ) currents are almost the same.

407978-1-4799-1068-7/13/$31.00 ©2013 IEEE


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Figure 1. The VCO circuit with IWCM

3. DC ANALYSIS

3.1. Analysis of I-V Characteristic

The negative differential resistance is obtained between points “a” and “b” in the circuit of Fig. 1. As

voltage V CC increases from zero, the current mirror and transistor Q1 are cut off. And the terminal current I t is

determined by the Ohm’s law

212 R RV I I CC t (1)

Until V CC equals

2211 R R RV V IN CC (2)

transistor Q1 is cut off. This region is indicated by the curve 0A in Fig. 2. At V CC 1, transistor Q1 turns ON andenters ohmic region because the voltage between drain and source of Q1 (V DS ) is very small.

Figure 2. Typical I-V characteristic of the VCO circuit

Since Q1 operates in the ohmic region then

P GS DS V V V (3)

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where V GS is the gate-to-source voltage of Q 1 and V P is the pinch-off voltage of Q1.

The drain-to-source and gate-to-source voltages are found by applying the KVL to the circuit of Fig. 1

IN IN CC DS V R R I R R

RV V

21

21

2 (4)

2121

1 R R I R R

RV V IN

CC GS

(5)

Applying the KCL to the node “a” in the circuit of Fig. 1, the terminal current I t can be found as

2121

2

R R

V I

R R

R I I CC OUT

IN t

(6)

It should be noted that in general the current I OUT is a function of the input current I IN .

As V CC is increased further, transistor Q1 enters the saturation region where

P GS DS V V V (7)

The threshold voltage V CC 2 is in the vicinity of the boundary between the ohmic and saturation regions of

Q1, and can be represented as

P IN CC V V V 2 (8)

Thus, the I-V characteristic has a positive slope between voltages V CC 1 and V CC 2. From equations (2) and (8)

follows that for reducing the interval of the supply voltages, where the I-V characteristic has a positive slope,

the current mirror input voltage, V IN , must be as small as possible.As V CC is increased further, the current I IN , which is the drain current of Q1, decreases due to the increasing

negative voltage V GS . And this drop in current I IN exceeds the rise in current I 2. Hence, the terminal current I t

begins to decrease as the voltage V CC is raised. This is the NDR region shown in Fig. 2 as line BC.

As V CC is increased further, eventually the decrease in currents I IN and I OUT becomes equal to the increase of

current I 2, that is

0CC t dV dI (9)

The voltage V CC 3 is shown as the valley point C in Fig. 2.

Any further increase of V CC results in increasing the terminal current I t . For V CC >V CC 3, the current I t is due

to the current I 2 and the decreasing currents I IN and I OUT . The currents I IN and I OUT become zero when the

gate-source voltage of transistor Q1 exceeds its pinch-off voltage, that is

P CC GS V R R RV V 211 (10)

From (10) finally follows that

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1213 R R RV V P CC (11)

3.2. Analytical Modeling the Drain Current of Q1

Neglecting the difference between currents I IN and I OUT in the first approximation we can assume that

IN OUT I I (12)

In this case equation (6) is simplified to

2121

21

R R

V

R R

R I I

CC IN t

(13)

However, the current I IN is the drain current of transistor Q 1, I IN = I D. Therefore (13) can be represented as

2121

21 R R

V

R R

R I I CC Dt

(14)

From (14) follows that the terminal current I t depends only on the resistor values, power supply voltage and

drain current of transistor Q1.

For the purpose of nonlinear modeling the microwave FETs, many models are available [10]. The following

three models are the most popular: the Curtice model, the Statz model, and the TOM (TriQuint’s Own Model).

The Curtice model defines the drain current in the saturation region with respect to the drain-source and

gate-source voltages as follows [10]:

DS DS P GS D V V V V I αtanhλ 1β2

(15)

where β, λ , and α are the model parameters; β is the transconductance, α is the tanh constant, and λ is the

channel length modulation coefficient.

Substituting V DS and V GS from (4) and (5) into (15) gives

21

21

221

21

2

2

21

21

1 αtanhλ 1β R R I V R R

RV R R I V

R R

RV V R R I

R R

RV I D IN

CC D IN

CC P D

CC D

(16)

As seen from (16), the drain current of Q1 is a nonlinear function of the Curtice model and VCO circuit

parameters.

The Statz static model is a modification of the Curtice model by means of replacing the hyperbolic tangent

function with a polynomial approximation. In the saturation region the Statz drain current equation is given by

[10]

P GS DS P GS D V V BV V V I 1λ 1β2

(17)

where B is the doping profile parameter.

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Substituting V DS and V GS from (4) and (5) into (17) finally results in the following equation:

IN D

CC

P DCC

P DCC

D V R R I

R R

RV

V R R I R R

RV B

V R R I R R

RV

I 21

21

2

21

21

1

2

21

21

1

λ 1

1

β

(18)

The TOM is popular because it fits the dc behavior of a FET accurately. The exponent in the

expression (V GS – V P )2 is changed from a constant 2 to the variable Q, so that the drain current is represented as

[10]

DS Q

P GS

Q

P GS D V V V V V I δβ1β (19)

The parameter δ in (19) is used for modeling the decreased drain conductance at low gate-source biases.

Substituting V DS and V GS from (4) and (5) into (19) results in the following equation:

IN D

Q

P DCC

Q

P DCC

D V R R I R R

RV V R R I

R R

RV V R R I

R R

RV I 21

21

2CC21

21

121

21

1 β1β δ (20)

The current I D as a function of V DD can be found numerically by solving the nonlinear equations (16), (18)

and (20). Then, by substituting I D into (14), the terminal current I t can be calculated.

4. SIMULATION R ESULTS

The simulation results were obtained using SPICE models of real components. A MESFET NE722S01 wasselected as transistor Q1. Four p-n-p BJTs of MRFC521 type were used for designing the IWCM. The values of

resistors R1 and R2 were chosen to be 0.47k Ω and 3.9k Ω, respectively. Panasonic resistors ERJ1GEJ471 and

ERJ2GEJ392 were selected. The simulated I-V characteristic of the VCO is shown in Fig. 3 by a solid line. As

seen, the NDR region is located between V CC 2=4V and V CC 3=31.2V. The dc operating point was selected at

V CCQ=6.5V and I tQ=8.2mA. The dot line in the NDR region corresponds to the theoretical approximations made

by using equations (16), (18) and (20). As seen from Fig. 3, a very good agreement exists between the simulated

and the theoretical results in the NDR region of the VCO I-V characteristic. Thus, any of the three obtained

equations (16), (18) and (20) can be used for modeling the drain current of transistor Q1 in the NDR region.

The surface mount varactor diodes SMV1104-34 were selected to change the VCO frequency from 1.233 to

1.679 GHz when a variable dc voltage V ctrl , applied to the diode cathodes, was changed from 2V to 12V. A

3.3-nH chip inductor ELJQF3N3 (Panasonic Semiconductors) was used in the VCO tank circuit. The values of

capacitors C 1 and C 2 were adjusted providing the following condition:

dB N C C

L21 ,

min (21)

where L N is the VCO phase noise. The optimized values of C 1 and C 2 are equal to 1nF and 100nF, respectively.

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Figure 3. The VCO I-V characteristics: solid line corresponds to the simulated characteristic; dot linecorresponds to the theoretical characteristics using the Curtice and Statz models, and the TOM

TDK and Panasonic multilayer chip capacitors C1005X5R1H102K (1nF) and ECJ1VB1C104K (100nF)

were selected as C 1 and C 2. The plots of simulated phase-noise versus offset frequency at V ctr =6V are shown in

Fig. 4. As seen, the phase-noise is very much dependent on the value of capacitors C 1 and C 2. The phase-noisedecreases until C 1 and C 2 reach 1nF and 100nF, respectively. A further increase in capacitance C 1 almost does

not reduce the phase-noise. While a further increase in capacitance C 2 even increases the phase-noise. The

phase-noise reaches a noise floor near -170dBc/Hz at offset frequency kHz600 f . It should be noted that themaximum in-band phase-noise of -146 dBc/Hz at 100-kHz offset is reached at V ctrl =2V. The amplitude of the

output voltage is varied from 2.7V to 3.7V when voltage V ctrl is changed from 2V to 12V.

(a) (b)

Figure 4. Simulated phase-noise of the proposed VCO at V ctrl =6V: (a) curve 1 – C 1=1pF, curve 2 - C 1=1nF;

(b) curve 1 – C 2=100pF, curve 2 – C 2=100nF

For evaluating the overall performance of the proposed VCO, a common FOM is used

mW1log10log20 0 diss N P f f f L FOM

where L N (Δ f ) is the phase-noise at a frequency offset f , f 0 is the oscillation frequency, and P diss is the power

dissipation. In Table 1, the phase-noise and FOM of the proposed VCO and earlier published VCOs are

compared. As can be seen from Table 1, the proposed VCO has very good performance.

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Table 1. Performance comparison of different VCOs

Reference Centralfrequency

(GHz)

Phase-noise(dBc/Hz)

FOM(dBc/Hz)

[11] 1.95 -126@100kHz -188.8

[12] 1.57 -120@1MHz -179.1[13] 2.0 -103@100kHz -182.2[14] 2.44 -134.3@1MHz -194.1

This work 1.456 -146@100kHz -212

5. EXPERIMENTAL R ESULTS

A prototype of the proposed oscillator was designed and implemented as shown in the photograph of Fig. 5

(a). The values of R1 and R2 were selected to be 270Ω and 2k Ω respectively. Agilent’s ATF-33143 low noise

PHEMT was used as transistor Q1. The IWCM was constructed using four BFT92 p-n-p BJTs. A 47nH chip

inductor of ELJRF47NJF2 type was selected. Radial silveredmica capacitors of 2.2pF were used instead of

varactors and capacitor C 1. The capacitor C 2 was set to 0. The oscillator output waveform is illustrated in Fig.

5(b). The measured I-V characteristic is shown in Fig. 5 (c). The operating point was selected in the NDR region

at V CCQ=3.2V with I tQ=4mA. The oscillator was connected to the oscilloscope through the unity gain buffer.

(a)

(b)

(c)

Figure 5. Practical implementation of the NDR oscillator circuit with IWCM: (a) the oscillator printed-circuit

board; (b) the oscillogram of the output voltage ; (c) the oscillator I-V characteristic.

True output voltage amplitude is around 1.2V with 20dB probe attenuation and approximately 18dB connecting

cable loss. The measured oscillation frequency is 230MHz. The measured frequency is less than its theoretical

value because of the parasitic capacitance of the printed circuit board and buffer input capacitance.

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CONCLUSION

A novel NDR VCO has been presented. It consists of a GaAs FET and a p-n-p BJT improved Wilson

current mirror. The mathematical modeling of the N -type I-V characteristic has been conducted using the TOM,

Curtice and Statz models. The designed VCO was simulated with Spice files of real components and showed

maximum in-band phase-noise of -146 dBc/Hz at 100-kHz offset frequency over the tuning range. With power

consumption of 53 mW, the VCO achieves a worst-case FOM of -212dBc/Hz, which is the best FOM at (12) -

GHz band. The operation principle of the proposed oscillator has been verified by implementing a 230 MHz

oscillator.

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Low Noise GaAs FET/BJT VCO