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Low Power and Error Resilient Probabilistic Floating Point Multiplier
By
Aman Gupta
200631001
SUBMITTED IN PARTIAL FULFILLMENT OF THE
REQUIREMENTS FOR THE DEGREE OF
Master of Science (by Research)
in
VLSI & Embedded Systems
Centre for VLSI & Embedded Systems Technologies
International Institute of Information Technology
Hyderabad, India
May 2011
ii
Copyright © 2011 by Aman Gupta
All Rights Reserved
iii
INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY
HYDERABAD, INDIA
CERTIFICATE
This is to certify that the work presented in this thesis, titled “Low Power and Error
Resilient Probabilistic Floating Point Multiplier” by Aman Gupta (200631001) submitted in
partial fulfillment for the award of the degree of Master of Science (by Research) in VLSI &
Embedded Systems, has been carried out under our supervision and it is not submitted elsewhere
for a degree.
__________ _____________
Date Advisor:
Prof. M. Satyam
Professor
IIIT, Hyderabad
__________ _____________
Date Advisor:
Prof. V. J. Mooney
Associate Professor
Georgia Tech, USA
and NTU, Singapore
iv
ACKNOWLEDGEMENTS
I would like to express my deepest gratitude to Prof. M. Satyam and Prof. Vincent J.
Mooney for providing invaluable guidance and encouragement which enabled me to accomplish
the work presented in this thesis. I would also like to thank them for providing significant
discussions and valuable feedback on different aspects of my work. The flexible and helpful
nature of both the advisors made it easier for me to pursue my research work in a simple and
exciting manner.
I would also like to thank Anshul Singh and Charvi Dhoot for their involvement in the
research discussions related to the work. I am grateful to Vinushree Chhajer for providing
constant support and motivation throughout the duration of my work. I take this opportunity to
thank Rishabh Ranjan, Jairaj Bhattacharya and Kirthi Krishna for their cooperation, discussions
and suggestions to the work.
Finally it is the support, encouragement and good wishes of my parents, my sister and
other family members without whom I would not have been able to complete my thesis. I thank
and owe my deepest regards to all of them and all others who have helped me directly or
indirectly.
v
ABSTRACT
Present day computing systems deal with calculations involving large range of numbers.
One of the ways by which such a wide number range can be provided is through the use of
floating point format for number representation. Among the floating point operations, floating
point multiplication has been a very power hungry operation, having the maximum share in the
power consumption in most of the applications. With the advent of mobile devices which have a
fixed power budget, there is a need for investigation of low power designs for a floating point
multiplier to trim down the power consumption of the whole system. The work presented in this
thesis aims at exploring techniques which can be used to reduce the power consumed in a single
precision floating point multiplier. We apply a combination of truncation and voltage scaling in
the mantissa multiplier to achieve power savings and implement redundancy in the exponent
calculation to attain error resilience.
With the scaling of technology and the supply voltage of CMOS transistors, it has been
predicted that noise will affect the correct functioning of circuits in the future technology nodes.
This will lead to computations which may not be deterministic but probabilistic. In such a
scenario, the technique of voltage scaling will lead to increased errors due to further reduction of
the noise margin. One of the methods by which the effect of the reduced noise margin can be
modeled is through introduction of random or Gaussian noise along with the signals. This noise
introduction results in erroneous calculation which is referred to as probabilistic computation in
this thesis.
Each of the low power techniques used (truncation and voltage scaling) lead to power
savings at the cost of errors in the computations. Hence, we apply these low power techniques in
the mantissa calculation of the floating point multiplier because it is less significant as compared
to the other calculations (exponent and sign) and is also the most power consuming calculation
of the floating point multiplier. This is done to achieve maximum power savings at the cost of
introducing some errors as far as the multiplication result is concerned. We also make the
exponent calculations less error prone by implementing redundancy in the exponent block. This
leads to substantial error reduction with very nominal increase in power, thereby keeping the
vi
overall error in the results low. By the low power techniques and redundancy we realize a
multiplier design with error tolerance and considerable power savings.
It is then demonstrated that sizeable amount of power savings can be achieved in a Ray
Tracing application by replacing a subset of the deterministic multiplications by probabilistic
multiplications. This was achieved at the cost of negligible degradation in the quality of the
output image generated.
vii
Table of Contents
List of Figures .............................................................................................. x
List of Tables ............................................................................................... xi
List of Relevant Publications ..................................................................... xii
1 Introduction .......................................................................................... 1
1.1 Probabilistic Computation ......................................................................................2
1.2 Target Applications for Energy Savings .................................................................3
1.3 Contributions of this Thesis ...................................................................................4
1.4 Thesis Organization ...............................................................................................5
2 Background/Basics ............................................................................... 6
2.1 Floating Point Multiplier ........................................................................................6
2.1.1 Floating Point Number Representation ............................................................6
2.1.2 Floating Point Multiplication ..........................................................................7
2.1.3 Implementation of a Single Precision Floating Point Multiplier.......................8
2.2 Probabilistic Computation .................................................................................... 14
2.2.1 Noise Modeling ............................................................................................ 14
2.3 Some Techniques for Power Reduction ................................................................ 18
2.3.1 Dynamic Power Reduction by Voltage Scaling ............................................. 18
2.3.2 Static Power Reduction by Threshold Voltage Variation ............................... 19
2.3.3 Truncation .................................................................................................... 19
2.4 Techniques for Improving Reliability of Circuits ................................................. 19
2.4.1 Redundancy .................................................................................................. 19
2.5 Simulation Environment ...................................................................................... 20
viii
3 Prior Work ...........................................................................................22
3.1 Low Power Floating Point Multiplier ................................................................... 22
3.2 Probabilistic Computation .................................................................................... 23
4 Low Power Probabilistic Floating Point Multiplier...........................25
4.1 Factors involved in the choice of Probabilistic Components ................................. 25
4.1.1 Significance of the Calculation ..................................................................... 25
4.1.2 Power Consumption of the Computation Block ............................................. 26
4.2 Low Power Probabilistic Design .......................................................................... 27
4.2.1 Probabilistic 24-bit Mantissa Multiplier ........................................................ 28
4.3 Low Power Techniques Used in the Floating Point Multiplier .............................. 30
4.3.1 Truncation Technique ................................................................................... 30
4.3.2 BIased VOltage Scaling (BIVOS) Technique ................................................ 31
4.3.3 The Proposed BIVOS + Truncation Technique ............................................. 32
5 C Simulator for Error Rate and Energy Calculations ......................34
5.1 Error Rate Simulation .......................................................................................... 34
5.1.1 Error Rate Calculation for a 1-bit Full Adder Using HSPICE ........................ 35
5.1.2 Error Rate Calculation for the Mantissa Multiplier Using the C Simulator .... 38
5.2 Energy Simulation ............................................................................................... 40
5.2.1 Energy Calculations for Sum and Carry Toggle Using HSPICE .................... 40
5.2.2 Toggle Rate Calculations for a Multiplier Using Verilog ............................... 42
5.2.3 Energy Calculation of the Mantissa Multiplier Using the C simulator ........... 43
6 Application Example: Ray Tracing ....................................................44
7 Experimental Simulations and Results ...............................................47
7.1 Low Power Design for Floating Point Multiplier .................................................. 47
ix
7.1.1 Details of Simulation Parameters .................................................................. 48
7.1.2 Mantissa Multiplier Simulation ..................................................................... 49
7.1.3 Application of the Low Power Techniques on the Ray Tracing Algorithm .... 54
8 Error Resilient Probabilistic Floating Point Multiplier ....................58
8.1 Error Resilient Probabilistic Design ..................................................................... 59
8.1.1 Critical Calculations in a Floating Point Multiplier ....................................... 59
8.1.2 Technique to Attain Error Resilience ............................................................ 59
8.1.3 Redundant Floating Point Multiplier Design ................................................. 60
8.2 Noise Modeling ................................................................................................... 61
8.2.1 Noise Modeling of Gates .............................................................................. 63
8.2.2 Noise Modeling of the Majority Voting Circuit ............................................. 64
8.3 Methods of Implementing Redundancy in Exponent Addition .............................. 66
8.3.1 Intra Adder Redundancy ............................................................................... 66
8.3.2 Inter Adder Redundancy ............................................................................... 66
8.4 Experimental Method ........................................................................................... 68
8.5 Simulations and Results ....................................................................................... 69
8.5.1 Inter Vs Intra Adder Redundancy .................................................................. 69
8.5.2 Triple-Modular Redundancy (TMR) Vs Five-Modular Redundancy (FMR) .. 70
Conclusion ...................................................................................................76
Appendix A: C Simulator Vs HSPICE ......................................................79
Bibliography ................................................................................................82
x
List of Figures
Figure 2-1: A General Floating Point Number Format .................................................................6
Figure 2-2: Single Precision Floating Point Multiplier Architecture .............................................9
Figure 2-3: Mantissa Multiplication .......................................................................................... 10
Figure 2-4: Rounding of Normalized Floating Point Numbers ................................................... 12
Figure 2-5: Gaussian Noise Samples with Mean=0 and RMS=0.2 ............................................. 15
Figure 2-6: Simulation of Noisy Behavior of a Full Adder......................................................... 16
Figure 2-7: Gaussian Noise Addition on Logic 0 and Logic 1 .................................................... 17
Figure 2-8: Increase in Error Samples Due to Voltage Reduction .............................................. 17
Figure 4-1: Probabilistic Floating Point Multiplier .................................................................... 28
Figure 4-2: A 24-bit Array Multiplier Structure ......................................................................... 29
Figure 5-1: Schematic of a Probabilistic Full Adder .................................................................. 35
Figure 5-2: Probability of Error Vs Supply Voltage ................................................................... 36
Figure 5-3: Full Adder Transistor Diagram................................................................................ 41
Figure 5-4: Energy per Toggle Vs Supply Voltage .................................................................... 42
Figure 6-1: Ray Tracing Algorithm ........................................................................................... 44
Figure 7-1: Energy – Error Relationship .................................................................................... 51
Figure 7-2: Images with Ray Tracing ........................................................................................ 56
Figure 8-1: Redundant Floating Point Multiplier ....................................................................... 60
Figure 8-2: Error Regions in a Gaussian Noise Environment ..................................................... 61
Figure 8-3: Gate Level Diagram of a Full Adder ....................................................................... 63
Figure 8-4: Noise Modeling of a Full Adder .............................................................................. 64
Figure 8-5: Noisy 3-way Majority Voting Circuit ...................................................................... 65
Figure 8-6: Noisy 5-way Majority Voting Circuit ...................................................................... 65
Figure 8-7: An 8-bit Ripple Carry Adder (RCA) ....................................................................... 66
Figure 8-8: Intra Adder Redundancy ......................................................................................... 67
Figure 8-9: Inter Adder Redundancy ......................................................................................... 67
Figure 8-10: Probability of Error with Inter & Intra Adder Redundancy .................................... 70
Figure 8-11: Error Magnitude of Non Redundant and Redundant Designs Vs Noise RMS......... 71
Figure 8-12: Probability of Error Comparisons in No Redundancy Vs TMR Vs FMR ............... 73
xi
List of Tables
Table 2-1: Bit Allocation to Various Types/Precision of Floating Point Representation ...............7
Table 4-1: Power Dissipation in a Single Precision Floating Point Multiplier [10] ..................... 26
Table 4-2: Example of a Voltage Profile for Truncation Technique ........................................... 31
Table 4-3: Example of a Voltage Profile for BIVOS Technique ................................................ 32
Table 4-4: Example of a Voltage Profile for the BIVOS + Truncation Technique ...................... 33
Table 5-1: Error Rate Characterization of a Full Adder.............................................................. 37
Table 5-2: Error Rate of a FA Feeding Carry to FA of Higher Supply Voltage .......................... 38
Table 5-3: Energy Characterization of a Full Adder................................................................... 41
Table 7-1: Error Magnitude Vs Energy Consumed for Truncation ............................................. 51
Table 7-2: Error Magnitude Vs Energy Consumed for BIVOS .................................................. 52
Table 7-3: Error Magnitude Vs Energy Consumed for BIVOS + Truncation ............................. 52
Table 7-4: Comparison of Low Power Schemes ........................................................................ 53
Table 7-5: Image Quality in dB Vs Energy Consumed .............................................................. 57
Table 8-1: Noise RMS Vs Error Magnitude ............................................................................... 71
Table 8-2: Comparison of Percentage Reduction in Error Magnitude with Noise RMS.............. 72
Table 8-3: Probability of Error Vs Redundancy at Each Exponent Bit ....................................... 73
Table 8-4: Area of Designs with Redundancy Vs Probability of Error ....................................... 74
xii
List of Relevant Publications
Aman Gupta, M. Satyam, V. J. Mooney, K. V. Ling, A. Basu, H. Johan and B.
Tandianus, “Low Power Probabilistic Floating Point Multiplier Design,” to appear in
ISVLSI 2011, July 2011, Chennai, India
Aman Gupta, V. J. Mooney, M. Satyam, “Minimal Redundancy for Resilient Floating
Point Multiplication in an Erroneous Future Silicon Technology Node,” VLSI-SoC
2011, October 3-5, 2011, Hong Kong, China (Under Review)
1
Chapter 1
1 Introduction
Modern computing systems use extensive arithmetic calculations involving large range of
numbers. There are various number formats available for representation, e.g., integer, fixed point
and floating point. Integers are used to represent natural numbers (including 0) while fixed point
and floating point representations have the capability to also represent numbers with fractional
parts. Different number formats have different range of numbers that can be represented. In a
fixed point representation, the position of the radix point is fixed in the sense that the number of
digits allocated to the fractional part is known beforehand. On the other hand, in a floating point
representation the position of the radix point can be anywhere relative to the digits and hence the
name “floating” point. Variable position of the radix point enables the floating point format to
provide a wide dynamic range number representation as compared to other number formats such
as fixed point and integer.
A floating point number has three components, namely, sign, exponent and
mantissa/significand. The information about the significant digits of the floating point number is
stored in the mantissa part while the position of the radix point is stored in the exponent. The
sign bit is used to represent the sign of the floating point number. The encoding of the value of
the floating point number in separate components along with the variable position of the radix
point makes it hard to perform even simple arithmetic operations such as addition and
multiplication on floating point numbers. Floating point arithmetic operations require complex
circuits consuming large area and power as compared to the circuits for fixed point and integer
operations. Hence, the wide number range comes at the cost of including a power (and area)
hungry floating point unit in an architecture. The use of floating point in embedded systems can
be limited because of its huge power utilization when implemented in hardware. But since there
are applications which require a wide range of numbers, it becomes inevitable to include a
floating point unit in the architecture. As the power budget of mobile devices is limited, there is a
need for designing low power circuits for floating point operations so that the overall power
2
expenditure of the system can be brought down. Hence, techniques which reduce power
consumption of the floating point units need to be investigated.
Among the most extensively used floating point operations, floating point multiplication is
typically the most frequent power consuming operation. Hence, the focus of the work presented
here is to attain low power floating point multiplication. Several investigations are carried out to
arrive at methods and circuits which result in low power floating point multiplications. Some
methods are proposed where the power of the floating point multiplication is reduced at the
expense of accuracy as demonstrated in [1] [2]. This thought process is the basis for the
investigations that are carried out in this thesis. In our work, we aim to explore a tradeoff
traditionally underutilized, namely, the tradeoff between power (energy) and the accuracy of
computation, i.e., savings in energy are gained at the cost of errors in the computations. The
accuracy of the computation may be interpreted as the probability of correct computation. In this
thesis, we call this somewhat inaccurate computation as probabilistic computation.
1.1 Probabilistic Computation
Probabilistic computation can be seen as a technique to achieve power savings in an
arithmetic circuit by trading off the accuracy of the computation. The idea of probabilistic
computation [3] [4] [5] is to devote energy in a circuit such that more energy is invested in more
significant calculations and less energy is invested in less significant calculations. This biased
energy investment is done keeping in view that calculations which are more significant have a
larger contribution in the computed result than the calculations which are less significant.
In the work presented here, energy investment is reduced by operating the less significant
circuitry either at a lower supply voltage or by putting off the power of the gates. But, as the
technology scales down, it is predicted in [6] that thermal noise is going to have a considerable
effect in the correct functioning of circuits. Hence, reducing voltage will lead to a decrease in the
noise immunity of a circuit. This means that, at a lower supply voltage, noise will have a greater
impact which may lead to erroneous results. Thus, there is a need for modeling the effect of
device noise for future technology nodes, which becomes all the more essential when using
voltage scaling. This leads to generation of tradeoffs between energy and accuracy, as lower
energy means lowering of supply voltage which in turn will lead to more erroneous calculations.
3
Such an attempt to develop energy efficient signal processing using probabilistic computations is
presented in [4] in which noise induced probabilistic behavior of the arithmetic circuits is
demonstrated.
Different calculations in a circuit have different sensitivity to errors. Calculations which
are less sensitive to errors can afford more errors and thereby provide more energy savings.
Hence, use of probabilistic computation to gain energy savings requires identification of the
calculations which can afford errors. Depending on the application in which the computations are
used, the amount of errors that can be tolerated in the calculation may vary and hence the energy
savings will also vary.
1.2 Target Applications for Energy Savings
It has been demonstrated in a lot of prior work [4] [5] that substantial energy can be saved
in applications by providing an acceptable or “reasonably good” result rather than the exact
result. By “reasonably good” we mean that the perceived quality of the output is almost the same
as the output generated from exact computations. The target applications for harnessing these
energy savings are mainly those applications, which generate data for human perception like
image and signal processing applications, and can trade some accuracy of the computation in
order to achieve energy savings.
Power can also be traded off with accuracy in those applications where the calculations
need not be very accurate and some percentage of error in the computation value can be
tolerated. An example of such a scenario is a Fuzzy system where the computations need not be
exactly correct but are limited to certain bounds. This type of requirement is perhaps present in
control systems where action is to be initiated based on the value lying between certain bounds.
One application which extensively uses floating point numbers is ray tracing [7]. Ray
tracing is a technique for generating photorealistic images by simulating the behavior of viewing
and light rays as in an actual physical environment. The algorithm requires a large dynamic
range of numbers and uses floating point representation for this purpose. A major share of the
total arithmetic operations required by a typical ray tracing algorithm is composed of single
precision floating point multiplications. Since this application uses floating point operations to
4
generate data for human perception, we conduct experiments on the ray tracing algorithm to
demonstrate the validity of the use of probabilistic multiplications to achieve low power in
floating point calculations. The primary idea is to exploit the dynamics of human perceptual
cognition to facilitate energy savings.
1.3 Contributions of this Thesis
The work presented in the thesis attempts at reducing the power in the floating point
multiplier while maintaining a tolerable accuracy in three stages:-
By truncating some of the gates in the mantissa multiplier which are used for less
significant calculations
By scaling the supply voltage of the remaining gates in the mantissa multiplier
By strengthening the accuracy scenario in the exponent calculations by the use of
redundant units, even though it implies slightly increased energy
With the implementation of the first two techniques it has been found that the performance
from the point of errors has deteriorated marginally with considerable savings in the power. With
the third technique, it has been demonstrated that the use of redundant circuits leads to
substantial reduction in the exponent error rate without much increase in the power consumption.
The need for reducing the error rate of the exponent arises because it is a very critical
computation in the floating point multiplier.
The thesis may be seen to contribute the following:-
1. It has been shown that considerable energy savings can be achieved by truncating
the mantissa appropriately with marginal change in the error performance
2. Application of voltage scaling in the remaining gates of the mantissa multiplier
leads to further reduction in energy by maintaining a tolerable error rate
3. The error performance can be improved considerably with marginal increase in the
power consumption by introducing redundancy in the exponent block
5
1.4 Thesis Organization
The rest of the thesis is organized as follows:-
Chapter 2 explains the basic concepts and functioning of the floating point
multiplier along with the idea of probabilistic computation and how noise is
modeled in the circuits.
Chapter 3 describes some of the prior work that has been done to reduce the power
consumed in a floating point multiplier and previous work done in the field of
probabilistic computing to attain energy efficient designs.
Chapter 4 presents the probabilistic design of the floating point multiplier and
explains the logic blocks of the floating point multiplier that are made probabilistic.
This chapter then describes the low power techniques that are implemented in the
probabilistic design.
Chapter 5 describes the C simulator developed to calculate the error rate and the
energy of the mantissa multiplier as simulations in HSPICE consume unreasonable
amount of time.
Chapter 6 explains the target application of Ray Tracing which is an algorithm used
for rendering of images and is presented here to validate the use of probabilistic
floating point multiplication.
Chapter 7 describes the simulations in details and shows the energy-error tradeoffs
for a floating point multiplier. This chapter also provides the results of application
of probabilistic multiplications on the Ray Tracing algorithm.
Chapter 8 provides details of the critical calculations in a floating point multiplier
which require error resilience and then describes how redundancy can be
implemented to bring down the error rate. The simulation results for the error
resilient design are also provided in this chapter.
Chapter 9 provides the conclusion of the work presented in the thesis
6
Chapter 2
2 Background/Basics
2.1 Floating Point Multiplier
2.1.1 Floating Point Number Representation
The scientific numbers used in various applications are stored in the computer as floating
point numbers. As the name suggests, these numbers have a “floating” radix point. An example
of a floating point number in decimal representation is −2.34 ∗ 104. The same number can be
represented as −23.4 ∗ 103 or −0.234 ∗ 105 but the correct scientific notation of the number
needs to have only one non-zero decimal value before the decimal point. When the numbers are
represented in binary format, the radix point is termed as the binary point. Similar to the decimal
representation, the standard representation in the binary format requires only one non-zero binary
value before the binary point. Since binary has only 1/0, the value before the binary point is
always 1. The value of the base is 2. An example of a binary floating point number
is 1.011001 ∗ 27. This way of representation is termed as normalized representation of a floating
point number.
A floating point number has three components, namely, sign, exponent and mantissa. The
bits are stored in such a way that the most significant bit is reserved for the sign of the floating
point number. The next set of bits store the value of the exponent followed by the mantissa bits.
The general format of a floating point number is shown in Figure 2-1.
S E E E M M M M M M
Sign Exponent Mantissa
Figure 2-1: A General Floating Point Number Format
7
The normalized representation of a floating point number is such that the binary point lies
before the mantissa bits. The digit to the left of the binary point is by default a 1 and is therefore
not stored, termed as the „hidden 1‟. Hence, the value of a normalized floating point number is
calculated as
𝐹𝑙𝑜𝑎𝑡𝑖𝑛𝑔 𝑃𝑜𝑖𝑛𝑡 𝑁𝑢𝑚𝑏𝑒𝑟 = 𝑆𝑖𝑔𝑛 1. 𝑀𝑎𝑛𝑡𝑖𝑠𝑠𝑎 ∗ 2𝐸𝑥𝑝𝑜𝑛𝑒𝑛𝑡
The precision that can be achieved from a format depends on the number of bits allocated
for representation. More the number of bits, greater is the precision in the number representation.
Depending on the precision of the numbers required, various bit length floating point
representations are provided in the IEEE Floating Point Standard [8]. The bit allocation for
various precisions is shown in Table 2-1. Amongst these, Single and Double precision formats
are the most extensively used floating point representations.
Table 2-1: Bit Allocation to Various Types/Precision of Floating Point Representation
Precision Sign Exponent Mantissa Total Bits
Half 1 5 10 16
Single 1 8 23 32
Double 1 11 52 64
Quad 1 15 112 128
2.1.2 Floating Point Multiplication
As this thesis deals with floating point multiplication, we present an example of a floating
point multiplication of two numbers to explain the concept. Consider two floating point numbers
A and B represented in the normalized form as
𝐴 = 𝑆𝑎 1. 𝑀𝑎 ∗ 2𝐸𝑎
𝐵 = 𝑆𝑏 1. 𝑀𝑏 ∗ 2𝐸𝑏
8
To calculate the floating point product, Z, of the two numbers A and B, we would need
three operations:-
Multiplication of the fractional part of the operands
Addition of the Exponents of the operands and
Calculation of the sign bit of the result
The equation for the result Z would be
𝑍 = 𝑆𝑎 ⨁ 𝑆𝑏 {1. 𝑀𝑎 ∗ 1. 𝑀𝑏 } ∗ 2𝐸𝑎+𝐸𝑏
After arriving at the above mentioned value of Z, two more operations namely,
Normalization and Rounding are done to arrive at the standard floating point representation of
the result. These operations are explained in detail in the next section. The final result (after
normalization and rounding) would be represented as
𝑍 = 𝑆𝑧 1. 𝑀𝑧 ∗ 2𝐸𝑧
2.1.3 Implementation of a Single Precision Floating Point Multiplier
In this thesis, we present our work on single precision floating point multiplication.
According to the IEEE standard [8], a single precision floating point number is represented as a
32 bit number with 23 mantissa bits, 8 exponent bits and 1 sign bit as shown in Table 2-1. The
architecture of a single precision floating point multiplier [9] is shown in Figure 2-2. Please note
that the result of the multiplication of two single precision floating point numbers is also a single
precision floating point number.
As explained, the normalized floating point representation has a „hidden 1‟ before the
mantissa bits. Hence the actual mantissa bit length is 24 bits including the „hidden 1‟.
Multiplication of two floating point numbers requires multiplication of the 24-bit mantissas of
the operands, addition of the 8-bit exponents and the calculation of the sign bit of the result.
These operations along with Normalization and Rounding are explained in detail in the following
sections.
9
Exponent (8) Mantissa (23)Sign (1)
24 bit
Multiplier
8 bit Adder
Shifter
Rounding
Unit
Mux
ControlIncrementer
Mux
1 1
Exponent (8) Mantissa (23)Sign (1)
Exponent (8) Mantissa (23)Sign (1)
Normalize
Operand 1 Operand 2
RESULT
Xor
Figure 2-2: Single Precision Floating Point Multiplier Architecture
2.1.3.1 Mantissa Calculation
The actual length of the mantissa of the operands is 24 bits. The mantissa multiplication is
performed by the 24-bit Multiplier block shown in Figure 2-2. The result of the 24-bit mantissa
multiplication is a 48-bit number. This number is then normalized to convert it into the standard
floating point representation. Since the product is a single precision floating point number, the
48-bit normalized mantissa has to be stored as a 24-bit mantissa of the multiplication result.
Hence, rounding is performed on the normalized 48 bits. These two operations are explained
below.
2.1.3.1.1 Normalization
Normalization is a process in which the number of leading zeroes in the 48-bit mantissa
product is calculated and the 48-bit product is shifted such that the binary point lies after the first
set bit. An example of a 24-bit mantissa multiplication is shown in Figure 2-3.
10
1.XXX XXXX
x 1.XXX XXXX
X X X X X X
X X X X X X
X X X X X X
1 X X X X X
Z1Z2.Z3 Z48
24-BIT MANTISSA 1
x 24-BIT MANTISSA 2
PRODUCT
Figure 2-3: Mantissa Multiplication
Since the most significant bit of each input mantissa is set (the hidden one), the partial
product bit leading to the calculation of the second Most Significant Bit (MSB) of the product,
Z2, is set. This means that during the product calculation either Z2 (the second MSB of the 48-bit
mantissa multiplication result) or Z1 (the MSB of the result) is set. The binary point in the result
lies after Z2 as shown in the Figure 2-3. If the MSB (Z1) is set, normalization would mean
shifting the number one place to the right so that there is only one set value before the binary
point. This would also require incrementing the value of the exponent by one. If the MSB (Z1) is
not set, this would mean that the second MSB (Z2) is set and the number is already in the
normalized format. Hence, it does not require any shifting. Thus in a single precision floating
point multiplier, normalization only requires shifting the mantissa product one place depending
on the value of the MSB of the mantissa product.
Another way to look at this is that, each mantissa value lies between a value of one and
two (the maximum value cannot be equal to two but can be just less than two). Hence, the
multiplication of two mantissas will yield a product value between one and four (less than four).
When the product value is less than two, the number is already in the normalized form but if the
value is between 2 and 4, a shift by one place (equivalent to division by 2) will result in a
number between one and two which is the normalized number. Hence, normalization would
either require a one bit shift or no shift at all.
11
The normalization process is carried out in the floating point multiplier by the Shifter and
the Incrementer as shown in the Figure 2-2. The Shifter is basically a set of Multiplexer (Mux)
gates, one for each bit. The inputs to the Mux gate of ith
bit position are the ith
and (i+1)th bits of
the mantissa product. The selection bit is the MSB of the 48-bit mantissa product. The Shifter
shifts the 48-bit mantissa multiplication result one place to the right and the Incrementer adds
one to the value of the exponent if the MSB of the 48-bit number is set. Otherwise, they just pass
the results without any changes. The normalized result is then passed to the Rounding Unit.
2.1.3.1.2 Rounding
Although the multiplication of the mantissas is a 48-bit number, the result has to be stored
in only 24 mantissa bits. Hence, the method of Rounding is used so that the stored 24-bit result is
as close as possible to the actual 48-bit product. Consider a number X, whose value is 6.47. If the
number has to be rounded to two decimal digits, the value of the number after the two decimal
digits is investigated. If that value is greater than half the maximum value representable, we
increment the least significant stored value by one. If it is less than half, we do not increment the
least significant value and just store the digits as it is. In our example, the value of the number
after two decimal digits is 7. Since 7 is greater than 5, one is added to 4, the least significant
stored value and the rounded off number is 6.5. Similarly in the binary representation we analyze
the value of the number formed by the bits that are not stored and if the number is greater than
half of the maximum value that can be represented, we add one to the least significant bit of the
stored value.
Three bits are used in rounding a binary floating point number. These are called the guard,
round and sticky bits. These bits are shown in Figure 2-4. The first bit, after the most significant
24 bits of the normalized mantissa value, is called the Guard bit. The next less significant bit
after the guard bit is called the Round bit. All the less significant bits after the Round bit
contribute to the value of the Sticky bit. If any one of the less significant bits after the Round bit
is set, the value of the Sticky bit is one. If all the less significant bits after the Round bit are zero
the value of the sticky bit is zero.
12
1.XXXXXXXXXXXXXXXXXXGRxxxxx
Hidden 1 23 Mantissa Bits
Guard
Round
Sticky
Figure 2-4: Rounding of Normalized Floating Point Numbers
If the value of the guard bit is zero, the contribution of the least significant 24 bits is less
than half the maximum value that can be represented by these bits, and hence, no change is made
in the value of the most significant 24 bits. On the other hand, if the guard bit is set and either the
round or the sticky bit is set, the contribution of the 24 LSBs is greater than half and a one is
added to the 24th MSB. When the guard bit is set and both the round and the sticky bits are zero,
then the contribution of the bits is exactly equal to half. In such a scenario, in the most widely
used rounding method, if the mantissa is odd, a one is added to its LSB but if the mantissa is
even, nothing is added. This method of rounding, called the roundTiesToEven [8], is the default
rounding mode in the floating point operations.
Please note that if all the 23 bits in the normalized mantissa are set and a one is added to
the LSB, then the one will ripple until the MSB. This will lead to a result which further requires
normalization. In such cases, the rounding unit generates a signal which is sent to the control
unit, as shown in Figure 2-2. This enables the Mux gate to select the rounded result and
normalization is performed again on the rounded result. The exponent value is incremented
accordingly.
The Rounding is performed on the normalized multiplication value to generate a 24-bit
mantissa. Out of these bits, the least significant 23 bits are stored as the mantissa of the output,
and the most significant bit, which is the „hidden 1‟, is not stored.
13
2.1.3.2 Exponent Calculation
The exponent addition is performed by an 8-bit Adder and an Incrementer. This is shown
in Figure 2-2. The 8-bit Adder takes the exponents of the operands as inputs and calculates the
sum. If the most significant bit of the 24-bit multiplier result is set, then there is a need to shift
the output of the 24-bit multiplier one place to the right to normalize it and also to increment the
value of the exponent by one. This increment is performed by an Incrementer, a unit which adds
one. Also, if there is a need for normalization again after rounding is performed, the Incrementer
is used again to add one, as shown in the Figure 2-2.
The value of the exponent is stored after an addition of a fixed exponent bias to the actual
exponent value. Exponent bias is used so that the value of the exponent is stored as an unsigned
number. The value of the bias is around half the maximum value that can be represented by the
exponent. For a single precision floating point number, the 8 exponent bits can represent
numbers up to 255. The exponent bias in this case is 127. The two extreme values of 0 and 255
are reserved for special number representation of zero and infinity, respectively. So the range of
the exponent allowed for normal number representation is actually [1,254]. This range changes
to [-126,127] with the introduction of exponent bias. In case of multiplication of two numbers,
the addition of the exponents should lie between -126 and 127 to be able to be represented in the
single precision format. If the addition is less than -126, the number is said to underflow and if
the addition is more than 127, the number is said to overflow. These cases along with the
occurrence of special numbers such as zero, infinity and NaNs in the operands are handled by an
Exception Handling Unit. When these cases arise special indicator signals are used to represent
the type of exception and a default way of handling the exception is undertaken. As the work
presented in this thesis does not land in the domain of special numbers we do not focus on
including and explaining the Exception Handling Unit in our work.
2.1.3.3 Sign bit Calculation
The sign bit of the result is calculated by a simple XOR operation on the sign bits of the
operands as shown in Figure 2-2.
The 23 rounded mantissa bits, along with the 8 bits from the exponent sum and the
calculated sign bit, form the 32-bit floating point multiplication result.
14
2.2 Probabilistic Computation
As the technology scales down, the size of the transistors is becoming smaller and smaller.
The supply voltage is also scaling down with technology. If the supply voltage is less, the gap
between the logic 1 and logic 0 is also narrow causing a reduction in the noise margin of the
circuits. This reduction of noise margin with technology scaling has posed a threat to reliable
computing in the future. It is predicted in [6] that at the current technology scaling rate, random
errors are expected to creep in the circuits due to noise in the future technology nodes. For this
reason, there is a need to model the effect of device noise for future technology nodes. In this
section we explain the widely used model for noise modeling along with a description of how
noise is modeled in the gates that are simulated in this thesis.
2.2.1 Noise Modeling
There are several noise sources in a device which may cause errors. Each noise source has
its own characteristics. The overall effect of the noise sources can be represented by a noise
source with Gaussian distribution which is usually called as Gaussian noise. The probability
density function, f(X), of the Gaussian distribution is given by
𝑓 𝑋 = 1
𝜎 2𝜋 𝑒𝑥𝑝 ( −
𝑋 − 𝑢 2
2𝜎2 )
where, u is the mean and σ is the standard deviation of the distribution of the random variable X.
The variance is given by the square of the standard deviation. When the mean of the
distribution is zero, the standard deviation is equal to the Root Mean Square (RMS) value of the
distribution. Hence, for a mean zero Gaussian distribution, the RMS value is sufficient for
describing the Gaussian distribution.
The thermal noise present in the circuits is modeled by a Gaussian distribution, i.e., the
instantaneous amplitude of the noise in the circuits is believed to follow a Gaussian distribution.
Generally, the frequency response is such that the amplitude of the noise is constant with
frequency and such a distribution is known as White noise. The noise is considered additive in
nature, i.e., the resultant signal is equal to the addition of the noise on the original signal and the
distribution is termed as Additive White Gaussian Noise (AWGN) distribution. True white noise
15
cannot exist as it is associated with infinite power. Normally the noise that is considered is band
limited noise. The thermal noise generated in the circuits is modeled as an AWGN. To model the
effect of noise in the circuits, we use Gaussian noise sources to generate Gaussian noise samples
and introduce these samples into the circuits.
2.2.1.1 Gaussian Noise Source
For carrying out simulations with noise, noise sources are available in tools like MATLAB
which can generate noise samples following a Gaussian distribution, given the mean and the
standard deviation as inputs. Since we use zero mean samples in our experiment, we use RMS
value to denote the characteristics of the noise. The Gaussian noise source is modeled in the
circuits with the help of MATLAB generated samples by connecting the samples in a triangular
fashion as shown in Figure 2-5. The plot is for 100 Gaussian samples with zero mean and RMS
value of 0.2. The amplitude of each sample denotes the value of noise (in volts) at that point of
time. Each noise sample is marked in the plot, shown in Figure 2-5, by a small circle.
Figure 2-5: Gaussian Noise Samples with Mean=0 and RMS=0.2
16
2.2.1.2 Simulation of Noise in Digital Circuits
A noisy gate is represented by an ideal gate along with a noise source which represents the
noise generated in the gate. To model the noise generated in a gate, a noise source is added at
each of the outputs of a gate [4]. The simulation of the noisy behavior of a full adder gate, which
has three inputs and two outputs, is shown in Figure 2-6. As seen from Figure 2-6, the ideal gate
generates the correct output and then noise sample is added at each output. The noise sources
considered in the experiments are uncorrelated and are independent of the inputs of the gate. The
noise samples generated from the noise sources are added to the signals generated by the gate to
arrive at the value of the resultant signals.
1-bit
FA
A B
Cin
Sum
Cout
Noise
Noise
Figure 2-6: Simulation of Noisy Behavior of a Full Adder
Logic 0 is considered 0V and logic 1 is considered equal to the supply voltage of the
circuits. Superimposition of Gaussian noise on logic 0 and logic 1 is shown in Figure 2-7. The
supply voltage is marked by Vdd1. If the correct logic value is 0 and the added noise sample is
greater than Vdd1/2 i.e., half the supply voltage, the final value is closer to logic 1 than logic 0.
This will lead to the value being read as logic 1 and is considered as an error. Similarly, if the
correct logic value is 1 and the added noise sample is less than -Vdd1/2, i.e., half the supply
voltage on the negative side, the final value is close to logic 0 and an error occurs. All these
samples are shown in Figure 2-7 marked by the area of the Gaussian curve at logic 1 having
value less than –Vdd1/2 and by the area of the Gaussian curve at logic 0 having value greater
than Vdd1/2. These are termed as error samples.
17
0 Vdd1Vdd1/2
Error Samples
Figure 2-7: Gaussian Noise Addition on Logic 0 and Logic 1
0 Vdd2Vdd2/2
Vdd2 < Vdd1
Error Samples
Figure 2-8: Increase in Error Samples Due to Voltage Reduction
The mean value of the Gaussian noise samples generated by the noise sources is
considered to be zero but the RMS is considered to be a finite value. The number of error
samples depends on the supply voltage and the noise RMS value. For a fixed RMS value, more
the supply voltage less is the number of error samples. On the other hand, as the supply voltage
decreases, there is a reduction in the noise margin. This reduction causes an increase in the
18
number of noise samples that are likely to cause errors. This is shown in Figure 2-8. As seen
from Figure 2-8, the area representing the error samples when the gate is operated at a lower
supply voltage Vdd2, is larger than the area with supply voltage Vdd1 (shown in Figure 2-7).
Hence, a reduction in the supply voltage causes an increase in the error rate of the probabilistic
gates. Thus a gate which is operated at a lower voltage is bound to have more errors than the gate
operated at a higher voltage for a fixed noise RMS value.
2.3 Some Techniques for Power Reduction
Lot of effort has been put in to investigate methods which can be used to reduce the power
consumed in CMOS circuits. With the advent of mobile devices, which have a low energy
budget, power reduction techniques become all the more essential. We explain some of the
techniques which are used for reduction of power in CMOS circuits.
The power consumed in a CMOS circuit can be broadly divided into dynamic energy
consumption and static energy consumption. Dynamic energy is the energy consumed when the
gates are changing their logic states depending on the inputs. The dynamic energy can be further
divided into switching and short circuit energy. Static energy is the energy consumed by the
circuit when there is no switching. This occurs due to a small amount of conduction in the
transistors even when they are off. Some of the techniques that focus on reducing dynamic
and/or static power are mentioned below.
2.3.1 Dynamic Power Reduction by Voltage Scaling
The power consumed in a CMOS circuit can be attributed mainly from the charging and
discharging of the nodal capacitances when there is switching in the logical state of the gate.
This energy consumed during the switching, E, is given by
𝐸 (𝑠𝑤𝑖𝑡𝑐𝑖𝑛𝑔) = 1
2 𝐶𝑉2
where C denotes the nodal capacitance and V denotes the supply voltage at which the gate is
operated. To bring down the power consumed by the circuits, the operational voltage of the
circuits can be reduced thereby reducing the switching energy for every transition. This leads to
power savings at the cost of increased delay in the gates and reduced noise margins. There is an
19
increase in the delay of the gates because of the reduction in the amount of current from the
lower supply voltage source which leads to an increase in the time for charging and discharging
of the load capacitances. Reduction of supply voltage reduces the noise immunity of the circuit
by reducing the gap between logic high and logic low. In a probabilistic scenario presented in the
previous section, this technique of voltage scaling will lead to errors in the circuits. These errors
will increase as the supply voltage is reduced thereby generating a tradeoff between the power
consumption and the accuracy of the computation.
2.3.2 Static Power Reduction by Threshold Voltage Variation
The power that is consumed in the circuit when the transistors are not switching is termed
as static power. Ideally, when the transistors are off, no current flows through the circuit but due
to effects like sub-threshold conduction, tunneling and leakage, power is dissipated even though
the transistors are in the off state. To reduce this power, the threshold voltage of the transistors is
increased thereby increasing the amount of voltage required to turn the transistor from off state
to on. This results in less conduction through the off transistor and saves the power. But the
increase in the threshold voltage causes the transistors to switch slowly thus increasing the delay
of the circuit. Multiple threshold voltage can be used where high threshold voltage is applied to
gates which are not in the critical path to save power and low threshold voltage is applied to
gates which are in the critical path to maintain performance (delay).
2.3.3 Truncation
The overall power consumed by a circuit can also be reduced by removing some of the
gates which are of less importance. This method is called truncation and leads to power savings
at the cost of decreased precision or errors in the computations. In some cases, when the
truncation is done on the gates which are in the critical path of the circuit, this method may lead
to a reduction in the overall delay of the circuit.
2.4 Techniques for Improving Reliability of Circuits
2.4.1 Redundancy
Circuits which are used for critical calculation are made redundant to ensure that the failure
rate is maintained very low and even if faults happen to occur, the majority of the redundant
20
circuits are fault free. In this method, N similar circuits are used to perform the same
computation and then the value that appears on the majority of the outputs of the N circuits is
taken as the final output. For example, in Triple Modular Redundancy (TMR), three copies of the
same circuit are made and the output value is considered to be the value which appears in at least
two of the three redundant outputs. In the scenario of probabilistic computing, where we are
trying to model future noisy gates, the circuits which calculate the majority vote of the redundant
outputs can also be erroneous.
2.5 Simulation Environment
MATLAB: - MATLAB is used to generate the noise samples that are used to model noise
in the circuits, as explained in Section 2.2.1.1. The inbuilt random function in MATLAB is used
to generate Gaussian samples by using the “normal” distribution option in the random function
which represents Normalized Gaussian Distribution. Since we use mean zero samples, the RMS
value is given as input for the generation of noise samples. These samples are then converted in a
Piece Wise Linear (PWL) format using MATLAB which is a format for representation of signals
in HSPICE. In this format, the value of the signal is defined at each point of time for which the
simulations are carried out. This type of format is generally used for representing signals which
are non periodic. A PWL waveform looks like the plot shown in Figure 2-5. This is done so that
the HSPICE can read the noise signals generated from MATLAB. The noise samples are
generated for each output of the gate in the circuit and are given as inputs to the HSPICE code.
HSPICE: - The definition of the gates in terms of transistors is written in HSPICE using
the models for NMOS and PMOS transistors available in the library provided by Synopsys. A
description of circuit developed from the gates is written in HSPICE. The average power
measurement feature available in HSPICE is used to measure the average power dissipated in the
gates of the simulated circuit. The noise signal generated from Gaussian samples in MATLAB is
added at the outputs of the gates in HSPICE to calculate the error rate of the gates. HSPICE
provides an analog simulation environment. Simulation of large circuits in HSPICE consumes a
large amount of time.
Verilog: - Verilog is a Hardware Description Language (HDL) which is used for modeling
of circuits and systems. The Verilog codes used in the work presented here are simulated on
21
Active HDL 6.3 which is an HDL simulation environment. Verilog provides a digital simulation
of the circuit and is faster as compared to HSPICE.
C : - The C programs written for the work presented here are compiled using gcc compiler
version 4.3.4. A program is written in this language for generating error rates of the mantissa
multiplier used in the floating point multiplier since simulations in HSPICE for a 24-bit mantissa
multiplier consume a lot of time. This is termed as the C simulator in the thesis and is explained
in detail in Chapter 5. The test vectors that are given as inputs to HSPICE for simulation of the
circuits are also generated through C.
22
Chapter 3
3 Prior Work
3.1 Low Power Floating Point Multiplier
Efforts have been made previously to reduce the power consumed by floating point
multipliers at the cost of having some calculation errors. This was achieved mostly by reducing
the number of bits of the operands or by truncating hardware in the floating point multiplier. The
results of floating point bit width reduction on various benchmarks are presented in [10]. The
authors have shown that with the use of a variable bit width floating point unit, large energy
savings can be achieved without sacrificing much program accuracy i.e., maintaining a tolerable
error rate.
It was analyzed in [10] that the maximum power consuming logic block in the floating
point multiplier is the mantissa multiplier and large bit width reduction in the mantissa bits can
be achieved even after maintaining high program accuracy. The rounding unit is shown to be the
next most power consuming logic block. It has also been shown in [10] that most of the
benchmarks are unaffected by ignoring the rounding off operation in the floating point
multiplication.
Truncating hardware in the floating point multiplier was shown in [1] [2]. Several of the
less significant columns of the mantissa multiplier were eliminated and the rounding logic for
floating point multiplication was simplified in [1]. This was done to achieve savings in area,
power and delay at the cost of a maximum error of less than one unit in the last significant place
in the mantissa.
A combined IEEE compliant and truncated floating point multiplier was presented in [2].
Digital signal processing and graphics applications in which strict adherence to the IEEE 754
floating point standard is often not necessary, were the target applications for truncated
multiplications in [2].
23
3.2 Probabilistic Computation
With technology scaling, the threat to reliable computing due to thermal noise has been
addressed in [6]. It is predicted in [6] that thermal noise is going to have a considerable effect on
the correct functioning of silicon circuits. It was pointed out that further increase of the
integration density of computer chips may face a physical limit. This can lead to abrupt and
major complications due to false bit occurrences generated by thermal fluctuations. Noise as an
obstacle in the functioning of the circuits is also addressed in [11] [12]. The International
Technology Roadmap for Semiconductors (ITRS) [13] predicts the following: “Relaxing the
requirement of 100% correctness for devices and interconnects may dramatically reduce costs of
manufacturing, verification, and test. Such a paradigm shift is likely forced in any case by
technology scaling, which leads to more transient and permanent failures of signals, logic
values, devices, and interconnects.”
Probabilistic computation, calculations which are correct with a certain probability, with
the aim to attain energy savings has been shown in [3] [14] [15] [16] [17]. It was shown that
applications which generate data for human perception can still work with some errors in the
computations. The main idea is to have fewer errors in more significant calculations and more
errors in less significant calculations, so that the effect of errors is minimal at the application
level.
Two ways in which probabilistic behavior can be induced in the arithmetic circuits,
namely, noise induced probabilistic behavior and delay induced probabilistic behavior were
discussed and application of noise induced probabilistic behavior to realize energy efficient
design was demonstrated in [4]. It was shown in [4] that energy savings of about 5.6X can be
achieved in an application when probabilistic arithmetic was used to compute Fast Fourier
Transform (FFT) in an energy efficient manner. Use of probabilistic computation in a ripple
carry adder and in a six bit integer array multiplier was done to gain low power. Significant
energy savings were shown at the cost of visually indistinguishable degradation in the quality of
the generated image with probabilistic arithmetic. These savings were achieved by application of
a novel voltage scaling method termed as BIased VOltage Scaling (BIVOS) in [4]. This method
of BIVOS invests energy in the gates depending on the significance of the calculation performed,
i.e., gates which calculate data for more significant bit positions are operated at a higher voltage
24
than the gates which calculate data for less significant bit positions. This was done to make sure
that large amount of energy can be saved with minimal amount of errors in the computation. This
was a novel idea over the conventional voltage scaling techniques [18] [19] where the voltage
scaling was done by the same amount in all bits independent of the bit position. The tradeoffs
between the energy consumed by the circuit and the probability of error were also demonstrated
in the work presented in [4]. Use of multiple supply voltages to reduce the power consumed in
the circuits was also shown in [20].
In the noise induced scenario, addition of noise is done to model the effect of noise in
future technology node. This noise addition leads to probabilistic behavior. In the delay induced
scenario, the voltage of operation of the gates is reduced without reducing the clock speed. Thus,
the gates are slowed down and this leads to errors in the computations due to propagation delay.
Such energy-error tradeoffs were investigated in the work presented in [21]. This technique was
then used to simulate probabilistic behavior in the current technology nodes without noise
addition.
Application of delay induced probabilistic behavior with voltage scaling in a Discrete
Fourier Transform technique for energy efficient design was shown in [5]. Voltage scaling was
demonstrated on a ripple carry adder to generate energy-error tradeoffs. Voltage assignment to
minimize energy usage of a probabilistic four bit integer array multiplier was done in [22]. The
array multiplier was divided into full adder columns and it was shown that full adders within a
column should be assigned the same supply voltage.
From this description it may be seen that attempts have been made to reduce the power
consumed in individual circuits like adders and multipliers by one of the techniques like
truncation or voltage scaling which was done mostly at the expense of tolerating errors. There
appears to be a possibility of applying both truncation and voltage scaling to reduce the power
consumption while maintaining a reasonable performance (low error rate). This may be possible
by reducing the errors produced in the exponent block while allowing a few errors in the
mantissa block. This thought process has been the background for the investigations reported in
this thesis.
25
Chapter 4
4 Low Power Probabilistic Floating Point
Multiplier
Probabilistic computation focuses on energy savings at the cost of lower precision and
some errors in the computations. The behavior of the components operated at lower energy is no
longer deterministic but probabilistic. This chapter explains the logic blocks of the floating point
multiplier that were made probabilistic and the design of the probabilistic floating point
multiplier. We then explain the low power techniques used in the probabilistic design to gain
energy savings.
4.1 Factors involved in the choice of Probabilistic Components
The techniques to attain low power are not applied in all the logic blocks of the floating
point multiplier. Some of the computational blocks are made probabilistic in such a manner that
maximum energy savings are attained with the least impact on the correctness of the
multiplication result. We now explain the factors that are involved in deciding which
components of the floating point multiplier can be made probabilistic.
4.1.1 Significance of the Calculation
A floating point number basically has three components, namely, exponent, mantissa and
sign. The value of a floating point number is calculated as value of the mantissa multiplied by the
base value raised to the value of the exponent as explained in Section 2.1.1. The base value here
is 2 as we are dealing in binary representation. Since the base is raised to the value of the
exponent, slight calculation errors in the value of the exponent can result in exponential
variations in the value of the floating point number. Also, errors in the sign bit can change
positive numbers into negative numbers and vice versa making this bit critical as well. The
mantissa part, on the other hand, can afford some calculation errors as it is less critical amongst
26
the three components, and is thus the target block for energy savings. Hence, depending on the
significance of the calculation the mantissa computation can be made probabilistic as it is less
significant as compared to the other calculations in the floating point format.
4.1.2 Power Consumption of the Computation Block
The other important factor that contributes in deciding which logic block can be made
probabilistic is the power consumed by various components in the circuit. The power dissipation
of various blocks as presented in [10] is shown in Table 4-1.
Table 4-1: Power Dissipation in a Single Precision Floating Point Multiplier [10]
Functional Block Power Dissipation (% of total)
Mantissa Multiplier 81.2
Rounding Unit 17.9
Exponent Unit 0.833
Others 0.066
The circuit diagram of the single precision floating point multiplier is shown in Figure 2-2.
As explained in Section 2, the mantissa multiplication is performed by the 24-bit Multiplier
block. It has been shown in [10] that 81% of the total power consumption of a single precision
floating point multiplier is from the 24-bit Multiplier block. As it is the maximum energy
consuming logic block in a floating point multiplier, energy savings on this logic block will be
substantial energy savings on the overall floating point multiplier. This is another factor that
makes mantissa calculation a prime component for energy savings. It happens to be in a floating
point multiplier that the least significant calculation (mantissa multiplication) is the maximum
energy consuming operation amongst all the operations in a floating point multiplication.
As seen from Table 4-1, the second most power consuming block is the rounding unit. The
rounding unit is used in the floating point multiplier to make sure that the multiplication result
stored is as close as possible to the exact multiplied value. This is because the precision of the
floating point multiplier is limited since a finite number of bits are used for number
representation. But in the probabilistic scenario where the computations may be incorrect, the
rounding unit is not much of a help. Rounding makes use of the less significant 24 bits of the
27
normalized result to decide on addition of one to the LSB of the mantissa. It can be seen that the
change in the value of the number due to rounding is equal to 2−23 , which is negligible. As we
are already making the computation erroneous, rounding or not rounding the result does not
make any significant change in the accuracy of the results. Also, given that the rounding unit is
the second most energy consuming unit of a single precision floating point multiplier, we choose
not to use any rounding in the probabilistic design of the floating point multiplier.
The rounding unit consumes around 18% of the total power [10]. Since we do not find
rounding to be needed in the probabilistic floating point multiplier design, around 99% of the
floating point multiplier energy is consumed in the 24-bit multiplier block. Hence, according to
the power consumption of various logic blocks, the 24-bit mantissa multiplier can be made
probabilistic.
4.2 Low Power Probabilistic Design
After investigation of the factors mentioned in the previous section, the logic block used
for mantissa multiplication in the floating point multiplier is made probabilistic in view of
harnessing maximum energy savings with minimal effect of the result. The block diagram of the
low power probabilistic floating point multiplier is shown in Figure 4-1. The difference between
the probabilistic design of Figure 4-1 and the typical design of Figure 2-2 is that
24-bit mantissa multiplier is made probabilistic
Rounding unit is not used
Except for the mantissa multiplier block, probabilistic techniques to achieve low power are
not implemented in any other logic block of the single precision floating point multiplier. We
now give the details of the 24-bit mantissa multiplier along with the circuit diagram in the
following section.
28
Exponent (8) Mantissa (23)Sign (1)
Probabilistic
24 bit Multiplier
8 bit Adder
ShifterControlIncrementer
1 1
Exponent (8) Mantissa (23)Sign (1)
Exponent (8) Mantissa (23)Sign (1)
Normalize
Operand 1 Operand 2
RESULT
Xor
Figure 4-1: Probabilistic Floating Point Multiplier
4.2.1 Probabilistic 24-bit Mantissa Multiplier
The low power techniques which make the circuit probabilistic are applied only to the
24-bit Multiplier block of the floating point multiplier used for mantissa multiplication. A 24-bit
Array multiplier, which is the most fundamental multiplier design, is chosen to implement the
mantissa multiplication. The circuit diagram of a 24-bit Array multiplier is shown in Figure 4-2.
The structure of an Array multiplier can be seen as full adders arranged in columns, each column
leading to a significant bit of the result, as shown in Figure 4-2. All the full adders within a
column contribute to the calculation of same significance. As explained, since the idea of
probabilistic computation is energy investment based on the calculation significance, use of an
Array multiplier makes it easier to realize and implement the low power techniques as the design
can be broken into full adder columns of different significance. The full adder columns leading
to calculation of more significant bits are termed as more significant columns while those leading
to calculation of less significant bits are termed as less significant columns.
The total number of columns in an Array multiplier is two less than the total number of
output bits since the least significant output bit, Z1, is directly the partial product bit, and the
29
most significant output bit, Z48, is the carry output of the full adder of the previous column.
Hence the number of columns in a 24-bit multiplier with 48 output bits is 46.
FAFAFAFA
FAFAFA
X1Y1X2Y1X24Y1
X1Y2X2Y2X23Y2X24Y2
FA
X3Y1
X1Y3X22Y3X24Y3 X23Y3
FAFAFA FA
X1Y24X22Y24X24Y24 X23Y24
Z2
Z1
Z3
Z24Z45Z46Z47Z48
Example of
a column
0
0
0
0
Figure 4-2: A 24-bit Array Multiplier Structure
The multiplier block consists of AND gates and full adders. The AND gates are used for
calculation of the partial product bits from the bits of the multiplication operands while the full
adders are used to calculate the sum of the partial product bits of same significance. All the bits,
shown in Figure 4-2, as XiYj are the partial product bits calculated by AND operation on the bits
Xi and Yj of the multiplication operands. The AND gates used for the calculation of the partial
product bits are not shown in the diagram.
In order to find out the blocks which consume considerable amount of power, the mantissa
multiplier made of AND gates and full adder was simulated using Synopsys 90nm technology. It
was seen from the experiment that the power consumed by the full adders is about 19 times the
power consumed by the AND gates. In other words, about 5% of the 24-bit multiplier block
energy is consumed by the AND gates. Hence, we focus on applying low power techniques only
in the full adders of the 24-bit multiplier block which consume 95% of the energy of the 24-bit
multiplier block. In our experiments, we take the energy savings achieved by the low power
techniques applied to the full adders to be approximately equivalent to the energy savings in the
whole multiplier.
30
4.3 Low Power Techniques Used in the Floating Point Multiplier
We basically use two techniques to attain low power in the mantissa multiplication of the
floating point multiplier. These low power techniques are based on either reducing the supply
voltage of the gates or in the extreme case putting off the non essential gates. Operating the
circuits at a lower voltage leads to increase in the error rate due to reduction in the noise margin.
These techniques make a multiplier circuit run at a lower power at the cost of some errors at the
output. Errors that can be tolerated in a calculation change with the bit position, i.e., errors in the
bits which have higher significance cause large errors in the result than errors in the bits of lower
significance. Hence, the higher significant bits can tolerate fewer errors whereas bits with lower
significance can tolerate more errors. With this basic idea, the lower voltages are used for gates
generating the lower significant bits and relatively higher voltages are used for gates generating
higher significant bits. In case of some of the LSBs, the power supply may be put off making
those circuits non operational. Each technique leads to different amount of power savings in the
circuit. More the energy savings more is the amount of errors in the calculations performed by
the circuit. Putting off the power supply of the gates leads to maximum savings in power.
The experiments presented in this thesis are performed using the Synopsys 90nm
technology library. The nominal voltage at 90nm technology is 1.2V. The supply voltage is
scaled to the following five voltages, namely, 1.2V, 1.1V, 1.0V, 0.9V and 0.8V, in that order,
applying higher voltage to higher significant calculations. The details of the simulation
parameters are provided in Chapter 7. A sequence of voltages which defines the supply voltage
of each full adder column is termed as a „voltage profile‟ of a multiplier. The low power
techniques are explained in the following sections.
4.3.1 Truncation Technique
The first technique, termed as the truncation technique, truncates some of the less
significant full adder columns of the array multiplier. The remaining full adder columns, which
are not truncated, are operated at the nominal technology voltage of 1.2V. All the outputs of the
truncated gates are considered to be logic 0. The larger the number of columns truncated, the less
is the energy consumed at the cost of decreased precision in the multiplication result. This
technique leads to maximum energy savings that can be attained from a gate since no power is
31
invested in the gate. These savings are at the expense of maximum errors in the computation as
no calculation is performed by the gates operated under this scheme. Since this technique has the
maximum error rate, we apply this technique in the least significant calculation within the
mantissa multiplier. This scheme is analogous to hardware truncation shown in [1] [2].
An example of a voltage profile for the 24-bit Multiplier operated under this scheme is
shown in Table 4-2. As explained earlier, a 24-bit Array multiplier has 46 full adder columns. A
column value of 1 refers to the least significant column whereas a column value of 46 refers to
the most significant column. As seen from the example, the least significant 23 columns are
truncated and the rest of the columns (24-46) are operated at the nominal technology voltage of
1.2V.
Table 4-2: Example of a Voltage Profile for Truncation Technique
Supply Voltage Truncation (0V) 1.2V
Columns
(LSB-MSB) 1-23 24-46
4.3.2 BIased VOltage Scaling (BIVOS) Technique
The second known technique makes use of BIased VOltage Scaling (BIVOS). This
technique invests less energy in the less significant calculation and more energy in the more
significant calculation by operating the gates which compute data of less significance at a lower
voltage than the gates which compute data of higher significance. Hence the name “Biased
Voltage Scaling” as the scaling is done biased to the significance of the calculation. More energy
is invested in the calculation of higher significant bits to ensure that fewer errors occur in more
significant bits.
The method of BIVOS was introduced and explained in [4]. This method was extended to
integer multipliers in [22], where the full adder columns receive a biased supply voltage
depending on the significance of the calculation performed by them. Full adders in the same
column receive the same supply voltage [22], since all the full adders in a column contribute to
the calculation of the same significance.
32
An example of a voltage profile for the 24-bit Multiplier operated under the BIVOS
scheme is shown in Table 4-3. In the example shown, the least significant 20 full adder columns
are operated at the lowest supply voltage of 0.8V and the supply voltage is increased as the
significance of the columns increases.
Table 4-3: Example of a Voltage Profile for BIVOS Technique
Supply Voltage 0.8V 0.9V 1.0V 1.1V 1.2V
Columns
(LSB-MSB) 1-20 21-29 30-33 34-35 36-46
4.3.3 The Proposed BIVOS + Truncation Technique
We propose a technique which builds on the Truncation and BIVOS techniques. It was
observed in the mantissa multiplication that the least significant calculations have a marginal
contribution in the final mantissa result. Hence, maximum errors can be tolerated in these
calculations. Thus in the proposed scheme, starting from the least significant columns, some
columns are truncated while the rest of the columns are given a biased supply voltage. The less
significant columns, which are not truncated, are operated at a lower voltage as compared to the
more significant columns. This BIVOS + Truncation technique is shown to out-perform either
the Truncation or the BIVOS technique alone.
The result of the 24-bit mantissa multiplication is a 48-bit number. This number is
normalized, which is a process in which the 48-bit number might be shifted one place to the right
or not shifted at all as explained in Section 2.1.3. After normalization, the least significant 24 bits
are used for rounding the result. As the probabilistic design does not implement rounding, the
least significant 24 bits are not used post normalization. Hence, large amount of errors can be
afforded in the least significant bits of the mantissa multiplication. Thus truncation is used in the
less significant full adder columns of the array multiplier used for mantissa multiplication to
harness maximum energy savings. We do not use any voltage shifters when passing a signal
from a gate operating at a lower voltage to a gate operating at a higher voltage. That is the reason
why we keep the difference between the voltage values small (0.1V).
33
An example of a voltage profile for the 24-bit Multiplier operated under the proposed
scheme is shown in Table 4-4. As seen from the example, the least significant 22 columns are
truncated and are non-operational. Columns after that are given a biased voltage supply
depending on the significance, i.e., lower significant columns 23-24 are operated at a lower
voltage as compared to the more significant columns 25-29 and so on.
Table 4-4: Example of a Voltage Profile for the BIVOS + Truncation Technique
Supply
Voltage Truncation
(0V) 0.8V 0.9V 1.0V 1.1V 1.2V
Columns
(LSB-MSB) 1-22 23-24 25-29 30-33 34-35 36-46
34
Chapter 5
5 C Simulator for Error Rate and Energy
Calculations
A single precision floating point multiplication requires a 24-bit mantissa multiplication.
Simulating a 24-bit Array multiplier in HSPICE for as few as 300 samples takes more than a day
on a high end machine which has Intel Core 2 Quad CPU at frequency 2.66 GHz with 4 GB main
memory. Also, since the performance of a multiplier in the presence of noise is a statistical
process, it is necessary to use large number of samples for simulations. The proposed low power
technique involves voltage scaling and application of thermal noise, which cannot be achieved in
traditional digital simulation environments which are faster than HSPICE. Since the usual
simulators used with Hardware Description Languages (HDLs) cannot be used for this
simulation and HSICE consumes unreasonable amount of simulation time, there is a need for a
simulator which can be used to quickly verify the applicability and provide comparisons of the
low power techniques in the floating point architecture, with a reasonable accuracy. This
motivated us to develop schemes to simulate error rate in the presence of noise and simulate the
energy consumed by the circuits which take very less simulation time as compared to HSPICE. It
has been found convenient to simulate the error rates through a C simulator developed for this
purpose. The energy estimates, however, have been based on information obtained through
Verilog, for the toggle rates, which is then used in the C simulator for energy estimation.
Whenever we refer to the C simulator in this thesis, we are referring to both the error rate and the
energy calculations.
5.1 Error Rate Simulation
In this section we explain how the error rate for the mantissa multiplier is calculated from
the C simulator. We calculate the error rate of a 1-bit full adder from HSPICE [23] and use that
35
in a C simulator to calculate the error rate at each output bit of a 24-bit mantissa multiplier. This
is explained in the following subsections.
5.1.1 Error Rate Calculation for a 1-bit Full Adder Using HSPICE
Deliberate injection of Gaussian noise at each full adder (FA) output is done to model the
effect of thermal noise in the circuit as explained in [23]. This is shown in Figure 5-1.
1-bit
FA
A B
Cin
Sum
Cout
Noise
Noise
Figure 5-1: Schematic of a Probabilistic Full Adder
We perform HSPICE simulations with a 90nm technology library from Synopsys. The
nominal supply voltage at this technology is 1.2V. The supply voltage of the full adders is varied
over five voltages, namely, 0.8V, 0.9V, 1.0V, 1.1V and 1.2V. The value of the root mean square
(RMS) of noise is chosen so that there are no errors at the output of the full adder when operated
at 1.2V even after injecting noise. The maximum noise RMS that does not cause any errors at
1.2V on the set of 100K samples obtained experimentally from HSPICE is found to be 0.15V. If
the supply voltage is lower than 1.2V, there are errors at the output which increase as the voltage
is lowered. In other words, in our experimental method, if the gates are operated at the nominal
technology voltage no errors arise at the output, but if voltage scaling is done to run the gates at a
lower supply voltage, there are errors at the output of the gates. This is how we predict a possible
noisy future technology node.
The full adder is simulated in HSPICE for the five stated supply voltages, at the noise
RMS of 0.15V. The load at the outputs of the full adders is also a full adder. We use the three
36
stage model for error modeling presented in [23] for error rate calculation of the full adders. The
full adder is fed by 100K random samples with uniform distribution of 1/0 at each input. These
random samples are generated from a C code. The Gaussian noise samples of RMS 0.15V and
zero mean are generated from MATLAB as explained in Section 2.2.1. The input samples
generated from the C code and the noise samples generated from MATLAB are given as inputs
to the HSPICE code for simulation of the probabilistic and the deterministic full adder. The
outputs of the probabilistic and the deterministic adders, for the same input sample, are compared
to calculate the number of errors that occur in the probabilistic design at each output. The sum
and the carry outputs are observed, and the probability of errors for each output is calculated as
explained in [23]. This process of calculating the error rate is termed as error rate
characterization. The simulations are repeated for all the supply voltage values and a look-up
table containing the error rate values corresponding to each voltage is formed. A graph showing
the probability of error for each voltage for the sum and the carry output is shown in Figure 5-2.
Figure 5-2: Probability of Error Vs Supply Voltage
37
Since no error was detected at the outputs of the full adder circuit operated at 1.2V for
noise RMS of 0.15V, the probability of error of sum and carry is zero for 1.2V. The value for the
error rate characterization of a full adder for each supply voltage is shown in Table 5-1.
Table 5-1: Error Rate Characterization of a Full Adder
Supply Voltage 0.8V 0.9V 1.0V 1.1V 1.2V
Probability of error of sum 3.9E-4 1.2E-4 5E-5 4E-5 0.0
Probability of error of carry 3E-4 9E-5 2E-5 0.0 0.0
As we use multiple voltages in the circuit, the error rate of a gate feeding its outputs to
another gate with the same supply voltage is different from the error rate of a gate feeding its
outputs to a gate with higher supply voltage. For example, consider a gate operating at 0.8V
feeding the carry output to another gate at 0.8V. For the gate at 0.8V, value below 0.4V is logic 0
and value above 0.4V is logic 1. If a noise sample of -0.37 occurs at the carry signal which is
logic 1 (0.8V), the value seen by the next gate (also operated at 0.8V) will be 0.43 (0.8 – 0.37).
This value is greater than 0.4 and will be taken as logic 1. Now, if a gate at 0.8V is feeding a gate
at 0.9V, the threshold for logic values at the second gate is 0.45. The same signal value of 0.43
will be taken as logic 0 since it is less than 0.45 and leads to an error. Hence, there is an increase
in the errors by incorrect reading of logic 1 to logic 0 during transition of signals from gates at
lower voltage to gates at higher voltage. Also there is a decrease in the errors from logic 0 to
logic 1 during this transition due to increase of logic threshold in the next gate. But this decrease
is much less than the increase in 1 to 0 errors and hence gates at the boundary of a lower voltage
feeding their outputs to gates at a higher voltage are simulated to get the error rates during this
voltage transition. Since all the full adders (FA) in a column are operated at the same voltage, the
sum output is always sent to the gate at the same voltage. Only the carry output might be sent to
a gate with higher supply voltage. Hence, error rates for the carry output are calculated and these
error rates are used at the boundary of two different voltages for error rate calculation. These
error rate values are shown in Table 5-2. As seen from the table, the error rates are high as
compared to the error rates when feeding the carry to the full adder with same supply voltage, as
given in Table 5-1. Allowing a gate at 0.8V to drive a gate at 1.0V will further increase the error
38
rate substantially. Hence in this experiment, we increase the voltage gradually in the same order,
i.e., a gate can feed gates which are either at the same supply voltage or at the immediate next
higher voltage, i.e., a gate at 0.8V can feed its outputs only to gates at either 0.8V or 0.9V.
Table 5-2: Error Rate of a FA Feeding Carry to FA of Higher Supply Voltage
Supply Voltage (From – To) 0.8V to 0.9V 0.9V to 1.0V 1.0V to 1.1V 1.1V to 1.2V
Probability of error of carry 9E-4 3.1E-4 1E-4 4E-5
5.1.2 Error Rate Calculation for the Mantissa Multiplier Using the C Simulator
The process of obtaining error rates of a full adder from HSPICE was explained in the
previous section. In this section we explain how the error rates of a full adder are used to
generate the error rates of the 24-bit multiplier output using the C simulator. First, we state the
timing assumptions that have been followed in the development of the simulator. It is assumed
that all the new inputs to a gate arrive at the same time. Hence, before calculating the output of
the current full adder in the circuit, all the gates whose outputs are the inputs of the current full
adder under consideration, have been simulated.
The C simulator has a full adder model which takes as input three bits and generates a
carry output and a sum output. Initially the correct outputs according to the inputs are calculated.
Each full adder then introduces errors at its outputs in accordance with the supply voltage, by
using the probability of error values from the error rate characterization of the full adder. Errors
are introduced in the full adder model of the C simulator with the help of the inbuilt random
number generator in C. We use the rand() function in C to generate uniformly distribute random
number between 0 and 1. The generated number is then compared with the probability of error
value (obtained from the characterization) of that output of the full adder. If the generated
number is less than the probability value, the output is flipped. This is how the probability of
error is used to introduce errors in the full adders of the C simulator. For example, say the
probability of error for a particular voltage is 0.3. This means that out of every 10 samples, 3
errors were obtained in the characterization. Now, we generate a random number between 0 and
39
1, and compare it with the probability value. Out of 10 random numbers from a uniform
distribution between 0 and 1, ideally three numbers will be less than 0.3. For all those numbers,
the output is flipped from its correct value to an erroneous value and hence the same number of
errors are generated in the C model as the number of errors in the characterization.
A description of the interconnection of the full adders to form the multiplier along with the
voltage profile and the error rate characterization of the full adder for each voltage are given as
inputs to the simulator. In the multiplication, each 24-bit input operand represents a mantissa of a
floating point number. Since these numbers represent mantissas, the most significant bit, i.e., the
24th bit for both operands (where the LSB is the 1
st bit) is fixed as 1 to model the „hidden 1‟ of a
normalized floating point mantissa. The less significant 23 bits are generated randomly with
equal chances for each bit to be 1/0. A model of a 24x24 array multiplier is developed in C
which takes as input two 24-bit numbers and generates the 48-bit multiplication result. The
binary operands representing the two mantissas are fed to the array multiplier model in the
simulator.
The voltage profile, which is a set of numbers and is one of the inputs to the simulator,
provides the value of the full adder columns that are operated at different supply voltages along
with the number of columns which are truncated. To model truncation in the simulator, the
partial product bits of the truncated columns are not calculated. Thus, the resultant bit, which is
the sum of the partial product bits of that column, remains as logic 0.
Each full adder in the array multiplier is fed with inputs according to the input operands
and the outputs of the previous gates, depending on the full adder‟s position in the array structure
shown in Figure 4-2. The generated outputs are propagated to the next gates. Errors are
generated at each full adder according to the supply voltage specified by the voltage profile, and
the 48-bit output is generated. The output is then normalized. The least significant 24 bits of this
normalized output are generally used for rounding. As the proposed floating point architecture
does not use any rounding, these bits are not considered in the result calculation. The most
significant 24 bits of the 48-bit normalized output forms the mantissa of the probabilistic result.
To calculate the error generated in the product, the probabilistic result needs to be compared with
the correct multiplication result. To do so, the same 24-bit input operands are correctly
multiplied to calculate the deterministic multiplication result. The absolute difference between
40
the value of the probabilistic result and the deterministic result is a measure of the error
generated. This absolute difference is termed as error magnitude. The multiplication is done for
100K samples and the value of error magnitude per sample is calculated by dividing the total
error magnitude by the total number of samples simulated. This value is used to evaluate the
amount of error generated by a low power scheme. The mantissa of the correct result is also
compared bitwise with the mantissa of the probabilistic result to generate the probability of error
of each bit at the output. The bitwise probability of error value is used to introduce errors in the
floating point multiplications of the Ray Tracing application.
5.2 Energy Simulation
Depending on the voltage profile, the circuit consumes different amounts of energy. The total
energy consumed by a gate depends on the number of toggles that occur at the gate‟s output and
the energy consumed per output toggle. We calculate, from HSPICE, the energy consumed when
the sum and the carry output of a full adder toggles. We then calculate the total number of
toggles that occur in a multiplier using Verilog and use this information in the C simulator to
calculate the total energy consumed in the multiplier. This is explained in the following sub
sections.
5.2.1 Energy Calculations for Sum and Carry Toggle Using HSPICE
The total energy consumed by the full adder can be divided into the energy consumed for sum
calculation and the energy consumed for carry calculation. The transistor diagram of a 1-bit full
adder with A, B and C as inputs, and Sum, Carry as outputs is shown in Figure 5-3. We identify
the part of the full adder circuit that calculates the sum output, shown in Figure 5-3 with supply
voltage named as „VDD_Sum‟, and the part of the full adder circuit that calculates the carry
output, shown in Figure 5-3 with supply voltage named as „VDD_Carry‟. We compute the
energy consumed in each part when the full adder is fed with 50K samples in HSPICE. This
provides the total energy consumed for sum calculation and the total energy consumed for carry
calculation. The input samples for this experiment were generated using random number
generation in C, and were fed as inputs in HSPICE, keeping uniform distribution of 1/0 at each
input. During the sample generation, the input samples were analyzed to calculate the total
number of toggles that will be generated by these samples at the sum and the carry output of the
41
full adder. We divide the total energy consumed for sum calculation by the total number of
toggles for sum to get the energy consumed per sum toggle. Similarly, we calculate the energy
consumed per carry toggle. These simulations are done for the five stated supply voltages, and a
look up table for every supply voltage is generated.
A B
C
A
B
A
BA B
A B C
A B C
A
A
B
B
C
C
VDD_Sum
VDD_Sum
VDD_Carry
Carry
VDD_Carry
VDD_Sum
Sum
Figure 5-3: Full Adder Transistor Diagram
Hence, for each supply voltage, the energy consumed per sum toggle, and the energy
consumed per carry toggle are tabulated. Such an energy characterization of the full adder at
each supply voltage is provided in Table 5-3. A graph showing this value is shown in Figure 5-4.
We assume that energy is consumed only when any output toggles. For the 90nm process we use,
leakage accounts for 0.1% of the energy consumed. For technologies with significant leakage,
we would need to add static power to our model.
Table 5-3: Energy Characterization of a Full Adder
Supply Voltage 0.8V 0.9V 1.0V 1.1V 1.2V
Energy consumed per
sum toggle ( x E-14 Joules)
2.24 2.96 3.85 4.90 5.97
Energy consumed per
carry toggle ( x E-14 Joules)
2.68 3.51 4.6 5.80 7.02
42
Figure 5-4: Energy per Toggle Vs Supply Voltage
5.2.2 Toggle Rate Calculations for a Multiplier Using Verilog
The energy consumed per carry toggle and per sum toggle is calculated as explained in the
previous section. To calculate the energy consumed by a larger circuit (e.g., an array multiplier)
consisting of full adders, the average number of toggles for sum and carry output for each of the
full adders in the circuit is required. A Verilog description of a 24-bit array multiplier was
simulated in ALDEC Active-HDL 6.3 [24] and its Toggle Coverage feature was used to
calculate the toggle rate. The number of toggles depends on the input to output delays of the full
adder. Hence, for each input combination, the delays from each input to each output were
calculated for the full adder from HSPICE. This was done for all the five voltages considered,
using the Synopsys 90nm library. Then, corresponding to each voltage, the delays were specified
in the Verilog description. The toggle rate was calculated for each low power scheme, given a
voltage profile, as the number of toggles is different for each scheme. Simulations were done for
50K random samples for each low power scheme with uniform distribution of 1/0 at each input
43
bit. The calculated average toggle rate for each sum and carry output of each full adder in the
multiplier circuit was then fed to the C simulator.
5.2.3 Energy Calculation of the Mantissa Multiplier Using the C simulator
The energy consumed per sum and carry toggle, and the toggle rate for each full adder
output of the multiplier along with the voltage profile for the multiplier are given as inputs to the
C simulator. Depending on the supply voltage of each full adder defined by the voltage profile,
the energy consumed per toggle for each output is multiplied by the average toggle rate of that
output in the C simulator to calculate the energy consumed by that full adder. The sum of the
energy consumed by each full adder gives the total energy consumed by the multiplier circuit.
A comparison of the results generated from HSPICE and the C simulator for 6 bit array
multiplier for the energy and error rate values are provided in Appendix A.
44
Chapter 6
6 Application Example: Ray Tracing
Ray tracing is a technique for generating photorealistic images by simulating the behavior
of viewing and light rays as in an actual physical environment. The algorithm requires a wide
range of numbers and thus uses floating point numbers for arithmetic operations. A flowchart
explaining the ray tracing algorithm along with the share of various arithmetic operations is
shown in Figure 6-1. It was observed in the algorithm that most of the arithmetic operations are
floating point multiplications. In the implemented ray tracing algorithm [7], single precision
floating point multiplications account for 54% of the total number of arithmetic operations as
shown in Figure 6-1.
Figure 6-1: Ray Tracing Algorithm
45
Out of the total multiplications, around 72% of the multiplications were from determinant
value calculations for matrices. These determinant calculations were of two types. Type 1
calculations were used in the algorithm to find the distance to the point of intersection. Type 2
calculations were used to find the interpolation parameters of the point of intersection.
Introduction of errors in the type 1 multiplications leads to wrong distance calculations. If the
distance calculated, using probabilistic multiplications, to the point of intersection of the ray,
yields a result less than the exact distance, the ray falls short of the point of intersection. On the
other hand, if the distance calculated is larger than the actual exact distance, the ray goes to a
point beyond the actual intersection point. Both of these cases may lead to an increase in the
number of rays in the simulation of light-object interaction. Due to the recursive nature of the
algorithm, larger numbers of rays cause an increase in the total number of operations as
compared to the case when exact calculations are done. The recursive nature can be seen by a
loop formation in the flow chart of Figure 6-1. Introduction of errors in the type 2 calculations
only cause a displacement in the position of the point of intersection, which does not lead to any
increase in the number of arithmetic operations executed by the algorithm. Type 2 operations
account for 69% of the matrix calculations which is around 50% of the total number of
multiplications. Hence, type 2 multiplications which account for 50% of the total single precision
floating point multiplications in the implemented Ray Tracing algorithm were made probabilistic
according to the low power techniques explained in Section 4.3.
The share of various operations shown in Figure 6-1 is calculated by simulating the ray
tracing algorithm for different graphics models such as Stanford Bunny, Stanford Dragon and
Stanford Armadillo [26], and taking the average value for each operation. These models are
courtesy of the Stanford Computer Graphics Laboratory.
Now we explain how the probability of error generated from the C simulator is injected in
to the multiplications of the ray tracing algorithm. First, the correct multiplication result is
calculated. This result is then converted into its 32-bit binary representation. Out of the 32 bits,
the 23 mantissa bits are extracted and errors are introduced in the same manner as was done in
Section 5.1.2 in the C simulator using the inbuilt random number generator. Errors are
introduced only in the mantissa bits of the number while the exponent and sign bit calculations
are error free. This erroneous 23-bit mantissa along with the 8-bit exponent and the sign bit of
46
the correct result is converted into a floating point number. This number replaces the correct
result in the ray tracing algorithm executed in C.
47
Chapter 7
7 Experimental Simulations and Results
As mentioned earlier, to achieve a low power floating point multiplier design, voltage
scaling and truncation have been considered in the mantissa calculation of the floating point
multiplier. Except for the mantissa multiplier, no other logic block is made probabilistic. Several
experiments have been carried out in the mantissa multiplier to evaluate the effect of these
techniques on the power savings as well as on the errors that might creep in because of these
techniques. As explained, since the bulk of the power of the floating point multiplier is
consumed by the mantissa multiplier, the focus is to reduce power consumed in this logic block.
This section describes the experiments connected with voltage scaling and truncation in the
mantissa multiplication.
7.1 Low Power Design for Floating Point Multiplier
The circuit diagram of the simulated mantissa multiplier is shown in Figure 4-2. The
simulation of the mantissa multiplier has been carried out in two stages. In the first stage, one bit
full adder is simulated in HSPICE for obtaining the error rate and the power consumed for all
values of supply voltages. The full adder is simulated for all the possible input combinations,
repeatedly, in random order using HSPICE. This process is termed as the energy and error
characterization of the full adder using HSPICE. The details of these characterizations are
provided in Section 5.1.1 and Section 5.2.1. The output of the simulated adder was then
compared with the correct output value according to the input vector to calculate the error rate of
the full adder. These simulations are done for all the supply voltage values and a look-up table
containing error rate corresponding to the supply voltage is formed. The average power
consumed by a full adder for each supply voltage is also calculated from HSPICE as explained.
This is how each full adder is characterized in terms of the operating voltage, power
consumption and the error rate using HSPICE.
48
The second stage of the simulation uses the error and energy values generated from the
HSPICE simulation of the 1-bit full adder to generate the error rate and energy consumed when
the full adders are interconnected to form the mantissa multiplier. This is carried out with the
help of a simulator developed in C. The C simulator is explained in detail in Chapter 5. In order
to reduce the time of simulation, which is very high if carried out in HSPICE simulator, we have
developed a C simulator to evaluate the performance of the low power techniques on the
mantissa multiplier. Please note that the simulator is developed exclusively for simulating the
multiplier circuit with features to calculate the error rate and power consumed by the multiplier
given the full adder characterization and the description of the way in which the full adders are
interconnected. In this section, whenever we refer to the error rate or the energy consumed by the
mantissa multiplier, we are referring to the values generated from the C simulator. We present
the details of the simulations performed for attaining low power in the floating point multiplier in
this section.
7.1.1 Details of Simulation Parameters
7.1.1.1 Choice of Supply Voltages
The experiments presented in this thesis are performed in HSPICE using the Synopsys
90nm technology. The nominal voltage at 90nm technology is 1.2V. We operate the most
significant gates at the nominal voltage of 1.2V and then decrease the supply voltage in steps of
0.1V until 0.8V as we move towards gates of lower significance. Hence the supply voltage is
scaled to the following five voltages, namely, 1.2V, 1.1V, 1.0V, 0.9V and 0.8V, in that order,
applying higher voltage to higher significant calculations. In case of some of the least significant
calculations, the power supply can be put off as they are found to be less significant in the result
calculation.
7.1.1.2 Choice of Noise RMS
As explained in Section 2.2, to model the effect of thermal noise in a future technology
node, Gaussian noise sources are added at the outputs of each gate. Since we implement the low
power techniques in the full adders of the mantissa multiplier, noise sources are added at the sum
output and carry output of each of the full adder in the 24-bit mantissa multiplier. The noise
RMS (Root Mean Square) value is so chosen that there are no errors at the outputs of the gates
operated at the nominal technology voltage of 1.2V even after noise injection. This RMS value
49
was found to be equal to 0.15V. In view of this, it is assumed that operating the gates at 1.2V
does not cause any errors in the full adder. If the supply voltage is lower than 1.2V, there are
errors at the output which increase as the voltage is lowered. This is how we predict a possible
noisy future technology node. A graph showing the error rate values of the full adder at each
supply voltage is shown in Figure 5-2.
7.1.1.3 Choice of Transistor Widths
As mentioned, we use the 90nm technology library provided by Synopsys. The minimum
channel length for transistors is taken as 100nm. The channel width of the minimum size NMOS
is taken as 250nm. The width ratios between the PMOS and NMOS is maintained as 2:1 to
ensure equal rise and fall time. Hence the minimal channel width of the PMOS is taken as
500nm. The simulations in HSPICE are carried out using these parameters.
7.1.2 Mantissa Multiplier Simulation
As explained, the mantissa multiplier performs multiplication of two 24-bit mantissas and
generates a 48-bit output. Since the final floating point multiplication result is also a single
precision floating point number, out of these 48 mantissa bits only the most significant 24 bits
after normalization are used for calculation of the mantissa of the result. As explained in
Section 2.1.3.1.1, there can be a maximum of 1-bit shift in the process of normalization. Hence
the most significant 25 bits out of the 48-bit mantissa product contribute to the value of the
mantissa. The mantissa value calculated using the low power techniques is termed as the
probabilistic value while the correct mantissa value calculated without truncation or error
injection is termed as the deterministic value. To evaluate the performance of the low power
scheme, the amount of error generated in the probabilistic value is calculated. We determine the
value of the probabilistic result formed by the most significant 25 bits of the mantissa product.
We also calculate the value of the most significant 25 bits of the deterministic result. To find the
amount of errors generated, the absolute difference between the probabilistic 25-bit mantissa
value and the deterministic 25-bit mantissa value is calculated. This absolute difference is termed
as error magnitude. This error magnitude is calculated over 100K multiplications using randomly
generated 24-bit mantissa values and the average error magnitude per sample is calculated.
Given a voltage profile, the average error magnitude per sample and the power consumed is
calculated by the C simulator explained in Chapter 6.
50
The first technique that we use to attain low power in the mantissa calculation is truncation
of the lower significant full adder columns of the array multiplier used for mantissa
multiplication. We vary the number of least significant columns that are truncated and calculate
the energy consumed and the error magnitude per sample generated for each truncation value. A
graph showing energy-error relationship is shown in Figure 7-1. As seen from the graph as the
amount of energy consumed by the circuit decreases the error magnitude per sample increases.
The energy consumed is reduced by increasing the number of truncated full adder columns.
Please note that the Error Magnitude shown on the Y-axis is in log scale. As explained earlier in
Section 2.1.3.1, the value of the mantissa multiplication lies between the value of one and four.
The energy-error values along with the amount of truncation are provided in Table 7-1.
The method of BIVOS is also used for generating energy-error values for different voltage
profiles and is plotted in Figure 7-1. Please note that in this method, the voltage profile which
gives the minimum power consumption is the one in which all the full adders of the mantissa
multiplier are operated at the minimum supply voltage, which is 0.8V in this experiment. This
lowest energy, when all the full adders are operated at 0.8V comes out to be around 38%. The
voltage profile used, the error magnitude generated and the energy consumed are shown for the
BIVOS technique in Table 7-2.
The proposed method of truncation and voltage scaling is also used to generate energy
error tradeoffs as shown in Figure 7-1. Compared to the truncation and BIVOS technique, it can
be seen from the graph that the proposed technique of Truncation + BIVOS is able to maintain
the same error rate at a lower energy value. Also, it can be seen that at a fixed energy value the
proposed scheme has a lower error rate as compared to the other schemes. The value of error
magnitude per sample and the energy consumed along with the voltage profile for each scheme
are shown in Table 7-3.
Please note that the 100% energy in the experiments, calculated from the C simulator, is
considered to be 1.35E-10J per multiplication sample. This is the energy consumed by the
mantissa multiplier when all the full adders are operated at the nominal technology voltage of
1.2V and is considered to be the base case. All the energy values in the experiments are with
respect to the energy of the base case. The error rate at the 100% energy case is zero.
51
Figure 7-1: Energy – Error Relationship
Table 7-1: Error Magnitude Vs Energy Consumed for Truncation
Error Magnitude
per Sample
Energy Consumed
(in %)
Truncated Columns from LSB
0 100 0
5.77E-11 93.83 10
3.00E-09 83.58 15
1.34E-07 66.04 20
5.96E-07 56.58 22
1.12E-05 34.73 26
7.99E-05 22.15 29
1.25E+00 0 46
52
Table 7-2: Error Magnitude Vs Energy Consumed for BIVOS
Error
Magnitude
per Sample
Energy
Consumed
(in %)
Voltage Profile
Truncated Columns
0.8 0.9 1.0 1.1 1.2
From To From To From To From To From To
0 100 0 0 0 0 0 0 0 0 0 1 46
2.38E-13 98.85 0 1 2 3 5 6 8 9 11 12 46
5.29E-11 92.02 0 1 9 10 13 14 17 18 20 21 46
3.20E-09 80.11 0 1 19 20 21 22 23 24 25 26 46
1.57E-07 63.57 0 1 24 25 27 28 29 30 31 32 46
5.64E-07 58.18 0 1 26 27 29 30 31 32 33 34 46
1.32E-05 46.81 0 1 32 33 34 35 36 37 38 39 46
9.20E-05 42.16 0 1 36 37 38 39 39 40 40 41 46
4.69E-03 38.27 0 1 46 0 0 0 0 0 0 0 0
Table 7-3: Error Magnitude Vs Energy Consumed for BIVOS + Truncation
Error
Magnitude
per Sample
Energy
Consumed
(in %)
Voltage Profile
Truncated Columns
0.8 0.9 1.0 1.1 1.2
From To From To From To From To From To
0 100 0 0 0 0 0 0 0 0 0 1 46
5.41E-11 90.51 9 10 13 14 16 17 17 18 18 19 46
4.12E-09 76.17 15 16 19 20 20 21 22 23 23 24 46
1.27E-07 54.47 19 20 24 25 26 27 28 29 29 30 46
5.10E-07 45.68 21 22 26 27 28 29 30 31 31 32 46
1.24E-05 26.23 26 27 30 31 31 32 33 34 34 35 46
8.65E-05 15.80 29 30 32 33 34 35 36 37 37 38 46
1.25E+00 0 46 0 0 0 0 0 0 0 0 0 0
53
The amount of energy consumed for approximately the same error magnitude for all the
schemes is shown in Table 7-4. As shown in the table, there is a substantial decrease in the
amount of energy consumed by using a combination of the BIVOS and Truncation schemes.
Table 7-4: Comparison of Low Power Schemes
Energy Consumed
Error Magnitude Truncation BIVOS BIVOS + Truncation
~3E-09 83.6% 80% 76.2%
~ 5E-07 56.6% 58.2% 45.7%
As seen from the Table 7-4, the proposed scheme performs better than BIVOS and
Truncation alone. One of the main reasons that this BIVOS + Truncation technique outperforms
either the Truncation or the BIVOS technique alone for a floating point multiplier is that,
although the output of the 24-bit multiplication is 48 bits, the least significant 24 bits after
normalization contribute merely to rounding and only the most significant 24 bits are stored as
mantissa. Hence, one can afford large errors in the least significant columns which can be
achieved by putting the full adders to Truncation. This is where the BIVOS scheme lags as
BIVOS will still invest some amount of energy in the least significant columns. The full adder
columns just after the columns which are truncated have a large amount of error because no
calculation has been performed prior to that column. So, even if we operate the next few columns
at the lowest available voltage, the new errors generated due to operation at a lower voltage are
much less than the errors propagated from the previous columns which are truncated. This is
where the Truncation scheme lags as Truncation will operate the next columns at the highest
voltage and will have almost the same error rate as the case when the columns are operated at a
lower voltage.
Depending on the amount of error that can be tolerated in an application, different amount
of power savings can be achieved. In the next section, we investigate the amount of savings that
can be attained in the multiplications of the Ray Tracing algorithm using the proposed low power
probabilistic floating point multiplier.
54
7.1.3 Application of the Low Power Techniques on the Ray Tracing Algorithm
As mentioned, to validate of the concept of probabilistic computation, we apply the low
power techniques mentioned in Section 4.3 in the multipliers of the Ray Tracing algorithm. The
multiplications in the Ray Tracing algorithm are made probabilistic according to each of the
mentioned low power techniques, and the performance of the technique is evaluated by the
quality of the image generated by the Ray Tracing algorithm. The error rate and the power
consumed for the low power schemes are calculated from the C Simulator explained in
Chapter 5.
7.1.3.1 Ideal Case and Base Case
For the experiments, we first define two cases called the ideal and the base case, which are
used for comparisons of the image quality generated from the Ray Tracing algorithm and the
power consumed by the low power schemes respectively.
Ideal Case: -The ideal case is taken as the one in which no errors are introduced into the
multiplications of the ray tracing algorithm. In other words, all the multiplications are
deterministic and do not have any errors. Correctly rounded multiplication results are used to
generate the output in the ideal case. The image in the ideal case is generated from multiplication
which does not have any deliberately introduced errors and is called the ideal image. To find out
the actual reduction in the quality of the image generated from the low power schemes, we
compare all the generated images with the ideal image to have a fair comparison. Peak Signal-to-
Noise Ratio (PSNR) is used to represent the quality of the generated image.
Base Case: - The base case is based on the probabilistic design of the floating point
multiplier explained in Section 4.2. Since we do not use rounding in our design, the base case is
considered to be the one in which only rounding errors are introduced in the floating point
multiplication. In this case, all the full adders of the mantissa multiplier are operated at the
nominal technology supply voltage of 1.2V. The energy consumed in this base case (note this is
not the ideal case) is considered to be 100% energy. Energy consumed by each of the low power
schemes is compared with respect to the base case.
55
7.1.3.2 Tolerable Error Rate
As mentioned earlier, a sequence of voltages which defines the supply voltage of each full
adder column is termed as a „voltage profile‟ of a multiplier. Given a voltage profile for the
24-bit mantissa multiplier, the C Simulator is used to generate the error rates of the mantissa of
the multiplication result. Introduction of these error rates in the Ray Tracing algorithm‟s floating
point multiplications leads to a reduction in the quality of the generated image. The idea of
introducing probabilistic computations is to harness energy savings in such a manner that the
quality of the generated output is kept above a certain threshold such that the difference between
the deterministic image and the probabilistic image is minimal. If the naked eye is unable to find
the difference between the ideal image and the image generated using the probabilistic
multiplications, the image “looks good” and we aim at generating such images. The tolerable
limit of error rates is decided by the quality of the generated image. If the output image “looks
good” the error rate is tolerable.
7.1.3.3 Results on the Ray Tracing Algorithm
The low power techniques explained in Section 4.3, are applied to the array multiplier used
for mantissa multiplication and the techniques‟ performance is evaluated in terms of power
consumption and error rate using the C simulator explained in Chapter 5. Each scheme is
evaluated for different voltage profiles consuming different energy values. Each profile generates
an error rate i.e., the probability of error for the mantissa bits which is then introduced in the Ray
Tracing algorithm. The generated image from the Ray Tracing is compared with the ideal image
to calculate the quality of the image generated. The quality of image generated is a measure of
the error rate of the low power scheme. Hence, tradeoffs between the image quality and energy
consumed are generated.
Multiplications were made probabilistic using the Truncation scheme by increasing the
amount of truncation and observing the quality of the output generated from the ray tracing
algorithm. It was found that there is negligible difference in the generated image and the ideal
image until a truncation of 22 full adder columns. We consider the error generated in this case as
the tolerable error rate. This truncation scheme has an error magnitude of around 5E-07 and
consumes around 56% energy as shown in Table 7-1 and Table 7-4. The proposed scheme was
used to generate the same image quality as obtained by the truncation technique. As shown in
56
Table 7-4, the proposed technique is able to generate the same error magnitude with around 45%
energy consumption. The images generated after ray tracing are shown in Figure 7-2. It can be
seen that this much error magnitude is tolerable and the differences are hardly noticeable with
the naked eye. The quality of the image generated with respect to the ideal image is given in
Table 7-5.
(a) Ideal Images
(b) BIVOS + Truncation at 45% Energy
(i) Stanford Bunny (ii) Stanford Dragon (iii) Stanford Armadillo
Figure 7-2: Images with Ray Tracing
57
Table 7-5: Image Quality in dB Vs Energy Consumed
Energy Consumed Image Quality of the Graphics Model with respect to the ideal image
Bunny Dragon Armadillo
100% (Base Case) 52.98dB 48.96dB 48.11dB
45% with
BIVOS + Truncation 44.27dB 41.54dB 39.27dB
The graphics models used in the ray tracing experiment are the Stanford Bunny, Stanford
Dragon and Stanford Armadillo [26]. The results are calculated from colored images of
resolution 200x200. As mentioned, there are no errors in the ideal case and there are only
rounding errors in the base case. Also, the energy consumed is with respect to the base case and
the image quality is with respect to the ideal image. On an average, there is a reduction of about
8dB in the image quality of each model from the base case. If the quality is lowered further, there
are considerable errors in the image generated which are easily visible.
Hence, the results show that the circuit of the floating point multiplier can be operated at
45% of its energy consumption rate and still attain a reasonably good output quality. Thus an
energy savings of 55% can be achieved in a floating point multiplier by application of the
proposed BIVOS + Truncation technique. The proposed scheme is shown to perform better than
the Truncation and BIVOS alone. These energy savings are achieved at the cost of slight
perceptual degradation in the quality of the image generated from the Ray Tracing algorithm. As
explained in Chapter 6, the low power schemes are applied to 50% of the total multiplications of
ray tracing algorithm. Hence, the overall application-level energy savings in the multiplications
is equal to around 27.5%. This is a significant improvement in energy savings of the floating
point multiplier.
58
Chapter 8
8 Error Resilient Probabilistic Floating
Point Multiplier
For the investigations carried out to attain low power in the floating point multiplier, we
chose a noise RMS value such that there are no errors at the nominal technology voltage of 1.2V.
This was calculated by simulation of 100K samples in HSPICE showing no errors for 1.2V. In
the future nodes, when the nominal voltage itself is very low, there exists a possibility of
occurrence of errors even at the nominal supply voltage. While the errors are tolerable in the
mantissa, the error in the exponent is likely to cause serious errors as the exponent is a very
critical calculation in the floating point multiplication. Thus, is this chapter, we investigate
techniques which can be used to reduce errors in the exponent block which may happen to be
very essential in future noisy technologies.
For generation of error rates of the mantissa multiplier in the low power design, we did
HSPICE simulations of a 1-bit full adder and used them in a C simulator to calculate the error
rate of the mantissa multiplier. The mantissa multiplier is only made of full adders and hence it
was rather easy to characterize just one gate (full adder) and use this data to calculate error rate
of the mantissa multiplier. In the scenario presented in this chapter, where errors can occur in any
part of the circuit, characterization of each type of gate and using that to calculate the error rates
of the complete circuit appears impractical. Since the aim of this experiment is to analyze
techniques which can lower the error rate of the exponent block, we use a simpler noise model
and simulate it using Verilog simulation. Thus, this chapter also explains the noise modeling
used to introduce errors in the digital simulation environment of Verilog and explains how the
probabilistic behavior is simulated.
Since the power consumed by the exponent logic is relatively small as compared to
mantissa, even if there is a small increase in the power for the exponent block to ensure reduction
59
in the exponent errors, it is worth incorporating the required modifications. One such technique
is the use of redundant circuits. The output value of redundant circuits is the value that appears in
the majority of the redundant circuits. For example, in case of Triple Modular Redundancy
(TMR) in which three redundant units are used to perform the same calculation, the correct value
is that which appears in at least two of the three redundant outputs. However, this block then
takes more than three times the power that is consumed by the single block due to extra majority
voting circuitry. This may not be a major issue as far as the floating point multiplier is concerned
as the power consumed by the exponent block (around 1%) is very small as compared to the
whole multiplier circuit. The following is the brief description of the circuits and simulations that
are carried out along with the description of the noise modeling.
8.1 Error Resilient Probabilistic Design
8.1.1 Critical Calculations in a Floating Point Multiplier
As explained in Section 2, the value of a floating point number is calculated as value of the
mantissa multiplied by the base value raised to the value of the exponent. As mentioned in
Section 4.1.1, slight calculation errors in the value of the exponent can result in exponential
variations in the value of the floating point number. Amongst the operations performed by the
floating point multiplier, exponent addition is found to be a critical calculation over mantissa
multiplication. For this reason, utmost care should be taken to ensure that the errors in the
exponent calculations are kept to a minimum.
8.1.2 Technique to Attain Error Resilience
Redundancy has long been used as a means to increase reliable computation in circuits
which have occasional errors. In this technique, some of the critical computation blocks are
repeated N number of times and then a majority vote is taken on the outputs of the repeated
blocks to calculate the result. The method of Triple Modular Redundancy (TMR) in which three
redundant units are used to achieve fault tolerant circuits was initially proposed in [25]. A
general term used for circuits with N redundant units is N-Modular Redundancy. Hence,
redundancy is used in exponent calculations of the floating point multiplier to maintain a low
error rate in the critical calculations as compared to the rest of the circuit.
60
8.1.3 Redundant Floating Point Multiplier Design
The circuit diagram of the single precision floating point multiplier is shown in Figure 2-1.
N-Modular Redundancy (NMR), i.e., making the circuit redundant N times, is observed in the
block which calculates the exponent of the result. As explained in Section 2.1.3, the exponent
addition is performed by an 8-bit Adder and an Incrementer. The proposed redundant floating
point multiplier is shown in Figure 8-1. As shown in Figure 8-1, the exponent addition is
independently performed by N similar units. The final value is the majority vote of the N
calculations. We perform the experiments with values of N being equal to three (Triple Modular
Redundancy) and five (Five Modular Redundancy). Depending on the value of N, the majority
voting circuit either performs a three-way majority vote or a five-way majority vote.
Increm-enter
Mux
1
MAJORITY VOTING
Exponent (8) Mantissa (23)Sign (1)
24 bit
Multiplier
Shifter
Rounding
Unit
Mux
Control
1 1
Exponent (8) Mantissa (23)Sign (1)
Exponent (8) Mantissa (23)Sign (1)
Operand 1 Operand 2
RESULT
Xor8 bit
Adder
Increm-enter
Mux
8 bit Adder
Increm-enter
Mux
8 bit Adder
2 N
Figure 8-1: Redundant Floating Point Multiplier
61
8.2 Noise Modeling
The simulation of the floating point circuit with N-Modular Redundancy (NMR) is carried
out using Verilog simulation. For the multiplier circuit with TMR, since Verilog does not handle
continuous signals, the noise sources that are incorporated are taken as digital noise pulses,
namely 0 and 1. To simulate noisy behavior, samples which follow a Gaussian amplitude
distribution [4] are generated using MATLAB. These samples have zero mean. For a given RMS
value of the noise and the supply voltage (Vdd), digital noise samples are obtained from the
Gaussian samples through MATLAB program. This is obtained using the criteria that if the
instantaneous amplitude of the noise is more than Vdd/2, the sample is considered as a 0-to-1
noise sample. If the amplitude is less than –Vdd/2, the sample is considered as a 1-to-0 noise
sample and if it is between Vdd/2 and –Vdd/2 it is considered as a sample which cannot create
any error. This is how noise samples are generated and categorized into three types namely,
0-to-1 noise samples, 1-to-0 noise samples and no error generating noise samples. These
concepts are shown in Figure 8-2.
0 Vdd/2-Vdd/2
0-to-1
Noise Samples
1-to-0
Noise Samples
No Error Region
Number of
Samples
Amplitude of Samples
Figure 8-2: Error Regions in a Gaussian Noise Environment
For the purpose of expressing the type of noise sample that is created in the digital
simulation, the noise signal is expressed in two bits since there are three types of noise samples.
62
The bit combination „11‟ corresponds to a 0-to-1 noise sample where as the bit combination „00‟
is used to represent a 1-to-0 noise sample. „10‟ stands for a no error sample. The noise samples
are generated at a rate equal to four times the rate of the input operands. Noise is input after
every 10ns while the operands are changed after every 40ns.
The noise samples are used to decide whether or not an error occurs at the gate‟s output
because of noise. If the last noise sample, before the output is sampled, is a 0-to-1 noise sample
the output signal is made logic 1 irrespective of the value of the output. This is because a 0-to-1
noise sample when superimposed on any logic signal (0/1), possesses sufficient amplitude to
convert the logic value to a logic 1. Similarly, if the last noise sample, before the output is
sampled, is a 1-to-0 noise sample, the output signal is made 0 as the noise sample when
superimposed on any logic signal (0/1), possesses sufficient amplitude to convert the logic value
to a logic 0. This change in the logic value may result in logic 0 becoming logic 1 and vice versa
resulting in generation of errors at the gates‟ outputs. This is how erroneous behavior is
simulated.
Whether a noise sample will cause an error at a gate‟s output or not also depends on the
width of the noise sample. Samples which have pulse width less than the minimum width
required to affect the output will appear as glitches at the output and these glitches will not be
seen by the next gate. Hence these samples are said to be filtered by the next gates and do not
appear at the outputs of subsequent gates. On the other hand, samples with width greater than the
minimum required width will appear at the gate‟s output and will also be seen by the next gates
and will appear at their outputs as well. Such samples have the potential to affect all the
subsequent gates. Please note that all the noise samples created for the experiment have the
minimum pulse width required to create an error at the output of the gate, i.e., an error sample at
a particular gate has the sufficient pulse width to be seen at the next gate and the gate after that.
So, the categorization of the samples is done on the basis of amplitude as all samples posses the
minimum required pulse width.
63
8.2.1 Noise Modeling of Gates
Since there are numerous ways in which the logic blocks of the floating point multiplier
can be designed, to have a simple and widely applicable method of noise modeling which can be
applied throughout the circuit, each logic block of a floating point multiplier is constructed from
gates like NAND, NOR, INVERTER, EXOR, EXNOR and MUX. These gates are considered
fundamental gates. For example, the 8-bit Adder used in exponent addition is realized as a
Ripple Carry Adder made of eight full adder blocks. Each full adder is then formed from
fundamental gates as shown in Figure 8-3. Although several existing full adder designs have
fewer transistors than the design used here, we stick with this full adder design for simplicity.
Similarly, all the other logic blocks of the floating point multiplier are formed from the
mentioned fundamental gates.
A
B
Cin
Cout
Sum
Figure 8-3: Gate Level Diagram of a Full Adder
To model the effect of erroneous substrate, noise is added at the output of each of these
fundamental gates as was done in [4] and in the mentioned low power design. Noise modeling
for a full adder is shown in Figure 8-4. Hence, each gate first calculates the correct output and
then noise is superimposed on that output to generate the probabilistic output. This probabilistic
output is then passed to the following gates. When the superimposed noise flips the correct
output, an error occurs at that gate‟s output and is propagated in the circuit.
64
A
B
Cin
Cout
Sumnoise
noise
noise
noise
noise
Figure 8-4: Noise Modeling of a Full Adder
8.2.2 Noise Modeling of the Majority Voting Circuit
Since the majority voting circuit is in the same substrate as the other logic blocks of a
multiplier, the gates of the majority voting circuit are equally likely to be erroneous. Hence,
errors are also added at the output of each fundamental gate of the majority voting circuit in the
same manner as is done for the multiplier circuit. An erroneous majority voting circuit for N
equal to three (Triple Modular Redundancy) is shown in Figure 8-5, and N equal to five (Five
Modular Redundancy) is shown in Figure 8-6. P, Q, R, S and T are the outputs of the redundant
circuits, and Z is the calculated majority vote.
The majority voting circuit for N equal to three, shown in Figure 8-5, adds noise at two
levels, one after the first level of NAND gates directly after the inputs, and another after the
NAND gate just before output. As the redundancy increases to five, the number of gates from the
inputs to the majority vote increases from two to three, and noise is added at three levels, as
shown in Figure 8-6. Thus the majority voting circuit of Five Modular Redundancy (FMR) is
likely to add more errors in the voting as compared to the voting circuit of Triple Modular
Redundancy (TMR). Hence, the complexity and the number of gates in the majority voting
circuit increases non-linearly with increase in the number of redundant units. The higher is the
number of gates from input to output, the greater is the amount of noise added in the circuit.
Thus, increase of redundant units might not necessarily mean more reliability as the majority
voting circuit itself may in fact become more erroneous as N increases.
65
Z
(Majority Vote)R
PQ noise
noise
noise
noise
Figure 8-5: Noisy 3-way Majority Voting Circuit
R
PQ
noise
noise
noise
noiseS
T
Z
(Majority Vote)
noise
noise
noise
noise
noise
noise
noise
noise
noise
noise
Figure 8-6: Noisy 5-way Majority Voting Circuit
66
8.3 Methods of Implementing Redundancy in Exponent Addition
It may be noted that there are two ways in which redundancy can be realized in an 8-bit
adder used in exponent addition. This section explains the two ways of realizing redundancy and
provides the comparisons of the two methods. As explained, the exponent addition is performed
by an 8-bit Adder and an Incrementer. The circuit diagram for an 8-bit Adder realized as a
Ripple Carry Adder (RCA) is shown in Figure 8-7. We investigate the two methods by which a
Triple Modular Redundancy can be observed in an 8-bit Adder in the following sections.
1-bit
FA
1-bit
FA
1-bit
FA
1-bit
FA
A1 B1
Cin
S1
A2 B2
S2
A8 B8
S8
Cout
A7 B7
S7
Figure 8-7: An 8-bit Ripple Carry Adder (RCA)
8.3.1 Intra Adder Redundancy
In the first redundancy method, for each bit position, we use three full adders fed with the
same input operands. This is shown in Figure 8-8. The majority votes of the three redundant sum
outputs and the three redundant carry outputs are computed to calculate the sum and carry bits
for each significant position. The majority voted sum directly becomes one of the bits of the 8-bit
Adder result whereas the majority voted carry output is then used as carry-in for the next
significant addition as shown in Figure 8-8. We refer to this way of applying redundancy as Intra
Adder redundancy.
8.3.2 Inter Adder Redundancy
The second way of implementing redundancy is to take three 8-bit Adders and perform the
addition with the same 8-bit input operands separately and then do a bit wise majority voting on
the results of the three 8-bit Adders. We refer to this method as Inter Adder redundancy. The
method is shown in Figure 8-9.
67
1-bit
FA
A1 B1
Cin
S1
1-bit
FA
A1 B1
1-bit
FA
A1 B1
M
A
J
O
R
I
T
Y
V
O
T
E
C
A
R
R
Y
Majority Vote
Sum
1-bit
FA
A2 B2
S2
1-bit
FA
A2 B2
1-bit
FA
M
A
J
O
R
I
T
Y
V
O
T
E
C
A
R
R
Y
Majority Vote
Sum
A2 B2
1-bit
FA
A8 B8
S8
1-bit
FA
1-bit
FA
M
A
J
O
R
I
T
Y
V
O
T
E
C
A
R
R
Y
Majority Vote
Sum
A8 B8
A8 B8
Cout
Figure 8-8: Intra Adder Redundancy
1-bit
FA
A1 B1
Cin
S1
1-bit
FA
A1 B1
1-bit
FA
A1 B1
Majority Vote
Sum
1-bit
FA
A2 B2
S2
1-bit
FA
A2 B2
1-bit
FA
Majority Vote
Sum
A2 B2
1-bit
FA
A8 B8
S8
1-bit
FA
1-bit
FA
M
A
J
O
R
I
T
Y
V
O
T
E
C
A
R
R
Y
Majority Vote
Sum
A8 B8
A8 B8
Cout
Figure 8-9: Inter Adder Redundancy
68
In theory, there are situations where Intra Adder redundancy can outperform Inter Adder
and vice versa. For example, if a single error occurs in carry bit j of one adder with another
single error occurring in the carry bit j+1 of a different adder, then, if the errors propagate along
the carry chain, from carry bit j+1 onwards the approach of the Inter Adder redundancy would
show errors (since Inter Adder majority voting only occurs on the sum output bits), whereas Intra
Adder would mask out the aforementioned case (since there is majority voting at each carry
output). On the other hand, if there is an error in the output of the majority voting logic itself for
carry bit j in Intra Adder redundancy – since we assume that all gates have susceptibility to
noise, so also does the majority voting logic – then such an error would not be corrected and
would propagate to bit j+1; in this case, since Inter Adder redundancy has no majority voting in
the middle of the carry bits of the Ripple Carry Adder (RCA), no errors in such majority voting
logic would occur in the Inter Adder case. In short, one can come up with a number of scenarios
where Intra Adder outperforms Inter Adder and vice versa. We address this question empirically
through simulation of a large number of test cases.
The simulation results between Inter Adder redundancy and Intra Adder redundancy show
that Inter Adder redundancy is much better than Intra Adder redundancy for the multiplication
dataset used. Since our experiments show worst results for Intra Adder redundancy, we
implement Inter Adder redundancy in the circuit used for exponent addition in the floating point
multiplier shown in Figure 8-1. These simulation results are presented later in the chapter in
Section 8.5.1. Please note that the incrementer used in the exponent block is realized as a Ripple
Carry Adder consisting of half adders. Thus the above methods are applicable in the incrementer
circuit as well.
8.4 Experimental Method
A Verilog description of the complete floating point multiplier, shown in Figure 8-1, was
simulated in Aldec Active HDL 6.3 [24]. The noise samples are generated from MATLAB and
are categorized as explained in Section 8.2. These noise samples are then scanned in the Verilog
code from the MATLAB generated files. Noise is input every 10ns while the multiplier output is
read every 40ns. A noise sample is scanned at every noise clock for each fundamental gate in the
circuit. The noise sample may be a 1-to-0 noise sample, a 0-to-1 noise sample, or a no error
69
sample as explained in Section 8.2. The logic value at each gate‟s output may change depending
on the scanned noise sample value and the correct logic value according to the gate‟s inputs. We
assume that the circuit is operated at 1.2V as we use a Synopsys 90nm technology model. Hence
all the noise samples from the Gaussian distribution having value greater than 0.6V are
considered 0-to-1 noise samples and all samples having value less than -0.6V are considered
1-to-0 noise samples. The noise RMS is varied from 0.16V to 0.2V. Three multiplier designs are
simulated, namely, the typical design without redundancy, design with redundancy equal to three
(TMR) and the design with redundancy equal to five (FMR). The redundant designs are
simulated using inter adder redundancy.
Actual floating point multiplication data is taken from the ray tracing application as input
samples for this experiment. These floating point numbers are converted into their binary
representation and are given as input to the Verilog description. The probabilistic simulation of
the circuit is done and the erroneous multiplication result of the input operands is calculated. The
erroneous multiplication result is compared with the correct result to calculate the probability of
error for each bit of the multiplication result. The experiment is done for 30K multiplication
samples for the non redundant and the proposed redundant designs, and the probability of error
for each exponent bit is calculated.
8.5 Simulations and Results
8.5.1 Inter Vs Intra Adder Redundancy
First we show the comparison results of Inter and Intra Adder redundancy. 8-bit additions
are performed on the exponents of 30K multiplication samples taken from the ray tracing
algorithm using Inter and Intra Adder redundancy. The noise RMS used for the samples is 0.2V.
The results are shown in Figure 8-10.
It turns out from the simulations that the error rate with Intra Adder redundancy is
significantly higher than Inter Adder redundancy. Similar results were obtained for other values
of noise RMS such as 0.18V and 0.16V. Hence the results show that Inter Adder Redundancy is
better than Intra Adder Redundancy.
70
Figure 8-10: Probability of Error with Inter & Intra Adder Redundancy
8.5.2 Triple-Modular Redundancy (TMR) Vs Five-Modular Redundancy (FMR)
The NMR circuit, shown in Figure 8-1, is simulated for redundancy values equal to three
and five using the noise modeling explained in Section 8.2. The probability of error for each
exponent bit of the typical design without redundancy and designs with Triple Modular
Redundancy (TMR) and Five Modular Redundancy (FMR) is calculated. The experiment is
repeated for different values of noise RMS. As mentioned, the exponent of a single precision
floating point multiplier has eight bits. From the probability values, the magnitude of error
generated in the exponent has been calculated by taking the weighted sum of the probability of
error values depending on the position of the bit as :-
𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝐸𝑟𝑟𝑜𝑟 𝑀𝑎𝑔𝑛𝑖𝑡𝑢𝑑𝑒 = 𝑃 𝑖 ∗ 2𝑖
7
𝑖=0
where, P(i) is the probability of error of the ith
bit from the LSB, considering the position
of LSB as i=0.
71
The average error magnitude for all the three cases has been calculated and is shown in
Table 8-1. As shown in the table, the measurements are done for RMS values of 0.16V, 0.18V
and 0.2V. A plot of the average error magnitude for different values of noise RMS for redundant
designs as compared to the typical design without redundancy is shown in Figure 8-11. Please
note that the Y-axis is in log scale.
Table 8-1: Noise RMS Vs Error Magnitude
Noise RMS Average Error Magnitude
No Redundancy TMR FMR
0.2V 9.513048 2.966792 3.703075
0.18V 2.847348 0.764874 1.282348
0.16V 0.617269 0.155156 0.325762
Figure 8-11: Error Magnitude of Non Redundant and Redundant Designs Vs Noise RMS
72
It may be seen from Figure 8-11 that there is a substantial reduction in the error
magnitude in redundant circuits as compared to the non redundant design. The percentage
reduction in error magnitude with the use of redundant designs with respect to the typical design
without redundancy is shown in Table 8-2. As shown in the table, on an average, the reduction is
the error magnitude with the use of TMR is about 72%. It may be noted that the error reduction
in TMR is higher than the error reduction in FMR.
Table 8-2: Comparison of Percentage Reduction in Error Magnitude with Noise RMS
Noise RMS
Percentage Reduction in Error Magnitude With Respect to the Case With
No Redundancy
TMR FMR
0.2V 69% 61%
0.18V 73% 55%
0.16V 74% 47%
The design with Triple Modular Redundancy is shown to perform better than a Five
Modular Redundancy. As the number of redundant units increase, the complexity and size of the
majority voting circuit also increases. Hence a larger majority voting circuit produces more
errors and, on the contrary, instead of reducing the error rate further can prove as a disadvantage
when the substrates are erroneous. Hence, from our experiments, large voting circuits appear to
reduce the advantage of more redundancy and prove to be less reliable.
A graph of probability of error for each of the three designs for all the bits of the
exponent for noise RMS of 0.2V is shown in Figure 8-12. As seen from the Figure 8-12, the
probability of error with redundant designs is much lower than the probability of error without
redundancy. The probability of error values are given in Table 8-3. An interesting observation
from the graph is that the lower significant bits tend to have a higher probability of error as
compared to the more significant bits in redundant designs. This is due to the fact that the
Incrementer, shown in Figure 2-2, adds 1 to the exponent depending on the value of the most
significant bit of the 24-bit Multiplier during normalization as explained in Section 2.1.3.1.1.
Hence, if an error occurred on the most significant bit of the 24-bit Multiplier, the input to all the
Incrementer units of the redundant design will be incorrect. If all the inputs are erroneous there is
73
no help from the redundant circuit and the error shows up at the lower significant bits of the
exponent. Since the carry chain is usually 2-3 bit positions, the least significant 2-3 bits tend to
have a higher error probability in redundant designs.
Figure 8-12: Probability of Error Comparisons in No Redundancy Vs TMR Vs FMR
Table 8-3: Probability of Error Vs Redundancy at Each Exponent Bit
Redundancy
Probability of Error for each Exponent Bit Position (LSB to MSB)
P(0)
(LSB) P(1) P(2) P(3) P(4) P(5) P(6)
P(7)
(MSB)
FMR 0.0245 0.0169 0.0132 0.0112 0.0112 0.0114 0.0114 0.0174
TMR 0.0211 0.0139 0.0100 0.0092 0.0091 0.0098 0.0113 0.0127
No Redundancy
0.0243 0.0227 0.0228 0.0266 0.0319 0.0371 0.0398 0.0383
74
Since all the logic blocks in the circuit are made from fundamental gates and the
transistor count of each fundamental CMOS gate is known, we calculate the total transistor count
of the floating point multiplier. Using redundancy increases the total number of transistors of the
circuit. The increase in area of the exponent addition circuitry with TMR as compared to the
design without redundancy is 2.3X. The overall increase in the area of the multiplier circuit is
only about 3.84% since the 24-bit mantissa multiplier actually takes up the vast majority of the
area in the floating point multiplier. Percentage increase in the overall area of the circuit by using
redundancy is compared with the average percentage decrease in the error magnitude of
exponent bits in Table 8-4. The average percentage decrease is calculated by taking an average
on the percentage decrease in error magnitude values over all the values of noise RMS shown in
Table 8-2.
Table 8-4: Area of Designs with Redundancy Vs Probability of Error
REDUNDANCY = TMR FMR
Increase in Area for Exponent Addition 2.3X 5.65X
Percentage Increase in Area as Compared to the Overall Multiplier Design 3.84% 9.41%
Average Percentage Decrease in the Error Magnitude of Exponent Bits 72% 55%
The results show that we can achieve an average decrease of around 72% in the error
magnitude of the exponent bits by using Triple Modular redundancy in the exponent addition of
the floating point multiplier. Such reduction in the error rate of a critical computation comes at
the cost of a nominal 3.84% increase in the overall area of the multiplier. It was shown that the
percentage power consumed by exponent calculation is around 0.83% of the total power of a
floating point multiplier in Table 4-1. The power share will roughly increase by 3.5-4X with the
use of TMR. The increase in power can be considered approximately equal to the increase in the
area of the multiplier. Hence, with a nominal 3-4% increase in the overall power consumption,
about 72% reductions in the error magnitude can be achieved with the use of TMR.
We also provide insights on how redundancy can be implemented in the Ripple Carry
Adder used for exponent addition in different ways and show which method is superior. Also, we
75
illustrate that increasing the redundancy from three to five does not decrease the error rate
further. Instead, it proves as a disadvantage to the circuit when the substrate is erroneous.
We also implemented redundancy in the sign calculation of the floating point multiplier.
We observed through experiments that using redundancy in the XOR operation used for sign
calculation increased the error rate of the sign bit. This is because the majority voting circuit
after redundancy is large as compared to the XOR gate and hence adds more errors than the
XOR gate itself. So, redundancy is not useful in the sign bit calculation.
76
Chapter 9
Conclusion
The work presented in this thesis aims at the study of low power techniques like truncation
and voltage scaling. These techniques have been studied in conjunction with a floating point
multiplier. This circuit has been chosen for two reasons. The first one is that there are parts of the
circuit which are more significant than other parts and may enable reduction of power in less
significant blocks of the circuit. The other one is that floating point multiplications are used in
large numbers in image processing and rendering techniques like Ray Tracing, and have
maximum share in the total power consumed in the system.
The experiments have been carried out on 90nm technology node. The investigations have
been carried out using HSPICE, Verilog, MATLAB and a C based program developed for this
purpose. As mentioned earlier, the floating point multiplication consists of three major
operations which are exponent addition, mantissa multiplication and sign calculation. Further
there are operations like Normalization and Rounding of the mantissa product. Out of all these
operations, the mantissa multiplier and the Rounding unit are the major power consuming blocks
in the floating point multiplier. The rounding of the product in a probabilistic scenario is not
important and hence the Rounding block has been removed. Further, the product of the mantissa
in a single precision floating point multiplier is of 48 bits and it is to be rounded off to only more
significant 24 bits. This clearly involves considerable wastage of adders in the mantissa
multiplier block. In view of this, the last few full adder columns have been truncated (removed)
which do not affect the result to a large extent. In the Truncation case shown, 22 full adder
columns in the mantissa multiplier are truncated and it is shown through HSPICE and C
simulation that the energy consumed in the multiplier has come down to 56% with error
magnitude in the range of 5.9E-07. Then with the proposed BIVOS + Truncation scheme, with
21 full adder columns truncated and the supply voltage of the rest of the columns (from the less
significant column) increased in steps of 0.1V for groups of columns varying in number from
one to five, it has been shown that at energy consumption of around 45% the error magnitude
77
was around 5.1E-07. Thus the combination of BIVOS and Truncation has been shown to result
in considerable power reduction of the floating point multiplier with about the same order of
error rates.
The exponent block is a very important block in the floating point multiplier and even a
single error in the exponent is likely to produce considerable change in the error magnitude of
the product. Since this exponent block consists of a few gates and consumes very small
percentage (around 1%) of the total multiplier power, the exponent calculation has been
strengthened by introducing Triple Modular Redundancy (TMR). This makes the multiplier error
resilient and even the remotest error which is very significant is prevented. Two ways of
implementing redundancy in the 8-bit Adder used in exponent addition are explained and are
compared. It has been shown that Inter Adder redundancy outperforms Intra Adder redundancy
in the case of a probabilistic scenario. Comparisons between Triple Modular Redundancy (TMR)
and Five Modular Redundancy (FMR) are conducted in a probabilistic scenario. The results
demonstrate that TMR is found to perform better than an FMR in a noisy scenario as the
complexity and the noise generated in the majority voting circuit increases with increase in the
value of redundancy. It is also shown that with TMR about 72% reduction can be achieved,
compared to the non redundant design, in the error magnitude of the exponent of the
multiplication result with a nominal 3-4% increase in the overall area and power of the
multiplier.
Thus by using power reduction for mantissa multiplier, removing the rounding block and
adding TMR to the exponent block, the floating point multiplier on the whole appears to provide
tolerable error rates with large reduction in the overall power consumption.
The utility of this has been demonstrated by implementing probabilistic multiplication in
Ray Tracing algorithm which involves large number of floating point multiplications. With the
modified low power floating point multiplier it has been possible to generate an image with
almost the same perceptual quality as compared to the image obtained from the power hungry
multipliers.
The proposed multiplier may have to be studied in future with technology involving
smaller feature sizes, to ascertain the validity of the architecture given in this thesis. As there are
78
ample applications like video games, image and video processing etc. which are used for
generating data for human perception, one may explore and find out the application value of the
suggested multiplier design for attaining low power operation in these applications.
79
Appendix A: C Simulator Vs HSPICE
To validate the error rate values generated by the C simulator, a comparison is done
between a 6-bit array multiplier simulated in HSPICE and in the C simulator. The comparison
was done for 50K samples for each of the low power schemes. Simulation of each scheme took
two days on a high end machine. The average inaccuracy in the results generated by the C
simulator is reported in Table I. The voltage profile used for each scheme is shown in Table II.
Note that the total number of full adder columns in a 6-bit multiplier is 10. The percentage
difference between the probability of error calculated from the C simulator and HSPICE was
calculated and was divided by the total number of output bits to arrive at the average inaccuracy
values reported in Table I.
Table I: Average Inaccuracy in C Simulator Results
Low Power Scheme Truncation BIVOS BIVOS +
Truncation
Average Inaccuracy per Output Bit
when Compared with HSPICE
4.13% 7.26% 5.29%
Table II: Voltage Profile for 6-bit Simulations
Scheme Truncated 0.8V 0.9V 1.0V 1.1V 1.2V
Columns
(LSB-MSB)
Truncation 1-3 - - - - 4-10
BIVOS - 1-10 - - - -
BIVOS +
Truncation 1-3 4 5 6 7 8-10
80
To verify the energy values generated from toggle calculations, a 6-bit array multiplier was
simulated in HSPICE and in the C simulator for each of the low power schemes, for the same
voltage profile shown Table II, and the results were compared. The energy consumed was
calculated for 50K samples and the results are reported in Table III.
Table III: Energy Calculations
Low Power
Scheme
Energy/sample (J)
calculated from
Energy/sample calculated
with respect to the
corresponding Truncation
scheme
Inaccuracy
in
C simulator
results HSPICE C simulator HSPICE C simulator
Truncation 1.92E-12 1.80E-12 100% 100% -
BIVOS 9.22E-13 8.45E-13 48.03% 46.93% 2.29%
BIVOS +
Truncation 1.53E-12 1.37E-12 80.03% 76.45% 4.47%
The final aim of the energy calculations is to compare the performance of the low power
techniques, i.e., to know how much more/less energy is consumed by a particular scheme as
compared to the other schemes. Assume that simulation of two designs, say A and B, in HSPICE
states that A consumes X% of the energy consumed by B. If the same designs were simulated
using C simulator and the results show that A consumes X% of the energy consumed by B, then
the comparisons are correct. Hence, instead of matching the actual energy values of A and B
from HSPICE and C simulator, we calculate the energy consumed by A with respect to B from
HSPICE and the energy consumed by A with respect to B from C simulator and compare that
value. For comparisons of the low power schemes, we focus on relative accuracy rather than
absolute accuracy, i.e., we compare all the schemes simulated in HSPICE with respect to one of
the scheme simulated in HSPICE and calculate the percentage of energy consumed by each with
respect to that one scheme. Similarly, we compare all the schemes simulated in C with respect to
81
one of the scheme simulated in C and calculate the percentage of energy consumed by each with
respect to that one scheme. This can be seen as normalization of the values with respect to that
one scheme. The comparisons can be made with respect to any scheme. In Table III, in the third
column, comparisons are done for HSPICE and C with respect to their corresponding Truncation
techniques.
BASE CASE: - The 24-bit mantissa multiplier was simulated for the base case in which all
the full adders are operated at 1.2V in the C simulator. Simulation for 2000 samples of 24-bit
multiplications took almost eight days on a high end machine. These simulations were done in 20
batches of 100 samples each. The average energy consumed per multiplication sample calculated
over 2K samples was found to be 1.373E-10 Joules per sample. This value is very close to the
energy value calculated from the C simulator which is 1.35E-10 Joules per sample.
82
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