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1
Low-Power CMOS Logic CircuitTopic Review
Part I: Overview (Shaw)
Part II: (Vincent)
•Low-Power Design Through Voltage Scaling
•Estimation and Optimization of Switching Activity
Part III: (Shaw)
•Reduction of Switched Capacitance
•Adiabatic logic circuit
2
Low-Power CMOS Logic CircuitTopic Review
Introduction
3
Low-Power CMOS Logic CircuitTopic ReviewMotivations:
Portability
Notebook computer
Portable communication devices
Personal digital assistants (PDAs)
Green Computer
"The computer must be designed to use only non-toxic materials, to be energy efficient, and to have minimal impact on the environment in every stage of its life cycle."
Reliability
4
Low-Power CMOS Logic CircuitTopic ReviewMethods?
Device level: Device characteristics (e.g., threshold voltage), device geometries, and interconnect properties.
Circuit level: proper choice of circuit design styles, reduction of the voltage swing, and clocking strategies.
Architecture level: smart power management of various system blocks, utilization of pipelining and parallelism, and design of bus structure.
Algorithm level: minimize the number of switching events.
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Low-Power CMOS Logic CircuitTopic Review
Overview Types of Power Consumption
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Low-Power CMOS Logic CircuitTopic Review
Three main components (CMOS circuit):
1. Dynamic (switching) power consumption
2. Short-circuit power consumption
3. Leakage power consumption
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Low-Power CMOS Logic CircuitTopic Review1. Switching Power Dissipation:
Charge-up: one-half of the energy drawn from the power supply is dissipated as heat in conducting pMOS transistors.
Charge-down: no energy is drawn from the power supply during the charge-down phase, yet the energy stored in the output capacitance during the charge-up is dissipated as heat in the conducting nMOS transistors.
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Low-Power CMOS Logic CircuitTopic Review
n
i
n
iinputerconnectdrainload CCCC
1 1int
2/
02/
))(()(1 T
T
T
outloadoutDD
outloadoutavg dt
dt
dVCVVdt
dt
dVCV
TP
(Periodic input with ideally zero rise- and fall-times)
CLKDDloadavg fVCP 2
Assumption: output undergoes
DDVto 00 toVDD
transition
Reality?
CLKDDloadTavg fVCP 2
Node transition rate can be slower than the clock rate!
T Node transition factor
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Low-Power CMOS Logic CircuitTopic Review
CLKDD
nodesof
iiiTiavg fVVCP
#
1
iC
iC
Ti
Represents the parasitic capacitance associated with each node in the circuit (including the output node)Represent the corresponding node transition factor associated with that node
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Low-Power CMOS Logic CircuitTopic Review2. Short-Circuit Power Dissipation:
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Low-Power CMOS Logic CircuitTopic Review
Conditions: smaller output load capacitance and larger input transition times
12
Low-Power CMOS Logic CircuitTopic Review
3)2(12
1)( TDD
DD
CLKavg VV
V
fkcircuitshortI
3)2(12
1)( TDDCLKavg VVfkcircuitshortP
Conditions: kkkwithinverterCMOSsymmetric pn
TpTnT VVV ,,
Very small capacitive load
fallrise
Short-circuit power dissipation
Input signal rise and fall times
13
Low-Power CMOS Logic CircuitTopic Review
Conditions: larger output load capacitance and smaller input transition times
14
Low-Power CMOS Logic CircuitTopic Review3. Leakage Power Dissipation:
Reverse diode leakage current & subthreshold current
(Reverse diode leakage current)
15
Low-Power CMOS Logic CircuitTopic Review
)1( kT
qV
sreverse
bias
eJAI
biasV
sJ
Reverse bias voltage across the junction
A
Reverse saturation current density. The typical reverse saturation current density is2/51 mpA
Junction area
16
Low-Power CMOS Logic CircuitTopic Review
(subthreshold current)
)(0)(
DSGSr VBVA
kT
q
kT
q
B
cnD ee
L
nWxqDldsubthreshoI
17
Low-Power CMOS Logic CircuitTopic Review4. Examples of Actual Power
Dissipation:Chip Intel 80386
DEC Alpha 21064
Cell based ASIC
Minimum feature size
1.5 0.75 0.5
Number of gates 36,808 263,666 10,000Clock frequency 16MHz 200MHz 110MHz
Supply voltage 5V 3.3V 3V
Total power dissipation
1.41W 32W 0.8W
Logic gates 32% 14% 9% Clock distribution
9% 32% 30%
Interconnect 28% 14% 15% I/O drivers 26% 37% 43%
CLKf
m m m
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Low-Power CMOS Logic CircuitTopic Review
In addition to the three major sources of power consumption in CMOS digital integrated circuits discussed in this section, some chips may also contain circuits which consume static power. One example is the pseudo-nMOS logic circuits which utilize a pMOS transistor as the pull-up device.
)(2staticleakagecircuitshortDDCLKDDloadTtotal IIIVfVCP
Summary
19
Low-Power CMOS Logic CircuitTopic Review
Method #1: Reduction of Switched CapacitanceSystem-Level Measures:
1. Large number of drivers and receivers sharing the same transmission medium
2. The parasitic capacitance of the long bus line.
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Low-Power CMOS Logic CircuitTopic ReviewCircuit-Level Measures:
XOR logic
CMOS circuitPass-gate logic
The capacitance is a function of the number of transistors that are required to implement a given function
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Low-Power CMOS Logic CircuitTopic ReviewMask-Level Measures:
The parasitic gate and diffusion capacitances of MOS transistors in the circuit typically constitute a significant amount of the total capacitance in a combinational logic circuit. Hence, a simple mask-level measure to reduce power dissipation is keeping the transistors (especially the drain and source regions) at minimum dimensions whenever possible and feasible.
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Low-Power CMOS Logic CircuitTopic Review
Trade-off:
Dynamic performance of the circuit
Power dissipation
minimum dimensions??
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Low-Power CMOS Logic CircuitTopic ReviewMethod #2: Adiabatic Switching
Adiabatic switching is also called energy-recovery “Adiabatic” describe thermodynamic
process that exchanges no heat with the environment
Keep potential drop switching device small Allow the recycling of energy to reduce the
total energy drawn from the power supply
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Low-Power CMOS Logic CircuitTopic Review
DDloadVCQ DDloadply VCE 2
sup
2/2DDloadstore VCE
DDVto 0 Transition of the output:
How much is the stored energy?
0 toVDD Transition of the output:
No charge is drawn from the power supply and the the energy stored in the load capacitance is dissipated in the nMOS network
CMOS Switching
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Low-Power CMOS Logic CircuitTopic ReviewAdiabatic Switching:
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Low-Power CMOS Logic CircuitTopic Review
Less dissipation only if:
–Current is constant and
Least power dissipation <- slowest transition
Energy dissipation is not only depend on the capacitance and swing voltage, but also proportional to the output resistance.
tIC
tV sourceC 1
)(
t
tVCI C
source
)(
TIRdtIRE source
T
sourcediss 2
0
2
)(2 TCVT
RCE Cdiss
RCT 2
27
Low-Power CMOS Logic CircuitTopic Review
Adiabatic amplifier circuit which transfers the complementary input signals to its complementary outputs through CMOS transmission gates
An example of Adiabatic Switching:
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Low-Power CMOS Logic CircuitTopic Review
The general circuit topology of a conventional CMOS logic gate
The topology of an adiabatic logic gate implementing the same function
Adiabatic Logic Gates:
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Low-Power CMOS Logic CircuitTopic Review
Circuit diagram of an adiabatic CMOS
30
Low-Power CMOS Logic CircuitTopic ReviewStepwise Charging Circuits:
A CMOS inverter circuit with a stepwise-increasing supply voltage
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Low-Power CMOS Logic CircuitTopic Review
Equivalent circuit, and the input and output voltage waveforms of the CMOS inverter circuit
32
Low-Power CMOS Logic CircuitTopic ReviewAnalysis:
R
VV
dt
dVCi out
iAout
c
)1(
Solving this differential equation with the initial condition )()( i
Aiout VtV
RCtddiAout e
n
VVtV /)1()(
2
1 2
20
2 ddcstep
VC
nRdtiE
2
1 2dd
steptotal
VCn
EnE
33
Low-Power CMOS Logic CircuitTopic Review
Stepwise driver circuit for capacitive loads. The load capacitance is successively connected to constant voltage sources Vi through an array of switch devices
34
Low-Power CMOS Logic CircuitTopic Review
Tradeoff!!
Reduction of energy dissipation
Expense of switching time
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Low-Power CMOS Logic CircuitTopic ReviewAdiabatic families:
Partially Adiabatic Logic–2N2P / 2N-2N2P –CAL (Clocked CMOS Adiabatic Logic)–TSEL (True Single Phase Adiabatic)–SCAL (Source-coupled Adiabatic Logic)
Fully Adiabatic Logic–PAL (Pass-transistor Adiabatic Logic)–Split-level Charge Recovery Logic (SCRL)
36
Low-Power CMOS Logic CircuitTopic Review
o oPC
out
in /in
/out
2N2P Inverter vs CMOS Inverter
oout
in
Vdd
2N2P Inverter
CMOS Inverter
CLKDDloadavg fVCP 2
Periodic ramp-like clocked power supply
Q=CV I=Q/T;
IRQRTIEd ech 2arg
T
37
Low-Power CMOS Logic CircuitTopic Review
38
Low-Power CMOS Logic CircuitTopic Review
39
Low-Power CMOS Logic CircuitTopic Review
40
Low-Power CMOS Logic CircuitTopic Review2N-2N2P Inverter
The primary advantage of 2N-2N2P over 2N2P is that the addition of the cross-coupled Nfets results in non-floating data valid over 100% of the HOLD phase.
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Low-Power CMOS Logic CircuitTopic Review
Analysis:
Reset Phase:
•The high output will ride down only to Vt,p, rather than GND.
Wait Phase:
•Floating at 0 and Vt,p
Evaluation Phase:
•If State has not changed
•If changed(nonadiabatic power consumption is )
2, ptCV
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Low-Power CMOS Logic CircuitTopic Review
Cascades require four-phase clocks Non-adiabatic occurs at brief interval in the
beginning of the evaluation phase Non-adiabatic dissipation proportional to Both inverting and non-inverting output
available
Characteristics of 2N2P / 2N-2N2P
2tpCV
43
Low-Power CMOS Logic CircuitTopic Review
o o
PCK
F1
CX
F0F0
F1
CX
CAL InverterCascades require single-phase clock and two auxiliary square-wave clocks
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Low-Power CMOS Logic CircuitTopic Review
45
Low-Power CMOS Logic CircuitTopic ReviewSimulated switching energy-vs-frequency curves
46
Low-Power CMOS Logic CircuitTopic Review