LOW-POWER DIGITAL VLSI DESIGN

CIRCUITS AND SYSTEMS

LOW-POWER DIGITAL VLSI DESIGN

CIRCUITS AND SYSTEMS

by

Abdellatif Bellaouar University of Waterloo

and

Mohamed I. Elmasry University of Waterloo

1IiI...

" SPRINGER SCIENCE+BUSINESS MEDIA, LLC

ISBN 978-1-4613-5999-9 ISBN 978-1-4615-2355-0 (eBook) DOI 10.1007/978-1-4615-2355-0

Consulting Editor: Jonathan Allen, Massachusetts Institute of Technology

Library of Congress Cataloging-in-Publication Data

A c.I.P. Catalogue record for this book is available from the Library of Congress.

Copyright © 1995 Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1995 Softcover reprint ofthe hardcover lst edition 1995

AlI rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Scie:noe+Business Media. LLC.

Printed on acid-free pa per.

CONTENTS

PREFACE ~

1 LOW-POWER VLSI DESIGN: AN OVERVIEW 1 1.1 Why Low-Power? 1.2 Low-Power Applications 1.3 Low-Power Design Methodology

1.3.1 Power Reduction Through Process Technology

1.3.2 Power Reduction Through Circuit/Logic design

1

3 4

4

6 1.3.3 Power Reduction Through Architectural Design 7 1.3.4 Power Reduction Through Algorithm Selection 7

1.3.5 Power Reduction in System Integration 7

1.4 This Book 7 1.4.1 Low-Voltage Process Technology 8

1.4.2 Low-Voltage Device Modeling 8

1.4.3 Low-Voltage Low-Power VLSI CMOS Circuit Design 9 1.4.4 Low-Voltage VLSI BiCMOS Circuit Design 9 1.4.5 Low-Power CMOS Random Access Memory Circuits 10

1.4.6 VLSI CMOS SubSystem Design 10 1.4.7 Low-Power VLSI Design Methodology 10

REFERENCES 11

2 LOW-VOLTAGE PROCESS TECHNOLOGY 13

2.1 CMOS Process Technology 2.1.1 N-well CMOS Process 2.1.2 Twin-Tub CMOS Process 2.1.3 Low-Voltage CMOS Technology

13 14 16

17

VI LOW-POWER DIGITAL VLSI DESIGN

2.2 Bipolar Process Technology 21 2.3 Isolation in CMOS and Bipolar Technologies 27

2.3.1 CMOS Device Isolation Techniques 27 2.3.2 Bipolar Device Isolation Techniques 31

2.4 CMOS and Bipolar Processes Convergence 34 2.5 BiCMOS Technology 36

2.5.1 Example 1: Low-Cost BiCMOS Process 37 2.5.2 Example 2: Medium-Performance BiCMOS Process 37 2.5.3 Example 3: High-Performance BiCMOS Process 40

2.6 Complementary BiCMOS Technology 43 2.7 BiCMOS Design Rules 44 2.8 Silicon On Insulator 52 2.9 Chapter Summary 56

REFERENCES 57

3 LOW-VOLTAGE DEVICE MODELING 63 3.1 MOSFET Structure and Operation 63 3.2 SPICE Models of the MOS Transistor 69

3.2.1 The Simple MOS DC Model 69 3.2.2 Semi-Empirical Short-Channel Model (LEVEL 3) 73 3.2.3 BSIM Model (LEVEL 4) 77 3.2.4 MOS Capacitances 82

3.3 CMOS Low-Voltage Analytical Model 84 3.3.1 Threshold Voltage Definitions 85 3.3.2 Subthreshold Current 86 3.3.3 Low-Voltage Drain Current 87

3.4 CMOS Power Supply Voltage Scaling 89 3.5 Modeling of the Bipolar Transistor 91

3.5.1 BJT Structure and Operation 91 3.5.2 Ebers-Moll Model 94 3.5.3 Bipolar Models in SPICE 101 3.5.4 Chapter Summary 109

REFERENCES 111

Contents Vll

4 LOW-VOLTAGE LOW-POWER VLSI CMOS CIRCUIT DESIGN 115

4.1 CMOS Inverter: DC Characteristics 116 4.1.1 Transfer Characteristics 117 4.1.2 Effect of /3 121 4.1.3 Noise Margins 121 4.1.4 Minimum Power Supply 123 4.1.5 Example of Noise Margins 123

4.2 CMOS Inverter: Switching Characteristics 124 4.2.1 Analytic Delay Models 125 4.2.2 Delay Characterization with SPICE 127

4.3 Power Dissipation 129 4.3.1 Static Power 130 4.3.2 Dynamic Power of the Output Load 132 4.3.3 Short-Circuit Power Dissipation 135 4.3.4 Other Power Issues 138

4.4 Capacitance Estimation 138 4.4.1 Estimation of Gin 139 4.4.2 Parasitic Capacitances 141 4.4.3 Wiring Capacitance 143 4.4.4 Example 144

4.5 CMOS static Logic Design 146 4.5.1 NAND/NOR Gates 146 4.5.2 Complex CMOS Logic Gates 149 4.5.3 Switching Activity Concept 152 4.5.4 Switching Activity of Static CMOS Gates 152 4.5.5 Glitching Power 160 4.5.6 Basic Physical Design 161 4.5.7 Physical Design Methodologies 165 4.5.8 Conventional CMOS Pass-Transistor Logic 169 4.5.9 CMOS Static Latch 174

4.6 CMOS Logic Styles 176 4.6.1 Pseudo-NMOS CMOS Logic 176 4.6.2 Dynamic CMOS Logic 177 4.6.3 Design Style Comparison 184 4.6.4 Clock Skew in Dynamic Logic 187

Vlll LOW-POWER DIGITAL VLSI DESIGN

4.7 Clocking 188

4.7.1 Storage Elements 190

4.7.2 Single-Phase Clocking 198

4.7.3 Two-Phase Clocking 202

4.8 Pass-Transistor Logic Families 203 4.8.1 CPL 203

4.8.2 DPL 207

4.8.3 Modified CPL 210

4.8.4 Pass-Transistor Logics Comparison 213

4.9 I/O Circuits 214

4.9.1 Input Circuits 214

4.9.2 Schmitt Trigger 218

4.9.3 CMOS Buffer Sizing 221

4.9.4 Clock Drivers and Clock Distribution 224

4.9.5 Output Circuits 227

4.9.6 Ground Bounce 233

4.9.7 Low-Swing Output Circuit 236

4.10 Low-Power Circuit Techniques 239

4.10.1 Low Static Power Techniques 239 4.10.2 Low Dynamic Power Techniques 245

4.11 Adiabatic Computing 247 4.12 Chapter Summary 249

REFERENCES 251

5 LOW-VOLTAGE VLSIBICMOS CIRCUIT DESIGN 257

5.1 Conventional BiCMOS Logic 257 5.1.1 DC Characteristics 259 5.1.2 Transient Switching Characteristics 260 5.1.3 CMOS and BiCMOS Comparison 266

5.1.4 Power Dissipation 266

5.1.5 Full-Swing with Shunting Devices 268

5.1.6 Power Supply Voltage Scaling 270

5.2 BiNMOS Logic Family 272

5.2.1 BiNMOS Gate Design 274

Contents IX

5.2.2 CMOS and BiNMOS Comparison 277

5.2.3 BiNMOS Logic Gates 277

5.2.4 Power Supply Voltage Scaling 278

5.3 Low-Voltage BiCMOS families 280 5.3.1 Merged and Quasi-Complementary BiCMOS Logic 281

5.3.2 Emitter Follower Complementary BiCMOS Circuits 283

5.3.3 Full-Swing Common-Emitter Complementary BiCMOS Circuits 284

5.3.4 Bootstrapped BiCMOS 287

5.3.5 Comparison of BiCMOS Logic Circuits 294

5.3.6 Conclusion 298

5.4 Low-Voltage BiCMOS Applications 299

5.4.1 Microprocessors and Logic Circuits 299 5.4.2 Random Access Memories (RAMs) 300 5.4.3 Digital Signal Processors 303 5.4.4 Gate Arrays 304

5.4.5 Application Specific ICs (ASICs) 306 5.5 Chapter Summary 307

REFERENCES 309

6 LOW-POWER CMOS RANDOM ACCESS MEMORY CIRCUITS 313

6.1 Static RAM (SRAM) 313 6.1.1 Basics of SRAMs 314 6.1.2 Static RAM Cells 318 6.1.3 Read/Write Operation 324 6.1.4 Low-Power Techniques 330 6.1.5 Address Transition Detector (ATD) Circuit 332 6.1.6 Decoders 332 6.1.7 Bit-line Conditioning Circuitry 337 6.1.8 Sense Amplifier 339 6.1.9 Output Latch 347

6.1.10 Hierarchical Word-Line for Low-Power Memory 348

6.1.11 Low-Voltage SRAM Operation and Circuitry 352 6.2 Dynamic RAM 356

x LOW-POWER DIGITAL VLSI DESIGN

6.2.1 Basics of a DRAM 358 6.2.2 DRAM Memory Cell 359 6.2.3 Read/Write Circuitry 363 6.2.4 Low-Power Techniques 364 6.2.5 Decoder 366 6.2.6 Sense Amplifier 367 6.2.7 Bit-Line Capacitance Reduction 367 6.2.8 Multi-Divided Word-Line 367 6.2.9 Half-voltage Generator 371 6.2.10 Back-Bias Generator 373 6.2.11 Boosted Voltage Generator 377 6.2.12 Self-Refresh Technique 377 6.2.13 Low-Voltage DRAM Operation and Circuitry 381

6.3 On-Chip Voltage Down Converter 389 6.3.1 Driver Design Issues 394 6.3.2 Reference Voltage Generator 395

6.4 Chapter Summary 399

REFERENCES 403

7 VLSI CMOS SUBSYSTEM DESIGN 409 7.1 Parallel Adders 409

7.1.1 Ripple Carry Adders 410 7.1.2 Carry Look-Ahead Adders 412 7.1.3 Carry-Select Adder 420 7.1.4 Conditional Sum Adders 423 7.1.5 Adder's Architectures Comparison 425

7.2 Parallel Multipliers 428 7.2.1 Braun Multiplier 429 7.2.2 Baugh-Wooley Multiplier 432 7.2.3 The Modified Booth Multiplier 434 7.2.4 Wallace Tree 442 7.2.5 Multiplier's Comparison 450

7.3 Data Path 450 7.3.1 Arithmetic Logic Unit 451 7.3.2 Absolute Value Calculator 454

Contents Xl

7.3.3 Comparator 455 7.3.4 Shifter 456 7.3.5 Register File 458

7.4 Regular Structures 460 7.4.1 Programmable Logic Array 462 7.4.2 Read Only Memory 467 7.4.3 Content Addressable Memory 470

7.5 Phase Locked Loops 473 7.5.1 Charge-Pumped PLL 474 7.5.2 PLL Circuit Design 476 7.5.3 Low-Power Design 482

7.6 Chapter Summary 484

REFERENCES 485

8 LOW-POWER VLSI DESIGN METHODOLOGY 489

8.1 LP Physical Design 489 8.1.1 Floorplanning 490 8.1.2 Placement and Routing 490

8.2 LP Gate-Level Design 490 8.2.1 Logic Minimization and Technology Mapping 490 8.2.2 Spurious Transitions Reduction 493 8.2.3 Precomputation-Based Power Reduction 496

8.3 LP Architecture-Level Design 498 8.3.1 Parallelism 498 8.3.2 Pipelining 500 8.3.3 Distributed Processing 502 8.3.4 Power Management 505

8.4 Algorithmic-Level Power Reduction 507 8.4.1 Switched Capacitance Reduction 507 8.4.2 Switching Activity Reduction 508

8.5 Power Estimation Techniques 510 8.5.1 Circuit-Level Tools 510 8.5.2 Gate-Level Techniques 512 8.5.3 Architecture-Level Power Estimation 516

XlI LOW-POWER DIGITAL VLSI DESIGN

8.5.4 Behavioral-Level Power Estimation 8.6 Chapter Summary

REFERENCES

INDEX

522 522

523

527

PREFACE

A major creative challenge facing today circuit and system VLSI designers is to design new generation products which consume minimum power. Power saving must be achieved without compromising high performance or minimum area. This has created a new design culture within the design community which we have just seen its preliminary results. The essence of this culture must be accessible to the new generation of designers.

The concern of power dissipation has been part of the design process since the early 1970s, but was less visible. High speed operation, and designing with minimum area, specially in memories, were the main design constraints. The state-of-the-art was driven towards lower delays and smaller chip area. Design tools were all geared towards achieving these two goals. Major milestones on chip integration and clock rates have been reported in technical conferences (e.g., IEEE International Solid-State Circuits Conference) and journals (e.g., IEEE Journal of Solid-State Circuits) from the late fifties till the early nineties. Power dissipation has taken a back seat as a figure of merit. However, as we approach the end of this century, power dissipation has become the main design concern in many applications. Two contributing factors were the area of portable electronics and the area of high-performance chips exceeding power dissipation limits.

This book addresses the design of low-power VLSI digital circuit and system design. The book starts with an introduction to the topic of low-power design. Followed with two supporting chapters on low-power process technology and device modeling. Circuit design for low-power is addressed in two chapters; one on CMOS and the other on BiCMOS. Low-power design applications are covered in subsequent chapters; one on low-power RAMs and the other on low­power subsystem designs. The subsystems include adders, multipliers, data path, regular structures and phase locked loops. The last chapter deals with overall low-power VLSI design methodology. The book addresses many design issues related to low-power; the concept of switching activity, the use of pass­transistor logic, designing using multi-and-Iow threshold voltage CMOS logic, the integration of on-chip voltage down converters, etc.

XlV LOW-POWER DIGITAL VLSI DESIGN

We hope that students and instructors find this book useful in their class-room instruction and also hope that it will be valuable to researchers working in this area.

Abdellatif Bellaouar Mohamed I. Elmasry Waterloo, Ontario Canada

Preface xv

Acknowledgements

Firstly we would like to acknowledge the countless blessings of God Almighty throughout our lives. During the course of writing this book we have devel­oped a greater appreciation for God's created biological processing circuits and systems in terms of low-power and low-energy design. Such systems provides a great aspiration to VLSI designers. The brain, with 30 Watts of active power and processing information at less than 0.01 pJ, is an excellent example of low-power processing/memory design. More research is needed to abstract low-power concepts from the brain and apply them to VLSI circuits and sys­tems.

We would also like to thank our families whose support and endurance helped us to complete writing this book. A. Bellaouar, would like to acknowledge his wife. She was very patient and helpful when he spent over 16 hours/day to complete this manuscript.

We also extend our thanks to Mr. Carl Harris from Kluwer Academic Publishers for encouraging us to work on this new era of VLSI design.

We would like to thank our colleagues at the VLSI Research Group of the De­partment of Electrical and Computer Engineering at the University of Waterloo for their encouragement and support, in particular, Issam S. Abu-Khater. We are grateful to Joan Pache for carefully proof reading the book.

We appreciate the financial support to our research provided in part by NSERC, MICRONET, ITRC, CMC, BNR and NTE.

Finally, we appreciate the effort of those who assisted us in preparing the manuscript and the figures, in particular, Kamel Benaissa, Muhammed Elrabaa, Ahmed R. Fridi and Phil Regier. Also, we thank Dave Bartholomew from Graphic Services at the University of Waterloo for helping in the design of the book front cover.

To

My parents, my wife G hania and my son Mouaadh Bellaouar

Elizabeth, Carmen, Samir, Nadia and Hassan Elmasry