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Low Power Low Noise System-on-Chip Design for ECG Monitoring and Diagnostic Team 5: Yang Xu Yanling Wu Xiaotong Jia

Low Power Low Noise System-on-Chip Design for ECG ...mgh-courses.ece.gatech.edu/ece6414/S17/Projects/Team5_Presentation...Low Power Low Noise System-on-Chip Design for ECG Monitoring

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Low Power Low Noise System-on-Chip Designfor ECG Monitoring and Diagnostic

Team 5:

Yang Xu

Yanling Wu

Xiaotong Jia

Introduction

System Overview

[1] [2]

[3][4]

Outline Reference Circuit

Beta Multiplier Reference

Low Drop-Out Regulator

Instrumentation Amplifier (IA)

Transconductance Stage

Transimpedance Stage

Bandpass filter

Amplifier Stage

Common Source Amplifier

Buffer

SAR ADC

DAC (S&H)

Comparator

Successive Approximation Register

Analog Front End

Reference Circuit (1/2) - Beta Multiplier ReferenceVbiasn 1 V

Vbiasp 2.081 V

Bias current 1.925 uA

Supply voltage sensitivity

250 ppm/V

Temperature sensitivity

692 ppm/

Voltage range 1.2-4.7 V

Start-up delay 36.3 us

Power 22 uw

Sensitivity:250 ppm/v

Reference Circuit (1/2)

Start-up Delay= 36.3 uS

Sensitivity:T/(Iref)*(dIref/dT)=692 ppm/

Reference Circuit (2/2) - Low Drop-Out Regulator

Supply voltage 3.7V

Output voltage 3.3V

Drop-out voltage 0.4V

Minimum load 677.6Ω

Maximum current 4.71mA

Static Power 22.91uW

Reference Circuit (2/2) - Low Drop-Out Regulator

Instrumentation Amplifier

Av=Rs/Rg

AC Analysis

Gain=26.95dBf-3dB=153.36HzPhase margin=89 deg

Transient Response (f=25Hz)Vp-p=2 mV

Vp-p=39.72mV

High Pass Filter

f1=495 mV f2=154 Hz

Gain=26.95dB

Amplifier Stage

Common source amplifier

NMOS in triode region

Frequency Response

Gain = 62.9dB, f1 = 0.495 Hz, f2 = 154 Hz

Total Input Referred Noise:33.794 nV/sqrt(Hz)*sqrt(150-0.5)=0.41u Vrms

33.794 nV/sqrt(Hz)

Output Signal to ADC (After Buffer)

Vp-p=2.6 V

Comparison with Previous Work

Analog to Digital Convertor

2.1 Bottom Switch design

Register

2.4 Successive approximation register

SAR simulation

Comparator Design

Comparator Simulation

ADC Top Level Design

ADC Layout

DAC Output voltage and digital bit output

DNL and INL

DAC 3.43uW

SAR 1.39uW

Comparator 0.9uW

Clock 64.7nW

Total 5.8uW

Power consumption

Summary

Total power consumption is 334.1 uW

Analog Front End Gain is 62.9 dB, total input referred noise is 0.41 uV

SAR ADC ENOB is 7.5 bits

Thank you!

Reference[1] https://www.digikey.com/product-detail/en/illinois-capacitor/RJD3555HPPV30M/1572-1627-ND/6159145

[2] https://datasheets.maximintegrated.com/en/ds/DS1099.pdf

[3] https://www.biopac.com/product/bionomadix-2ch-ecg-amplifier/

[4]https://www.researchgate.net/profile/Tapas_Mondal/publication/220144425_A_Wireless_Wearable_ECG_Se

nsor_for_Long-Term_Applications/links/00b4953b44a3b3afe0000000.pdf

[5] D. S. Kumar et al., "A high CMRR analog front-end IC for wearable physiological monitoring," 2012 Annual

IEEE India Conference (INDICON), Kochi, 2012, pp. 385-388.

[6] Chia-Hao Hsu, Chi-Chun Huang, Kian Siong, Wei-Chih Hsiao and Chua-Chin Wang, "A high performance

current-balancing instrumentation amplifier for ECG monitoring systems," 2009 International SoC Design

Conference (ISOCC), Busan, 2009, pp. 83-86.