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Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514

*Corresp

621-181-273

E-mail a

(P. Fischer

0168-9002/$

doi:10.1016

Low swing differential logic for mixed signal applications

P. Fischera,*, E. Kraftb

a Institut f .ur Technische Informatik, Universit .at Mannheim, GermanybPhysikalisches Institut, Universit .at Bonn, Germany

Abstract

Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise

in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current

between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for

differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore

proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly

simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using

radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power.

r 2003 Elsevier B.V. All rights reserved.

PACS: 07.50.Ek; 07.50.Qx; 84.30.Sk

Keywords: Differential logic; Sensor readout; Mixed signal electronics; Pixel readout chips

1. Introduction

One of the challenges in mixed signal designs isthe reduction of crosstalk between digital andsensitive analog sections. The usual precautions(guard structures, separate supplies, shielding, aphysical separation of blocks) cannot always beapplied or they cause significant complications onthe system level. Pixel readout chips for instancehave several thousand pixel cells which eachcontain a low noise charge sensitive amplifier andfast ð> 10 MHzÞ digital data processing electronicson an area of typically 100 mm� 100 mm: The cellsare arranged in a seamless checkerboard pattern

onding author. Tel.: +49-621-181-2735; fax: +49-

4.

ddress: peter.fischer@ti.uni-mannheim.de

).

- see front matter r 2003 Elsevier B.V. All rights reserve

/j.nima.2003.11.072

on the chip so that analog and digital parts aredensely interwoven.Low swing differential logic operated at con-

stant current can address the crosstalk problem.Fig. 1 shows the general topology of a differentialgate. A bias current I0 is steered with a differentialswitching network into load circuits which trans-form the currents into voltages. The outputvoltage levels must be suited to drive other gatesof the same type. The benefits of this approach aresmall crosstalk due to small swings, cancellation ofinjections due to the differential nature and theabsence of voltage spikes on the supply voltage(even during signal transients!). Several drawbacksof constant current, low swing differential logic areoften stressed. Some of them are briefly discussedhere.The power consumption is constant also during

switching and should therefore be compared to the

d.

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in + in -

out +out -

I0

loadcircuits

Fig. 1. Inverter implemented in differential logic. The bias

current I0 is steered to one of the load circuits where it is

converted to a voltage.

bias

in

vss gnd

1/2 I0

vss=vlow

I0

vhigh

a

b

Fig. 2. (a) Characteristic and (b) implementation of the

proposed load circuit.

1

2

3

I Load

[µA

]

P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514512

dynamic consumption of CMOS circuits. At highspeed, the significantly smaller signal swingsrequire less current per transition. At low speed,the DC consumption of differential logic can bemade very small ðo mAÞ so that it may not pose aproblem. Furthermore, the input capacitance ofdifferential logic is significantly smaller than inCMOS (in particular in radiation tolerant designs)so that less current is needed.Differential gates require more transistors. A

gate with N inputs requires 4 NMOSþ ð1þ 2NÞPMOS devices for the proposed logic, as comparedto N NMOSþ N PMOS in CMOS. Complex logicfunctions can, however, often be implementeddirectly in differential logic due to the availabilityof the inverse signal. As an example, a static latchwith a two input multiplexer requires at least 7þ 7devices in CMOS and 4þ 11 devices in theproposed logic.The layout area of gates is often dominated by

one type of devices (enclosed NMOS devices inradiation tolerant design, PMOS in standardCMOS). A constant number of the ‘large’ devices,independent of the complexity of the gate, can beadvantageous. A PMOS switch network leads tosmall layouts for radiation tolerant design withlarge NMOS devices.

0.0 0.1 0.2 0.3 0.4 0.5

0

ULoad [V]

Fig. 3. Measured characteristic of the proposed load circuit for

various bias conditions and for vss ¼ 0 and 0:2 V:

2. Proposed load circuit

Several load circuits for differential logic havebeen proposed. They require, however, careful

transistor sizing [1] or a regulation [2] and make itdifficult to operate the gates with individual biascurrents in order to save current where possible.An ‘ideal’ load circuit should deliver a constantcurrent of I0=2 so that the current available forcharging up/down a load capacitance is 7I0=2:This leads to equal slew rates for both edges. Thespeed of the circuit can be increased by raising I0as opposed to a purely resistive load where thesignal swing increases with the bias current so thatthe RC time constant remains unchanged. In orderto obtain well defined voltage levels, the ‘ideal’load must sink a very high current as soon as theoutput reaches the high level. The current must fallto zero below the low voltage level.

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Fig. 4. Layout of a 16-bit static ripple counter with a parallel

bus readout. Annular NMOS devices and guard rings have been

used in a 0:25 mm technology. The size is E50 mm� 50 mm:

P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514 513

This step-wise characteristic can be approxi-mated by a parallel connection of an NMOSoperated in saturation as a current source and anelement with a very steep characteristic. A second,diode connected NMOS is used in the proposedload circuit Fig. 2(b). Other implementations usingdiodes could also be used. The turn-on voltage andthe capacitance of the element and the compat-ibility with the technology used must be consid-ered. The expected characteristic shown inFig. 2(a) illustrates that the low differential voltagelevel is well defined by the auxiliary supply voltagevss and the high level is reasonably well fixed bythe turning on of the NMOS diode. Someimportant characteristics of this load are:

* The voltage levels are relatively insensitive tothe bias current. The current can therefore beadapted in every gate to the load capacitanceand the speed requirements.

* The sizing of the two transistors is not critical.In particular, the choice does not depend muchon the bias current.

* The voltage swing can be adjusted very easily bychanging vss. It can therefore be set to theminimum value sufficient to switch the differ-ential tree. For devices operated in weakinversion, some 100 mV are sufficient.

3. Prototype results

A prototype chip has been designed in a 0:25 mmCMOS technology with threshold voltages ofE500 mV for NMOS and PMOS devices. En-closed NMOS devices and guard rings have beenused in the layout for radiation hardness [3,4]. Thetransistor sizes and bias conditions have beenoptimized for a moderate speed of several10 MHz: This allows a supply voltage of only1:2 V and leads to typical bias currents in themicroampere range per gate so that most devicesoperate in weak inversion. A typical value for vssis 0:2 V at a high level of E400 mV so that thevoltage swings are only E200 mV: Fig. 3 showsthe measured load characteristic for vss ¼ 0 V andvss ¼ 0:2 V for various bias settings.Several test circuits have been studied. An

inverter in an inverter chain has a power-delay

product of below 3 mW ns: A shift register withparallel load input runs at E80 MHz if operatedat 3 mW per stage. A simple 8-bit synchronouscounter consumes 35 mW if operated at 8 MHz: A16-bit static ripple counter can be operated withless bias current in the higher bits because they areclocked at lower speed. This power-efficient designleads to a consumption of only E6:5 mW for amaximum clocking frequency of 20 MHz: Thelayout of the full counter including a bus readoutis shown in Fig. 4. It occupies an area ofE50 mm� 50 mm:

4. Summary

A simple load circuit for differential current-steering logic has been proposed. The logic swingis nearly independent of the bias current so thatthe gates can be operated at different powerconsumption depending on their capacitive loadand the speed required. The layout area whenusing radiation tolerant design rules is comparableto CMOS.

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P. Fischer, E. Kraft / Nuclear Instruments and Methods in Physics Research A 518 (2004) 511–514514

References

[1] S.R. Maskai, et al., IEEE J. Solid State Circuits 27 (8)

(1992) 1157.

[2] J.G. Maneatis, et al., IEEE J. Solid State Circuits 28 (12)

(1993) 1273.

[3] D.R. Alexander, et al., IEEE NSREC Short Course, Vol. 1,

1996.

[4] W. Snoeys, et al., Nucl. Instr. and Meth. A 439 (2000)

349.