Low-voltage High-efficiency Fast-transient

Voltage Regulator Module

By

Xunwei Zhou

Dissertation submitted to the Faculty of the

Virginia Polytechnic Institute and State University

in partial fulfillment of the requirements for the degree of

DOCTOR OF PHILOSOPHY

in

Electrical Engineering

Fred C. Lee, Chair

Dusan Borojevic

Dan Chen

Alex Q. Huang

Douglas J. Nelson

Key Words: Low voltage, High efficiency, Fast transient response

July 1999Blacksburg, Virginia

i

Low-Voltage High-Efficiency Fast Transient

Voltage Regulator Modules

By

Xunwei Zhou

Dr. Fred C. Lee, Chairman

Electrical Engineering

(ABSTRACT)

In order to meet demands for faster and more efficient data processing, modern

microprocessors are being designed with lower voltage implementations. The processor

voltage supply in future generation processors will decrease to 1.1 V ~ 1.8V. More

devices will be packed on a single processor chip, and processors will operate at higher

frequencies, beyond 1GHz. Therefore, microprocessors need aggressive power

management. Future generation processors will draw current up to 50 A ~ 100 A [2].

These demands, in turn, will require special power supplies and Voltage Regulator

Modules (VRMs) to provide lower voltages with higher currents and fast transient

capabilities for microprocessors.

This work presents several low-voltage high-current VRM technologies for future

generation data processing, communication, and portable applications. The developed

advanced VRMs with these new technologies have advantages over conventional ones in

power density, efficiency, transient response, reliability, and cost.

ii

The multi-module interleaved quasi-square-wave VRM topology achieves a very

fast transient response and a very high power density. This topology significantly reduces

the filter inductance and capacitance, while having small output and input ripples. The

analysis, design, and experimental verification for this new topology are presented in this

work.

The current sensing and current sharing techniques are developed with simple and

cost-effective implementations. With this technique, traditional current transformers and

sensing resistors are not required, and the inductance value, MOSFET on resistance and

other parasitics have no effect on current sharing results. The design principles are

developed and experimentally verified. A generalized approach and an extension of the

novel current sharing control are presented in this work.

The techniques for improving VRM light load efficiency are developed in this

work. By utilizing the duty cycle signal, VRMs can be implemented with advanced

power management functions to reduce further the power consumption at light loads to

extend the battery-operation time in portable systems or to facilitate the compliance with

various "energy star" ("green" power) requirements in office systems. Four improved

approaches are presented and verified with experimental results.

The high-input-voltage VRM topology, push-pull forward converter, can be used

in high-bus-voltage distributed power systems. This converter has a high efficiency, a

high power density, a fast transient response, and can be easily packaged as a standard

module. The circuit design and experimental evaluation are addressed to demonstrate the

operation principles and advantages of this topology.

iii

Acknowledgments

I would like to express my sincere appreciation to my advisor, Dr. Fred C. Lee,

for his guidance, encouragement, and support throughout the course of this work. Dr.

Lee’s extensive knowledge, vision, and creative thinking have been a source of

inspiration for me.

I gratefully thank Dr. Gary Hua, Dr. Dan Y. Chen, and Dr. Alex Q. Huang for

many enlightening discussions, suggestions, and encouragement. I thank Dr. Dusan

Borojevic and Dr. Douglas J. Nelson for their valuable contributions as members of my

advisory committee.

It has been a great pleasure associating with the excellent faculty, staff, and

students at the Virginia Power Electronics Center. The friendships, discussions, and

challenges have made my stay at VPEC pleasant and enjoyable. Special thanks are due to

my fellow students Dr. Hengchun Mao, Dr. Michael Zhang, Dr. C.Y Lin, Dr. Ning Dai,

Dr Richard Zhang, Dr. Qiong Li, Dr. Wei Chen, Dr. Jingrong Qian, Dr. Kun Xin, Mr.

Jingdong Zhang, Mr. Budong You, Mr. Qun Zhao, Mr. Fengfeng Tao, Mr. David Weng,

Mr. Gang Wang, and Mr. Changrong Liu. I am grateful to the VPEC staff for their

assistance and cooperation, and would like to extend my thanks to Ms. Teresa Shaw, Ms.

Evelyn Martin, Ms. Linda Rush, Ms Teresa Rose, Ms. Ann Craig, Mr. Jeffery Batson,

Mr. Steve Chen, and Mr. Joe Price-O'Brien.

I am especially indebted to my teammates from the VRM group for their help and

friendship. It is wonderful to work with such a talented, hard-working, creative and active

iv

group. I would like to thank Mr. Pitleong Wong, Mr. Peng Xu, Mr. Bo Yang, Mr. Luca

Amoroso, Mr. James Liu, Mr. Nick Sun, Mr. Hopu Wu, Mr. Gary Yao, Mr. Yuhui Chen,

Mrs. Qiaoqiao Wu, Mr. Mauro Donati, Professor Xingzhu Zhang, Professor Wei Chen,

and Robin Chen.

Finally, my heartfelt appreciation goes to my parents for their love.

This work is supported by Intel, Texas Instruments, SGS Thomson, National

Semiconductor, and Delta Electronics.

v

TABLE OF CONTENTS

1 CHAPTER ONE ....................................................................................................... 1

1.1 BACKGROUND...................................................................................................... 1

1.2 TECHNICAL CHALLENGES FORVRM DESIGN........................................................ 4

1.2.1 Transient Response ...................................................................................... 4

1.2.2 Power Devices ............................................................................................. 9

1.2.3 The High-Input-Voltage Voltage Regulator Module ................................... 12

1.3 OBJECTIVES ANDDISSERTATIONOUTLINE .......................................................... 16

1.3.1 Fast-Transient Low-Voltage VRMs ............................................................ 16

1.3.2 Current-Sensing and Current-Sharing Control in VRMs ............................ 17

1.3.3 Improved Light-Load Efficiency for Synchronous Rectifier Applications.... 17

1.3.4 High Input Voltage VRMs .......................................................................... 18

1.3.5 Future VRMs ............................................................................................. 18

2 CHAPTER TWO .................................................................................................... 19

2.1 INTRODUCTION................................................................................................... 19

2.2 LIMITATION OF TODAY ’S TECHNOLOGY............................................................... 21

2.2.1 Transient Limitation .................................................................................. 21

2.2.2 Efficiency Limitation.................................................................................. 33

2.3 CANDIDATE VRM TOPOLOGIES.......................................................................... 36

2.3.1 Fast transient VRM topology ..................................................................... 36

2.3.2 Fast VRM with small ripple ---- interleaved QSW VRM ............................. 39

2.4 EXPERIMENTAL EVALUATIONS AND PRACTICAL ISSUE......................................... 49

vi

2.4.1 Experimental Evaluations .......................................................................... 49

2.4.2 Practical issue ........................................................................................... 55

2.5 SUMMARY .......................................................................................................... 60

3 CHAPTER THREE................................................................................................ 61

3.1 INTRODUCTION................................................................................................... 61

3.2 TRADITIONAL CONTROL USED IN MODULE-PARALLELING APPLICATION ................ 62

3.2.1 Single loop Voltage mode Control.............................................................. 62

3.2.2 Peak current mode control ......................................................................... 64

3.3 A NOVEL CURRENT SENSING AND CURRENT SHARING TECHNIQUE........................ 73

3.3.1 A novel current sensing technique.............................................................. 73

3.3.2 A novel current sharing control technique.................................................. 76

3.3.3 Design and Experimental Results............................................................... 82

3.4 GENERALIZATION AND EXTENSION OF THE NOVEL CURRENT SHARING CONTROL... 90

3.4.1 Generalization of the novel current sharing control technique ................... 90

3.4.2 Extension applications of the novel current sharing control technique ....... 92

3.5 SUMMARY .......................................................................................................... 96

4 CHAPTER FOUR................................................................................................... 97

4.1 INTRODUCTION................................................................................................... 97

4.2 CHALLENGE IN SYNCHRONOUS RECTIFIER BUCKVRM......................................... 99

4.3 DETECT INDUCTOR CURRENT MODE AUTOMATICALLY ....................................... 107

4.4 IMPROVEVRM LIGHT LOAD EFFICIENCY: FIXED FREQUENCY CONTROL.............. 111

4.4.1 Disable synchronous rectifier at light load................................................ 111

4.4.2 With synchronous rectifier at light load.................................................... 115

vii

4.5 IMPROVEVRM LIGHT LOAD EFFICIENCY: HYBRID MODE CONTROL.................... 126

4.5.1 Disable synchronous rectifier at light load................................................ 126

4.5.2 With synchronous rectifier at light load.................................................... 131

4.6 SUMMARY ........................................................................................................ 137

5 CHAPTER FIVE .................................................................................................. 138

5.1 INTRODUCTION................................................................................................. 138

5.2 LIMITATION OF TODAY ’S APPROACH................................................................. 140

5.3 A NOVEL HIGH-INPUT-VOLTAGE VRM ----- PUSH-PULL FORWARDVRM............ 145

5.3.1 Operation of the push-pull forward converter .......................................... 145

5.3.2 ZVS operation.......................................................................................... 152

5.4 COMPARED WITH OTHER TOPOLOGIES............................................................... 157

5.5 EXPERIMENTAL EVALUATION ............................................................................ 163

5.6 A NOVEL NON-ISOLATED HIGH -VOLTAGE VRM TOPOLOGYIM PROVEDCENTER

TAP INDUCTORSTRUCTURE...................................................................................... 178

5.7 SUMMARY ........................................................................................................ 184

6 CHAPTER SIX ..................................................................................................... 185

6.1 HIGH FREQUENCY OPERATION........................................................................... 185

6.2 ADVANCED POWER DEVICE TECHNOLOGIES....................................................... 189

6.3 ADVANCED INTEGRATION PACKAGING TECHNOLOGIES...................................... 192

6.4 ADVANCED HIGH-INPUT-VOLTAGE VRM TOPOLOGIES....................................... 196

6.5 CONCLUSIONS.................................................................................................. 198

7 REFERENCE.............................................ERROR! BOOKMARK NOT DEFINED.

viii

LIST OF ILLUSTRATIONS

Figure 1.1 Today’s VRM ................................................................................................ 3

Figure 1.2 Conventional VRM technology ...................................................................... 5

Figure 1.3 Practical VRM load model ............................................................................ 6

Figure 1.4 Transient response of conventional VRMs for future load .............................. 7

Figure 1.5 Capacitance needed in a conventional VRM................................................... 8

Figure 1.6 Using high frequencies to improve transient response................................... 10

Figure 1.7 VRM efficiency based on today’s devices .................................................... 11

Figure 1.8 The input filter capacitor vs. the input voltage .............................................. 13

Figure 1.9 The trend of computer power system architecture......................................... 14

Figure 1.10 Efficiency comparison: high-input-voltage VRM vs. low-input-voltage VRM

.............................................................................................................................. 15

Figure 2.1 Conventional Buck Converter....................................................................... 22

Figure 2.2 Synchronous Rectifier Buck ......................................................................... 22

Figure 2.3 VRM and processor...................................................................................... 23

Figure 2.4 Practical VRM load model ........................................................................... 24

Figure 2.5 Transient response of conventional VRMs.................................................... 25

Figure 2.6 Processor on cartridge .................................................................................. 28

Figure 2.7 Processor and VRM on Cratridge ................................................................. 29

Figure 2.8 improve VRM transient response by increasing switching frequency............ 30

Figure 2.9 To meet the transient requirement, the VRM needs to operate at 16MHz...... 31

Figure 2.10 VRM efficiency at high frequency.............................................................. 32

Figure 2.11 Conventional VRM efficiency .................................................................... 34

ix

Figure 2.12 Conventional VRM efficiency .................................................................... 34

Figure 2.13 Switching loss and gate drive loss and conduction loss of IRL3803 ............ 35

Figure 2.14 Efficiency of synchronous buck VRM ........................................................ 35

Figure 2.15 QSW topology............................................................................................ 37

Figure 2.16 Transient response of QSW ........................................................................ 38

Figure 2.17 Efficiency of QSW compared with conventional VRM............................... 38

Figure 2.18 Current ripple canceling effect of interleaved QSW.................................... 40

Figure 2.19 Ripple canceling effect ............................................................................... 41

Figure 2.20 4-module interleaved QSW VRM............................................................... 43

Figure 2.21 Transient response of 4-module interleaved QSW (2 times bulk cap needed)

.............................................................................................................................. 44

Figure 2.22 Control strategySaturating duty cycle................................................ 45

Figure 2.23 VRM transient response with duty cycle saturating control (1 time bulk cap

needed).................................................................................................................. 46

Figure 2.24 Capacitance needed in conventional VRM and interleaved VRM ............... 47

Figure 2.25 Efficiency comparison................................................................................ 48

Figure 2.26 4-module interleaved QSW VRM............................................................... 50

Figure 2.27 Integrated magnetic .................................................................................... 51

Figure 2.28 VRM transient response ............................................................................. 52

Figure 2.29 Efficiency of 4-module interleaved QSW VRM.......................................... 53

Figure 2.30 The delays in the VRM system................................................................... 56

Figure 2.31 The control delay........................................................................................ 57

Figure 2.32 The power switch delay ............................................................................. 58

x

Figure 2.33 Effect of delay time .................................................................................... 59

Figure 3.1 Equivalent model.......................................................................................... 65

Figure 3.2 Parallel converters with only single loop voltage mode control..................... 66

Figure 3.3 Current sharing result with only single loop voltage mode control ................ 68

Figure 3.4 Peak current mode control diagram............................................................... 70

Figure 3.5 Control signal: the effect of different inductance value ................................. 71

Figure 3.6 the effect of different inductance value on current sharing ............................ 72

Figure 3.7 A R and C switching network....................................................................... 74

Figure 3.8 A novel current sensing technique ................................................................ 75

Figure 3.9 A novel current sharing technique ................................................................ 78

Figure 3.10 Control Vc2 = Vc1 ..................................................................................... 79

Figure 3.11 A completed current sharing control diagram.............................................. 80

Figure 3.12 Difference in MOSFET on resistance and inductance value........................ 81

Figure 3.13 Test set up and the R3 in each module ........................................................ 84

Figure 3.14 Current sharing control loop design ............................................................ 85

Figure 3.15 Current sharing result: Input current in each module vs. total load current .. 86

Figure 3.16 Voltage Loop Compensator Design ............................................................ 87

Figure 3.17 Measured loop gain................................................................................ 88

Figure 3.18 Transient response...................................................................................... 89

Figure 3.19 Generalized implementation of the current sharing technique ..................... 91

Figure 3.20 Utilize input parasitics ................................................................................ 93

Figure 3.21 Applied in paralleled boost converters ........................................................ 94

Figure 3.22 Applied in paralleled isolated converters .................................................... 95

xi

Figure 4.1 Synchronous Rectifier Buck VRM ............................................................... 98

Figure 4.2 Light load inductor current of a synchronous rectifier buck VRM............... 100

Figure 4.3 Efficiency of 4-module interleave QSW VRM............................................ 101

Figure 4.4 Approach A: fixed frequency control.......................................................... 103

Figure 4.5 Approach B: hybrid mode control............................................................... 104

Figure 4.6 VRM Efficiencies under Different Control ................................................. 106

Figure 4.7 Equivalent model........................................................................................ 108

Figure 4.8 Automatically detecting inductor current .................................................... 110

Figure 4.9 Fixed frequency: disable synchronous rectifier at light load........................ 112

Figure 4.10 Tested VRM power stage ......................................................................... 113

Figure 4.11 Efficiency test results (including gate driver loss) ..................................... 114

Figure 4.12 Fixed frequency: with synchronous rectifier at light load.......................... 116

Figure 4.13 The current emulating network................................................................. 118

Figure 4.14 Control function block for fixed frequency control ................................... 121

Figure 4.15 Key waveforms at heavy load................................................................... 122

Figure 4.16 Key waveforms at light load..................................................................... 123

Figure 4.17 Testing power stage.................................................................................. 124

Figure 4.18 Efficiency test results (including gate driver loss) ..................................... 125

Figure 4.19 Hybrid mode control: disable synchronous rectifier at light load............... 127

Figure 4.20 Control function block for hybrid mode control: ....................................... 128

Figure 4.21 Efficiency test results (including gate driver loss) ..................................... 129

Figure 4.22 The switching frequency vs. the load........................................................ 130

Figure 4.23 Hybrid mode control: with synchronous rectifier at light load................... 132

xii

Figure 4.24 Control function block for hybrid mode control: ....................................... 133

Figure 4.25 Key waveforms at heavy load................................................................... 134

Figure 4.26 Key waveforms at light load..................................................................... 135

Figure 4.27 Efficiency test results (including gate driver loss) ..................................... 136

Figure 5.1 The trend of computer power system architecture....................................... 139

Figure 5.2 An asymmetrical transient response due to low output voltage ................... 141

Figure 5.3 Input filter design ....................................................................................... 143

Figure 5.4 Input filter capacitor vs. input voltage......................................................... 144

Figure 5.5 A novel nigh-input-voltage VRMPush-pull forward converter .......... 146

Figure 5.6 Key operation waveform ............................................................................ 147

Figure 5.7 Equivalent operating circuit during t1 ~ t2.................................................. 149

Figure 5.8 t2 ~ t3: discharge transformer leakage inductor current............................... 151

Figure 5.9 t3 ~ t4: freewheeling time........................................................................... 153

Figure 5.10 Achieve ZVS by utilizing small output filter inductance ........................... 155

Figure 5.11 Achieve ZVS by utilizing small magnetizing inductance .......................... 156

Figure 5.12 Push-pull converter .................................................................................. 158

Figure 5.13 Half bridge converter................................................................................ 159

Figure 5.14 Active clamp forward converter................................................................ 160

Figure 5.15 Flyback converter..................................................................................... 161

Figure 5.16 Flyback forward converter........................................................................ 164

Figure 5.17 Open loop control to output body plot of forward flyback......................... 165

Figure 5.18 Open loop control to output body plot of push pull forward. ..................... 166

Figure 5.19 Test set up ................................................................................................ 168

xiii

Figure 5.20 Integrated magnetic structure.................................................................... 169

Figure 5.21 Integrated magnetic design ....................................................................... 170

Figure 5.22 Efficiency of push-pull forward (Vin=12V, fs=100kHz)........................... 171

Figure 5.23 Efficiency of push-pull forward (Vin=48V, Vo =1.2V, fs=100kHz).......... 172

Figure 5.24 Vds waveform of primary switch (Vin = 12V, Fs = 100kHz).................... 173

Figure 5.25 Design of the asymmetrical half bridge..................................................... 174

Figure 5.26 Design of the symmetrical half bridge ...................................................... 175

Figure 5.27 Design of push-pull forward converter...................................................... 176

Figure 5.28 Efficiency comparison of push-pull forward, symmetrical half bridge ...... 177

Figure 5.29 Center-tapped inductor buck converetr ..................................................... 179

Figure 5.30 Improved center-tapped buck converter .................................................... 180

Figure 5.31 Improved center-tapped inductor buck converter with a novel lossless

sunbber................................................................................................................ 181

Figure 5.32 Experimental test...................................................................................... 182

Figure 5.33 Efficiency results...................................................................................... 183

Figure 6.1 Transient response of interleaved QSW...................................................... 186

Figure 6.2 Inductance and capacitance needed in interleaved QSW VRM topology..... 187

Figure 6.3 VRM efficiency based on today’s device.................................................... 188

Figure 6.4 Advanced power device technology............................................................ 190

Figure 6.5 Advanced integrated magnetic technology.................................................. 193

Figure 6.6 VRM chip design ....................................................................................... 194

Figure 6.7 Advanced packaging technology ................................................................ 195

Figure 6.8 Candidate high-input-voltage VRM topology ............................................. 197

xiv

LIST OF TABLES

Table 2.1 Specifications for present and future VRMs................................................... 20

Table 2.2 Comparison of 4-module interleaved QSW VRM and conventional VRM ..... 54

Table 6.1 VRM Efficiency Comparison....................................................................... 191

1

1 Chapter One

Introduction

It is the purpose of this work to develop the advanced low-voltage high-current Voltage

Regulator Module technology for future generation data processing, communication, and

portable applications.

1.1 Background

Evolution in microprocessor technology poses new challenges for supplying power to

these devices. The evolution began when the high-performance Pentium processor was created, it

is driven by a non-standard, less-than-5-V power supply, instead of drawing its power from the

5-V plane on the motherboard [1].

In order to meet demands for faster and more efficient data processing, modern

microprocessors are being designed with lower voltage implementations. The processor voltage

supply in future generation processors will decrease to 1.1 V ~ 1.8V. More devices will be

packed on a single processor chip and the processors will operate at higher frequencies, beyond

1GHz. Therefore, microprocessors need aggressive power management. Future generation

processors will draw current up to 50 A ~ 100 A [2]. These demands in turn require special

power supplies, Voltage Regulator Modules (VRMs), to provide lower voltages with higher

current capability for microprocessors.

2

Meanwhile, as the speed of the processors increases, the dynamic loading of the VRMs

significantly increase as well. Future microprocessors are expected to exhibit higher current slew

rates of 5A/ns. These slew rates represent a severe problem for the large load changes that are

encountered when the systems transfer from the sleep mode to the active mode, and vice versa.

In this case, the parasitic impedance of the power supply connection to the load and the ESR and

ESL of capacitors have a dramatic effect on VRM voltage [2]. If this impedance is not low

enough, the supply voltage may fall out of the required range during the transient period.

Moreover, the total voltage tolerance will be much tighter. Currently, the voltage tolerance is 5%

(for a 3.3 V VRM output, the voltage deviation can be± 165mV). In the future, the total voltage

tolerance will be 2% (for a 1.1 V VRM output, the voltage deviation can only be± 33 mV). All

these requirements pose serious design challenges.

Figure 1.1 shows an example of today’s VRMs. Most of today’s VRMs use conventional

buck or synchronous rectifier buck topologies, as shown in Figure 1.2. When considering future

microprocessor applications, the limitations of these topologies becomes very clear. In order to

maintain future voltage regulation requirements during the transient, more output filter and

decoupling capacitors will be needed [3]. However, the space on the VRM and motherboard is

very limited. Increasing capacitors is an impractical approach. In order to meet future

specifications, VRMs with a significantly higher efficiency level, higher power density and faster

transient must be developed. On the other hand, an advanced integrational approach is required

to minimize the effects of connection and component parasitics.

To achieve this target, there are a number of critical technical challenges. For example,

advanced VRM topologies for fast transient responses and low ripple voltages together with

3

intel

Pentium

1000

200

MHz

Processor Speed

Year1995 2000 2005

AB

C

D A — 3.3 V @ 6 A

B — 2.6 ~ 3.3 V @ 12 A

C — 1.2 ~ 1.8 V @ 50 A

D — < 1 V

Figure 1.1 Today’s VRM

4

advanced packaging technologies for improving power density and thermal management are

required for future applications. Also, advanced power devices and control technologies are

needed for high efficiency levels and high-frequency operation. Today’s vertical power device

technology cannot provide acceptable conversion efficiency at multi-megahertz levels due to its

high conduction and switching and gate drive losses. Besides, innovative power system

architectures should be developed to meet the new performance envelope while offering a cost-

effective solution to these challenges.

1.2 Technical Challenges for VRM Design

1.2.1 Transient Response

Figure 1.3 shows the practical VRM load model (processor model). The packaging

capacitor is the parasitic capacitor package. Inside the microprocessor, there are a number of

decoupling capacitors near and around the microprocessors, to reduce noise and maintain voltage

regulation. Bulk capacitors are VRM output capacitors. All these capacitors have parasitic ESR

and ESL. There are interconnection parasitic inductances and resistances between bulk

capacitors and decoupling capacitors and between decoupling capacitors and packaging

capacitors. Future microprocessor load transitions will have a 5A/ns-slew rate. In this case, all

these parasitics have a significant effect on VRM transient voltage. Figure 1.4 shows the

transient response of a synchronous rectifier VRM. It can be determined that for future

microprocessor loads, today’s VRM topologies cannot meet the 2% transient requirement. Due

to the slow dynamic response, large output capacitors are employed. To meet future

5

L

CControlV i n

Q 1 V x

D1

(a) Conventional Buck Converter

L

CControlV i n

Q1V x

Q2

(b) Synchronous Rectifier Buck

Figure 1.2 Conventional VRM technology

6

1.6A/ns13 A

Synchronous Rectifier Buck VRM Pentium Pro Processor Model

Cdec_die

Rdec_die5V

2mΩ2.0µH

Driver

1nH

3.28mF

3mΩ

REF=3.1V

300KHz

electrolytic

inter-connection

1.2mΩ1nH

Ldec

Cdec

Rdec

decouplingcapacitors

ceramic

1.2mΩ1nHLdec_die

RpkgLpkg

RpkgLpkg RdieLdie

RdieLdie

Cdie

Vo Vd

Figure 1.3 Practical VRM load model

7

2% Limit

100 mV V output

V decoupling

Figure 1.4 Transient response of conventional VRMs for future load

8

DecouplingBulk

ConventionalVRM

CPUChip

Processor Cartridge

26X3X+

VO

-

+VD

-

CB=9.84mF CD=520µF

1~3V

1~50A

5A/nS

a) Increased capacitance to meet transient response

2% limit

100mV limit

VO

VD

b) Simulation results

Figure 1.5 Capacitance needed in a conventional VRM

9

requirements, 23 times the decoupling capacitors and three times VRM bulk capacitors are

needed, as shown in Figure 1.5. This makes future VRMs very bulky and expensive.

The transient limitation of today’s VRM topologies comes from their large output filter

inductance. To reduce inductance, higher frequencies are more desired. Figure 1.6 shows the

transient response of the high-frequency VRM. For future requirements, conventional VRMs

will have to operate at 16MHz to achieve a 34nH small inductance. Based on today’s device

technology, most VRMs’ operating frequencies are lower than 300 kHz. Even at this frequency,

the VRM cannot meet the efficiency requirements, as shown in Figure 1.6. As the frequency

increases, VRM efficiency is shown in Figure 1.5. At 10 MHz, VRM will only have 40%

efficiency. This efficiency level makes thermal management and packaging very difficult.

1.2.2 Power Devices

The current power MOSFET technologies are not suitable for future processors with

lower voltages and higher currents because of the figure of merit. This is defined as the product

of the on-resistance multiplied by the gate charge (RON * QG). The figure of merit is so large that

the VRM efficiency will drop significantly in future processors. The commercially available

low-voltage power devices are currently constructed based on the vertical DMOS technology,

and are rated at 30V. Their high on-resistance and large gate and drain charges severely limit the

efficiency of the VRMs. These devices are usually rated at 30 V because of large market

demand for this voltage rating. While scaling down the voltage rating to about 10-15 V will

reduce losses to some extent, the effectiveness of the voltage scaling is fundamentally limited by

large substrate and packaging resistances. Alternatively, scaling down cell size using VLSI

10

2% limit

VRM Output

Figure 1.6 Using high frequencies to improve transient response

(fs=16MHz, L=34nH)

11

η=80%

20 40 60 80 1000.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

20 40 60 80 1000.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Eff

Load(A)

fs = 300 kHz

fs = 1 MHz

fs = 10 MHz

Figure 1.7 VRM efficiency based on today’s devices

(Vin=5V, Vo=2V, Switches: 5 IRL3803 in parallel)

12

technology is limited by the presence of a parasitic JFET in the DMOS structure. Although using

trench technology eliminates the bottleneck created by the JFET effect, its design rule scaling is

expected to be much slower than that of the DMOS technology. In addition to these two

limitations, vertical power MOSFET technology generally faces a fundamental limitation: it

must trade off on-resistance with the gate charge, or trade off conduction loss with switching

loss. In order to reduce the conduction loss, the size of the device has to be increased, which will

increase the gate and drain charges, and hence produce more switching loss. Especially at multi-

megahertz switching frequencies, switching loss becomes the dominant loss in the VRMs.

1.2.3 The High-Input-Voltage Voltage Regulator Module

Today’s VRM is powered up from the voltages already in existence that are used for

supplying various parts of the system; For example, disk drives (12-V or 5-V) and the logic

circuits operate from higher voltages (5-V). Future VRMs will be required to provide lower

voltages and higher currents with tighter voltage regulations. The traditional centralized power

system low-voltage VRM will no longer meet the stringent requirements for voltage regulation,

because of the distributed impedance associated with a long power bus and the parasitic ringing

due to high-frequency operation. On the other hand, with much higher loads in the future, the bus

loss becomes significant. In order to maintain system stability, a huge silverbox output

capacitance is also needed. At the same time, to avoid the interaction between different outputs, a

very large VRM input filter capacitance is needed. Figure 1.8 shows this necessary capacitance.

For future applications, if the VRM input voltage is 5V, its input filter capacitance will be 10mF.

As a result, future computer power systems will be low-efficiency and low power density with

poor regulation and severe noise problems.

13

1

10

100

1000

10000

100000

1000000

0 10 20 30 40 50

Vin (V)

Cin

(uF

)

Figure 1.8 The input filter capacitor vs. the input voltage

14

Front End

Distribution Bus

AC

AC Silver Box

Hybrid Power System ( HPS)

- Personal computers- low end servers

Centralized Power System ( CPS)- Consuming appliance (video, audio)

Distributed Power System ( DPS)- High end servers- Telecom equipment- Mini computer- Mainframe computers

VRM

VRM

VRM

AC Silver Box

VRMVRM

Distribution Bus(5/12V)

Figure 1.9 The trend of computer power system architecture

15

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

0 10 20 30 40 50 60 70 80

Iload (A)

Eff η=80%

48V Input 1.2V Output

Synchronized Buck with Schottky5V Input 1.2V Output

Figure 1.10 Efficiency comparison: high-input-voltage VRM vs. low-input-voltage VRM

16

Figure 1.9 shows the trend of computer power system architecture. In the future, a distributed

power system (DPS) with a high-voltage bus, 12V or 48V, can be the solution for servers’ and

workstations’ power systems. For high-voltage input, transformers can be used to optimize

VRMs design, which results in higher VRM efficiency, as shown in Figure 1.10, and higher

power density.

1.3 Objectives and Dissertation Outline

The primary objectives of this dissertation are to develop advanced topologies and

control technologies for low-voltage and high-current computer power system applications. The

major contributions will be:

a) a proposed fast transient VRM topology for desktop PC computer applications;

b) a proposed current sharing control approach to control parallel module operation;

c) a proposed approach to improveVRM light-load efficiencyfor mobile applications; and

d) a proposed high-input-voltage VRM topology for server and workstation applications.

1.3.1 Fast-Transient Low-Voltage VRMs

In order to meet future transient requirements, a novel fast-transient and high-power-

density VRM topology, interleaved with QSW VRM, is proposed in Chapter 2. The advantages

of this possible VRM topology are evaluated with experimental results, and practical issues are

addressed. Finally, the design for a future VRM is proposed.

17

1.3.2 Current-Sensing and Current-Sharing Control in VRMs

For integration purposes, a novel current-sensing and current-sharing technique for

parallel modules is proposed in Chapter 3. With this technique, current-sharing control can be

easily implemented in parallel modules without traditional current-sensing approaches. The four-

module interleaved QSW VRM is used to evaluate this technique. The current sharing control

design guideline are provided. Finally, a generalized approach and an extension of the novel

current-sharing control are proposed.

1.3.3 Improved Light-Load Efficiency for Synchronous Rectifier Applications

For many low-voltage applications, like mobile and portable battery applications, VRMs

are always expected to be implemented with advanced power management functions to further

reduce the power consumption at light loads, in order to extend the battery-operation time in

portable systems or to facilitate compliance with various "energy star" ("green" power)

requirements in office systems. In Chapter 5, a new technique for improving can improve light

load efficiency by utilizing the duty cycle signal is proposed. Since current sensors are not

required by this technique, a high density and high efficiency can be achieved that makes the

whole circuit suitable for integration. In this chapter, four improved approaches are proposed and

verified with experimental results. The first two are designed for the fixed-frequency-controlled

VRMs. The second two are designed for the hybrid-mode-controlled VRMs, whose switching

frequencies change proportionally to the loads at light load and keep constant at heavy load.

18

1.3.4 High Input Voltage VRMs

For server and workstation applications, a novel high-input-voltage VRM, push-pull

forward converter that can be used in high-bus-voltage distributed power systems, is proposed in

Chapter 5. This converter has a high efficiency level, high power density, and high performance.

As a result, this converter can be easily packaged as a standard module. The experimental

evaluation and circuit design are addressed. This novel topology is also compared with today’s

conventional high-input-voltage VRM topologies.

1.3.5 Future VRMs

In order to develop low-cost, high efficiency, low profile, high-power density, fast

transient response VRM modules for future generation microprocessor loads, higher operating

frequencies are desirable. In Chapter 6, a high-frequency VRM design is proposed. Based on the

interleaved QSW technique, the packaging and integrated magnetic design is presented.

Meanwhile, the vision for future VRM development is addressed.

19

2 Chapter Two

Fast-Transient Low-Voltage VRM

2.1 Introduction

Low-voltage power management issues are becoming increasingly more critical in state-

of-the-art computing systems. The current generation of high-speed CMOS processors (e.g.

Alpha, Pentium, Power PC) operate at above 300MHz with 2.5 to 3.3 V output voltage. Future

processors will be designed with even lower logic voltages down to 1.1~1.5 V, and an increase in

current demand from 13 A to 50~100 A. Meanwhile, the operating frequency will increase above

1 GHz. For future generation processors, the high transient current-slew-rate (several Amperes

per Nanosecond) will result in significant voltage transient. To ensure proper operation, a more

stringent voltage regulation from 5% to 2% regulation is imposed. These demands in turn

require a special power supply, voltage regulator module (VRM), to provide lower voltages with

higher current and fast transient response capability for microprocessors. Table 1 shows the

specifications for present and future VRMs.

With today’s VRM technologies, large output filter capacitors and decoupling capacitors

will be needed to maintain voltage regulation during the transient, which make these

technologies impractical for future applications. This chapter analyzes the limitations of present

VRM technologies. To solve these problems, a candidate VRM topology for the future

microprocessor, interleaved Quasi-Square-Wave (QSW) topology, is proposed. In addition, the

advantages of this candidate VRM topology are evaluated with experimental results.

20

Table 2.1 Specifications for present and future VRMs

Present Future

Output Voltage: 2.1~3.5V 1~3V

Load Current: 0.3~13A 1~50A

Outut Voltage Tolerance: ± 5% ± 2%

Current Slew at decoulp-

ing Capacitors

1A/nS * 5A/ns

*: Current Slew rate at today’s VRM output is 30A/uS

21

2.2 Limitation of today’s technology

2.2.1 Transient Limitation

Most of today’s VRMs use conventional buck or synchronous rectifier buck topology.

Figure 2.1 shows the conventional buck circuit, which is the most cost-effective approach.

Usually, Schottky diodes are used as a rectifier. The top MOSFET transfers energy from the

input and the bottom rectifier conducts the inductor current. The control regulates the output

voltage by modulating the conduction interval of the top MOSFET. Figure 2.2 shows the

synchronous rectifier buck circuit. This topology increases efficiency by replacing the rectifier

with a low Rds(on) MOSFET. The synchronous switch is controlled by the complementary

signal of the top switch’s gate signal. The synchronous rectifier buck always operates in

continuous current mode. In order to reduce output ripple, the conventional VRM’s inductor

design is according to:

fsIo

DVoVinL

××−×≥ )(10

…………………………………………………………. (2.1)

Where D is the duty cycle. Vin is the input voltage, Vo is the output voltage. Io is the full

load current and Fs is switching frequency. Today’s VRMs use large output filter inductance,

2~4µH. Figure 2.3 shows how the VRM is connected to a processor. The VRM is plugged into a

slot. Through the connection and the motherboard, the VRM output power is transferred to the

processor. In this case, the parasitic impedance of the power supply connection to the load and

the ESR and ESL of capacitors have a dramatic effect on VRM voltage. Figure 2.4 shows the

practical VRM load model (processor model). The packaging capacitor is the parasitic capacitor

inside the microprocessor package. There are many decoupling capacitors near and around the

22

L

CControlV i n

Q 1 V x

D1

Figure 2.1 Conventional Buck Converter

L

CControlV i n

Q1V x

Q2

Figure 2.2 Synchronous Rectifier Buck

23

Figure 2.3 VRM and processor

24

1.6A/ns13 A

Synchronous Rectifier Buck VRM Pentium Pro Processor Model

Cdec_die

Rdec_die5V

2mΩ2.0µH

Driver

1nH

3.28mF

3mΩ

REF=3.1V

300KHz

electrolytic

inter-connection

1.2mΩ1nH

Ldec

Cdec

Rdec

decouplingcapacitors

ceramic

1.2mΩ1nHLdec_die

RpkgLpkg

RpkgLpkg RdieLdie

RdieLdie

Cdie

Vo Vd

Figure 2.4 Practical VRM load model

25

Ld

rd

Cd

decouplingcapacitorsVRM

inter-connection

rboardLboard

LB

rB

CB

packaging

die

Controller

GD5V

1st2nd3rd

Vo

a) The processor model can be considered as three resonant loops with different resonant

frequencies

2% Limit

100 mV V output

V decoupling

1st spike

2nd spike

3rd spike

b) Transient response

Figure 2.5 Transient response of conventional VRMs

26

microprocessor to reduce noise and maintain voltage regulation. Bulk capacitors are

VRM output capacitors. All these capacitors have parasitic ESR and ESL. There are

interconnection parasitic inductances and resistances between bulk capacitors and decoupling

capacitors and between decoupling capacitors and packaging capacitors. Future microprocessor

load transitions will have a 5A/ns-slew rate. In this case, all of these parasitics have a significant

effect on VRM transient voltage. Figure 2.5 shows the transient response of a synchronous

rectifier VRM. During the transient, there are three spikes in the voltage drop [3]. The first high

frequency spike is dominated by loop 1, which combines the parasitic of the packaging

capacitors and decoupling capacitors and the interconnection between them. The second spike is

controlled by loop 2, which combines the parasitic of the decoupling capacitors and VRM bulk

capacitors and the interconnection between them. The third spike is decided by loop 3, which

combines the parasitic of the VRM output filter inductor and bulk capacitors. In Figure 2.5, it

can be determined that for future microprocessor loads, today’s VRM topologies cannot meet the

2% transient requirement.

Since the interconnection parasitic has a dramatic effect on VRM transient response.

Industry has made many efforts to reduce the interconnection parasitic impedance. Figure 2.6

shows a processor that is placed on a cartridge. With this approach, the packaging parasitic

impedance can be reduced. However, for future microprocessors, with heavier load currents,

higher load transient slew rate, and tighter voltage tolerance requirements, still more decoupling

capacitors are required to reduce the second spike, and more VRM output bulk capacitors are

required to reduce the third spike. As a result, in order to meet future specifications, 23 times the

decoupling capacitors are needed and 3 times the VRM bulk capacitors are needed [3]. The

VRM will be very big and expensive. The space of the VRM is very limited, and the

27

motherboard’s real estate is very expensive. The need for a large quantity of capacitors makes

the VRMs, which use these topologies, impractical for future microprocessors. Figure 2.7 shows

that the VRM is packaged with a processor together. But this approach cannot yet improve

VRMs’ transient response inherently.

Nobody realized that the transient limitation of today’s VRM topologies comes from their

large output filter inductance. Due to the large inductance, the energy transfer speed is limited

and the capacitors have to store or discharge all the energy from the load during the transient. In

order to reduce the filter inductance, according to conventional design guidelines, VRMs have to

increase switching frequency. Figure 2.8 shows the VRM transient response at 1MHz switching

frequency. Compared with 300kHz switching frequency, the VRM’s inductance is reduced and

transient response is improved. However, to meet the transient requirement, the VRM’s

operating frequency has to be increased to 16 MHz, as shown in Figure 2.9. Based on today’s

device technology, the VRM’s efficiency is terribly low, which is shown in Figure 2.10. As a

result, novel fast transient VRM topologies have to be developed for future applications.

28

8A/ns30 A

Synchronous Rectifier Buck VRM Future Processor Model

Cdec_die

Rdec_die5V

2mΩ2.0µH

Driver

1nH

3.28mF

3mΩ

REF=1.5V

300KHz

electrolytic

inter-connection

1.2mΩ1nH

Ldec

Cdec

Rdec

decouplingcapacitors

ceramic

1.2mΩ1nHLdec_die

RpkgLpkg

RpkgLpkg RdieLdie

RdieLdie

Cdie

Vo

(a) Reduce packaging parasitic

Processor in Socket Processor on Cartridge

VRM moduleCartridge

Processor

Mother board

(b) Processor on cartridge

Figure 2.6 Processor on cartridge

29

8A/ns30 A

Synchronous Rectifier Buck VRM Future Processor Model

Cdec_die

Rdec_die5V

2mΩ2.0µH

Driver

1nH

3.28mF

3mΩ

REF=1.5V

300KHz

electrolytic

inter-connection

1.2mΩ1nH

Ldec

Cdec

Rdec

decouplingcapacitors

ceramic

1.2mΩ1nHLdec_die

RpkgLpkg

RpkgLpkg RdieLdie

RdieLdie

Cdie

Vo

(a) Reduce interconnection parasitic

Processor in Socket Processor and VRM on Cartridge

VRM module

Cartridge

Processor

Mother board

(b) Processor and VRM on Cratridge

Figure 2.7 Processor and VRM on Cratridge

30

8A/ns30 A

Synchronous Rectifier Buck VRM Future Processor Model

Cdec_die

Rdec_die5V

2mΩ2.0µH

Driver

1nH

3.28mF

3mΩ

REF=1.5V

300KHz

electrolytic

inter-connection

1.2mΩ1nH

Ldec

Cdec

Rdec

decouplingcapacitors

ceramic

1.2mΩ1nHLdec_die

RpkgLpkg

RpkgLpkg RdieLdie

RdieLdie

Cdie

Vo

(a) Reduce VRM filter inductance by high switching frequency

2% Limit Fs=1MHzL=670nH

Fs=300kHzL = 2uH

VRM Output

(b) VRM transient response at 1 MHz

Figure 2.8 improve VRM transient response by increasing switching frequency

31

2% limit

VRM Output

Figure 2.9 To meet the transient requirement, the VRM needs to operate at 16MHz

32

η=80%

20 40 60 80 1000.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

20 40 60 80 1000.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Effi

cien

cy

Load (A)

fs = 300 kHz

fs = 1 MHz

fs = 10 MHz

Figure 2.10 VRM efficiency at high frequency

33

2.2.2 Efficiency Limitation

Another limitation of the conventional VRMs is efficiency. Figure 2.11 shows the

conventional VRM efficiency at 2-V output. Using IRL3803 as switches, with an on-resistance

of 6mΩ and 30 V voltage rating, the conventional VRMs cannot meet the 80% efficiency

requirement at heavy load. For lower output voltage, it will be even more difficult to meet the

efficiency requirement. Figure 2.12 shows the conventional VRMs’ efficiency at 1.2-V output.

Their efficiency cannot meet the 80% requirement for the whole load range.

This limitation is from today’s power device’s technology. Based on vertical power

MOSFET technology, most of today’s low-voltage power MOSFETs are available at a rating of

30 V. Roughly, the total power loss of a power device can be divided into three parts: 1)

conduction loss; 2) gate drive loss; and 3) switching loss. Figure 2.13 shows the relationship

between conduction loss and gate drive plus switching loss. For this kind of low-voltage high-

current application, conduction loss contributes a large percentage of the total loss. When only

one IRL3803 is used, the MOSFET’s conduction loss is 25 times the gate drive plus switching

loss. To reduce conduction and total loss, more switches need to be paralleled. However, this

does not necessarily mean that more parallel switches equals lower total loss. When five

IRL3803s are paralleled, the total loss is reduced to the minimum. After this point, adding more

switches will not improve efficiency. Figure2.14 shows the VRM efficiency with five IRL3803s

in parallel. With the optimized efficiency design, the VRM efficiency still cannot meet the 80%

requirement for the whole load range. This limitation is due to the high Figure of Merit (FOM) of

today’s devices. FOM is equal to Rdsontimes Qg. For today’s device technology, the lowest FOM

value is around 400 (mΩ× nC). With such a high FOM value, power devices not only limit the

VRM’s efficiency,

34

10 20 30 40 500.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

I load (A)

10 20 30 40 500.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95Con Buck Syn Buck

η=80%

Eff

Figure 2.11 Conventional VRM efficiency

(Vin=5V, Vo=2V, fs=300kHz, Switches: IRL3803)

10 20 30 40 500.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

I load (A)

10 20 30 40 500.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

Con Buck

Syn Buck

η=80%

Eff

Figure 2.12 Conventional VRM efficiency

(Vin=5V, Vo=1.2V, fs=300kHz, Switches: IRL3803)

35

0

2

4

6

8

1 0

1 2

1 4

1 6

1 2 3 4 5 6 7 8

N u m o f S W

Loss

(W)

G a te L o s s + S w L o s s

C o n d L o s s

T o ta l L o s s

Figure 2.13 Switching loss and gate drive loss and conduction loss of IRL3803

vs parallel switch number (Vin=5V, fs=300kHz, Iload=50A)

10 20 30 40 500.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

I load(A)

η=η=η=η=80%

Eff

Figure 2.14 Efficiency of synchronous buck VRM

(Vin=5V, Vo=1.2V, fs=300kHz, 5 IRL3803 in parallel)

36

but also limit the VRM’s ability to operate at higher operating frequencies. Most of today’s

VRMs operate at a switching frequency lower than 300 kHz. This low switching frequency

causes slow transient response and very large energy storage components.

2.3 Candidate VRM Topologies

2.3.1 Fast transient VRM topology

To overcome the transient limitation occurring in conventional VRMs, smaller output

filter inductance is more desirable to increase the energy transfer speed. Figure 2.15(a) shows the

Quasi-Square-Wave (QSW) circuit. Figure 2.15(b) shows the operation waveform of QSW

VRM. When Q1 turns on, the input voltage charges the inductor current from negative to

positive. After Q1 turns off, and before Q2 turns on, the inductor current flows through Q2’s

body diode. Then Q2 can turn on at zero voltage. After Q2 turns on, the inductor current is

discharged to negative. After Q2 turns off, and before Q1 turns on, the inductor current flows

through the Q1 body diode. Then Q1 can turn on at zero voltage. In the QSW topology, both the

top switch and bottom switch can turn on at zero voltage. The miller effect in both switches is

eliminated and gate drive loss and switching loss is reduced.

The QSW topology keeps the VRM output inductor current peak to peak value is two

times the full load current, which makes the inductor current go negative in all load ranges. Its

inductor design is according to:

fsIo

DVoVinL

×××−≤

2)(

…….………………………….. (2.2)

37

L

CControl

V i n

Q1 V x

Q2

D1

D2

V gsQ 1

V gsQ 2

V x

IL Io

Q 1 D 2 Q 2 D 1

Figure 2.15 QSW topology

38

Vo

iL

Figure 2.16 Transient response of QSW

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Single QSW

Con Buck

Syn Buck

I load(A)

Eff

Figure 2.17 Efficiency of QSW compared with conventional VRM

(Vin=5V, Vo=2V, fs=300kHz)

39

Compared with the inductor design (Equation 1) in conventional buck and synchronous

buck topologies, its output filter inductance is reduced significantly, 20 times smaller. At 13 A

load and 300 kHz switching frequency, it needs only a 160 nH inductor as compared with a 3.2

µH inductor used in the conventional design at the same frequency. This small inductance makes

the VRM transient response much faster. Figure 2.16 shows the transient response of the QSW

topology. The third spike in output voltage becomes insignificant, and the second spike is

reduced significantly.

There are two disadvantages in this fast VRM topology. The first one is the large current

ripple. Large VRM output filter capacitance is needed to suppress the steady state ripple. Smaller

inductance results in faster transient response, but requires larger bulk capacitance. The second

one is its low efficiency, as shown in Figure 2.17. Due to the large ripple current, QSW switches

have larger conduction loss. Their efficiency is lower than that of conventional VRMs.

2.3.2 Fast VRM with small ripple ---- interleaved QSW VRM

In order to meet both the steady state and transient requirements, a novel VRM topology,

interleaved QSW, is proposed in Figure 2.18. The interleaved QSW topology naturally cancels

the output current ripple and still maintains the fast transient response characteristics of the QSW

topology. Smaller capacitance is needed as compared to both single-module QSW VRM and

conventional VRM design. Figure 2.19 shows the comparison of ripple canceling effect of two-

module interleaved QSW VRM and four-module interleaved QSW VRM. In a two-module

interleaved VRM, only when duty cycle is0.5, the ripple is fully canceled. But in four-module

40

LoadIL1

IL2

Io

IL1

IL2

Io

T/2

Figure 2.18 Current ripple canceling effect of interleaved QSW

41

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Duty Cycle

Vin=10Vo Vin=3.3Vo

Rip

ple

Rat

io

Vin=2Vo

(a) Two modules interleaved

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Duty Cycle

Vin=10Vo Vin=3.3Vo

Rip

ple

Ra

tio

Vin=2Vo

(b) Four modules interleaved

Figure 2.19 Ripple canceling effect

42

interleaved VRM, the ripple can be fully canceled when the duty cycle is 0.5 or 0.25 or 0.75. If

the duty cycle is not at these points, for example, when the duty cycle is 0.3, 80% ripple is

canceled in 4-moduel structure and only 45% ripple is canceled in 2-module structure.

Figure 2.20 shows a 4-module interleaved QSW VRM. The more the modules that are in

parallel, the better the ripple canceling effect. Figure 2.21 shows its transient response. Figure

2.21(a) shows the current in each single module, which has large ripple. Figure 2.21(b) shows

the total current in output, which has very small ripple. Figure 2.21(c) shows the output voltage

during transient. As a result, only two times the VRM output filter capacitances needed as

compared to three times the capacitance needed in conventional design. To further improve

transient response, the control strategy shown in Figure 2.22 can be used. When the VRM output

voltage drops below the reference (-), all top MOSFETs are turned on, and all bottom MOSFETs

are turned off. When the VRM voltage drop is higher than the reference (+), all top MOSFETs

are turned off, and all bottom MOSFETs are turned on. This approach can increase the energy

transfer speed. Figure 2.23 shows its transient response. With this approach, it is not necessary to

increase the VRM output capacitance to meet transient requirement. Figure 2.24 compares the

capacitance needed in the conventional VRM and the 4-module interleaved QSW VRM for

future applications. Compared with traditional technology, the capacitance needed in sn

interleaved QSW VRM is much smaller: one third bulk capacitance needed. Due to the fast

transient response, the decoupling capacitance is also reduced, only one-ninth capacitance is

needed as compared to conventional VRMs. Actually, interleaved QSW topology cannot reduce

43

Load

Figure 2.20 4-module interleaved QSW VRM

44

(a) Current in each module

(b) Total output current

2 % L im i t

(c) Output voltage

Figure 2.21 Transient response of 4-module interleaved QSW (2 times bulk cap needed)

45

PWM SAT PWM

Vo

Vref -

DT

DT

DT

DT

DT

DT

DT

DT

PW

M

S Ssync

Vref +3% Vref -3%

±3% Window

Vf

Figure 2.22 Control strategySaturating duty cycle

46

IL1 IL2 IL4IL3

saturation time

Figure 2.23 VRM transient response with duty cycle saturating control (1 time bulk cap needed)

47

DecouplingBulk

ConventionalVRM

CPUChip

Processor Cartridge

26X3X+

VO

-

+VD

-

CB=9.84mF CD=520µF

1~3V

1~50A

5A/nS

(a) Conventional VRM

DecouplingBulk

Interleaved

QSW VRMCPUChip

Processor Cartridge

3X1X+

VO

-

+VD-

CB=3.3mF CD=30µF

1~3V

1~50A

5A/nS

(b) 4-module interleaved VRM

Figure 2.24 Capacitance needed in conventional VRM and interleaved VRM

48

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

4 modules parallel QSW

Con Buck

Syn Buck

Syn Buck w/schottky

Single QSWEF

F

Figure 2.25 Efficiency comparison

49

output current ripple only, but also can reduce input current ripple. For the same load, both input

and output filter sizes can be reduced dramatically. As a result, the interleaved QSW VRM can

achieve very high power density, and motherboard space can be saved. On the other hand,

compared with the single-module QSW topology, its efficiency is improved significantly. Figure

2.17 shows the efficiency comparison results. Since each module handles lower power, the

interleaved QSW VRM will be packaged easily.

2.4 Experimental Evaluations and practical issue

2.4.1 Experimental Evaluations

A four-module interleaved QSW VRM is built and tested to evaluate the advantages of

this technique. This VRM is designed for 5 V input voltage and 2 V output voltage. The load

current changes from 0.8 A to 30 A. The power devices are an Si4410DY, which has 14mΩ on

resistance, and an SO-8 package. The switching frequency is 300 kHz in each module. The

output ripple frequency is 1.2 MHz. The inductance in each module is 320nH. The equivalent

inductance of the 4-module interleaved VRM is 80nH, and integrated magnetic structure is used.

Two inductors use one magnetic core. The output filter capacitance is totally 1200µF. The output

capacitors are combined by ceramic and tantalum capacitors. The profile of the power stage is

0.3in. The power density is higher than 30W/in3.

Figure 2.26 shows the prototype picture. Figure 2.27 shows the integrated magnetic

structure [5]. By taking advantage of interleaving technology, the AC flux of the two inductors

is canceled in the center leg. As a result, the core loss and center leg crossing area is reduced.

The planar core structure makes the VRM very low profile. And this kind of low profile

50

PCB windingsIntegrated Magnetic

Figure 2.26 4-module interleaved QSW VRM

51

CoreWinding

PC Board

Gap

L1 L2

(a) Integrated magnetic Structure

L1

L2

1

2 0

PC Board Winding

Through Hole1 20

(b) Implementation of integrated magnetic

Figure 2.27 Integrated magnetic

52

50mv/div

50mv/div Step up

Step down40mv

40mv

5us/div

5us/div

50mv/div

100us/div

50mv/div

100us/div

50mV170mV

10us/div

50mv/divStep down

Step up

10us/div

50mv/div140mV

150mV

(a) 4-module interleaved QSW VRM (b) Conventional VRM

Figure 2.28 VRM transient response

(Step down: load changes from 15A to 0.8A; Step up: load change from 0.8A to 15A)

53

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

0 5 10 15 20 25 30 35

Load Currnt (A)

Effi

cien

cy

Figure 2.29 Efficiency of 4-module interleaved QSW VRM

54

Table 2.2 Comparison of 4-module interleaved QSW VRM and conventional VRM

InterleavedQSW

ConventionalVRM

Vin

Bulk capacitance

Output inductance

Vo@load

Transient voltage drop

Power stage power density

5 V 5 V

1200 uF 7500 uF

320 nH (*4) 3.8 uH

40mV(Io: 0-15)150mV(Io: 0-15)

2V@30A 2V@15A

30 W/in 5 W/in3 3

55

magnetic also has good thermal management. In the magnetic design, the PCB trace is used as

the inductor winding. This approach is very cost effective. Besides, the termination loss is

eliminated.

Figure 2.28 shows the VRM transient response. When the load changes from 0.8 A to

15A and vice versa, the 4-module interleaved QSW VRM has only 40 mV voltage drop as

compared to the conventional VRM which has a 150 mV voltage drop. Figure 2.29 show the

VRM efficiency. At 30A full load, its efficiency is higher than 85%. Table 2.2 compares the

design of interleaved QSW VRM and the conventional VRM. The interleaved QSW VRM uses

much smaller capacitance, only one-sixth the capacitance used in the conventional VRM. Its

power density is also much higher, six-times higher than that of a conventional one.

2.4.2 Practical issue

One important practical issue is the delay in the VRM system. Fig. 2.30 shows the delays

in the system. These are the control delay and the power switch delay. The control delay, shown

in figure 2.31, is the delay time between the point when the load begins to change and the point

when the gate sign begins to change. The device delay, shown in figure 2.32, is the delay time

between the point when the gate sign begins to change and the point when the switch fully turns

on or turns off.

These delays have a significant effect on the VRM transient response. The simulation

results in Figure 2.33 show the effect of different delay times. In Figure 2.33(a), if total delay

time is 300 ns, the output voltage drop is 100 mV. In Figure 2.25(b), if the total delay time is 150

ns, the output voltage drop is only 50 mV. For the future VRM, if an advanced signal can be

56

Load

Vc1

Vc2

Controller

Vref1

Vref2

Vo

Control delay td1

Device delay td2

V1Vgs

Vds1

Vds2

Figure 2.30 The delays in the VRM system

57

t d1

V gs1

V gs4

V gs2

V gs3

Io

V o

V ref

Figure 2.31 The control delay

58

VgsQ2

V dsQ1

V dsQ2

V x

t d2

VgsQ1

turn-on delay

turn-off delay

Figure 2.32 The power switch delay

59

Vo50mv/div 100mV

(a) Delay 300nS

50mVVo

50mv/di

(b) Delay 150nS

Figure 2.33 Effect of delay time

(Vo=2V, Load change from 0.5A to 13A)

60

given to saturate the duty cycle of the switches or if a faster controller and switch can be used,

the transient response of the interleaved QSW VRM will be improved noticeably. However, for

conventional VRMs, due to the limitation of the large output inductance, reducing delay time is

not helpful. Except for adding capacitors, it is difficult for conventional VRMs to reduce voltage

drop during the transient.

2.5 Summary

Except for adding capacitors, it is difficult for conventional VRMs to meet the transient

requirements for future microprocessors. The interleaved QSW topology can improve VRM

transient response significantly. With this technique, both VRM input current ripple and output

current ripple are canceled. Both VRM input and output filter size can be reduced dramatically.

As a result, the interleaved QSW VRM can achieve very high power density and can be

packaged easily.

61

3 Chapter Three

A Novel Current Sensing and Current Sharing Technique

3.1 Introduction

In order to achieve fast transient response and high power density and high efficiency,

small-inductance high-frequency interleaved multi-module synchronous rectifier QSW VRM is

much more desirable. Due to interleaved approach, both VRM input and output current ripples

are canceled and VRM filter size is dramatically reduced. The complex of the interleaved

technique is current sharing control. Although this is a common issue in module parallel

application, due to the strict cost and size and efficiency requirements and integration purpose,

the current sensing and control sharing control techniques become more critical in the VRM

application. In traditional approaches, a current transformer or sensing resistor has to be used to

sense the current in each module. However, a current transformer is too expensive and bulky,

and a sensing resistor significantly reduces converter efficiency in this kind of low-voltage high-

current application. On the other hand, the traditional current sharing control, such as voltage

mode control or peak current mode control, are affected strongly by the switch-on resistance or

inductance value, which are difficult to control by the manufacturer.

In this chapter, a novel current sensing and current sharing technique is proposed. With

this technique, current sharing control can be implemented simply in parallel modules without

traditional current sensing approaches, and it is as easy to integrate as an IC chip. The 4-module

interleaved QSW VRM is used to evaluate this technique.

62

3.2 Traditional control used in module-paralleling application

3.2.1 Single loop Voltage mode Control

In module paralleling application, the single loop control with only voltage loop control

is the simplest approach. With this approach, current sensing and current sharing control is

involved. The uniform current distribution between the modules depends on the uniformity of the

different modules. Practically, it is difficult to achieve current sharing without a specific current-

sharing control. There are many factors that contribute to such non-uniform distribution:

component tolerances, non-identical characteristics of the connection from the converters to the

shared load, and non-identical changes in components’ characteristics due to differences in

component aging and different physical conditions.

The reason why industry tries this approach for VRM application is due to its cost-

effective implementation. The Semtech VRM controller, SC1144, is designed in this way, which

keenly rely on the identity of the power devices in different modules. Since it is difficult to

control the sameness of semiconductor devices, the current sharing result is poor. As a result,

thermal management becomes more thorough, the VRM efficiency is reduced, and VRM power

stage cost is increased.

Actually, the current sharing with only voltage mode control becomes more obstinate in

low-voltage high-current application. Figure 3.1 shows the practical equivalent converter model.

Figure 3.1(a) shows the MOSFET model, which is equal to one ideal switch in series with a

resistor. This resistor is its on resistor. Figure 3.1(b) shows the equivalent model for a

synchronous rectifier buck converter. Where, Ron1 and Ron2 represent the on-resistance of the

63

top switch and the bottom switch, R3 is the sum of equivalent winding resistance and layout

resistance. If we consider the effect of these parasitics, the buck converter duty cycle becomes:

)12(

)32(

RonRonIoVin

RRonIoVoD

−×++×+= ………………………………… (3.1)

In conventional application, since Vo is much larger than Io*(Ron2+R3), the effect of

this item can be ignored. However, in low-volatge high-current application, Vo is small and the

effect of Io*(Ron2+R3) becomes much more significant. For example, if Vo is 2V, Vin is 5V,

Ron1 and Ron2 are 14 mΩ, when the load changes from 0A to 30A, the converter duty cycle will

change from 0.4 to 0.5. Normally, MOSFET on-resistance, Ron, is much larger than the winding

and layout resistance,R3, and Vin is larger thanIo*(Ron2-Ron1). Equation 3.1 can be simplified as:

Vin

RonIoVoD

2×+= …………………………………………. (3.2)

This feature strongly affects the current sharing result when only a single voltage loop is

used. Figure 3.2 shows the circuit diagram of two parallel modules with only single voltage loop

control. For module 1, its duty cycle is:

Vin

RonIoVoD

1211

×+= ………………………………………… (3.3)

For module 2, its duty cycle is:

Vin

RonIoVoD

2222

×+= …………………………………….…. (3.4)

Where, Io1 and Io2 are the output current in each module. Ron12 and Ron22 are the on

resistance of the synchronous rectifier in each module. Since the error signal, Vc, is the common

signal used to be compared with the ramp signal to generate the duty cycle signal for each

64

module, if the ramp amplitudes are the same, D1 is equal to D2. From equation 3.2 and 3.3, there

is:

222121 RonIoRonIo ×=× …………………………………… (3.5)

The current sharing can be achieved only if Ron12 is equal to Ron22. But this is the most

difficult part to control. Usually, there is a±20% difference in the same types of devices. Table

3.1 shows some examples from the industry data sheet. It is very difficult to realize uniform

current distribution by this approach. Figure 3.3 shows the effect of MOSFET on-resistance on

current rsharing. The larger the load current, the worse the current sharing result.

3.2.2 Peak current mode control

To avoid the effect of MOSFET on-resistance, current mode control can be used. Peak

current mode control is one of the most popular methods used today. Its implementation is very

simple. Figure 3.4 shows the control diagram. The error signal from the voltage loop

compensator is used as a reference signal to be compared with the peak current signal from each

module. The result is the duty cycle signal for each module.

The advantages of this approach are simple and unaffected by device parasitics. The

disadvantages are poor current sharing at light load and the effected of the inductance value of

each module. Figure 3.5 shows how the difference in inductance value affects the current sharing

result. Since, in this parallel system, each module has the same input and output voltage. If the

inductance is different in each module, the inductor current peak-peak value in each module will

be different. The module that has small filter inductance will have large peak-peak current value.

Because the peak current mode control only limits the maximum peak current value in each

65

module, the average current in each module is controlled. As a result, the module with small

filter inductance has smaller current. Practically, the inductance value is difficult to control.

Normally, there is 20~30% difference in different inductors.

IdealSwitch

Rds(on)

Equivalent model of MOSFET

Ron1

Ron2

R3L

(b) Equivalent model of Syn rectifier buck

Figure 3.1 Equivalent model

66

R 1 1

R 1 2

R 1 3L 1

R 2 1

R 2 2

R 2 3L 2

V i n V o

Z 1

Z 2

V r e fC o m p a r a t o r 1

C o m p a r a t o r 2

V o l t a g e L o o p C o m p e n s a t o r

V c

D 1

D 2

C o n t r o l l e r

Control diagram

V c

R a m p 1

R a m p 2

D 1

D 2

D 1 = D 2

(b) Control signal

Figure 3.2 Parallel converters with only single loop voltage mode control

67

Table 3.1 MOSFET on resistance

* Test condition: Vgs=4.5V

Device Rds(on) (typ) Rds(on) (max)

Si4410 0.015 0.020

Si4412

Si4420

Si9804

0.030 0.042

0.010 0.013

0.022 0.030

68

20m

20m

2m320nH

10m

10m

2m320nH

Vin=5V

Vo=2V

I 1

I 2

0

1

2

3

4

5

6

7

8

9

0 2 4 6 8 10 12 14

Load(A)

Cur

rent

inpe

rm

odul

e(A

)

I 1

I 2

222121 RonIoRonIo ××××≈≈≈≈××××

Figure 3.3 Current sharing result with only single loop voltage mode control

69

Figure 3.6 shows the effect of different inductance value. The effect can be expressed as:

)1

1

2

1()(

221

LLVoVin

fs

DIoIo −×−×

×=− …………………… (3.6)

Where fs is switching frequency. The current difference in each nodule is fixed from light

load to heavy load. Relatively, at light load, the current sharing result is worse. The difficulty of

peak current control in VRM application is that the current transformer or sensing resistor is

needed to detect the peak current signal.

70

Vc

Load

S1

S2

S4

S3

L1

L2

Z1

Z2

Vref

Voltage Loop Compensator

Comparator 1

Comparator 2

External ramp

External ramp

Peak Current Signal

Peak Current Signal

Figure 3.4 Peak current mode control diagram

71

ExternalRamp

Ramp of channel 1 Ramp of channel 2

InductorCurrent(L1>L2)

Io1Io2

IL1 IL2

ControlSignal(L1>L2)

Channel 1 Channel 2

Vc

External ramp+sensed current signal

Figure 3.5 Control signal: the effect of different inductance value

72

R11

R12

R13300nH

R21

R22

R23320nH

Vin=5V

Vo

=2V

I 1

I 2

0

1

2

3

4

5

6

7

8

0 2 4 6 8 10 12 14

Load(A)

Cur

rent

inea

chch

anne

l(A

)

I 1

I 2

Figure 3.6 the effect of different inductance value on current sharing

73

3.3 A novel current sensing and current sharing technique

3.3.1 A novel current sensing technique

For future low-voltage high-current module parallel system application, a current sensing

and current sharing control technique that is simple, cheap and non-sensitive to parasitic

parameters is required.

Figure 3.7 shows a RC switching network. The two switches turn on and turn off in a

complementary fashion, like those in a synchronous rectifier buck converter. When the top

switch, S1, turns on, the bottom switch, S2, turns off and the output capacitor is charged by the

difference of the input voltage and the capacitor voltage through the resistor, R. When S1 turns

off, S2 turns on and the output capacitor is discharged by the output voltage through R and S2.

The duty cycle of this switching network is:

Vin

VcD = …………………………………………….. (3.7)

It is like the duty cycle of a buck converter. Actually, this buck-type-switching network

does not transfer energy to output. At steady state, the average voltage on R is zero, since the

average current flowing through the output capacitor is zero. If this switching network is

combined with a synchronous rectifier buck converter, the additional switching network does not

affect the characteristics of the synchronous rectifier, since there is no energy through this R and

C branch. Figure 3.8 shows the combination, where R3 is the sum of the winding resistor and the

layout resistor. Ron1 and Ron2 are the MOSFET on-resistance. In steady state, since the average

voltage on the output inductor, L, and the resistor, R, is zero. The average voltage of Vc is:

74

Vc(avg) = Vo + R3× IL(avg) ………………………. (3.8)

R on 1

R on2

R

V in V c

Ic

Ic

V c

R

V oV in −

R

V o−

∆V

Figure 3.7 A R and C switching network

75

Ron1

Ron2

R3L

Vo

R

VcControlVinC

Figure 3.8 A novel current sensing technique

76

Where IL is the inductor current and Vo is the output voltage of the synchronous rectifier

buck converter. From equation 3.8, the average inductor current can be obtained:

3

)()(

R

VoavgVcavgI L

−= ……………………………... (3.9)

In equation 3.9, the detected average inductor current is decided only by R3, the winding

resistance. The accurancy of R and C, the inductance value, and the MOSFET on-resistance have

no effect on the current sensing result. With this switching RC network, the traditional current

transformer or sensing resistor is not required and the average inductor current can be measured

by the average capacitor voltage. Compared with the MOSFET on-resistance and the inductance

value, the winding resistor is easier to control during manufacturing. The implementation of this

current sensing approach is simple, cheap, and has no effect on converter efficiency.

3.3.2 A novel current sharing control technique

With the proposed current sensing approach, a simple current sharing control technique

without traditional current sensing approaches is proposed in Figure 3.9. Taking advantage of

average Vc signal, the average inductor current in each module is controlled. Figure 3.9 shows

the control function block, which includes the current sharing control loop and voltage loop. All

parallel modules use a common voltage loop. Every module has its own current sensing RC

network and its own current sharing control loop.

It should be pointed out that, although in the following analysis only the parallel

connection of two modules is considered, the proposed current sharing control approach is

applicable to any number of modules connected in parallel. The only reason for focusing on the

77

two-module parallel connection is to explain the principle of the operation in the simplest and

most obvious manner.

In Figure 3.9, the sensed average current information is included in the capacitor voltage

signal. In module 1 and module 2, there are:

VoRIoavgVc +×= 131)(1 ………………………...….. (3.10)

VoRIoavgVc +×= 232)(2 ……..…………………….. (3.11)

Where Io1 and Io2 are the average current in each module. First, let us assume that R13

is equal to R23, which means that the inductor winding design and layout design are symmetrical

in each module. Actually, this kind of symtery is easy to control in manufacturing. In order to

achieve uniform current distribution,Vc1(avg) has to be equal to Vc2(avg). From equation 2.10

and 2.11, when Vc1(avg) is equal to Vc2(avg), R13 is equal to R23, and Io1 is equal to Io2.

Now, it is clear that the purpose of the current sharing control loop is to control Vc1 and Vc2 and

make them the same.

Figure 3.10 shows a simple approach of how to control these two RC networks and make

Vc1 equal Vc2. In figure 2.10, the current sharing control loop is an integrator-type compensator.

A common reference signal is used for all the modules. Since the control includes an integrator,

there is no steady state error. Both RC network outputs, Vc1 and Vc2, should be equal to the

reference voltage. Figure 3.11 shows a completed control diagram. An integrator is used in

current sharing control loop. The error signal from the voltage compensator is used as a reference

to control the RC network output in each module.

78

R21

R22

R23L2

R11

R12

R13L1

Load

Ve

Vref

Z2

Z1

D1

D2

R

R C

C

Current sharing

control loop 1

Vc1=Io1*R13+Vo

Io2

Io1

Vc2=Io2*R23+Vo

Current sharing

control loop 2Voltage loop compenstor

Figure 3.9 A novel current sharing technique

79

R21

R22

R11

R12

Vref

R11

R21

C22

D1

D2

C12

R

R C

C

Compensator 1

Compensator 2

Vc1=Vc2

Vc2=Vc1

Figure 3.10 Control Vc2 = Vc1

80

R21

R22

R23L2

R11

R12

R13L1

Load

Ve

R11

Vref

Z2

Z1

R21

C22

D1

D2

C12

R

R C

C

Current sharing 1

Vc1=Vc2

Vc2=Vc1

Current sharing 2

Voltage loop control

Figure 3.11 A completed current sharing control diagram

81

Io =1A, I1avg - I2avg =0.026A Io =13A, I1avg - I2avg =0.02A

11

I 2I 2

11

20m

20m

1m320nH

10m

10m

1m300nH

Vin=5V

Vo=2V

I 1

I 2

Figure 3.12 Difference in MOSFET on resistance and inductance value

has no effect on current sharing result

82

With the control approach shown in Figure 3.11, Vc1 is always equal to Vc2. From

equation 3.10 and 3.11, there is:

232131 RIoRIo ×=× ……………….………………… (3.12)

The current sharing result depends on the ratio of R13 and R23. When R13 is equal to

R23, the current sharing has very good results and the difference in MOSFET on-resistance and

inductance value has no effect on current sharing. Figure 3.12 shows a simulation result. There

are two modules in parallel. In one module, the MOSFETs’ on-resistance is 20mΩ and the

output filter inductance is 320 nH. In other module, the MOSFET’s on resistance is 10 mΩ and

the output inductance is 300nH. When the load changes from a light load, 1A, to a heavy load,

13A, the current difference in the difference module is smaller than 30mA.

3.3.3 Design and Experimental Results

Figure 3.13 shows the test circuit. The power stage is a 4-module interleaved QSW

VRM. The inductance of each module is 320nH. The switching frequency is 300 kHz. The input

voltage is 5 V. The output voltage is 2 V. The maximum load is 30 A. In the test circuit, the PCB

trace is used as the inductor winding. R3 is the PCB trace resistance. Figure 3.13 also shows the

trace resistor, R13, R23, R33 and R43. Although these resistances are very small, 1mΩ each, the

current sharing result has not been affected. In fact, the current sharing is decided by the ratio of

these resistances. As shown in Figure 3.13, all the traces have almost the same length and width.

As a result, R13, R23, R33 and R43 have almost the same resistance, and uniform current

sharing can be achieved.

83

With the proposed current sharing control technique, the control design is very simple.

The current sharing control loop uses an integrator, and the voltage loop can be designed in a

traditional manner. Figure 3.14 shows the compensator design in the current sharing control

loop. To make sure the loop is stable, R * C in the RC network is 10 times smaller than Rf * Cf in

the integrator. With this current sharing control loop design, the 4-module interleaved QSW

VRM shows very good current sharing performance. Figure 3.15 is the test. When the load

current increases from 0.5 A to 30 A, the difference in the input currents is less than 50mA.

Since the uniform current sharing is achieved, the VRM efficiency has high efficiency, as shown

in Figure 2.20.

Figure 3.16 shows the voltage loop compensator design, which is a traditional two-pole

one-zero compensator. The voltage loop design is to make sure its close-loop bandwidth is high

and its transient response is fast enough. Figure 3.17 shows the measured VRM close-loop loop

gain. The bandwidth is 85 kHz and the phase margin is 62 degrees. Due to the wide bandwidth,

the output impedance of the VRM is small and the converter has fast-transient response. Fig 3.18

shows a transient response of the 4-module interleaved QSW VRM, which uses the proposed

current sharing control approach. When the load changes from 0.5 A to 15 A (the load change

slew rate is 30 A/uS), the output voltage drops only 40 mV. The output capacitance is 1200 uF.

With the novel current sharing control, the new VRM has 10 times higher power density, much

faster transient response, and high efficiency as compared to conventional VRMs.

84

R13

R33

Integrated magnetic

R23 R43

Figure 3.13 Test set up and the R3 in each module

85

+

-

V1

V2

Cf

Rf

R

C

Vea

(a) Current sharing control loop compensator design

f

ff CRR ⋅+⋅

⋅ )(

1

2

1

τ

CRR

RR

f

f ⋅+⋅⋅

⋅1

21

τ

2 0 lo g (V 2 /V 1 )

(b) Body Plot

Figure 3.14 Current sharing control loop design

86

0 .0 00

0 .5 01 .0 01 .5 00

2 .0 00

2 .5 03 .0 00

3 .5 00

4 .0 0

0 .0

1 0 .0

2 0 .0

3 0 .0

4 0 .0L o a d (A )

Iin

c h 1

c h 2

c h 3

c h 4

Figure 3.15 Current sharing result: Input current in each module vs. total load current

87

R2

Vo

Vc

Vref

R3 C2

R1

C3

VcVo

Frequency

Figure 3.16 Voltage Loop Compensator Design

88

Figure 3.17 Measured loop gain

89

5 0 m v /d iv

5 0 m v /d iv

5 0 m v /d iv S te p u p

S te p d o w n4 0 m v

4 0 m v

1 0 0 u s /d iv

5 u s /d iv

5 u s /d iv

5 0 m V

Figure 3.18 Transient response

(Load changes from 0.5A to 15A and vice versa)

90

3.4 Generalization and extension of the novel current sharing control

3.4.1 Generalization of the novel current sharing control technique

The previous section discusses the implementation of the novel current sharing technique

when the winding resistance in each channel is the same. To generalize the application of this

technique, it is necessary to investigate its implementation when all the winding and layout

resistances are different.

Figure 3.19 shows the implementation of this technique when R13 and R23 are different.

Let us assume R13 and R23 have a fixed ratio:

kR

R =23

13……………………………………………… (3.13)

The control shown in Figure 3.19 is different from that shown in Figure 3.11. There are

two additional propotional amplifiers added in current sharing control loop 1. These two

amplifiers are used to adjust the current distribution ratio in different modules. In Figure 3.19, Va

and Vb are:

VoVcVoRb

RaVa +−×= )1( ………..………..………….. (3.14)

VoVoVcRb

RaVb +−×= )1( …………………………….. (3.15)

The two integrators in the two current sharing control loops make Vb equal to Vc2. From

equation 3.10, 3.11 and 3.15, the following relationship can be obtained:

2*231*13 IoRIoRRb

Ra =× ……………...…………….. (3.16)

91

R21

R22

R23L2

R11

R12

R13L1

Load

VeVref

Z2

Z1

R21

C22

D1

D2

C12

R11

R

R C

C

Current sharing 1

Vc1

Vc2

Current sharing 2

Voltage loop control

Vo

Ra RbRR

VaVb

Figure 3.19 Generalized implementation of the current sharing technique

92

As a result, if Ra and Rb satisfy the following relationship, Io1 is equal to Io2.

kR

R

Rb

Ra 1

13

23 == ……………………………………………. (3.17)

By controlling the ratio of Ra and Rb, the current distribution ratio can be decided.

Practically, in current sharing control loop design, it is not necessary to only use an integrator

compensator. Other compensations, like two-pole and one-zero compensators, can be used to

adjust the bandwidth of the current sharing control loop to improve current response speed.

3.4.2 Extension applications of the novel current sharing control technique

The proposed current sharing approach can be explored to other topologies and isolation

version converters, and it is not necessary to use only the output parasitics. Actually, in any kind

of parallel converter, when there is a common point for parasitics in different modules, this

technique can be used. The only thing that needs to be changed is the reference of the

proportional amplifiers in the current sharing control loop.

Figure 3.20 shows an approach of how to utilize the input parasitics in paralleled buck

converters. In Figure 3.20, the references of the proportional amplifiers are changed to Vin.

Figure 3.21 shows how to control current sharing in paralleled boost converters. Its references

also use Vin. Figure 3.22 shows how to control sharing in paralleled isolated converters. This

only shows some examples of how to use this technique. Practically, its application is not limited

by topologies, and the implementation is very simple and cheap. Besides, this technique can

easily to be integrated as an IC chip.

93

Load

VeVref

Z2

Z1

R21

C22

D1

D2

C12

R11

C

Current sharing 1

Vc2

Current sharing 2

Voltage loop control

Vin

Ra RbRR

VaVb

L1

R

L2

RC

Vin

Figure 3.20 Utilize input parasitics

94

R

R

Load

VeVref

Z2

Z1

R21

C22

D1

D2

C12

R11

Current sharing 1

Vc1

Vc2

Current sharing 2

Voltage loop control

Vin

Ra RbRR

VaVb

Figure 3.21 Applied in paralleled boost converters

95

R23L2

Load

VeVref

Z2

Z1

R21

C22

D1

D2

C12

R11

R

R C

C

Current sharing 1

Vc1

Vc2

Current sharing 2

Voltage loop control

Vo

Ra RbRR

VaVb

Converter 1

Converter 2

Figure 3.22 Applied in paralleled isolated converters

96

3.5 Summary

The proposed current sensing and sharing technique can be implemented simply without

current transformers and current shunts. There are many advantages to this technique. (1) The

difference of MOSFET on-resistance and inductance value has no effect on current sharing. (2)

Good current sharing results can be achieved easily. (3) Control design and the implementation

of this technique are simple. (4) The current sensing approach is cheap and has no effect on

converter efficiency. The R and C in the sensing network do not have to be precise. (5) With this

technique, VRMs have fast transient response, high power density, and high efficiency. (6)

Utilize the ratio of parasitics, not their absolute value. It is easy to control in manufacturing. (7)

This technique can be used widely without limitation from topologies. (8) This technique can be

integrated easily to an IC chip.

4 Chapter Four

Improve Light Load Efficiency for Synchronous Rectifier

Voltage Regulator Module

4.1 Introduction

For future microprocessor applications, QSW synchronous rectifier buck converter,

because of its small inductance, can easily achieve fast transient response and high power

density. The disadvantage of this topology is its low efficiency at light load, due to the large

conduction loss and gate driver loss. Actually, this is a common drawback to synchronous

rectifier type of converters. However, for many low-voltage applications, like mobile and

portable and battery applications, VRMs are always expected to be implemented with advanced

power management functions to further reduce the power consumption at light load, in order to

extend the battery-operation time in portable systems or to facilitate the compliance with various

"energy star" ("green" power) requirements in office systems. Therefore, it is very important that

VRMs have high efficiency at both light load and heavy load.

This chapter proposes a new technique that can improve light load efficiency by utilizing

the duty cycle signal. Since current sensors are not required by this technique, high density and

high efficiency can be achieved that makes the whole circuit suitable for integration. In this

chapter, four improved approaches are proposed and verified with experimental results. The first

two is designed for the fixed frequency controlled VRMs. The left two is designed for the hybrid

98

L

CControlV i n

Q1V x

Q2

Figure 4.1 Synchronous Rectifier Buck VRM

99

mode controlled VRMs [3] whose switching frequency changes proportionally to the load at

light load and keeps constant at heavy load.

4.2 Challenge in synchronous rectifier buck VRM

Most of VRMs use synchronous rectifier buck topology. Figure 4.1 shows the

synchronous rectifier buck circuit. This topology increases the efficiency of low-output-voltage

DC-to-DC converters by replacing the rectifier in a conventional buck converter with a

MOSFET. To overcome the transient limitation of the conventional synchronous buck VRM,

smaller output filter inductance is desirable in VRM applications to increase the energy transfer

speed. The VRMs with small inductance (one-tenth inductance used in today’s VRM), like QSW

VRM, can have very fast transient response and only need small filter capacitance [5]. It can

achieve very high power density.

The disadvantage of the small inductance VRM is its large current ripple, which in turn

makes its light load efficiency very low. For synchronous rectifier buck VRM, since the main

switch and the synchronous rectifier switch are always complementarily on. Its inductor current

can go negative at light load. Figure 4.2 shows the light load inductor current of a synchronous

rectifier buck VRM with small inductor. The negative current represents the circulation energy.

The smaller the inductance, the larger the circulation energy, the larger the conduction loss, and

the lower the efficiency at light load. Besides, with synchronous rectifier, the additional gate

drive loss and switching loss make the synchronous rectifier buck VRM have very low light load

efficiency. Figure 4.3 shows the efficiency of a QSW VRM. Its light load efficiency is lower

than 50%.

100

V g sQ 1

V g sQ 2

V x

IL Io

Q 1 D 2 Q 2 D 1

Figure 4.2 Light load inductor current of a synchronous rectifier buck VRM

with filter small inductance

101

10 20 30 40 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

I load (A)

10 20 30 50

1

EFF

Icri

Figure 4.3 Efficiency of 4-module interleave QSW VRM

102

There are several approaches to improve VRM light load efficiency. The first approach is

fixed frequency control: stop the inductor current from going negative and force the inductor

current to go into DCM mode after current lower than the critical current Icri shown in Figure

4.3. This can reduce VRM conduction loss at light load. In turn, VRM light load efficiency is

improved. Figure 4.4 explains the operation of this approach.

The second approach is hybrid mode control: fixed frequency control is used at heavy

load; after the load is lower than the critical current, VRM switching frequency is reduced

proportionally to the load. By hybrid mode approach, the inductor current is forced to go into

DCM mode. Its conduction loss is reduced at light load. Meanwhile, its gate driver loss is also

reduced because of its lower switching frequency. As a result, VRM with this approach can have

very high efficiency at light load. Figure 4.5 explains the operation of this approach. Figure 4.6

shows the expected efficiency curve at different load. The VRM light load efficiency is

constant when variable frequency control is used [8]. For variable frequency control, no matter

what constant on or constant off control, the inductor current peak value is constant. In DCM

mode, synchronous rectifier buck conduction loss is proportional to the switching frequency.

Also, its gate drive loss and switching loss is proportional to the switching loss. As a result, its

total loss is proportional to the switching frequency:

fskPloss ×= 1 ……………………………………………… (4.1)

103

Heavy load

Light load

IL

Figure 4.4 Approach A: fixed frequency control

104

Heavy load

Light load

I L

Figure 4.5 Approach B: hybrid mode control

(Fixed frequency control at heavy load, and variable frequency at light load)

105

Where, k1 is a constant and fs is switching frequency. In hybrid mode control, at light

load, the switching frequency is proportional to the load current. The output power is

proportional to the switching frequency:

VofskVoIoPout ××=×= )2( ……………………………… (4.2)

Where, k2 is a constant. The synchronous rectifier buck converter efficiency is:

12

111

kVok

k

PlossPout

Ploss

+×−=

+−=η ...…………………… (4.3)

Obviously, this efficiency is a constant.

The difficulty of these approaches is how to turn off synchronous rectifier automatically

when the inductor current goes negative at light load. The same question is how to predict

inductor current when it changes from CCM mode to DCM mode. Actually, for synchronous

rectifier buck, the inductor can change from DCM mode to CCM mode automatically. But when

the load change from heavy load to light load, it cannot detect the mode changing automatically

[10]. It needs to sense the inductor current to tell the switches when the converters should go into

DCM. With a conventional approach, current transformers are too bulky and expensive; sensing

resistors reduce converter efficiency significantly. Now, the challenge is how to detect the

critical point of CCM and DCM mode automatically without current sensing.

106

Load Increase

Efficiency

Const. Freq.

Vari. Freq

Figure 4.6 VRM Efficiencies under Different Control

107

4.3 Detect inductor current mode automatically

Many papers discuss the current detecting approach without current sensing. In the paper

[3], Thomas forces the converter to go into DCM periodically, which causes an output voltage

spike when the inductor current changes from CCM to DCM. In the paper [6], Barry Arbetter

took advantage of the inductor winding resistance and controlled the peak value of inductor

current. Since, in particle, low winding resistance is required for low-voltage high-current VRMs

to achieve high efficiency, this approach is very complicated and noise sensitive. The simplest

way to measure an inductor current is to use the Rds(on) by measuring the voltage drop (Vds)

between the source and drain when MOSFET is on. The measured peak voltage represents the

inductor peak current.

)()()( onRdspeakIpeakVds L ×= ………..………………… (4.4)

In fact, the Vds waveform of low Rds(on) MOSFET is very noisy. As a result, it is really

difficult to utilize the peak signal of Vds. To avoid the noise problem, the best way is to measure

average inductor current. Now the question is how to measure average inductor current without

traditional current sensing approach. If Vds is used to estimate the average load current, the

approach will be very complicated, because Vds includes too much information, such as dead

time, load current, duty cycle information, parasitic inductance and Rds(on).

Normally, the duty cycle of a buck converter shown in Figure 4.1 can be expressed as:

Vin

VoD = …………………………………………………….. (4.5)

108

IdealSwitch

Rds(on)

(a) Equivalent model for MOSFET

Ron1

Ron2

L

(b) Equivalent Model for synchronous rectifier

Figure 4.7 Equivalent model

109

However, this is not precise in low-voltage high-current application. Look at the model of

a synchronous rectifier shown in Figure 4.7. As described in chapter 3, its duty cycle is

approximately equal to:

Vin

RonIoVoD

2×+= …………..……………………………... (4.6)

Where, Ron2 is on resistance of bottom switch, Io is the average of inductor current and

Vo is output voltage. Since the input voltage and the output voltage are fixed, the duty cycle

changes with load. For example, when Vin is 5 V, Vo is 2 V, Ron2 is 14 mΩ and the load

changes from 0 A to 30 A, the duty cycle will change from 0.4 to 0.48.

By detecting the change of duty cycle, the average inductor current can be estimated. In

fact, duty cycle signal can be expressed as a voltage signal in the control. This voltage signal can

be used to tell the switches whether the inductor current is larger than the critical current. Figure

4.8 shows the operation function block. Like a traditional control loop design, there is a voltage

loop compensator. The error signal generated by voltage loop compensator is compared with the

ramp signal in comparator 1. The output of comparator 1 is the duty cycle signal. The duty cycle

signal is compared with Vcri to generate the current detecting signal that tells whether inductor

current should be in CCM mode or DCM mode. The reference voltage of comparator 2, Vcri, is

proportional to Dcri. Dcri is the critical duty cycle when the inductor current reaches the critical

point Icri. Dcri is:

Vin

RonIcriVoDcri

2×+= …..…………………..……………. (4.7)

110

Ron1

Ron2Vin Vo

Z1

Z2

Vref

Comparator 1

Comparator 2

Voltage Loop Compensator

VEA

D

Currentdetectingsignal

Logic

Vcri

Figure 4.8 Automatically detecting inductor current

111

Usually, the on resistance of MOSFET has± 20% variation range. It’s impossible to

define an accurate critical point for every individual converter. Practically, select Dcri as:

Vin

RonIoVoD

(max)2×+= …………………………………… (4.8)

Where, Ron(max) is the maximum on resistance value given by its datasheet. This

ensures a synchronous rectifier buck in DCM after load current lower than critical current.

4.4 Improve VRM light load efficiency: fixed frequency control

4.4.1 Disable synchronous rectifier at light load

The control function block is the same as that shown in Figure 4.8. The idea is to shut

down the synchronous rectifier after the load current is lower than critical current. Figure 4.9

explains the operation. At heavy load, synchronous rectifier buck converter operates at CCM

mode. At light load, when the average duty cycle signal is lower than Vcri, a disable signal is

generated from comparator 2 and the synchronous rectifier is shut down.

Figure 4.10 shows the tested VRM power stage. The input voltage is 5V. The output

voltage is 2V. The switching frequency is 300kHz. The output filter inductance is 340nH. The

load changes from 0.2A to 8A. A schottky diode D, 95SQ015, is in anti-parallel with

synchronous rectifier Q2. At light load, Q2 is shut down, and the schottky diode D is used to

continue the inductor current. Figure 4.11 shows the test results. The bottom curve shows the

112

VgsQ1

VgsQ2

ILIo

(a) At heavy load

VgsQ1

VgsQ2

I L Io

Disabled

(b) at light load

Figure 4.9 Fixed frequency: disable synchronous rectifier at light load

113

L=340nH

CControl

IRF7805

IRF7805D

Figure 4.10 Tested VRM power stage

(Vin=5 V, Vo=2 V, fs=300 kHz, Io: 0.2 A ~8 A)

114

30

40

50

60

70

80

90

100

0 2 4 6 8

Output current (A)

Conventional control (CCM)

Shut down synchronous rectifier at light load (CCM+DCM)

Figure 4.11 Efficiency test results (including gate driver loss)

115

VRM efficiency when conventional control approach is used, with which the VRM

always operates in CCM mode. The top curve is the efficiency tested when the synchronous

rectifier is shut down at light load. The results show that there is 30% improvement at light load.

With this approach, the gate driver loss and switching loss of the synchronous rectifier is saved.

The cost added is the anti-paralleled schottky diode.

4.4.2 With synchronous rectifier at light load

This approach is explained in Figure 4.12. At heavy load, the synchronous rectifier VRM

operates at CCM mode. At light load, the synchronous rectifier is turned off when the inductor

current goes into negative and the VRM operates at DCM mode. In order to control the

synchronous rectifier turn off timing, an inductor current emulating signal is required. Figure

4.13 shows the inductor current emulating network. It is like a dual network of a synchronous

rectifier buck converter. The two current sources, I1 and I2, is used to replace the two voltage

sources, Vin and Vo. The resistor, R, is used to replace the inductor and is in parallel with the

capacitor. In Figure 5.13, (I1-I2) is used to charge the capacitor, and the charge time is controlled

by duty cycle. –I2 is used to discharge the capacitor. The duty cycle of this switching network is:

2

/)(1

I

RavgVcID

+= .………………...……………………… (4.9)

116

VgsQ1

VgsQ2

ILIo

(a) At heavy load

VgsQ1

VgsQ2

IL Io

(b) At light load

Figure 4.12 Fixed frequency: with synchronous rectifier at light load

117

Compared with equation 4.6, if I1 and I2 are proportional Vin and Vo respectively, Vc is

proportional to the inductor current. For example, When Vin is 5V and Vo is 2V, if I1 is 5mA

and I2 is 2mA, and if the two duty cycle of the two switching network is the same, then Vc is:

1000)(

RRonIoavgVc

××= ……………….….……………… (4.10)

Therefore, the average value of Vc is proportional to the average inductor current Io.

From equation 4.10, at critical point, Vc(avg),cri is:

1000),(

RRonIcricriavgVc

××= ………………………………. (4.11)

The capacitor ripple volatge is:

fsC

DIIVc

××−=∆ )21(

………………………………………... (4.12)

At critical point,∆Vc,cri is:

fsC

DcriIIcriVc

××−=∆ )21(

, …………...……………………. (4.13)

The control function block is shown in Figure 4.14. The selection of Vcri is according to

Equation 4.7. Vc signal is compared with Vcri to control synchronous rectifier buck DCM

operation. Here, select C to meet:

VcricriVccriavgVcVc =∆+= ,),( ……………………..… (4.14)

118

IC

Vc

21 II −

2I−

RVc

IcI1 I2

Figure 4.13 The current emulating network

119

With this control strategy, when the load changes, the inductor current of the synchronous

rectifier can change the mode automatically from CCM mode to DCM mode, and vice versa.

Figure 4.15 shows the key control waveforms when buck operates at heavy load. At heavy load,

there is no intersection between load emulating signal Vc and Vcri, which means that its load is

higher than the critical current. The synchronous rectifier buck operates at CCM mode. At heavy

load, in current emulating network, the capacitor C’s charging time, t1, is equal to duty cycle

time, D*T. Its discharging time, t2, is equal to (1-D)*T. There is:

)()1(2

1

VoVin

Vo

TD

TD

t

t

−=

×−×= …..………………………….. (4.15)

Actually, at heavy load, the operation of this control is the same as conventional buck

PWM control.

Figure 4.16 shows the key control waveforms when synchronous rectifier buck operates

at light load. Since the load is reduced, there is intersection between load emulating signal Vc

and Vcri. The generated current-detect signal blocks the gate signal of the synchronous rectifier.

As a result, the conduction period of the synchronous rectifier is reduced. The synchronous

rectifier buck is forced to operate in DCM mode. The main switch is turned on after the current

emulating signal Vc larger than Vcri. Then, the inductor current is charged up from zero. After

duty cycle time, D1*T, the inductor current is charged up to∆IL:

L

TDVoVinI L

××−=∆ 1)(…..……………………………… (4.16)

After the main switch turned off, the synchronous rectifier is turned on and the inductor

current is discharged. The discharge time is D2*T. If the inductor current is prevented from

going into negative, D2*T should be:

120

Vo

LITD L ×∆

=×2 …………………………………………. (4.17)

In other words, from equation 4.16 and 4.17, D1*T and D2*T should meet:

)(2

1

VoVin

Vo

TD

TD

−=

××

………………………………………. (4.18)

From Figure 4.16, D1*T is equal to t11 and D2*T is equal to t21. Therefore,

2

1

2221

1211

22

12

21

11

2

1

t

t

tt

tt

t

t

t

t

TD

TD =++===

××

……………………… (4.19)

From equation 4.15, there is:

)(2

1

2

1

VoVin

Vo

t

t

TD

TD

−==

××

…………..……………………... (4.20)

With this control approach, at light load, the main switch on time and the synchronous

rectifier switch on time are reduced proportional. As a result, at light load, the inductor does not

go into negative and the converter conduction loss is reduced

Figure 4.17 shows the tested power stage. The switches used here are IRF 7805. Input

voltage is 5 V. Output voltage is 2 V. Switching frequency is 300 kHz. The inductance is 340

nH. Compared with Figure 4.10, there is no anti-paralleled schottky diode. In the design, the

critical current is about 4 A. The load changes from 0.2 A to 8 A. Figure 4.18 shows the test

results. The bottom curve shows the results by using conventional control approach, which use

two complementary signals to control main switch and synchronous rectifier respectively. With

this control approach, because its conduction loss is reduced at light load, its light load efficiency

is improved significantly. However, its light load power loss is dominated by gate drive loss of

the two switches. Compared with the first approach, its light load efficiency is lower. The trade

off here is the cost of the schottky diode and the light load efficiency.

121

Ron1

Ron2Vin Vo

Z1

Z2

Vref

Comparator 1Voltage Compensator

VEAD

Logic

Vcc

C R

I1I2

VcCurrentdetectingsignal

Vcri

Currentemulatingnetwork

Figure 4.14 Control function block for fixed frequency control

122

Currentdetectsignal

Vcri

Vgs1

Vgs2

Vc

IL

D*T

(1-D)*T

t2 t1

Figure 4.15 Key waveforms at heavy load

123

Vc

Currentdetectsignal

Vcri

Vgs1

Vgs2

IL

D1*T

D2*T

t21t22 t12

t11

I L∆∆∆∆

t2 t1

Figure 4.16 Key waveforms at light load

124

L=340nH

CControl

IRF7805

IRF7805

Figure 4.17 Testing power stage

(Vin=5V, Vo=2V, fs=300kHz, Io: 0.2A ~8A)

125

3 0

4 0

5 0

6 0

7 0

8 0

9 0

1 0 0

0 1 2 3 4 5 6 7 8Output current (A)

Effi

cenc

y(%

)

Improved DCM+CCM control (w/o disable Ssyn)

Conventional control(CCM)

Improved DCM+CCM control (disable Ssyn)

Figure 4.18 Efficiency test results (including gate driver loss)

126

4.5 Improve VRM light load efficiency: hybrid mode control

Constant frequency control has high efficiency at heavy load when conduction loss

dominates, but low efficiency at light load when switching loss dominates. Variable frequency

control, proposed by Barry Arbetter in [7], results in almost uniform efficiency over the entire

load range. However the efficiency is relatively low at heavy load due to high conduction loss.

Hybrid mode control has fixed frequency at heavy load; after the current is lower than critical

point, the switching frequency is reduced proportionally to the load. By hybrid mode control,

both heavy load and light load efficiency can be optimized. [8].

4.5.1 Disable synchronous rectifier at light load

Figure 4.19 shows one hybrid mode control approach. The synchronous rectifier is shut down

after the load is light load. Before the load is higher than the critical current, the converter

operates in CCM mode at fixed frequency. After the load is lower than the critical current, the

converter operates in DCM mode at variable frequency. Figure 4.20 shows the control function

block, which is constant on time control. During the whole load range, the main switch on time is

kept constant.

Its test circuit is the same as that shown in Figure 4.10. A schottky diode is in anti-

parallel with the synchronous rectifier. Figure 4.21 shows the test results. Compared with fixed

frequency control, its light load efficiency is higher. The reason is that at light load, switching

frequency is reduced, as a result, the gate drive loss of the main switch is reduced. Figure 4.22

shows the switching frequency range. At heavy load, the switching frequency is fixed. At light

load, the switching frequency is proportional to the load.

127

VgsQ1

VgsQ2

I LIo

(a) At heavy load: fixed frequency

VgsQ1

VgsQ2

I L Io

Disabled

(b) At light load: variable frequency

Figure 4.19 Hybrid mode control: disable synchronous rectifier at light load

128

Ron1

Ron2Vin Vo

Z1

Z2

Vref

VEA

Logic

Vcri

VCOMonostableTon

Disable signal

Figure 4.20 Control function block for hybrid mode control:

disable synchronous rectifier at light load

129

Output current (A)

Effi

cien

cy(%

)

30

40

50

6070

80

90

100

0 1 2 3 4 5 6 7 8

Conventional control (CCM, fixed frequency fs = 400kHz)

Variable frequency control (disabled Ssyn)

Fixed frequency (disable Ssyn)

Figure 4.21 Efficiency test results (including gate driver loss)

130

0

5 0

1 0 0

1 5 0

2 0 0

2 5 0

3 0 0

3 5 0

4 0 0

4 5 0

0 2 4 6 8

O u tp u t c u r r e n t (A )

Fre

quen

cy(k

Hz)

Figure 4.22 The switching frequency vs. the load

131

4.5.2 With synchronous rectifier at light load

Figure 4.23 explains the operation. At heavy load, the converter operates in CCM mode

at fixed frequency. At light load, the synchronous rectifier is turned off when the inductor current

goes into negative and the VRM operates in DCM mode at variable frequency. Using the current

emulating network shown in Figure 4.13, the control function block is shown in Figure 4.24.

There is a litter difference between Figure 4.14 and Figure 4.24. In Figure 4.14, the control is

fixed frequency control. In Figure 4.24, the control is constant on time control. There is one more

controlled switch in the current emulating network in Figure 4.24. This switch is used to control

the capacitor C in current emulating network to have constant charge time at variable frequency.

Figure 4.25 shows the key waveforms at heavy load. At heavy load, the converter operates in

CCM mode. Since the load current is higher than the critical current, there is no intersection

between current emulating signal Vc and Vcri1. The synchronous rectifier buck converter

operates at fixed frequency. The main switch on time is controlled by monostable function

output. At heavy load, its operation is similar to the conventional approach, which uses two

complementary signals to control the main switch and synchronous rectifier respectively.

Figure 4.26 shows the key waveforms at light load. When the load changes from heavy

load to light load, the current emulating signal Vc moves down. When the load is equal to the

critical current, the current emulating signal Vc touches Vcri1. Then stop discharging C. Vc is

kept at Vcri. At the same time, the current detecting signal is changed to low level and the

synchronous rectifier is turned off. The converter is forced to operate in DCM mode. Since the

on time of the main switch is constant, its switching frequency is reduced and its change is

proportional to the load.

132

VgsQ1

VgsQ2

ILIo

(a) At heavy load: fixed frequency control

VgsQ1

VgsQ2

IL Io

(b) At light load: variable frequency control

Figure 4.23 Hybrid mode control: with synchronous rectifier at light load

133

Ron1

Ron2Vin Vo

Z1

Z2

Vref

Logic

Vcc

C R

I 1

I 2

VcCurrentdetectingsignal

Vcri

Currentemulatingnetwork

Monostable VCOTon

Figure 4.24 Control function block for hybrid mode control:

with synchronous rectifier at light load

134

Currentdetectsignal

Vcri

Vgs1

Vgs2

Vc

IL

Figure 4.25 Key waveforms at heavy load

135

Vgs1

Vgs2

Vc

Vcri

IL

Currentdetectsignal

Figure 4.26 Key waveforms at light load

136

Output current (A)

Effi

cenc

y(%

)

30

40

50

60

70

80

90

100

0 1 2 3 4 5 6 7 8

Conventional control (CCM, fixed frequency fs = 400kHz)

Variable frequency control with Ssyn

Variable frequency control disable Ssyn

Figure 4.27 Efficiency test results (including gate driver loss)

137

Its test circuit is the same as that shown in Figure 4.17. In the test, the load changes from

0.2 A to 8 A. Figure 4.27 shows the test results. Compared with previous approach, disable

synchronous rectifier, its light load efficiency is higher. The reason is that with this approach,

converter’s light load conduction loss is reduced due to the use of synchronous rectifier. In the

whole range, the converter efficiency is higher than 80%. In fact, with this approach, it is easy to

optimize the converter efficiency at both light load and heavy load. Compared all other

approaches, this approach has the highest light load efficiency.

4.6 Summary

For low-voltage high-current applications, synchronous rectifier technologies are widely

used. However, its light load efficiency is low. To improve its light load efficiency, the

converters have to operate at DCM mode to reduce its conduction loss and at lower switching

frequency to reduce its gate drive loss. In this chapter, several new control approaches, which

utilize the duty cycle signal, are proposed. These approaches can detect inductor current mode

automatically and do not need current sensors. Experimental results verify that these approaches

improve synchronous rectifier buck converter light load efficiency significantly. And the hybrid

mode control with synchronous rectifier at light load has the best result.

138

5 Chapter Five

A Novel High-input-voltage Voltage Regulator Module

------- Push-pull Forward Converter

5.1 Introduction

Most of today’s VRMs draw power from a 5 V output of a silver box. This silver box has

existed for more than two decades. However, its loads, such as microprocessors and memory

chips, keep updating every eighteen months. Since the silver box output can not meet the strict

transient and efficiency requirements from these kinds of loads, the Voltage Regulator Module is

inserted between the loads and the silver box output. In today’s computer, the processor needs a

2.8~3.3V power supply with an 11~15A current capability. In the future, the VRM needs to

provide lower voltage, 1.1 ~ 1.5V with much higher current capability, 100A. It is very possible

that there is more than one VRM in the system. Figure 5.1 shows a trend of computer power

system architecture. Today, for PC application, hybrid power system is used. The 5-V bus needs

to provide power to the microprocessor, the memory chip, the video card, and to the sub bus.

Definitely, this bus voltage is too low for future applications. In the future, a Distributed Power

System (DPS) with high-voltage bus, 12V or 48V, can be the solution for servers’ and

workstations’ power systems. Meanwhile, the high-voltage, high performance VRMs must be

required.

139

Front End

Distribution Bus

AC

AC Silver Box

Hybrid Power System ( HPS)

- Personal computers- low end servers

Centralized Power System ( CPS)- Consuming appliance (video, audio)

Distributed Power System ( DPS)- High end servers- Telecom equipment- Mini computer- Mainframe computers

VRM

VRM

VRM

AC Silver Box

VRMVRM

Distribution Bus(5V)

Figure 5.1 The trend of computer power system architecture

140

5.2 Limitation of today’s approach

Most of today’s VRMs use synchronous rectifier buck topology and are powered from a

silver box 5-V output. Since future VRMs’ outputs are lower and lower, the VRMs’ duty cycle

become very asymmetrical. Figure 5.2 shows the asymmetrical transient response of a

synchronous buck VRM. When the load changes from light load to heavy load, since the

inductor charging voltage, Vin-Vo, is high, the VRM’s step-down voltage drop is small. When

the load changes from heavy load to light load, since the inductor discharging voltage, Vo, is

low, the VRM’s step-up voltage drop is large. This asymmetrical transient response makes the

output filter over-designed. Besides, it is difficult to optimize efficiency in an asymmetrical duty

cycle converter.

Another limitation from today’s approach is the VRM input current slew rate. In today’s

power system, in order to minimize the interaction effect between different loads, the VRM input

current slew rate is required to be smaller than 0.1A/µs. This requirement, actually, is the design

guide for the VRM input filter. During the load change, the output filter needs to provide energy

to the load. At the same time, the input filter needs to keep the input current slew rate smaller

than 0.1A/µs and to provide the energy to the output filter. The energy that should be provided

by the input filter capacitor is shown in Figure 5.3. The shadow area in Figure 5.3(b) decides this

energy. According to this energy, the input filter capacitor can be calculated:

2

2

)(2 VinVinIinSR

PCin o

×∆××> …..………………………… (5.1)

141

(a) Asymmetrical transient response

Vin VinVO VO

(b) Step down: di/dt = (Vin – Vo)/L (c) Step up: di/dt = -Vo/L

Figure 5.2 An asymmetrical transient response due to low output voltage

142

Where, SR(Iin) is the input current slew rate.∆Vin is the input voltage tolerance. Vin is

input voltage. Po is the output power, which approximately is equal to the shadow area in Figure

5.3(b). For future applications, it needs a 13mF input capacitance. In today’s VRMs, there is a

3mF input capacitance, which makes VRMs already very bulky.

A Distributed Power System (DPS) with high-voltage bus can be the solution for future

computer systems. Compared to low voltage (such as 5V bus) distributed system, a high voltage

distributed system is more attractive. In a high voltage distributed system, the transient of the

load end converter will have less effect on the bus voltage, and thus less effect on the other load

end converters. The parasitic components in the power system would also have smaller impacts

in a high voltage distributed system. The conduction loss of the bus is lower, and the

distribution bus is easy to design. One big advantage in the high-voltage bus DPS is that the

VRMs’ input filter size can be reduced significantly. Figure 5.4 shows the results. When input

voltage is 48V, the input capacitance is 14µF. Compared with the 13mF capacitance used in the

5V input voltage, it is one thousand times smaller. Another benefit from the high voltage bus

system is that, by using a transformer, the VRMs can simply adjust their duty cycle to optimize

efficiency and output filter size.

In this chapter, a novel high-input-voltage VRM, a push-pull forward converter that can

be used in high-bus-voltage distributed power systems, is proposed. This converter has high

efficiency, high power density and high performance. As a result, this converter can be packaged

easily as a standard module.

143

Vin Vo

Input Filter Buck Converter Fast Load

Iin IL IO

Cin CO

0.5µH

13mF

1µH

50mF

(a) A VRM designed for future requirement

(Vin=5V, Vo=1.2V, Iload: 0~50A, Slew rate of Iin < 0.1 A/µs, Slew rate of IL < 1A)

t

I in: 0.1 A/µs

I L:1A/µs14A

Charges requiredfrom input cap. forfuture spec.

(b) The energy needs to be provided by input filter capacitor

Figure 5.3 Input filter design

144

1

10

100

1000

10000

100000

1000000

0 10 20 30 40 50

Vin (V)

Cin

(uF

)

Figure 5.4 Input filter capacitor vs. input voltage

145

5.3 A novel high-input-voltage VRM ----- push-pull forward VRM

Figure 5.5 shows the novel high-input-voltage VRM topology t he push-pull forward

converter. In the primary side, the switch and transformer windings are connected alternately in a

circle. A capacitor is connected between either of the two interleaved terminations. The left two

terminations are connected to input and the ground respectively. The two primary windings have

the same turns. The secondary side is the current doubler connection, which cancels both the

switch and output current ripple. This topology has high efficiency and small input current

ripple. Like a buck converter, it is a second-order system. Its control loop design is easy, and its

bandwidth can be very large, which significantly improve the VRM transient response. In

addition, compared with other topologies, this topology is easier to package and to meet future

requirements.

5.3.1 Operation of the push-pull forward converter

Figure 5.6 explains the operation of this converter.

1) t1~ t2:

Switch S1 is turned on, and switch S2 is turned off. The capacitor voltage, Vc, is equal to

the input voltage. When S1 turns on, Vc is applied on winding 2. The input voltage is applied on

winding 1. Actually, in this period, the push-pull forward is like two forward converters in

parallel. Figure 5.7 shows the equivalent operation circuit.

The current in winding 1 flows through Vin, S1, T1 and the ground. It transfers energy

from input to output. The equivalent circuit structure is like a forward converter. I1 is equal to:

146

S1 S3

S4

VoVin

S2

C

T1

T2

I1

I2

IL1

IL2

Iin

L1

L2

Imag/2

Imag/2

Io

Figure 5.5 A novel nigh-input-voltage VRMPush-pull forward converter

147

I a

I a

V g s 1

V g s 2

I 1

I 2

I S 1

I in

V x

I S 2

t1 t2 t 3 t 4

V d s( s 1 )

I S 4

I S 3

I L 1

I L 2

I m a g

I o

Figure 5.6 Key operation waveform

148

2

Im

41

ag

n

IoIaI +

×+= ……………………………………. (5.1)

The current in winding 2 flows through C, T2 and S1. It transfers energy from the

capacitor to the output. Its equivalent circuit is also like a forward converter. I2 is equal to:

2

Im

42

ag

n

IoIaI −

×−= ……………………………………. (5.2)

Here, assume the load is a current source, Io. IL1=IL2=Io/2. Ia is the charging current for

the input capacitor, C. Imag is the transformer’s magnetizing current. The current in switch S1,

Is1 is equal to:

agn

IoIs Im

21 +

×= …………………………………………. (5.3)

Since the current of winding 2 flows in the loop of C, T2 and S1, the input current Iin is

equal to the current in T1. Iin is:

2

Im

4

ag

n

IoIaIin +

×+= ………………………………….…. (5.4)

The input current ripple peak to peak value is:

2

Im

4)(

ag

n

IoppIin +

×=− …………………………………. (5.5)

In conventional topologies, like forward or flyback, the input current ripple peak to peak

value is:

agn

IoppIin Im)*( +=− ………………………………….. (5.6)

149

L 1

L 2

Q 1

Q 2

Io

I1= Ia + Io /2 n

I2= Ia - Io /2 n

S 1V in

S 1+_

V c = V in

E q u iv a le n tc ir c u i t

S 1

S 2

V x

I2

I1L 1

L 2

Q 1

Q 2

IoV C

_

+

n

n1

Figure 5.7 Equivalent operating circuit during t1 ~ t2.

Like two forward converters in parallel.

150

Comparing equations 5.5 and 5.6, the input current ripple value in a flyback or forward

converter is at least two times larger than that in a push-pull forward converter. But the input

current ripple frequency is only half of that in a push-pull forward converter. As a result, the

push-pull forward can use smaller input filter.

During this period, the transformer magnetizing current is charged up and is distributed

evenly in windings T1 and T2. In the secondary, the current doubler structure is used. S3 is

turned off and S4 is turned on. Inductor current IL1 flows through inductor L1, the output

capacitor, S4 and the transformer secondary winding. Switching current IS4 is the sum of IL1

and IL2. The current ripple is canceled in IS4. The output current is also the sum of IL1 and IL2.

Its ripple is canceled too.

2) t2 ~t3:

In this period, the transformer leakage inductor current is discharged. From equations 5.1

and 5.2, during t1 ~ t2, I1 is always larger than I2. After S1 turns off, since I1 is larger than I2,

the body diode of S2 is forced to turn on to continue the leakage inductor current. During this

period, the input voltage is applied to winding 2 to discharge the leakage inductor current of

winding 2, and Vc is applied to winding 1 to discharge the leakage inductor current of winding1.

After the I1 and I2 reach the same value (Ia), this period ends. During the whole period, Vds of

switch S1 is clamped to twice the input voltages. The operation in this period is shown in Figure

5.7.

151

S 1

S 2

C

I 1

I 2

V d s ( s 1 )+ _

V x

V in

Figure 5.8 t2 ~ t3: discharge transformer leakage inductor current

152

3) t3 ~ t4:

In this period, both switches S1 and S2 are turned off. Current Ia flows from Vin, through

winding T2, C and winding T1, to the ground. Capacitor C is charged during this period. In the

secondary, both switch S3 and S4 are turned on. The magnetizing current freewheels through the

transformer secondary winding. The voltage on the transformer winding is zero. Figure 5.8

shows the circuit operation in this period. Switch current IS3 and IS4 are:

nagI

I LS ×+= Im

21

3 ………………………………………. (5.7)

nagI

I LS ×−= Im

22

4 ………………………………………. (5.8)

After t4, S2 is turned on and S4 is turned off. The circuit operation is symmetrical.

5.3.2 ZVS operation

ZVS operation can reduce converter turn on switching loss. There are several approaches

which can make the push-pull forward converter operate at a ZVS condition. From Equation 5.3,

before S1 turns on, if Io/(2*n) is smaller than the magnetizing current, the switch current, IS1,

will go negative. At this moment, if S3 is turned off, IS1 will flow through the body diode of

switch S1 and ZVS operation can be achieved.

Usually, a self-driven technique is used to drive the secondary synchronous rectifier. In

this case, the synchronous rectifier is tuned off after the primary switch is turned on. In order to

realize ZVS operation, secondary synchronous rectifiers need to use the external gate drive to

153

S 1

S 2

V x

I2

I1

L 1

L 2

S 3

S 4

Io

Figure 5.9 t3 ~ t4: freewheeling time

154

turn off the synchronous rectifier before the primary switch is turned on. For example,

before S1 is turned on, S3 should be turned off. And before S2 turned on, S4 should be turned

off. This can provide a short time to let current flow through the switch body diode and discharge

the switch output capacitor before the switch is turned on.

The first approach is to use a small output filter inductor to reduce the load current part in

Equation 5.3. Figure 5.10 shows the ZVS operation. Actually, it is like a QSW converter, which

utilizes large ripple current to force current to go negative before the primary switch is turned on.

However, in a QSW converter, due to the large current ripple, the converter efficiency is reduced

significantly. In a push-pull forward converter, the synchronous rectifier does not see such a

large ripple since the current flowing through it is the sum of the two-inductor current. On other

hand, the primary switch only see the reduced current, Io/(2*n). As a result, the conduction loss

increase is not much compared to when a large inductance is used.

The second approach is to use a small transformer magnetizing inductance to reduce the

magnetizing current part in equation 5.3. This is a very traditional approach that is widely used in

active clamp forward and asymmetrical half bridge. Figure 5.11 shows the ZVS operation. The

third approach is to reduce both transformer magnetizing inductance and output filter inductance.

Actually, all these approaches are a trade off between the frequency-related loss, which includes

gate drive loss and switching loss of primary switch, and conduction loss of both primary and

secondary switches. In a 48-V or lower voltage bus system, if the converter operates a frequency

lower than 500kHz, based on today’s device technology, conduction loss dominates the loss

budget.

155

Ia

Vgs2

Vgs1

IaI1

I2

IL1

IL2

Imag

IS1

Vds(s1)

Vgs3

Vgs4

Figure 5.10 Achieve ZVS by utilizing small output filter inductance

156

Ia

V gs2

V gs1

IaI1

I2

I L1

I L2

I m ag

IS1

V ds(s1)

V gs3

V gs4

Figure 5.11 Achieve ZVS by utilizing small magnetizing inductance

157

5.4 Compared with other topologies

(a) Compared push-pull converter

Figure 5.12 shows a push-pull converter. Due to the leakage inductance, the primary

switch has a large voltage spike after it is turned off. In a push-pull forward converter, there is a

path to discharge the leakage inductor current and its switch voltage is clamped at two times

input voltage. Compared with the push-pull forward converter, push-pull converter needs higher

voltage rating primary switch and snubber, which make it expensive and low efficiency. Besides

the leakage inductance problem, push-pull converter needs to sense the input current to balance

the transformer flux, which is balanced automatically in the push-pull forward converter by its

input capacitor. On the other hand, the input current ripple of a push-pull converter is

proportional to Io/(2*n). However, in a push-pull forward converter, its input current ripple is

proportional to Io/(4*n).

(b) Compared with half bridge converter

Figure 5.13(a) shows a symmetrical half bridge converter. Figure 5.13(b) shows an

asymmetrical half bridge converter. Half bridge topology is used widely in today’s power

electronics industry, since it has low switch voltage stress and high efficiency. But in 48-V or

lower voltage, like 24-V or 12-V, bus system, its efficiency is lower than that of the push-pull

converter. This is because of its low turns ratio. For example, if the bus voltage is 12V and the

load is 1.2V ~ 1.65V, the turns ratio in a symmetrical half bridge or an asymmetrical half bridge

has to be 1 to 1. For future microprocessors, the load current can be as high as 100A. As a result,

its primary conduction loss is very large. For the same requirement, push-pull forward converter

158

S1

S2

S3

S4

Vo

Figure 5.12 Push-pull converter

159

S1

VinS3

S4S2

(a) Symmetrical Half bridge

S1

VinS3

S4

Cin

S2C

(b) Asymmetrical half bridge

Figure 5.13 Half bridge converter

160

C

L

Q1

Q2

Q3Ccl

Vin

Figure 5.14 Active clamp forward converter

161

VinCo

Leakage Inductor(Reduced)

Q1 Q2

Figure 5.15 Flyback converter

162

can have a 3 to 1 turns ratio, which dramatically reduces the primary conduction loss and makes

it more suitable to a low-voltage high-current data processing power system. Like the push-pull

converter, the half bridge topology has two times the input current ripple as the push-pull

forward converter.

(c) Compared with forward and flyback converters

Figure 5.14 shows an active-clamp forward converter. In its secondary, the output

inductor current flows through the synchronous rectifier. Since there is only a single channel

inductor, the switch current ripple cannot be canceled. For future microprocessor applications,

fast transient response is required and the small output filter inductor is more desirable. As a

result, both the switch current ripple and output current ripple are very large. Also the secondary

conduction loss is very large. Figure 5.15 shows a flyback converter. It needs a high voltage-

rating switch due to the leakage inductance. On the other hand, since both its output and input

current is pulse, large filter capacitance is needed. Compared with the push-pull forward

converter, the input current ripple of both the forward and flyback converters is proportional to

Io/n, which is four times larger.

(d) Compared with flyback-forward converter

Figure 4.16 shows a flyback-forward converter. This topology has high efficiency. One

drawback of this topology is that it is a fourth-order system, which makes its control design very

difficult and makes its close loop bandwidth very low to ensure the system stable. Figure 5.17

shows its open-loop control to output body plot. This problem also exists in asymmetrical half

bridge. Another disadvantage is its slow transient response. During the transient response, this

topology can cause a transformer saturation problem and can induce the diode reverse recovery

163

current problem, which in turn increases switch stress. The push-pull forward converter is a

second-order system. Figure 5.18 shows the open-loop control to output body plot of a push-pull

converter. Its control is very easy. Like a buck converter, it can have very large close-loop

crossover frequency. On the other hand, since the transformer magnetizing inductor is charged

and discharged symmetrically in every switching cycle, there the same problems that occur in the

flyback-forward converter during the load transient are not present. The push-pull converter

should have faster transient response. As a result, it needs smaller output filter capacitance and

higher power density.

5.5 Experimental evaluation

Figure 4.19 shows the test circuit. In the push-pull forward converter design, the

integrated magnetic structure [7] is used. The integrated magnetic structure is shown in Figure

5.20. The three transformer windings and two-output inductor are integrated on one magnetic

core. Figure 5.21 shows the integrated magnetic design. EI core is used and secondary is one

turn. The detail operation of this structure is described in paper [7].

Figures 5.22 shows the efficiency of the push-pull forward converter designed for 12V

input voltage. In this design, two IRL3103D1 are used as primary switches and total four

MTP75N03, every two in parallel, are used as synchronous rectifiers. Its transformer turns ratio

is 3 to1. The secondary is one turn. The magnetic core uses Philips 3F3 E32. The output filter

inductance is 400nH each. Output filter capacitors use 4-mF OSCON capacitors. The input

164

S1

S2

+_

S3

S4

Vo

Figure 5.16 Flyback forward converter

165

Gain

Phase

Figure 5.17 Open loop control to output body plot of forward flyback

(Fourth-order system)

166

Gain

Phase

Figure 5.18 Open loop control to output body plot of push pull forward.

(Second-order System)

167

capacitor, C, uses a 10-µF ceramic capacitor. The push-pull forward converter can achieve 81%

efficiency at1.2V@60Aoutput.

Figures 5.23 shows the efficiency of the push-pull forward converter designed for 48V

input voltage. In this design, two IRF630 are used as primary switches and a total of four

MTP75N03s, every two in parallel, are used as synchronous rectifiers. The magnetic core uses

Philips 3F3 E32. The output filter inductance is 400nH each. The input capacitor, C, uses a 10-

µF ceramic capacitor. Its transformer turns ratio is 12 to 1. This push-pull forward converter can

achieve 83.6% efficiency at1.2V@60Aoutput and 81% at 1.2V@70A. Figure 5.24 shows the

Vds waveform of the primary switches. The voltage peak is always clamped to two times the

input voltages.

In order to compare the push-pull converter with half bridge converters, asymmetrical

and symmetrical half bridge, these three converters are built. For the purpose of comparison, all

three converters are designed for 48V input with3.3V@30A output. The design of the

asymmetrical and the symmetrical half bridge is shown in Figure 5.25 and Figure 5.26. For both

symmetrical and asymmetrical half bridges, the transformer turns ratio is 3 to 1. Two IRF540N

are used as primary switches, and a total of four MTP75N03s, every two in parallel, are used as

synchronous rectifiers. The design of the push-pull forward is shown in 5.27. For the push-pull

forward converter, the transformer turns ratio is 6 to 1. Two IRF3315 are used as primary

switches, and a total of four MTP75N03s, every two in parallel, are used as synchronous

rectifiers. Figure 5.28 shows the efficiency comparison of the push-pull forward converter, and

the symmetrical and asymmetrical half bridge converters. Due to smaller primary conduction

168

Figure 5.19 Test set up

169

Vin T3

T2

L1

L2

T1

+-

+ -

Vin

Q1

Q2

Q3

Q4

C

c

d

ea

a'b

b'

Figure 5.20 Integrated magnetic structure

170

Primary Winding EI Core Secondary Winding

Figure 5.21 Integrated magnetic design

171

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0 20 40 60 80

Load (A)

Eff

Vo=1.65

Vo=1.2

Figure 5.22 Efficiency of push-pull forward (Vin=12V, fs=100kHz)

(Secondary totally uses four MTP75N03DHL; primary side uses two IRL3103D1)

172

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0 10 20 30 40 50 60 70 80

Load

Eff

Figure 5.23 Efficiency of push-pull forward (Vin=48V, Vo =1.2V, fs=100kHz)

(Secondary totally uses four MTP75N03DHL; primary side uses two IRF630)

173

Vgs

Vx

10V/div

Figure 5.24 Vds waveform of primary switch (Vin = 12V, Fs = 100kHz)

174

Q1

VinQ3

Q4

Cin

Q2C1

Q1, Q2:IRF 540N

Q3, Q4:MTP75N03 *

2 for each

Transformer:Philips PlanarCore E22/6/16

3:1

9.4u

260nH

260nH

4m

Figure 5.25 Design of the asymmetrical half bridge

175

Q1

VinQ3

Q4Q2

Q1, Q2:IRF 540N

Q3, Q4:MTP75N03 *

2 for each

4.7u

4.7u

4m

260nH

260nH

Transformer:Philips PlanarCore E22/6/16

3:1

Figure 5.26 Design of the symmetrical half bridge

176

Q1

Vin

Q3

Q4

4.7u

Q2

260nH

260nH

4m

Q1, Q2:

IRF 3315Q3, Q4:

MTP75N03 *2 for each

Transformer:Philips PlanarCore E22/6/16

6:1

Figure 5.27 Design of push-pull forward converter

177

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

0 5 10 15 20 25 30 35

Push-pull Forward

AHB

SHB

Load

EFF

Figure 5.28 Efficiency comparison of push-pull forward, symmetrical half bridge

and asymmetrical half bridge. (Vin=48V, Vo=3.3V, fs=200kHz)

178

loss, the push-pull forward converter can achieve 92% efficiency at 30A load, which is 2 ~ 3%

higher than those of half bridges.

5.6 A Novel Non-isolated High -voltage VRM Topology Improved Center Tap Inductor

Structure

Center tap inductor structure is another approach to adjust VRM duty cycle. Figure 5.29

shows a center-tapped inductor buck converter. With center-tapped inductor, the voltage stress

on synchronous rectifier is reduced to:

OOin

QDS Vn

VVV +

−=2, …….…………………………. (5.9)

In conventional synchronous rectifier buck converter, the voltage stress is Vin. By

reducting the voltage stress, the synchronous rectifier’s switching loss is reduced. Figure 4.30

shows a modified version. The center-tapped inductor is separated. The first part is in srise with

top switch and is moved to the front of the top switch. The second part of the center-tapped

inductor is in series with the rectifier. The operation of the modified version is the same as that

shown in Figure 5.29. The difference is that, in the modified version, it is not necessary to use

isolated gate drive for top switch.

The disadvantage of the center-tapped inductor structure is its lage voltage spike induced

by the leakage inductance. To overcome this problem, a novel lossless snubber is proposed in

Figure 5.31. The operation of the lossless snubber is smiliar to that of push-pull forward. The

advantages of this technique are: 1) volatge spike is reduced; 2) efficiency is improved; 3) input

current ripple is reduced. The disantage is its pulsing out current. Figure 5.32 shows the test set

up. In order to reduce cost, scottky is used to replace the synchronous rectifier. In the test,

179

Highinput

voltage

L

Co

Q1

Q2

n:1

IL1 IL2

(a)Center-tapped inductor buck converter

I L 1

V d s( Q 2 )

I L 2

(b) Key waveforms

Figure 5.29 Center-tapped inductor buck converetr

180

Highinput

voltage

CoQ1

Q2

n

1

Figure 5.30 Improved center-tapped buck converter

181

Highinput

voltage

CoQ1

n

D

n

Figure 5.31 Improved center-tapped inductor buck converter with a novel lossless sunbber

182

CoQ1(IRL3103D1)

n=3

D(95SQ015)

n=3

Vx 1Vin=12V

(a) Test set up

(b) Vx (without snubber) (c) Vx (with the lossless snubber)

Figure 5.32 Experimental test

183

0.78

0.79

0.8

0.81

0.82

0.83

0.84

0.85

0 2 4 6 8 10 12

Load (A)

EF

F

Vo=2.1V

Vo=1.65V

Figure 5.33 Efficiency results

184

IRL3103D1 is used as top switch, whose Rdson is 13 mΩ. Schottky, 95SQ019, is used as

rectifier. Compared with the non-snubber center-tapped inductor structure, the voltage spike is

reduced significantly. Figure 5.33 shows the efficiency results. The novel topology can achieve

79% efficiency at1.65Vo@10Aand 81.5% at2.1Vo@10A.

5.7 Summary

The proposed high-input-voltage VRM topology can achieve high efficiency. Compared

with conventional high voltage VRM topologies, it has small input and output current ripple, low

device stress and high efficiency. And it does not have a leakage inductor problem. Since it is

only a second-order system, this topology can have fast transient response with small filter

inductance and capacitance. In addition, its transformer and inductors can be integrated easily.

Plusing with small filter capacitance and high efficiency, very high power density can be

achieved. As a result, compared with conventional high-input-voltage VRM topologies, this

topology is cost effective and has high performance.

185

6 Chapter Six

Future VRMs and Conclusions

Future generations of microprocessors are expected to operate at a much lower voltage,

1.2-2 V, a much higher current, 50-100A and to operate at a clock rate above 1 GHz. The future

generation of Voltage Regulator Modules (VRM) has to be improved dramatically to meet future

challenges, such as faster transient slew rate, tighter voltage tolerance and higher conversion

efficiency. Furthermore, there is also a strong need for a significantly higher power density, with

much-reduced capacitor and inductor size, suitable for integration with the processor.

6.1 High frequency operation

In order to develop low-cost, high efficiency, low profile, high-power density, fast

transient response VRM modules for future generation microprocessor loads, high operating

frequency is much more desirable. Figure 6.1 shows the transient response of an interleaved

QSW VRM when it operates at 1 MHz. Obviously, the voltage spike is reduced significantly.

VRM density also is improved. Figure 6.2 shows the inductance and capacitance needed in an

interleaved QSW VRM when it operates at high switching frequency. At 10 MHz, the inductance

needed is only 9.25 nH and the capacitance needed is only 5.26µF. With such small inductance

and capacitance, very high power density VRMs can be achieved and energy storage costs can be

reduced dramatically.

186

1% Vo

Vo

Figure 6.1 Transient response of interleaved QSW

(Vin=5V, Vo=2v, fs=1MHz)

187

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E+00 2.00E+06 4.00E+06 6.00E+06 8.00E+06 1.00E+07

Frequency

9.25nH

(a) Inductance needed vs. frequency

Frequency

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0.00E+00 2.00E+06 4.00E+06 6.00E+06 8.00E+06 1.00E+07

5.26µF

(b) Capacitance needed vs. frequency

Figure 6.2 Inductance and capacitance needed in interleaved QSW VRM topology

at high operating frequency

188

η=80%

20 40 60 80 1000.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

20 40 60 80 1000.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Eff

Load(A)

fs =300 kHz

fs =1 MHz

fs =10 MHz

Figure 6.3 VRM efficiency based on today’s device

(Vin=5V, Vo=2V, Switches: 5 IRL3803 in parallel)

189

Due to today’s device technology, most VRMs operating frequency are lower than 300

kHz. With today’s device technology, VRM efficiency is shown in Figure 2.28. At 10 MHz,

VRM will only have 40% efficiency. This efficiency makes thermal management and packaging

very difficult. In future VRMs, the power device must have smaller FOM value (<100(mΩ ×

nC)) and lower miller charge.

6.2 Advanced power device technologies

By taking advantage of the VLSI technology available to produce low voltage devices

with a lateral structure, the substrate resistance and the Miller capacitance can be virtually

eliminated. The drain-to-source capacitance also is reduced significantly. For future

applications, lateral devices with lower voltage ratings and lower figures of merit are key to

improving the circuit efficiency and to reducing the size and weight of the VRM. Figure 6.4

shows the difference between a vertical DMOS and the proposed LDD MOSFET on SOI

structure. With improved device technology, for example SOI LDDMOS technology [4], future

VRM efficiency will be higher than 90% at operating frequency of several MHz. Table 6.1

shows the VRM efficiency comparison based on today’s device technology and improved

LDDMOS technology. In CPES, Professor Alex Q. Huang and Nick Sun are working the

advanced device structure.

190

n+ substrate

n

p

n+p+

S G

D

(a)

S G D

n+ p n n+

p-

(b)

Today’s Device VDMOS Future Device SOI LDDMOS

Figure 6.4 Advanced power device technology

191

Table 6.1 VRM Efficiency Comparison

Optimized Efficiency

For Interleaved QSW VRMVin=5V,

Vo=2V

BV

(V)

FOM

(mΩ*nC) 300kHz 1 MHz 10MHz

LDDMOS 10 77 95% 91% 88%

Today’s

Device

30 473 87% 79% 60%

192

6.3 Advanced integration packaging technologies

To minimize the effect of the interconnection parasitic, an innovation design with

possible integration of the VRM and the processor is key to meet the ever increasing demand of

processor performance and speed.

With advanced integrated magnetic technologies, shown in Figure 6.5, the integration of

the VRM with the processor can take either a hybrid or monolithic approach. With LDD device

technology, the VRM can be made as a silicon chip with all the control functions. Figure 6.6

shows one design example. Professor Alex Q. Huang and Nick Sun are working on this. Figure

6.7 shows an integration-packaging example. Several VRM chips can be put in parallel and be

mounted close to the microprocessor on the same cartridge. Ceramic capacitors with small ESR

and ESL can be used as the output capacitors and be placed on the PCB board next to the

processor. By connecting the output of the VRM and the power input of the processor via a path

through a magnetic material sheet, the small output inductor also can be achieved. With this kind

of packaging approach, the effect of the interconnection parasitics can be minimized.

193

Magnetic Layer

Copper LayerA B C D

MagneticPlate Insulator

CopperWinding Hole

A B C D

L1L2

L3

L4

a) Matrix Inductor b) Film Inductor

Figure 6.5 Advanced integrated magnetic technology

194

Top Switch

Bottom Switch

4mm

2mm

topdriver

bottomdriver

Figure 6.6 VRM chip design

195

Magnetic layer

Heat Sink

processorcapVRM

PCB Laminated

VRM

Insulation layer

input capoutput cap

Magnetic layer(a)

(b)

Processor

Figure 6.7 Advanced packaging technology

(a) 3-D View (b) Side View

196

6.4 Advanced high-input-voltage VRM topologies

For future high voltage computer power systems, advanced high power density and high-

efficiency and fast-transient VRM topologies are required. Pitleong Wong [8] proposed a

candidate topology for future applications, which is shown in Figure 6.8. The front part is DC

transformer. The following part is an interleaved QSW structure. With this kind of structure, the

high-voltage VRM can have very fast transient response. Actually, for a different power system,

the requirement for the VRM is different. There are DC bus systems and AC bus systems. There

are still many technical issues.

197

S1

S2

S3

S4

S5

S6+

_

_

+

S7

S8

DC Transformer Interleaving QSW

48V

Figure 6.8 Candidate high-input-voltage VRM topology

198

6.5 Conclusions

Low-voltage power management issues are becoming increasingly more critical in state-

of-the-art computing systems. The current generation of high-speed CMOS processors (e.g.

Alpha, Pentium, Power PC) operate at above 300MHz with 2.5 to 3.3 V output voltage. Future

processors will be designed with even lower logic voltages down to 1.1~1.5 V, and an increase

in current demand from 13 A to 50~100 A. Meanwhile, the operating frequency will increase

above 1 GHz. For future generation processors, the high transient current-slew-rate (several

Amperes per Nanosecond) will result in significant voltage transient. To ensure proper operation,

a more stringent voltage regulation from 5% to 2% regulation is imposed. These demands in

turn require a special power supply, voltage regulator module (VRM), to provide lower voltages

with higher current and fast transient response capability for microprocessors. This dissertation

proposes and verifies several new technologies for this low-voltage power management

application.

The multi-module interleaved quasi-square-wave (QSW) VRM topology presented in

Chapter 2 achieves a very fast transient response and a very high power density. With this

technique, both the VRM input current ripple and output current ripple are cancelled. Both the

VRM input and output filter sizes can be reduced dramatically. Experimental results prove that

this technique can improve power density by six times and improve transient speed by four times

as compared to conventional VRM designs. The interleaved QSW topology is well-suited for

future microprocessor applications, where the transient response and converter size are primary

concerns.

The current sensing and sharing technique developed in Chapter 3 can be implemented

simply without current transformers and current shunts. There are many advantages to this

199

technique. First, the difference of MOSFET on-resistance and inductance value has no effect on

current sharing. Second, good current sharing results can be easily achieved. Third, control

design and the implementation of this technique are simple. Fourth, the current sensing approach

is inexpensive and has no effect on converter efficiency. The R and C in the sensing network do

not have to be precise. Fifth, with this technique, VRMs have a fast transient response, a high

power density, and high efficiency. Sixth, this technique provides for the utilization of the ratio

of parasitics, not their absolute value. This is easy to control in manufacturing. Seventh, this

technique can be widely used without topology limitations. And eighth, this technique can be

integrated easily into an IC chip.

The techniques for improving VRM light load efficiency are discussed in Chapter 4. By

utilizing the duty cycle signal, these techniques can detect the inductor current mode

automatically and do not need current sensors. Experimental results verify that these approaches

significantly improve synchronous rectifier buck converter light-load efficiency. The hybrid

mode control with a synchronous rectifier at light load achieves the best result.

The high-input-voltage VRM topology, push-pull forward converter that can be used in

high-bus-voltage distributed power systems is investigated in Chapter 5. This topology can

achieve a high efficiency. Compared with conventional high-voltage VRM topologies, it has

small input and output current ripples, low device stress and high efficiency. Besides, one of its

significant advantages is that it does not have a leakage inductor problem. Since it is only a

second-order system, this topology can have a fast transient response with a small filter

inductance and capacitance. In addition, its transformer and inductors can be easily integrated. In

addition with a small filter capacitance and high efficiency, a very high power density can be

200

achieved. As a result, compared with conventional high-input-voltage VRM topologies, this

topology is cost-effective and has a high performance.

201

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Vita

The author, Xunwei Zhou, was born in Hangzhou, Zhejiang, China on July 12th,

1969. He received his B. S. and M. S. degrees from Zhejiang University, China in 1991

and 1994 respectively, both in electrical engineering.

Since 1995, he has been with Virginia Power Electronics Center at Virginia

Polytechnic Institute and State University. His research work has been concentrated on

low-voltage high-current DC/DC converters, soft-switching technique, high-frequency

power conversion and power factor correction technology.

The author is a member of IEEE Power Electronics Society.