Low-Voltage, Low-Power CMOS OperationTransconductance Amplifier with Rail-to-Rail

Differential Input Range

Trung-Kien Nguyen Sang-Gug LeeInformation and Communications University Information and Communications University

119 Munjiro, Yuseong-gu, Daejeon, South Korea 119 Munjiro, Yuseong-gu, Daejeon, South Korea

Abstract-This paper presents a new configuration for linear proposed transconductor is described. The experimentalMOS operation transconductance amplifier (OTA) based on a results and discussions are presented in Section III. Thestandard 0.25 g CMOS technology. The proposed circuit proposed transconductor has been fabricated in a standardcombines two previously reported linearization techniques: 0.25 tm CMOS technology, using 1.25 V supply. And then,source degeneration using MOS transistor and class AB the conclusion is presented in Section IV.linearization. Measured results show that the proposed circuitprovides rail-to-rail differential input range. Total harmonicdistortion of the proposed circuit is -60 dB at 5 MHz for 0.6- II. CIRCUIT DESIGNVpp differential input voltage while dissipating only 25 gW A. Circuit topologiesfor linear CMOS OTAfrom 1.25 V supply.

In this section, we will review some linearizationtechniques that are reported in literature. The simplest

I. INTRODUCTION technique to linearize the transfer characteristic of the MOSThe trend toward lower operating supply voltages and transconductor is the one with source degeneration using

lower power consumption in mixed signal ICs has some resistors as shows in Fig. 1.strong motivations: 1) portable equipment capable of the voperating with minimum number of battery cells to reduce Vddvolume and weight, 2) voltage limitations resulted fromsmaller feature sizes ofmodem IC technology, and 3) longer 'outi ,out2operating periods without battery recharging or replacement.

The operational transconductance amplifier (OTA) is a Ml M2 Hbasic building block in analog circuit applications including Vin+ vincontinuous-time filter, data converter, variable gainnRamplifiers and other interface circuit [1]-[3]. In many of Rthese applications, OTA at the input determines the overall ss ss

linearity of the system [4]. As device sizes, supply voltageand power consumption are scaled down to achieve higher Fig. 1 MOS transconductor with resistive degenerationoperating-speeds, obtaining high linearity with reasonable The linearization is achieved because now the outputsignal levels becomes ever challenging. Several circuittechniques have been proposed in literature to improve the current lou = - 'ou2 becomeslinearity ofMOS transconductors. The linearization methods 1 (V -Id tR)2 K (include: cross-coupling of multiple differential pairs, [5]-[7], iout = - (J'L -I0UR) I 1adapting biasing [8], source degeneration (using resistor or 2 ss

transistor) [9], [10], shift level biasing [1 1], series connection whereof multiple differential pairs [12], class AB configuration 1 W[13], and pseudodifferrential stages (using transistors in the 2 K = 2 Ltriode region or in saturation) [14], [15]. This paper presentsan improved linear MOS transconductor that uses both the * Vtn and Vid are the threshold voltage ofNMOS andsource degeneration using MOS transistor and class AB the differential input voltage respectively.configuration approaches. Section II reviews these twolinearization techniques and the configuration of the newly

0-7803-9390-2/06/$20.00 ©)2006 IEEE 1639 ISCAS 2006

* W and L are the width and length of the transistor. Another topology to achieve highly linear MOSI,, and R are the bias current and degeneration transconductance with low supply voltage is reported in [13].resistor respectively. The idea is to use class AB V-I linearization technique which

The transconductance Gm is is shown in Fig. 3. In this topology, the transistors M3, M4,M5, M6 are biased in triode region, therefore the voltage at

GC 9. (2) drain of M1, M2 would be very close to supply voltage andm 1 + gmR the source voltage can be as low as several tens mV and can

where g,m is the transconductance of transistor M1, M2 ( here be neglected [13]. The transfer function is given bywe assume that MI, M2 are matched) KK(VI-L/)(V1 -2V)

Notice that in (1), the nonlinear term now depends on out - M7 M8 2Kp(Vb - Vt) idVid - oUtR rather than Vid. When R >> 1/gm the non-linearterm becomes zero so high linearity can be obtained. The where Kn, K, Kp are transconductance parameter ofNMOSsdisadvantage of this configuration is the large resistor value, (M1, M2), (M7, M8), and PMOS (M3, W4), respectively. Vtp iswhich is needed to achieve a widely linear input range. Since threshold voltage of PMOS. Vd = V,,+ - Vf-,IVb = Vdd -Vbin this case Gm - 1/R, the obtained transconductance is V V + V - 2V and V V-V-V -V As canrestricted by the value of degeneration resistor. If we would / 2 s,M7,M8 ' 1 2 - d,M3 d,M4like to obtain high transconductance with higher linearity R be seen from (4) that the output current Iout is a function ofshould be reduced while g. should be increased. High gm the differential input voltage Vid. V1 and V2 are very close torequires higher power consumption. Moreover, this Vdd, thus V1+ V2 is almost constant and its nonlinear effect cantechnique eliminates the tenability of the Gm is set by the be ignored. However, with the supply voltage lower than 2degeneration resistor. V, the nonlinear term can be occurred [13]

The second technique is also using source degeneration Vddbut replacing the degeneration resistor with two MOStransistors operating in the triode region that is shown inFig.2 [9]. Qualitatively, when the amplitude of the input VbDsignal rises, the triode-mode degeneration MOS resistors willbe more biased such that the synthesized resistance is reduce. MThis allows less degeneration and results in more Gm of thedifferential pair to compensate for the drop of Gm. As outiV Iout2discussed in [9], the size ratio of M1/M3 = 6.7 is used to l Dt| loM2|obtain the maximally linear behavior. The quantitative Vin+ in-

relationship is given by

louti lout2 Mi1i Mg M5 M6 Mio M12

ED>- MIl M2 ---cI Fig. 3 Class AB Transconductor [13]Vin+ 1 Sl Vin-

B. Proposed Transconductance AmplifierAs discussed in [13], when the supply voltage is reduced

below 2V the nonlinear can be increased due to the value ofV1 + V2 is not constant. In this design, since we use supplyvoltage of 1.25V, therefore, the nonlinearity becomes more

Fig. 2. Transconductor with source degeneration using MOS transistors [9] significant. To resolve this problem, this paper proposes thenew transconductor stage configuration that combines the

4K1Kn3 (VGSI - Vtn )f two techniques discussed above: source degeneration using(4K +K ) /E (3) MOS transistor and class AB linearization. The proposed V-I(4n3 + Knl) nl circuit is shown in Fig. 4. In this topology, transistors M3 -

As can be seen in (3), the transconductance can be tuned M8 are operated in triode region. Now, the small-signalby changing Iss. However the nonlinearity is up to 1% for drain-source resistance of M7, M8 is given by [17]'out I IS . In some filtering application it is required to have 1better linearity in order to achieve a total harmonic distortion rdS7 = rdS8=(5(TUD) of-60 dB or less [16] 2K"7 (V(; ^- f,)(5

The small-signal source resistance of WI1, WI2 is

1640

1 proposed circuit shows widely linear behavior over the fullr =r = (6) input voltage range (rail-to-rail) compare to all the other

nKl1 (GS~1 t~n) ones. The total harmonic distortion (THD) of the output

In order to understand how the varying triode transistors differential current versus the amplitude of the input voltagehelp to improve the linearity ofthis circuit, let us start with a for three topologies is plotted in Fig. 6. Once can be seen insmall differential input signal. Qualitatively, assume that if Fig. 6, the proposed OTA achieves approximately -60 dB atthe amplitude of V,n± and Vn is increased, which will reduce 5 MHz for 0.6-Vpp differential input voltage. The obtainedthe value of V1+ V2 (due to saturation in V1 or V2) therefore result is lower than other linearization techniques. Thethe value of V1+ V2 is no longer constant for large input measured DC characteristics are shown in Fig. 7. Thesignal. From (4) as discussed before the nonlinear cannot be transconductance plot has been obtained by differentiatingneglected. To alleviate this reduction for large input signals, the measured output V-I characteristic. From Fig. 7 we canthe gates of M7 and M8 being connected to the input signals see that the transconductance of proposed OTA almostas shown in Fig. 4 can be helpful. Now as the input signal is flattens in the input signal range. The microphotographs ofincreased, the small signal resistance of one of the two-triode three topologies are shown in Fig. 8. The active sire are oftransistors in parallel, M7 or M8 is reduced based on (5). This the proposed OTA is 0.1 mm2.reduced resistance tends to boost the value of the V1+ V2 8resulting in a partial canceling of the VI+ V2 reduction.Therefore we can conclude that by using two triode 6 Proposed OTAtransistors M7 and M8, constant current through Ml and M2 OTAin[13]will be forced. The constant current through Ml and M2 4 OTA in [9]/1-means the value of V1+ V2 stays constant that will maintain 2the linearity range. Simulation results show that when the ¢ratio K1IK7 = 5, the proposed topology will give the best 0°linearity. In Fig.4, the V-I characteristic can be tuned by ° -2controlling the bias voltage, Vb, of the load transistors, M3,M4. Another advantage of this topology is that it is easily -4modified to have multiple outputs current by multiplying thesize of transistor M13, M14 while it does not affect the V-Iconversion process -8

Vdd -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7Vin [V]

VbD 1tM3 ltM4 | Fig. 6. The comparison measured V-1 characteristic ofOTA in [9], [13] and

Vbg. 4. Schematicproposed OTA.

mio Mg ~~~~~~~~~~~~~~~~-40V1 V2 -a0- OTA in [9]

asofOTA in [13]

lOSt degneaton cls B rncndco, n h

proposed transconducto5 are f Proposed OTA

-60

-70

Fig. 4. Schematic of the proposed OTA 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

III. RiESULTS AND DisscussioNsVn V

Fig. 7 The comparison measured THD of OTA in [9], [13], and proposedIn order to compare the performance of different circuit

linearization techniques, three circuits: transconductor usingMOS degeneration, class AB transconductor, and the

8 with severe linearity requirement. The proposed circuit hasgood tuning capability and lower THD compared to other

6 approaches. The proposed OTA dissipates only 25 gLW from4 ~~~~~~~~~~~~~~1.25V supply.

2 ~~~~~~~~~~~~~AcKNOWLEDGMENT0

~~~~~~~~~~~~~Thiswork was supported by the SRC/ERC program of0 ~~~~~~~~~~~~~MOST/KOSEF(Intelligent Radio Engineering Center)

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A new linearMOS transconductor, combining twoAJoniWiey al.Soun, beBiM SC1997.TmeFltrfrihlinearization..techniques..has.been.presented...The.topologycan achieve rail-to-rail linear V-I transfer characteristic and it.................................can be used in implementing fully differential GmC filter.............................Frquny ppictin,"IEE ouna f old-taeCicuts vl