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LPC
1700
Ser
ies
2
Con
tent
s
Intro
duct
ion
Ben
chm
arks
Mem
ory
supp
ort
Key
sys
tem
blo
cks
Pow
er m
anag
emen
t
Per
iphe
ral s
uppo
rt
Tool
s &
eco
syst
em
3
Intr
oduc
tion
Ser
ies
Ove
rvie
w
Brid
ging
AR
M7
and
Cor
tex-
M3
Blo
ck D
iagr
am
4
LPC
1700
Ser
ies
Sm
ooth
mig
ratio
n fro
m A
RM
7
Uni
que
Impl
emen
tatio
ns:
–M
PU
–N
VIC
–W
IC–
Flas
h A
ccel
erat
or–
DM
A
Tailo
red
for c
omm
unic
atio
n w
ith 1
5 se
rial i
nter
face
s
Low
pow
er o
pera
tion
Indu
stry
’s F
IRST
Cor
tex-
M3
impl
emen
tatio
n ru
nnin
g at
100
MH
z
5
Serie
s O
verv
iew
6
Brid
ging
Tw
o G
REA
T Fa
mili
es-A
RM
7 &
C
orte
x-M
3
7
LPC
2300
Blo
ckD
iagr
am
8
LPC
1700
Blo
ck D
iagr
am (P
art 1
)
9
Mul
tilay
er A
HB
Bus
Mat
rix
10
Blo
ckD
iagr
am(P
art 2
)
11
Bit-
Ban
d R
egio
ns
http
://w
ww
.arm
.com
s/In
troT
oCor
tex-
M3.
12
LPC
1700
Bit
Ban
d R
egio
ns
1313
Adv
anta
ges
over
Cor
tex
M3
com
petit
ion
100
MH
z C
lock
Spe
ed
Flas
h A
ccel
erat
or fo
r Zer
o-W
ait
Flas
h at
max
clo
ck
Ave
rage
35%
Hig
her P
erfo
rman
ce th
an le
adin
g co
mpe
titor
s (E
EM
BC
)
Sim
ulta
neou
s E
ther
net,
US
B a
nd C
AN
ope
ratio
n w
ithou
t bot
tlene
cks
Fully
-com
plia
nt U
SB
2.0
Mem
ory
Pro
tect
ion
Uni
t (M
PU
)
Em
bedd
ed T
race
Mac
roce
ll (E
TM)
Full
Deb
ug/T
race
Rev
isio
n 2
Cor
tex
core
14
Ben
chm
arks
15
Abo
ut E
EMB
CEm
bedd
ed M
icro
proc
esso
r Ben
chm
ark
Con
sort
ium
Dev
elop
s an
d ce
rtifie
s re
al-w
orld
ben
chm
arks
and
ben
chm
ark
scor
es
–D
esig
ned
to h
elp
desi
gner
s se
lect
the
right
pro
cess
or fo
r the
ir sy
stem
EE
MB
C b
ench
mar
king
repr
esen
ts d
iffer
ent w
orkl
oads
/cap
abili
ties
in:
–A
utom
otiv
e/in
dust
rial –
benc
hmar
ks u
sed
by N
XP fo
r LPC
1700
–C
omm
unic
atio
ns–
Net
wor
king
–C
onsu
mer
–O
ffice
aut
omat
ion
–E
mbe
dded
Jav
a–
Net
wor
k st
orag
e-re
late
d ap
plic
atio
ns
Mem
bers
incl
udin
g le
adin
g se
mic
ondu
ctor
, int
elle
ctua
l pro
perty
, and
co
mpi
ler c
ompa
nies
ww
w.e
embc
.org
1516
Sum
mar
yLP
C17
00 is
the
indu
stry
’s h
ighe
st p
erfo
rman
ce C
orte
x-M
3 M
CU
–B
ased
on
resu
lts E
EM
BC
LPC
1700
exe
cute
s ap
plic
atio
n co
de o
n av
erag
e 35
% fa
ster
than
the
lead
ing
Cor
tex-
M3
com
petit
ors
whe
n ru
nnin
g at
the
sam
e cl
ock
spee
ds
NX
P’s
per
form
ance
adv
anta
ge is
eve
n gr
eate
r at h
ighe
r clo
ck s
peed
s
LPC
1700
has
bee
n ce
rtifie
d by
EE
MB
C a
t 72,
100,
and
120
MH
z
LPC
1700
ope
rate
s hi
gh-b
andw
idth
com
m. p
erip
hera
ls w
ithou
t bo
ttlen
ecks
–E
ther
net,
US
B O
n-Th
e-G
o/H
ost/D
evic
e an
d C
AN
sim
ulta
neou
sly
16
17
EEM
BC
Ben
chm
ark
Res
ults
17
Max
Clo
ck o
f com
petit
or is
72
MH
z (w
ith 2
wai
t sta
tes)
Max
Clo
ckof
com
petit
oris
72M
Hz
(with
2w
aits
tate
s)
18
Mem
ory
Supp
ort
Inte
rnal
Mem
orie
s
Flas
h A
ccel
erat
or
Boo
ting
Mem
ory
Pro
tect
ion
Uni
t (M
PU
)
19
Mem
ory
Supp
ort
20
Mem
ory
Supp
ort E
xpla
ined
On-
chip
Fla
sh–
Max
imum
512
KB
–Ze
ro w
ait-s
tate
per
form
ance
with
Fla
sh A
ccel
erat
or
On-
Chi
p S
RA
M–
Tota
l 64
KB
•32
KB
SR
AM
–ac
cess
ible
by
the
CP
U a
nd D
MA
con
trolle
r on
a hi
gher
sp
eed
bus
•Tw
o ad
ditio
nal 1
6 K
B S
RA
M –
sepa
rate
sla
ve p
ort o
n th
e A
HB
m
ultil
ayer
mat
rix.
•A
llow
s C
PU
and
DM
A a
cces
ses
to b
e sp
read
ove
r 3 s
epar
ate
RA
Ms
that
can
be
acce
ssed
sim
ulta
neou
sly.
On-
Chi
p R
OM
–8
KB
RO
M–
Flas
h pr
ogra
m/e
rase
AP
Is
21
Flas
h A
ccel
erat
or
Just
one
regi
ster
con
figur
atio
n-“F
LAS
HC
FG”
Con
figur
ing
Flas
h Ti
min
g–
100M
Hz,
80M
Hz,
60M
Hz,
40M
Hz
and
20 M
Hz
22
Boo
ting
23
Mem
ory
Prot
ectio
n U
nit (
MPU
)
Inde
pend
ent a
ttrib
ute
setti
ngs
for e
ach
regi
on
Ove
rlapp
ing
regi
ons
Exp
ort o
f mem
ory
attri
bute
s to
the
syst
em
Eig
ht s
epar
ate
mem
ory
regi
ons,
0-7
A b
ackg
roun
d re
gion
24
Key
Sys
tem
Blo
cks
Clo
ckin
g
Nes
ted
VIC
DM
A S
uppo
rt
25
Clo
ck S
truc
ture
(Inp
uts)
Inte
rnal
RC
osc
illat
or
–C
lock
sou
rce
for t
he W
DT,
and
/or a
s th
e cl
ock
that
driv
es th
e P
LL a
nd
subs
eque
ntly
the
CP
U
–Th
e no
min
al IR
C fr
eque
ncy
is 4
MH
z ±
1% a
ccur
acy
over
the
entir
e te
mp
and
volta
ge ra
nge
Mai
n os
cilla
tor
–C
lock
sou
rce
for t
he C
PU
, with
or w
ithou
t usi
ng th
e P
LL.
–Th
e m
ain
osci
llato
r als
o pr
ovid
es th
e cl
ock
sour
ce fo
r the
ded
icat
ed U
SB
P
LL–
Ope
rate
s at
freq
uenc
ies
of 1
MH
z to
25
MH
z
RTC
osc
illat
or–
Clo
ck s
ourc
e fo
r the
RTC
blo
ck, t
he m
ain
PLL
, and
sub
sequ
ently
the
CP
U.
–1
Hz
cloc
k to
RTC
26
Clo
ck S
truc
ture
(PLL
s)
Mai
n P
LL (P
LL0)
–In
put c
lock
freq
uenc
y in
the
rang
e of
32
kHz
to 5
0 M
Hz.
–
May
run
from
the
mai
n os
cilla
tor,
the
inte
rnal
RC
osc
illato
r, or
the
RTC
osc
illat
or–
Out
put f
requ
ency
from
10
MH
z up
to th
e m
ax. C
PU
rate
US
B P
LL (P
LL1)
–In
put c
lock
freq
uenc
y fro
m th
e m
ain
osci
llato
r onl
y (1
0-25
MH
z)–
Out
put f
requ
ency
of 4
8MH
z us
ed o
nly
by th
e U
SB
sub
syst
em–
Ded
icat
ed to
pro
vide
clo
ckin
g fo
r the
US
B in
terfa
ce to
allo
w a
dded
fle
xibi
lity
for t
he m
ain
PLL
set
tings
27
Clo
ckin
g Ex
plai
ned
28
Clo
ck O
UT
29
LPC
1700
NVI
C F
eatu
res
LPC
1700
sup
ports
35
vect
ored
inte
rrup
ts w
ith
prog
ram
mab
le 3
2 pr
iorit
y le
vels
for e
ach
inte
rrup
t–
Gro
upin
g of
prio
rity
valu
es in
to g
roup
prio
rity
and
sub-
prio
rity
field
s
An
Ext
erna
l Non
-Mas
kabl
e In
terr
upt(
NM
I)
Det
erm
inis
tic in
terr
upt l
aten
cy
Adv
ance
d fe
atur
es–
Prio
rity
pre-
empt
ion
–Ta
il ch
aini
ng
30
NVI
C In
terr
upt L
aten
cy
Det
erm
inis
tic in
terr
upt l
aten
cy
Cor
tex-
M3
has
an in
terru
pt la
tenc
y of
12
cycl
es a
nd 1
2 cy
cles
to re
turn
from
ser
vici
ng
AR
M7
does
not
hav
e de
term
inis
tic in
terr
upt l
aten
cy
PU
SH
PO
PIS
RC
orte
x-M
3
IRQ
1212
31
NVI
C In
terr
upt T
ail C
hain
ing
In th
e ca
se o
f bac
k-to
-bac
k in
terr
upts
, tra
ditio
nal s
yste
ms
wou
ld re
peat
the
com
plet
e st
ate
save
and
rest
ore
cycl
e tw
ice,
resu
lting
in h
ighe
rlat
ency
Tail-
chai
ning
ach
ieve
s m
uch
low
er la
tenc
y by
repl
acin
g se
rial s
tack
pop
and
pu
sh a
ctio
ns th
at n
orm
ally
take
ove
r 30
cloc
k cy
cles
with
a s
impl
e 6
cycl
e in
stru
ctio
n fe
tch
http
://w
ww
.arm
.com
s/In
troT
oCor
tex-
M3.
32
Cor
tex-
M3
Exce
ptio
n Ty
pes
No.
Exce
ptio
n Ty
pePr
iorit
yTy
pe o
f Prio
rity
Des
crip
tions
1R
eset
-3 (H
ighe
st)
fixed
Res
et
2N
MI
-2fix
edN
on-M
aska
ble
Inte
rrupt
3H
ard
Faul
t-1
fixed
Def
ault
faul
t if o
ther
han
dler
not
impl
emen
ted
4M
emM
anag
e Fa
ult
0se
ttabl
eM
PU v
iola
tion
or a
cces
s to
ille
gal l
ocat
ions
5Bu
s Fa
ult
1se
ttabl
eFa
ult i
f AH
B in
terfa
ce re
ceiv
es e
rror
6U
sage
Fau
lt2
setta
ble
Exce
ptio
ns d
ue to
pro
gram
erro
rs
7-10
Res
erve
dN
AN
A
11S
VC
all
3se
ttabl
eSy
stem
Ser
vice
Cal
l
12D
ebug
Mon
itor
4se
ttabl
eBr
eakp
oint
s, w
atch
poi
nts,
ext
erna
l deb
ug
13R
eser
ved
NA
NA
14P
endS
V5
setta
ble
Pend
able
requ
est f
or S
yste
m D
evic
e
15S
YS
TIC
K6
setta
ble
Syst
em T
ick
Tim
er
16In
terru
pt#0
7se
ttabl
eEx
tern
al In
terru
pt #
0
----
----
----
---
--se
ttabl
e--
----
----
----
----
----
----
-
256
Inte
rrupt
#239
247
setta
ble
Exte
rnal
Inte
rrupt
#24
0
33
Cor
tex-
M3
Vect
or T
able
Vec
tor T
able
sta
rts a
t loc
atio
n 0
Vec
tor T
able
con
tain
s ad
dres
ses
(vec
tors
) of e
xcep
tion
hand
lers
and
IS
Rs
Mai
n st
ack
poin
ter i
nitia
l val
ue in
lo
catio
n 0
–S
et u
p by
har
dwar
e du
ring
Res
et
Vec
tor T
able
can
be
relo
cate
d to
S
RA
M–
Via
the
Vec
tor T
able
Offs
et (R
egis
ter
cont
aine
d in
the
NV
IC)
Add
ress
Vect
or
0x00
Initi
al M
ain
SP
0X04
Res
et
0x08
NM
I
0X0C
Har
d Fa
ult
0x10
Mem
ory
Man
age
0x14
Bus
Fau
lt
0x18
Usa
ge F
ault
0x1C
–0x
28R
eser
ved
0x2C
SVC
all
0x30
Deb
ug M
onito
r
0x34
Res
erve
d
0x38
Pend
SV
0x3C
Sys
tick
0x40
IRQ
0
----
----
-M
ore
IRQ
s
34
Inte
rrup
t Prio
ritiz
atio
n
On
the
LPC
1700
, eac
h in
terr
upt s
ourc
e ha
s an
5-b
it in
terr
upt p
riorit
y va
lue
Con
trolle
d by
PR
IGR
OU
P fi
eld
of th
e A
pplic
atio
n In
terr
upt
and
Res
et C
ontro
l reg
iste
r in
NV
IC
The
softw
are
prog
ram
mab
le P
RIG
RO
UP
regi
ster
fiel
d of
th
e N
VIC
cho
oses
how
man
y of
the
5-bi
ts a
re u
sed
for
“gro
up-p
riorit
y”an
d ho
w m
any
are
used
for “
sub-
prio
rity”
35
Inte
rrup
t Prio
ritiz
atio
nIf
PR
IGR
OU
P =
3, t
hen
5 bi
ts u
sed
to fo
rmat
per
iphe
ral i
nter
rupt
leve
l will
be d
efin
ed
as X
XX
X :
Y w
here
XX
XX
–gr
oups
(can
hav
e to
tal1
6 gr
oups
), an
d Y
–su
b-pr
iorit
y w
ithin
eac
h gr
oup
–(c
an h
ave
tota
l 2 s
ub-p
riorit
ies
with
in e
ach
grou
p)
If P
RIG
RO
UP
= 5
, the
n 5
bits
use
d to
form
at p
erip
hera
l int
erru
ptle
vel w
ill be
def
ined
as
XX
: Y
YY
whe
re X
X –
grou
ps (c
an h
ave
tota
l 4 g
roup
s), a
nd Y
YY
–su
b-pr
iorit
y w
ithin
eac
h gr
oup
–(c
an h
ave
tota
l 8 s
ub-p
riorit
ies
with
in e
ach
grou
p)
If P
RIG
RO
UP
= 2
, the
n 5
bits
use
d to
form
at p
erip
hera
l int
erru
ptle
vel w
ill be
def
ined
X
XX
XX
whe
re X
XX
XX
–gr
oups
(can
hav
e 32
gro
ups)
, via
sof
twar
e -c
anno
t set
sub
-pr
iorit
y w
ithin
gro
up.
Pre-
empt
ing
Prio
rity
(Gro
up P
riorit
y)Su
b-Pr
iorit
y(S
ub-L
evel
)PR
IGR
OU
P(3
bits
)B
inar
y Po
int
(Gro
up: s
ub)
Bits
Leve
lsB
itsLe
vels
25:
05
bits
for g
roup
s, 0
bit
for s
ub-p
riorit
y5
320
0
34:
14
bits
for g
roup
s, 1
bit
for s
ub-p
riorit
y4
161
2
43:
23
bits
for g
roup
s, 2
bits
for s
ub-p
riorit
y3
82
4
52:
32
bits
for g
roup
s, 3
bits
for s
ub-p
riorit
y2
43
8
61:
41
bitf
or g
roup
, 4 b
its fo
r sub
-prio
rity
12
416
70:
50
bitf
or g
roup
, 5 b
its fo
r sub
-prio
rity
00
532
3 52
36
Inte
rrup
t Prio
ritiz
atio
n
Exam
ple:
We
have
two
inte
rrup
ts in
our
sys
tem
-E
INT0
and
GP
IO In
terr
upt a
nd w
e w
ant t
o as
sign
bot
h in
terru
pts
unde
r the
sam
e gr
oup
with
diff
eren
t sub
-prio
ritie
s w
here
G
PIO
Inte
rrup
t has
a h
ighe
r sub
-prio
rity
than
EIN
T0
–W
e ca
n se
t PR
IGR
OU
P to
4. W
e ca
n ha
ve 8
gro
ups
tota
l and
4 s
ub-le
vels
with
in e
ach
grou
p.–
We
set p
riorit
y fie
ld (b
it 23
:19)
of E
INT0
to 2
so
it w
ill 00
010
whi
ch m
eans
EIN
T0 is
from
gr
oup
0 an
d ha
s su
b-pr
iorit
y of
2 w
ithin
gro
up 0
–W
e se
t prio
rity
field
(bit
15:1
1) o
f GP
IO In
terru
pt(E
INT3
) to
1 so
it w
ill be
000
01w
hich
mea
ns
GP
IO In
terru
pt (E
INT3
) is
from
gro
up 0
and
has
sub
-prio
rity
of 1
with
in g
roup
0–
So if
bot
h in
terru
pts
take
pla
ce a
t the
sam
e tim
e, G
PIO
Inte
rrupt
will
be s
ervi
ced
first
and
then
E
INT0
Inte
rrupt
(exa
mpl
e of
Tai
l-Cha
inin
g)
Pre-
empt
ing
Prio
rity
(Gro
up P
riorit
y)Su
b-Pr
iorit
y(S
ub-L
evel
)PR
IGR
OU
P(3
bits
)B
inar
y Po
int
(Gro
up: s
ub)
Bits
Leve
lsB
itsLe
vels
25:
05
bits
for g
roup
s, 0
bit
for s
ub-p
riorit
y5
320
0
34:
14
bits
for g
roup
s, 1
bit
for s
ub-p
riorit
y4
161
2
43:
23
bits
for g
roup
s, 2
bits
for s
ub-p
riorit
y3
82
4
52:
32
bits
for g
roup
s, 3
bits
for s
ub-p
riorit
y2
43
8
61:
41
bitf
or g
roup
, 4 b
its fo
r sub
-prio
rity
12
416
70:
50
bitf
or g
roup
, 5 b
its fo
r sub
-prio
rity
00
532
37
DM
A S
uppo
rt
AH
B B
us m
aste
r
Eig
ht D
MA
cha
nnel
s w
ith a
four
-wor
d FI
FO
per c
hann
el
SS
P, I
2S, U
AR
T, A
DC
&
DA
C. D
MA
can
als
o be
trig
gere
d by
a ti
mer
m
atch
con
ditio
n
Sin
gle
and
burs
t re
ques
ts s
uppo
rted
38
Perip
hera
l Sup
port
15 S
eria
l Int
erfa
ces
Tim
ers
Mot
or C
ontro
l
Ana
log
Blo
cks
Gen
eral
Pur
pose
IO
39
1011
0101
1010
0101
1011
0110
0111
1000
0010
0000 10
1001
0110
1101
100
15 S
eria
l Int
erfa
ces
40
SPI0
/ SSP
(0 &
1)S
PI c
ontro
ller (
Ser
ial P
erip
hera
l Int
erfa
ce)
–S
ynch
rono
us, S
eria
l, Fu
ll D
uple
x C
omm
unic
atio
n.–
SP
I mas
ter o
r sla
ve.
–8
to 1
6 bi
ts p
er tr
ansf
er–
Pro
gram
mab
le c
lock
pol
arity
and
pha
se fo
r dat
a tra
nsm
it/re
ceiv
e op
erat
ions
–M
axim
um p
ossi
ble
spee
d of
the
SP
I (m
aste
r/sla
ve) 1
2.5
Mbi
ts/s
ec
SS
P c
ontro
ller (
Syn
chro
nous
Ser
ial C
omm
unic
atio
n)–
8 Fr
ame
FIFO
’s fo
r bot
h Tr
ansm
it an
d R
ecei
ve a
nd m
ulti-
prot
ocol
ca
pabi
litie
s.–
4 to
16
bits
fram
e si
zes
–D
MA
sup
port
–M
axim
um p
ossi
ble
spee
d of
the
SS
P 5
0 M
bits
/s (M
aste
r Mod
e), 8
Mbi
ts/s
(S
lave
Mod
e)
41
I2 C (0
,1 &
2)
I2C
com
plia
nt b
us in
terfa
ce, a
nd c
an b
e co
nfig
ured
as
Mas
ter,
Sla
ve, o
r M
aste
r/Sla
ve.
Bi-d
irect
iona
l dat
a tra
nsfe
r bet
wee
n m
aste
rs a
nd s
lave
s
Sup
ports
Fas
t Mod
e P
lus
(I2 C0
only
)
SDA
SCL
I2 CIn
terf
ace
42
I2 S Sup
ports
3-w
ire d
ata
trans
mit
and
rece
ive
OR
4-w
ire c
ombi
ned
trans
mit
and
rece
ive
conn
ectio
ns
Aud
io M
aste
r Clo
ck in
put/o
utpu
t (us
ed o
n m
any
I2S
cod
ecs)
The
I2S
inpu
t and
out
put c
an e
ach
oper
ate
inde
pend
ently
in b
oth
mas
ter a
nd
slav
e m
ode
DM
A s
uppo
rt
CK
LPC
1700
NXP
SD WS
MC
LK
CK
Aud
io C
odec
SD WS
MC
LK
Digital Interface
Analog Interface
43
UA
RTs
(0, 1
, 2 &
3)
16 b
yte
Rec
eive
and
Tra
nsm
it FI
FOs.
Frac
tiona
l div
ider
for b
aud
rate
con
trol,
auto
-bau
d ca
pabi
litie
s, a
nd
impl
emen
tatio
n of
sof
twar
e or
har
dwar
e flo
w c
ontro
l
DM
A s
uppo
rt
EIA
-485
/RS
-485
and
9-b
it m
ode
supp
ort
Mod
em c
ontro
l sup
port
IrDA
sup
port
for i
nfra
red
com
mun
icat
ion
UA
RT1
is id
entic
al to
UA
RT0
/2/3
, with
the
addi
tion
of a
mod
em
inte
rface
and
RS
-485
/EIA
-485
mod
es, n
o IrD
A s
uppo
rt
44
CA
N (1
& 2
) & E
ther
net
CA
N2.
0B c
ontro
llers
(Con
trolle
r Are
a N
etw
ork)
–Fu
ll im
plem
enta
tion
of th
e C
AN
-Pro
toco
l acc
ordi
ng to
the
CA
N
Spe
cific
atio
n V
ersi
on 2
.0B
–D
ata
rate
s to
1 M
bit/s
on
each
bus
–B
uilt-
in H
ardw
are
Acc
epta
nce
Filte
r rec
ogni
zes
11-a
nd 2
9-bi
t Rx
Iden
tifie
rs
Eth
erne
t Int
erfa
ce–
Con
tain
s a
Eth
erne
t MA
C (M
edia
Acc
ess
Con
trolle
r) w
ith R
MII
inte
rface
(red
uced
Med
ia In
depe
nden
t Int
erfa
ce)
–S
uppo
rts 1
0 or
100
Mbp
s P
HY
dev
ices
–
Ded
icat
ed D
MA
con
trolle
r–
Fully
com
plia
nt w
ith 8
02.3
x Fu
ll D
uple
x Fl
ow C
ontro
l and
Hal
f D
uple
x ba
ck p
ress
ure
45
USB US
B 2
.0 F
ull S
peed
(12
Mbp
s) D
evic
e an
d O
n-Th
e-G
o/O
pen
Hos
t C
ontro
l Int
erfa
ce.
Bui
lt-in
on-
chip
PH
Y fo
r Dev
ice/
Hos
t/OTG
func
tions
.
Ded
icat
ed D
MA
con
trolle
r
46
Tim
ers
Four
Gen
eral
Pur
pose
tim
ers
Wat
chdo
g tim
er
Rep
etiti
ve in
terr
upt t
imer
PW
M (T
imer
ope
ratio
n)
Sys
tick
timer
47
Tim
ers
(1)
Gen
eral
Pur
pose
Tim
ers
–To
tal 8
cap
ture
inpu
ts, a
nd 4
ext
erna
l mat
ch o
utpu
ts
–Ti
mer
as
coun
ter o
r tim
er m
ode.
–
Sel
ecte
d tim
er e
vent
s ca
n se
lect
ivel
y ge
nera
te D
MA
requ
ests
. Thi
s al
low
s fo
r tim
ed m
emor
y-to
-mem
ory
trans
fers
.–
Mat
ch o
utpu
t can
togg
le, g
o hi
gh, g
o lo
w o
r do
noth
ing
Wat
chdo
g Ti
mer
–E
nabl
ed b
y so
ftwar
e bu
t req
uire
s a
hard
war
e re
set o
r a W
atch
dog
rese
t/int
erru
pt to
be
disa
bled
–C
an b
e us
ed in
Dee
p S
leep
mod
e–
Deb
ug m
ode
(inte
rrup
t)
48
Tim
ers
(2)
Rep
etiti
ve In
terr
upt T
imer
(RIT
)–
An
inte
rrup
t is
gene
rate
d w
hen
the
coun
ter v
alue
equ
als
the
com
pare
va
lue,
afte
r mas
king
–Th
is a
llow
s fo
r com
bina
tions
not
pos
sibl
e w
ith a
sim
ple
com
pare
PW
M ti
mer
–S
even
mat
ch re
gist
ers
allo
w u
p to
6 s
ingl
e ed
ge c
ontro
lled
or 3
dou
ble
edge
con
trolle
d P
WM
out
puts
, or a
mix
of b
oth
type
s. T
he m
atch
regi
ster
sal
so s
ever
al o
pera
tions
at m
atch
–M
ay b
e us
ed a
s a
stan
dard
tim
er if
the
PW
M m
ode
is n
ot e
nabl
ed–
Two
32 b
it ca
ptur
e ch
anne
ls ta
ke a
sna
psho
t of t
he ti
mer
val
ue w
hen
an
inpu
t sig
nal t
rans
ition
s. A
cap
ture
eve
nt m
ay a
lso
optio
nally
gen
erat
e an
in
terru
pt–
Sha
dow
latc
h m
echa
nism
49
Tim
ers
(3)
Sys
tick
Tim
er–
24-b
it tim
er th
at c
ount
s do
wn
to z
ero
and
prov
ides
10
milli
seco
nd ti
me
inte
rval
be
twee
n in
terru
pts
–C
an b
e cl
ocke
d in
tern
ally
by
the
CP
U c
lock
or b
y a
cloc
k in
put f
rom
a p
in
(STC
LK)
–D
efau
lt re
gist
er s
ettin
gs g
ives
a 1
0ms
inte
rrupt
if th
e C
PU
clo
ck ra
te is
100
MH
z
50
Mot
or C
ontr
ol P
WM
s
TC LIM
MA
T
DT
CA
P
MC
OA
0M
CO
B0
MC
OA
1M
CO
B1
MC
OA
2M
CO
B2
Cha
nnel
1C
hann
el 2
51
Mot
or C
ontr
ol-A
n O
verv
iew
52
Ope
ratin
g M
odes
53
Qua
drat
ure
Enco
der
Inte
rfac
e (Q
EI)
54
QEI
-Key
Fea
ture
s
Trac
ks e
ncod
er p
ositi
on
Dig
ital f
ilter
with
pro
gram
mab
le d
elay
s fo
r enc
oder
inpu
t si
gnal
s
Pro
gram
mab
le fo
r 2X
or 4
X p
ositi
on c
ount
ing.
Vel
ocity
cap
ture
Inde
x co
unte
r for
revo
lutio
n co
untin
g
Can
com
bine
inde
x an
d po
sitio
n in
terr
upts
to p
rodu
ce a
n in
terr
upt f
or w
hole
and
par
tial r
evol
utio
n di
spla
cem
ent
55
Ana
log
Blo
cks-
12-b
it A
DC
M
easu
rem
ent r
ange
0 V
to V
RE
FP (t
ypic
ally
3 V
; not
to e
xcee
d V
DD
A v
olta
ge
leve
l)12
bit
conv
ersi
on ra
te o
f 200
KH
zB
urst
con
vers
ion
mod
e fo
r sin
gle
or m
ultip
le in
puts
Opt
iona
l con
vers
ion
on tr
ansi
tion
on in
put p
in o
r Tim
er M
atch
sig
nal
DM
A s
uppo
rt
Sele
ct C
hann
elA
DC
R (7
:0)
30
12
75
64
12-b
it A
DC
AD
CIn
puts
VR
EFN
AD
DR
0
AD
DR
7
VR
EFP
V3A
VSS
A56
Ana
log
Blo
cks
(con
td.)
10 B
it D
AC
(Dig
ital t
o A
nalo
g C
onve
rter)
–10
bit
digi
tal t
o an
alog
con
verte
r–
Res
isto
r stri
ng a
rchi
tect
ure
–B
uffe
red
outp
ut–
Pow
er-d
own
mod
e–
Sel
ecta
ble
spee
d vs
. pow
er
Pow
er-o
n-R
eset
(PO
R)
BO
D–
Two
thre
shol
ds-2
.65V
& 2
.95V
57
RTC
Dom
ain
58
RTC
Fea
ture
sM
easu
res
the
pass
age
of ti
me
to m
aint
ain
a ca
lend
ar a
nd c
lock
–P
rovi
des
seco
nds,
min
utes
, hou
rs, d
ay o
f mon
th, m
onth
, yea
r, da
yof
wee
k,
and
day
of y
ear
Ultr
a-lo
w p
ower
des
ign
to s
uppo
rt ba
ttery
pow
ered
sys
tem
s. L
ess
than
1
uA re
quire
d fo
r bat
tery
ope
ratio
n–
Use
s po
wer
from
the
CP
U p
ower
sup
ply
whe
n it
is p
rese
nt
20 b
ytes
of B
atte
ry-b
acke
d st
orag
e an
d R
TC o
pera
tion
whe
n po
wer
is
rem
oved
from
the
CP
U
Ded
icat
ed 3
2 kH
z ul
tra lo
w p
ower
osc
illat
or w
ith d
edic
ated
bat
tery
po
wer
sup
ply
pin
RTC
pow
er s
uppl
y is
isol
ated
from
the
rest
of t
he c
hip
RTC
will
wor
k do
wn
as lo
w a
s 2.
1 V
59
Gen
eral
Pur
pose
I/O
(GPI
O)
70 H
igh
Spe
ed G
PIO
s (L
QFP
100)
and
52
Hig
h S
peed
G
PIO
s (L
QFP
80)
All
pins
hav
e co
nfig
urab
le p
ull-u
ps/p
ull-d
owns
New
con
figur
atio
n -o
pen-
drai
n m
ode
(app
lies
to a
ll G
PIO
pi
ns)
GP
IO re
gist
ers
are
loca
ted
on a
per
iphe
ral A
HB
bus
for f
ast
I/O ti
min
g
Mas
k re
gist
ers
allo
w tr
eatin
g se
ts o
f por
t bits
as
a gr
oup,
le
avin
g ot
her b
its u
ncha
nged
GP
IO re
gist
ers
are
acce
ssib
le b
y th
e G
P D
MA
60
GPI
O &
Ext
erna
l Int
erru
pts
Exte
rnal
inte
rrup
t inp
uts
–U
p to
46
edge
sen
sitiv
e in
terr
upt i
nput
s (4
2 G
PIO
+ 4
EIN
T) c
ombi
ned
with
up
to fo
ur le
vel s
ensi
tive
exte
rnal
inte
rrup
t inp
uts
(EIN
T pi
ns)a
s se
lect
able
pi
n fu
nctio
ns–
The
exte
rnal
inte
rrup
t inp
uts
can
optio
nally
be
used
to w
ake
up th
e pr
oces
sor f
rom
Pow
er-d
own
mod
e
61
Pow
er M
anag
emen
tP
ower
Dom
ains
Pow
er d
own
mod
es
Wak
eup
Inte
rrup
t Con
trolle
r (W
IC)
62
Pow
er d
omai
nsS
ingl
e 3.
3 V
pow
er s
uppl
y (2
.4 V
to 3
.6 V
)–
VD
D(r
eg)(
3V3)
–on
-chi
p vo
ltage
regu
lato
r–
VD
D(3
V3)
–I/O
pad
s
VB
AT
pin
(2.1
V to
3.6
V)
–P
ower
onl
y to
the
RTC
–N
o B
atte
ry R
AM
–B
acku
p R
egis
ters
(20
byte
s)
12 B
it A
DC
(2.7
V to
3.6
V)
–V
DD
A
–V
RE
FP
63
Pow
er M
odes
(1)
Act
ive
Pow
er o
ptio
ns–
Wid
e ra
ge o
f clo
ck s
ourc
es to
sta
tic c
lock
ing
–A
bilit
y to
div
ide
dow
n or
shu
t off
cloc
ks to
indi
vidu
al o
n-ch
ip p
erip
hera
ls
Pow
er re
duce
d m
odes
–Sl
eep
•C
PU
exe
cutio
n is
sus
pend
ed
•Pe
riphe
rals
con
tinue
runn
ing
•(S
imila
r to
Idle
Mod
e on
AR
M7)
•W
akeu
p >>
Ext
erna
l res
et o
r any
ena
bled
inte
rrupt
whi
ch o
ccur
s
–D
eep-
Slee
p•
Mai
n os
cilla
tor a
nd a
ll in
tern
al c
lock
s ex
cept
the
IRC
are
sto
pped
•Fl
ash
mem
ory
is in
sta
ndby
, rea
dy fo
r im
med
iate
use
64
Pow
er M
odes
(2)
Pow
er-d
own
–S
ame
as D
eep-
Sle
ep m
ode
exce
pt F
lash
and
IRC
are
shu
t dow
n–
Sta
te is
pre
serv
ed
Dee
p po
wer
-dow
n–
All
cloc
ks in
clud
ing
IRC
are
sto
pped
. Int
erna
l vol
tage
is tu
rned
off
–C
ompl
ete
syst
em s
tate
is lo
st, o
nly
spec
ial r
egis
ters
in th
e R
TCdo
mai
n ar
e pr
eser
ved
–O
ptio
n to
run
RTC
–W
ake-
up >
>> re
set o
r RTC
inte
rrup
t
65
Wak
eup
Inte
rrup
t Con
trol
ler (
WIC
)
Ena
bles
the
chip
to w
ake
up fr
om D
eep
Sle
ep a
nd P
ower
do
wn
mod
e (w
ithou
t the
use
of N
VIC
)
Com
plet
ely
cont
rolle
d in
har
dwar
e (n
o pr
ogra
mm
ing
requ
ired)
Inte
rrup
ts u
sed:
–N
MI,
Ext
erna
l Int
erru
pts
EIN
T0 th
roug
h E
INT3
, GP
IO in
terru
pts,
E
ther
net W
ake-
on-L
AN
inte
rrup
t, B
row
nout
Det
ect,
RTC
Ala
rm,
CA
N a
ctiv
ity in
terr
upt a
nd U
SB
act
ivity
inte
rrup
t –
In a
dditi
on, t
he w
atch
dog
timer
can
wak
e up
the
part
from
Dee
p S
leep
mod
e if
it is
clo
cked
by
the
IRC
osc
illat
or
Onl
y av
aila
ble
in R
elea
se 2
of C
orte
x-M
366
Tool
s &
Eco
syst
em
67
Emul
atio
n an
d de
bugg
ing
Deb
ug a
nd tr
ace
func
tions
are
inte
grat
ed in
to th
e A
RM
Cor
tex-
M3.
Sta
ndar
d JT
AG
deb
ug (5
pin
)
Ser
ial w
ire d
ebug
(SW
D) (
two
pins
) and
Ser
ial w
ire o
utpu
t (S
WO
) (on
e pi
n)
Em
bedd
ed T
race
Mac
roce
ll (E
TM) i
nter
face
(5 p
ins)
for r
eal-t
ime
trace
Sup
port
up to
eig
ht b
reak
poin
ts a
nd fo
ur w
atch
poin
ts.
NXP
has
the
best
Deb
uggi
ng a
vaila
ble
on a
ny C
orte
x M
3
68
Ove
rvie
w o
f JTA
G, S
W a
nd T
race
Pin
s
6969
LPC
1700
Too
ls H
ighl
ight
sE
valu
atio
n bo
ards
–E
mbe
dded
Arti
sts
–H
itex
LPC
17xx
-Stic
k–
IAR
KS
DK
-LP
C17
xx–
Kei
l MC
B17
xx
IDE
s–
AR
M/K
eil µ
Vis
ion3
–C
odeR
ed R
edS
uite
–H
itex
HiT
OP
–IA
R E
mbe
dded
Wor
kben
ch fo
r AR
M
JTA
G d
ebug
gers
–A
ll de
bugg
ers
supp
ortin
g C
orte
x-M
3
Plu
s m
any
mor
e to
ols
avai
labl
e!
70
Com
plet
e lis
ting
of T
ools
ww
w.n
xp.c
om/lp
czon
e
71
Than
k Yo
u!
72
