1

LT1166

Power Output StageAutomatic Bias System

FEATURES Set Class AB Bias Currents Eliminates Adjustments Eliminates Thermal Runaway of IQ Corrects for Device Mismatch Simplifies Heat Sinking Programmable Current Limit May Be Paralleled for Higher Current Small SO-8 or PDIP Package

The LT®1166 is a bias generating system for controllingclass AB output current in high powered amplifiers. Whenconnected with external transistors, the circuit becomes aunity-gain voltage follower. The LT1166 is ideally suitedfor driving power MOSFET devices because it eliminatesall quiescent current adjustments and critical transistormatching. Multiple output stages using the LT1166 can beparalleled to obtain higher output current.

Thermal runaway of the quiescent point is eliminatedbecause the bias system senses the current in each powertransistor by using a small external sense resistor. A highspeed regulator loop controls the amount of drive appliedto each power device. The LT1166 can be biased from a pairof resistors or current sources and because it operates on thedrive voltage to the output transistors, it operates on anysupply voltage.

DESCRIPTION

U

Biasing Power MOSFETs High Voltage Amplifiers Shaker Table Amplifiers Audio Power Amplifiers

APPLICATIONSU

Unity Gain Buffer Amp Driving 1Ω Load

INPUT

OUTPUT

0V

0V

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATION

U

7

3

6

ILIM+

VOUT

ILIM–

LT1166

VTOP

VBOTTOM

1µF

1µF

1k

1k

R3 100Ω

RSENSE–

0.33Ω

RSENSE+

0.33Ω

1Ω

VOUT

4 IBOTTOM = 15mA

1 ITOP = 15mA

300pF

R2 100Ω

300pF

IRF9530

IRF530

2N2222R4

100Ω 47ΩMPS2222

+220µF

2N2907

R1

100ΩMPS2907

+220µF

15V

–15V

5.6k

VINVIN4.3k 2

1166 • F01

SENSE– 5

SENSE+ 8

47Ω

Figure 1. Unity Gain Buffer with Current Limit

1166 • TA01

2

LT1166

ABSOLUTE MAXIMUM RATINGS

W WW U

PACKAGE/ORDER INFORMATION

W UU

ORDER PARTNUMBER

Supply Current (Pin 1 or Pin 4) ............................ 75mADifferential Voltage (Pin 2 to Pin 3) ......................... ±6VOutput Short-Circuit Duration (Note 1) .........ContinuousSpecified Temperature Range (Note 2) ........ 0°C to 70°COperating Temperature Range ................ –40°C to 85°CStorage Temperature Range ................. –65°C to 150°CJunction Temperature (Note 3) ............................ 150°CLead Temperature (Soldering, 10 sec).................. 300°C

S8 PART MARKING

1166TJMAX = 150°C, θJA = 100°C/ W (N8)TJMAX = 150°C, θJA = 150°C/ W (S8)

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITSOutput Offset Voltage Operating Current 15mA to 50mA 50 250 mVInput Bias Current Operating Current 15mA to 50mA (Note 4) 2 10 µAInput Resistance Operating Current 15mA to 50mA (Note 5) 2 15 MΩVAB (Top) Measure Pin 8 to Pin 3, No Load 14 20 26 mVVAB (Bottom) Measure Pin 5 to Pin 3, No Load – 14 –20 – 26 mVVoltage Compliance Operating Current = 50mA (Notes 6, 9) ±2 ±10 VCurrent Compliance Operating Voltage = ±2V ±4 ±50 mATransconductance (Note 7)

gmCC2 Pin 1 = 2V, Pin 4 = – 2V 0.08 0.100 0.13 mhogmEE2 Pin 1 = 2V, Pin 4 = –2V 0.08 0.100 0.13 mhogmCC10 Pin 1 = 10V, Pin 4 = –10V 0.09 0.125 0.16 mhogmEE10 Pin 1 = 10V, Pin 4 = –10V 0.09 0.125 0.16 mho

PSRRCC (Note 8) 19 dBPSRREE (Note 8) 19 dBCurrent Limit Voltage Operating Current 15mA to 50mA

Pin 7 Voltage to Pin 3 1.0 1.3 1.5 VPin 6 Voltage to Pin 3 –1.0 –1.3 –1.5 V

The denotes specifications which apply over the full operatingtemperature range.Note 1: External power devices may require heat sinking.Note 2: Commercial grade parts are designed to operate over thetemperature range of –40°C to 85°C but are neither tested nor guaranteedbeyond 0°C to 70°C. Industrial grade parts specified and tested over–40°C and 85°C are available on special request, consult factory.Note 3: TJ calculated from the ambient temperature TA and the powerdissipation PD according to the following formulas:

LT1166CN8: TJ = TA + (PD • 100°C/W)LT1166CS8: TJ = TA + (PD • 150°C/W)

Note 4: ITOP = IBOTTOM

Note 5: The input resistance is typically 15MΩ when the loop is closed.When the loop is open (current limit) the input resistance drops to 200Ωreferred to Pin 3.Note 6: Maximum TJ can be exceeded with 50mA operating current andsimultaneous 10V and –10V (20V total).Note 7: Apply ±200mV to Pin 2 and measure current change in Pin 1and 4. Pin 3 is grounded.Note 8:

Note 9: For Linear Operation, Pin 1 must not be less than 2V or more than10V from Pin 3. Similarly, Pin 4 must not be less than 2V or more than10V from Pin 3.

Pin 1 = 2V, Pin 4 = – 2V, Operating current 15mA and RIN = 20k, unless otherwise specified.

1

2

3

4

8

7

6

5

TOP VIEW

VTOP

VIN

VOUT

VBOTTOM

SENSE+

ILIM+

ILIM–

SENSE–

N8 PACKAGE 8-LEAD PDIP

S8 PACKAGE 8-LEAD PLASTIC SO

+1

PSRRCC = gmCC2 – gmCC10

gm CC2PSRREE = gmEE2 – gmEE10

gm EE2

LT1166CN8LT1166CS8

3

LT1166

TYPICAL PERFORMANCE CHARACTERISTICS

UW

Input Bias Current vsCurrent Source Mismatch

CURRENT SOURCE MISMATCH (%)–10

INPU

T BI

AS C

URRE

NT (µ

A)

–5.0 0 5.0 10

LT1166 • TPC01

150

100

50

0

–50

–100

–150–7.5 –2.5 2.5 7.5

ITOP = IBOTTOM = 50mA

ITOP = IBOTTOM = 4mA

TEMPERATURE (°C)–50

OUTP

UT O

FFSE

T VO

LTAG

E (m

V)

60

55

50

45

40

35

3025 75

LT1166 • TPC03

–25 0 50 100 125

RL = ∞ ITOP = IBOTTOM = 15mA RIN = 4.3k

Output Offset Voltage vsTemperature

Output Offset Voltage vsCurrent Source Mismatch

Input Bias Current vsTemperature

TEMPERATURE (°C)–50

INPU

T BI

AS C

URRE

NT (µ

A)

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.00 50 75

LT1166 • TPC04

–25 25 100 125

RL = ∞ ITOP = IBOTTOM = 15mA

RIN = 4.3k

INPUT VOLTAGE (V)–10

OUTP

UT V

OLTA

GE S

WIN

G (V

)

10

8

6

4

2

0

–2

–4

–6

–8

–106

LT1166 • TPC05

–6–8 –4 0 4 8–2 2 10

RIN = 4.3k C1 = C2 = 500pF RL = 10Ω SEE FIGURE 8

ITOP = IBOTTOM = 12mA

RTOP = RBOTTOM = 1k

Output Voltage vs Input VoltageOpen-Loop Voltage Gain vsFrequency

Closed-Loop Voltage Gain vsFrequency

Current Limit Pin Voltage vsTemperature

FREQUENCY (MHz)

GAIN

(dB)

2

1

0

–1

–2

–3

–4

–5

–6

–7

–80.001 0.1 1 10

LT1166 • TPC07

0.01

VS = ±15V RIN = 4.3k ITOP = IBOTTOM = 12mA C1 = C2 = 500pF SEE FIGURE 8

RL = ∞

RL =10Ω

Voltage Across Sense Resistorsvs Temperature

TEMPERATURE (°C)–50VO

LTAG

E DR

OP A

CROS

S SE

NSE

RESI

STOR

S (m

V) 24

22

20

18

16

–16

–18

–20

–22

–240 50 75

LT1166 • TPC08

–25 25 100 125

SENSE+

SENSE–

TEMPERATURE (°C)–50

I LIM

PIN

VOL

TAGE

REF

EREN

CED

TO V

OUT

(V) 1.25

1.20

1.15

–1.15

–1.20

–1.250 50 75

LT1166 • TPC09

–25 25 100 125

PIN 7 TO PIN 3

PIN 6 TO PIN 3

VIN = ±1.5V

ITOP AND IBOTTOM MISMATCH (mA)–1.0

OUTP

UT O

FFSE

T VO

LTAG

E (m

V)

1.0

LT1166 • TPC02

–0.5 0 0.5

800

600

400

200

0

–200

–400

–600

–800–0.75 –0.25 0.25 0.75

ITOP = IBOTTOM = 50mA

RIN = 20k

RIN = 2k

FREQUENCY (MHz)

GAIN

(dB)

30

25

20

15

10

5

0

–5

–10

–15

–200.001 0.1 1 10

LT1166 • TPC06

0.01

VS = ±15V RIN = 4.3k ITOP = IBOTTOM = 12mA C1 = C2 = 500pF SEE FIGURE 8

RL = ∞

RL =10Ω

4

LT1166

TYPICAL PERFORMANCE CHARACTERISTICS

UW

SUPPLY VOLTAGE (V)0

INPU

T TR

ANSC

ONDU

CTAN

CE (m

hos)

0.120

0.110

0.100

0.090

0.080

–0.080

–0.090

–0.100

–0.110

–0.1208

LT1166 • TPC10

21 3 5 7 94 6 10

VIN = ±200mV RL = 0 RIN = 0

125°C

25°C

–55°C

125°C

–55°C25°C

gmCC

gmEE

Input Transconductance vsSupply Voltage

LOAD CURRENT (mA)

10 8 6 4 2 0 2 4 6 8 10

SENS

E PI

N VO

LTAG

E RE

FERE

NCED

TO

V OUT

(mV)

LT1166 • TPC12

1000

100

10

1RSENSE = 100Ω

VBOTTOM VTOP

SINKING SOURCING

Sense Pin Voltage Referenced toVOUT vs Load Current

FREQUENCY (kHz)

0.1TO

TAL

HARM

ONIC

DIS

TORT

ION

(%)

1

0.01 1 10 100

LT1166 • TPC11

0.010.1

10RL = 10Ω PO = 1W SEE FIGURE 8

Total Harmonic Distortion vsFrequency

PIN FUNCTIONS

UUU

VTOP (Pin 1): Pin 1 establishes the top side drive voltagefor the output transistors. Operating supply current entersPin 1 and a portion biases internal circuitry; Pin 1 currentshould be greater than 4mA. Pin 1 voltage is internallyclamped to 12V with respect to VOUT and the pin currentshould be limited to 75mA maximum.

VIN (Pin 2): Pin 2 is the input to a unity gain buffer whichdrives VOUT (Pin 3). During a fault condition (short circuit)the input impedance drops to 200Ω and the input currentmust be limited to 5mA or VIN to VOUT limited to less than±6V.

VOUT (Pin 3): Pin 3 of the LT1166 is the output of a voltagecontrol loop that maintains the output voltage at the inputvoltage.

VBOTTOM (Pin 4): Pin 4 establishes the bottom side drivevoltage for the output transistors. Operating supply cur-rent exits this pin; Pin 4 current should be greater than4mA. Pin 4 voltage is internally clamped to – 12V withrespect to VOUT and the pin current should be limited to75mA maximum.

SENSE– (Pin 5): The Sense – pin voltage is establishedby the current control loop and it controls the outputquiescent current in the bottom side power device. Limitthe maximum differential voltage between Pin 5 and Pin 3to ±6V during fault conditions.

ILIM– (Pin 6): The negative side current limit, limits the

voltage at VBOTTOM to VOUT during a negative fault condi-tion. The maximum reverse voltage on Pin 6 with respectto VOUT is 6V.

ILIM+ (Pin 7): The positive side current limit, limits the

voltage at VTOP to VOUT during a positive fault condition.The maximum reverse voltage on Pin 7 with respect toVOUT is –6V.

SENSE+ (Pin 8): The Sense + pin voltage is established bythe current control loop and it controls the output quies-cent current in the top side power device. Limit themaximum differential voltage between Pin 8 and Pin 3 to±6V during fault conditions.

5

LT1166

APPLICATIONS INFORMATION

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Overvoltage Protection

The supplies VTOP (Pin 1) and VBOTTOM (Pin 4) have clampdiodes that turn on when they exceed ±12V. These diodesact as ESD protection and serve to protect the LT1166when used with large power MOS devices that producehigh VGS voltage. Current into Pin 1 or Pin 4 should belimited to ±75mA maximum.

Multiplier Operation

Figure 2 shows the current multiplier circuit internal to theLT1166 and how it works in conjunction with poweroutput transistors. The supply voltages VT (top) and VB(bottom) of the LT1166 are set by the required “on”voltage of the power devices. A reference current IREF setsa constant VBE7 and VBE8. This voltage is across emitterbase of Q9 and Q10 which are 1/10 the emitter area of Q7and Q8. The expression for this current multiplier is:

VBE7 + VBE8 = VBE9 + VBE10

or in terms of current:

(IC9)(IC10) = (IREF)2/100 = Constant

The product of IC9 and IC10 is constant. These currents aremirrored and set the voltage on the (+) inputs of a pair of

internal op amps. The feedback of the op amps force thesame voltage on the (–) inputs and these voltages thenappear on the sense resistors in series with the powerdevices. The product of the two currents in the powerdevices is constant, as one increases the other decreases.The excellent logging nature of Q9 and Q10 allows thisrelation to hold over many decades in current.

The total current in Q7 and Q8 is actually the sum of IREFand a small error current from the shunt regulator. Duringhigh output current conditions the error current from theregulator decreases. Current conducted by the regulatoralso decreases allowing VT or VB to increase by an amountneeded to drive the power devices.

Driving the Input Stage

Figure 3 shows the input transconductance stage of theLT1166 that provides a way to drive VT and VB. When apositive voltage VIN is applied to RIN, a small input currentflows into R2 and the emitter of Q2. This effect causes VOto follow VIN within the gain error of the amplifier. Theinput current is then mirrored by Q3/Q4 and currentsupplied to Q4’s collector is sourced by power device M1.The signal current in Q4’s emitter is absorbed by externalresistor RB and this causes VB to rise by the same amount

Figure 2. Constant Product Generator

VAB+

VAB–

1k

1k

1Ω

1Ω

8

1

3

5

4

VO

V–

V+

Q7 × 10

Q8 × 10

Q9 × 1

Q10 × 1

RB 1k

RT 1k

–

+

–

+

M2

VTOP

VBOTTOM

IREF

IREF 10SHUNT

REGULATOR

1166 • F02

M1

1Ω

1Ω

R1

R2

1

3

4

VO

V–

V+

Q11

Q12

Q1

Q2

RB 1k

RT 1k

M2

VTOP

VBOTTOM

1166 • F03

Q4 × 32

Q6 × 32

Q3 × 1

Q5 × 1

CEXT1

VIN

RIN

CEXT2

2

M1

Figure 3. Input Stage Driving Gates

6

LT1166

APPLICATIONS INFORMATION

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as VIN. Similarly for VT, when positive voltage is applied toRIN, current that was flowing in R1 and Q1 is now suppliedthrough RIN. This effect reduces the current in mirror Q5/Q6. The reduced current has the effect of reducing the dropon RT, and VT rises to make VO track VIN.

The open-loop voltage gain VO/(VIN – VPIN2) can beincreased by replacing RT and RB with current sources.The effect of this is to increase the voltage gain VOUT/ VINfrom approximately 0.8 to 1 (see Typical PerformanceCharacteristics curves). The use of current sources in-stead of resistors greatly increases loop gain and thiscompensates for the nonlinearity of the output stageresulting in much lower distortion.

Frequency Compensation and Stability

The input transconductance is set by the input resistor RINand the 32:1 current mirrors Q3/Q4 and Q5/Q6. Theresistors R1 and R2 are small compared to the value ofRIN. Current in RIN appears 32 times larger in Q4 or Q6,which drive external compensation capacitors CEXT1 andCEXT2. These two input signal paths appear in parallel togive an input transconductance of:

gm = 16/RIN

The gain bandwidth is:

GBW = 16 2π(RIN)(CEXT)

Depending on the speed of the output devices, typicalvalues are RIN = 4.3k and CEXT1 = CEXT2 = 500pF giving a–3dB bandwidth of 1.2MHz (see Typical PerformanceCharacteristics curves).

To prevent instability it is important to provide goodsupply bypassing as shown in Figure 1. Large supplybypass capacitors (220µF) and short power leads caneliminate instabilities at these high current levels. The100Ω resistors (R2 and R3) in series with the gates of theoutput devices stop oscillations in the 100MHz region as dothe 100Ω resistors R1 and R4 in Figure 1.

Driving Capacitive Loads

Ideally, amplifiers have enough phase margin that theydon’t oscillate but just slow down with capacitive loads.Practically, amplifiers that drive significant power requiresome isolation from heavy capacitive loads to preventoscillation. This isolation is normally an inductor in serieswith the output of the amplifier. A 1µH inductor in parallelwith a 10Ω resistor is sufficient for many applications.

Setting Output AB Bias Current

Setting the output AB quiescent current requires no ad-justments. The internal op amps force VAB = ±20mVbetween each Sense (Pins 5 and 8) to the Output (Pin 3).At quiescent levels the output current is set by:

IAB = 20mV/RSENSE

The LT1166 does not require a heat sink or mounting onthe heat sink for thermal tracking. The temperature coef-ficient of VAB is approximately 0.3%/°C and is set by thejunction temperature of the LT1166 and not the tempera-ture of the power transistors.

Output Offset Voltage and Input Bias Current

The output offset voltage is a function of the value of RINand the mismatch between external current sources ITOPand IBOTTOM (see the Typical Performance Characteristicscurves). Any error in ITOP and IBOTTOM match is reducedby the 32:1 input current mirror, but is multiplied by theinput resistor RIN.

Current Limit

The voltage to activate the current limit is ±1.3V. Thesimplest way to protect the output transistors is to con-nect the Current Limit pins 6 and 7 to the Sense pins 5 and8. A current limit of 1.3A can be set by using 1Ω senseresistors. To keep the current limit circuit from oscillatingin hard limit, it is necessary to add an RC (1k and 1µF)between the Sense pin and the ILIM as shown in Figure 1.

The sense resistors can be tapped up or down to increaseor decrease the current limit without changing AB biascurrent in the power transistors. Figure 4 demonstrates

7

LT1166

APPLICATIONS INFORMATION

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how tapping the sense resistors gives twice the limitcurrent or one half the limit current.

Foldback current limit can be added to the normal or“square” current limit by including two resistors (30ktypical) from the power supplies to the ILIM pins as shownin Figure 5. With square current limit the maximum outputcurrent is independent of the voltage across the power

devices. Foldback limit simply makes the output currentdependent on output voltage. This scheme puts dissipa-tion limits on the output devices. The larger the voltageacross the power device, the lower the available outputcurrent. This is represented in Figure 6, Output Voltage vsOutput Current for the circuit of Figure 5.

Driving the Shunt Regulator

It is possible to current drive the shunt regulator directlywithout driving the input transconductance stage. Thishas the advantage of higher speed and eliminates the needto compensate the gm stage. With Pin 2 floating, theLT1166 can be placed inside a feedback loop anddriven through the biasing current sources. The inputtransconductance stage remains biased but has no effecton circuit operation. The RL in Figure 7 is used to modu-late the op amp supply current with input signal. This opamp functions as a V-to-I with the supply leads acting ascurrent source outputs. The load resistor and the positiveinput of the op amp are connected to the output of theLT1166 for feedback to set AV = 1V/V. The capacitor CFeliminates output VOS due to mismatch between ITOP andIBOTTOM, and it also forms a pole at DC and a zero at1/RFCF. The zero frequency is selected to give a –1V/Vgain in the op amp before the phase of the MOSFETsdegenerate the stability of the loop.

8

7

3

6

5

SENSE+

ILIM+

VOUT

ILIM–

SENSE–

LT1166

VTOP

VBOTTOM

0.5Ω

0.5Ω

1Ω

VOUT

V+

V–

4

1

VINVIN

RIN 2

1166 • F04

1Ω

(2)(ILIM)

(1/2)(ILIM)

8

7

3

6

5

SENSE+

ILIM+

VOUT

ILIM–

SENSE–

LT1166

VTOP

VBOTTOM

1µF

1µF

1k

1k

100Ω

10Ω

10Ω

30k

30k

VOUT

4

1

100Ω

IRFR9024

IRFR024

15V

–15V

VIN5.1k 2

1166 • F05

+330pF

330pF

20mA

20mA

mA

Figure 5. Unity Gain Buffer Amp with Foldback Current Limit

Figure 4. Tapping Current Limit Resistors

OUTPUT VOLTAGE (V)–10

OUTP

UT C

URRE

NT (m

A)

200

160

120

80

40

0

–40

–80

–120

–160

–2006

LT1166 • F06

–6–8 –4 0 4 8–2 2 10

SQUARE ILIM+

SQUARE ILIM–

FOLDBACK ILIM+

FOLDBACK ILIM–

Figure 6. Output Current vs Output Voltage

8

LT1166

APPLICATIONS INFORMATION

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APPLICATION CIRCUITS

Bipolar Buffer

Similar to the unity gain buffer in Figure 1, the LT1166 canbe used to bias bipolar transistors as shown in Figure 8.The minimum operating voltage for the LT1166 is ±2V, soit is necessary to bias the part with adequate voltage from

the output stage. The simplest way to do this is to useDarlington drivers and series diodes. There are no thermaltracking circuits or adjustments necessary and the LT1166does not need to be mounted on the heat sink with thepower devices. RTOP and RBOTTOM can be used to replaceITOP and IBOTTOM; see Typical Characteristics curves.

Figure 8. Bipolar Buffer AmpFigure 7. Current Source Drive

8

7

3

6

5

SENSE+

ILIM+

VOUT

ILIM–

SENSE–

LT1166

VTOP

VBOTTOM

1Ω

1Ω

VOUT

4

1

M2

M1

V+

V–

VIN

VIN

RIN

2

1166 • F07

IT

IB

–

+

RL

RFCF

8

7

3

6

5

SENSE+

ILIM+

VOUT

ILIM–

SENSE–

LT1166

VTOP

VBOTTOM

100Ω

1Ω

1Ω

150Ω

150Ω

10Ω

VOUT

4

IBOT = 15mA

1

ITOP = 15mA 100Ω

2N2222

47Ω

100Ω2N2222

+220µF

2N2907

47Ω100Ω

2N2907

+220µF

–15V

15V

5.6k

VINVIN4.7k 2

1166 • F08

500pF

TIP29

2N2222

IN4001

IN4001

500pF

TIP30

2N2907

RTOP

RBOTTOM

9

LT1166

Adding Voltage Gain

The circuit in Figure 9 adds voltage gain to the circuit inFigure 1. At low frequency the LT1166 is in the feedback

loop of the LT1360 so the gain error and the VOS arereduced and the closed-loop gain is 10V/V.

Figure 10. Power Amp Driving 1Ω Load Figure 11. Power Amp at 6A Current Limit

INPUT

OUTPUT

INPUT

OUTPUT0V

0V

0V

0V

Figure 9. Power Op Amp AV = 10

7

3

6

ILIM+

VOUT

ILIM–

LT1166

VT

VBOT

100Ω

0.33Ω

0.33Ω

1Ω

4

15mA

1

15mA

100Ω

MPS2222

110Ω

110Ω

5.1k

5.1k

+440µF

15V

–15V

VIN39k 2

1166 • F09

300pF

300pF

MPS2907

IRF530

IRF9530

1µF

1µF

1k

1k

LT1004-2.5

LT1004 2.5

–

+

CF 500pF 0.1µF

0.1µF

1k LT1360

76

4

3

2

909Ω

500pF

100Ω +440µF

SENSE+

SENSE–

8

5

VIN

VOUT

APPLICATIONS INFORMATION

WU UU1166 • F10 1166 • F11

10

LT1166

1A Adjustable Voltage Reference

The circuit in Figure 12 uses the LT1166 in a feedback loopwith the LT1431 to make a voltage reference with an“attitude.” This 5V reference can drive ±1A and maintain0.4% tolerance at the output. If other output voltages aredesired, external resistors can be used instead of theLT1431’s internal 5k resistors.

HIGH VOLTAGE APPLICATION CIRCUITS

In order to use op amps in high voltage applications it isnecessary to use techniques that confine the amplifier’s

common mode voltage to its output. The following appli-cations utilize amplifiers operating in suspended-supplyoperation (Figure 13). See “Linear Technology Magazine”Volume IV Number 2 for a discussion of suspendedsupplies. The gain setting resistors used in suspended-supply operation must be tight tolerance or the gain will bewrong. For example: with 1% resistors the gain can be asfar off as 75%, but with 0.1% resistors that error is cut toless than 5%. Using the values shown in Figure 13, theformula for computing the gain is:

AV = = –11.22R8(R9 + R10) (R8 • R9) – (R7 • R10)

OUT

1166 • F13

–

+

R8 1k

R7 10k

R9 9.1k

R10 1k

IN

Figure 13. Op Amp in Suspended-Supply Operation

8

7

3

6

5

SENSE+

ILIM+

VOUT

ILIM–

SENSE–

LT1166

VTOP

VBOTTOM

100Ω

1Ω

1Ω

5k

5k

4

1

100Ω

12V

VIN2k

1387

65

4

1166 • F12

1µF

1µF

1k

1k

100Ω

100Ω12V

12V

220µF+

5VOUT2

1k

COLV+

2.5V

REFRTOP RMID

GND/SENSE– GND FORCE

–

+

LT1431 IRF9530

IRF530

Figure 12. ±1A, 5V Voltage Reference

APPLICATIONS INFORMATION

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11

LT1166

Parallel Operation

Parallel operation is an effective way to get more outputpower by connecting multiple power drivers. All that isrequired is a small ballast resistor to ensure currentsharing between the drivers and an isolation inductor tokeep the drivers apart at high frequency. In Figure 14 onepower slice can deliver ±6A at 100VPK, or 300W RMS into16Ω. The addition of another slice boosts the poweroutput to 600W RMS into 8Ω and the addition of two ormore drivers theoretically raises the power output to1200W RMS into 4Ω. Due to IR loss across the sense

resistors, the FET RON resistance at 10A, and somesagging of the power supply, the circuit of Figure 14actually delivers 350W RMS into 8Ω. Performance photosand a THD vs frequency plot are included in Figure 15through 18. Frequency compensation is provided by the2k input resistor, 180µH inductor and the 1nF compensa-tion capacitors. The common node in the auxiliary powersupplies is connected to amplifier output to generate thefloating ±15V supplies.

Figure 14. 350W Shaker Table Amplifier

8

7

3

6

5

SENSE+

ILIM+

VOUT

ILIM–

SENSE–

LT1166

VTOP

VBOTTOM R11 100Ω

R4 0.22Ω

R17 0.22Ω

R3 0.22Ω

4

1

R2 100Ω

2N3904

R12 100Ω

R1 100Ω

VIN

RIN 2k 2

1166 • F14

1nF

1nF

2N3906

IRF230

C1 1µF

C2 1µF

R5 1k

R6 1k

–

+LT1360

7

6

4

3

2

100V

–100V

L1** 0.4µH

L3*** 1.5µH

180µH

FB

FB

POWER SLICE

POWER SLICE

R8* 1k

R7* 10k

R15 390Ω

R10* 1k

R9* 9.1k

C4 0.1µF

LT1004-2.5

LT1004-2.5

15V

–15V

VIN

R13 200Ω

C3 3300pF

R16 390Ω

+10µF

+10µF

R14 1k

1Ω

10A FAST-BLOW

VOUT

+C5 220µF 25V

+C6 220µF 25V

C7 1000µF 35V

C8 1000µF 35V

–15V

15V~

~

+

–

110V AC

DIODE BRIDGE

+

+

7815

7915

0.1% RESISTORS 4 TURNS T37-52 (MICROMETALS) 6 TURNS T80-52 (MICROMETALS)

* **

***

–12.5V

12.5V

IRF9240

AUXILARY SUPPLIES

APPLICATIONS INFORMATION

WU UU

12

LT1166

100W Audio Power Amplifier

The details of a low distortion audio amplifier are shown inFigure 19. The LT1360, designated U1, was chosen for itsgood CMRR and is operated in suspended-supply mode ata closed-loop gain of –26.5V/V. The ±15V supplies of U1are effectively bootstrapped by the output at point D andare generated as shown in Figure 14. A 3VP-P signal at VINwill cause an 80VPP output at point A. Resistors 7 to 10 setthe gain of – 26.5V/V of U1, while C1 compensates for theadditional pole generated by the CMRR of U1. The rest ofthe circuit (point A to point D) is an ultralow distortionunity-gain buffer.

The main component in the unity-gain buffer is U4(LT1166). This controller performs two important func-tions, first it modifies the DC voltage between the gates ofM1 and M2 by keeping the product of the voltage acrossR20 and R21 constant. Its secondary role is to performcurrent limit, protecting M1 and M2 during short circuit.

The function of U3 is to drive the gates of M1 and M2. Thisamplifier’s real output is not point C as it appears, butrather the Power Supply pins. Current through R6 is usedto modulate the supply current and thus provide drive toVTOP and VBOTTOM. Because the output impedance of U3(through its supply pins) is very high, it is not able to drivethe capacitive inputs of M1 and M2 with the combinationof speed and accuracy needed to have very low distortionat 20kHz. The purposes of U2 are to drive the gatecapacitance of M1 and M2 through its low output imped-ance and to reduce the nonlinearty of the M1 and M2transconductance. R24, C4 set a frequency above whichU2 no longer looks after U3 and U4, but just looks afteritself as its gain goes through unity. R1/R2 and C2/C3 arecompensation components for the CMRR feedthough.Curves showing the performance of the amplifier areshown in Figures 20 through 22.

FREQUENCY (Hz)10

0.01

TOTA

L HA

RMON

IC D

ISTO

RTIO

N (%

)

0.1

1.0

1k 100k100 10k

LT1166 • F18

PO = 350W RL = 8Ω

Figure 18. THD vs FrequencyFigure 16. Clipping at 1kHz, RL = 8Ω

APPLICATIONS INFORMATION

WU UU

1166 • F15

Figure 15. 0.3% THD at 10kHz, PO = 350W, RL = 8Ω

1166 • F16

1166 • F17

Figure 17. 2kHz Square-Wave, CL = 1µF

13

LT1166

8 7 3 6 5

SENS

E+

I LIM

+

V OUT

I LIM

–

SENS

E–

U4

LT11

66

V TOP

V BOT

TOM

R21

0.22

Ω

R20

0.22

Ω

41

R18

100Ω

R14

500Ω

R17

500Ω

V IN

2

1166

• F

18

M1

IRF5

30

M2

IRF9

530

C10

1µF

C11

1µFR1

9 1k R2

2 1k

– +

U3

LT13

60

7

6

4

3 2

L1

1µH

R4

1k

LT10

09-2

.5

LT10

09-2

.5

R23

10Ω

V OUT

C14

0.1µ

FC1

5 22

µF

+

C6

22µF

+

–50V

C12

0.1µ

FC1

3 22

µF+

50V

C7

0.01

µF

R5

3.3k

C5

3300

pF

R16

30Ω

C9

0.01

µF

R13

30Ω

R15

100Ω

+ –15V

**

2N39

04

R12

100Ω

C8

22µF

+

+ –15V

**

2N39

06

R11

100Ω

R3

10k

–+U2

LT

1363

7

6

4

3 2

C2

470p

FR2

10

0Ω

R1

100Ω

C4

20pF

C3

470p

F

C

B

A

R24

2.4k

– +

7

6

4

3 2

U1

LT13

60

R10*

1k

R8*

1k

R9*

9.6k

R7*

10k

C1

10pF

D

* 0

.1%

RES

ISTO

RS

** S

EE P

OWER

SUP

PLY

OF F

IGUR

E 13

R6

160Ω

V IN

Figu

re 1

9. 1

00W

Aud

io A

mpl

ifier

APPLICATIONS INFORMATION

WU UU

14

LT1166

RL = 8Ωf = 8kHz

RL = 8Ωf = 20kHz

Figure 20. Square Wave Response Into 8Ω Figure 21. 100W 20kHz Sine Wave and Its Distortion

FREQUENCY (Hz)10

0.001

TOTA

L HA

RMON

IC D

ISTO

RTIO

N (%

)

0.01

0.1

1k 100k100 10k

LT1166 • F21

RL = 8Ω POWER OUT = 100W

Figure 22. THD vs Frequency

APPLICATIONS INFORMATION

WU UU

1166 • F20 1166 • F21

15

LT1166

SCHEMATIC WW

SI PLIFIED

VAB+

VAB–

1k

1k

R1 200Ω

R2 200Ω

8

7

1

32

5

6

4

Q7 × 10

Q8 × 10

Q9 × 1

Q10 × 1

–

+

–

+

Q11

Q12

Q1

Q2

IREF

IREF 10

SHUNT REGULATOR

1166 • SS

Q4 × 32

Q3 × 1

Q6 × 32

Q5 × 1

VTOP

SENSE+

VBOTTOM

SENSE–

ILIM–

VOUT

ILIM+

VIN

N8 0695

0.005 (0.127)

MIN

0.100 ± 0.010 (2.540 ± 0.254)

0.065 (1.651)

TYP

0.045 – 0.065 (1.143 – 1.651)

0.130 ± 0.005 (3.302 ± 0.127)

0.015 (0.380)

MIN

0.018 ± 0.003 (0.457 ± 0.076)

0.125 (3.175)

MIN

1 2 3 4

8 7 6 5

0.255 ± 0.015* (6.477 ± 0.381)

0.400* (10.160)

MAX

0.009 – 0.015 (0.229 – 0.381)

0.300 – 0.325 (7.620 – 8.255)

0.325+0.025 –0.015+0.635 –0.3818.255( )

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

Dimensions in inches (millimeters) unless otherwise noted.PACKAGE DESCRIPTIONU

N8 Package8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

16

LT1166

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1995

LT/GP 1195 6K • PRINTED IN USA

Dimensions in inches (millimeters) unless otherwise noted.PACKAGE DESCRIPTION

U

S8 Package8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

1 2 3 4

0.150 – 0.157** (3.810 – 3.988)

8 7 6 5

0.189 – 0.197* (4.801 – 5.004)

0.228 – 0.244 (5.791 – 6.197)

0.016 – 0.050 0.406 – 1.270

0.010 – 0.020 (0.254 – 0.508)

× 45°

0°– 8° TYP0.008 – 0.010

(0.203 – 0.254)

SO8 0695

0.053 – 0.069 (1.346 – 1.752)

0.014 – 0.019 (0.355 – 0.483)

0.004 – 0.010 (0.101 – 0.254)

0.050 (1.270)

BSCDIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

*

**

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