Model Question PaperSubject Code: BC0036Subject Name: Digital systemsCredits: 4 Marks: 140Part A (One mark questions)

1. Position of each bit in a given sequence has a numerical __________A) DigitB) DataC) ErrorD) Weight.

2. 1101(2) is equal to __________________in decimal number system.A) 12(10)B) 13(10)C) 14(10)D) None of the above

3. Repeated multiplication method is the more systematic method usually used in_____________ part of decimal number in decimal to binary conversion.A) fractionalB) IntegerC) differentialD) None of the above

4. Binary Equivalent of (17.125)10 is ________________A) 1 0 0 0 1 . 0 1 1 0B) 1 0 0 1 . 0 0 1 0C) 1 0 0 0 1 . 0 0 1 0D) 1 0 0 1 1 . 0 0 1 0

5. In the year ____, the mathematician George Boole published a book entitled “AnInvestigation of the Laws of Thought on Which Are Founded the Mathematical Theories ofLogic and Probabilities”.A) 1897B) 1854.C) 1856D) 1990

6. If A is an input to the NOT gate, then its output is given by

A) AB) AC) AIID) None of the above

7. If a and b are the inputs of an OR gate and x is the output, then x is given byA) x = abB) x = a-bC) x a bD) None of the above

8. The output of the NAND gate is high only when________A) All inputs are highB) Only one input is lowC) All inputs are lowD) One or more inputs are low

9. SOP stands for __________________A) Sum of productsB) Set of productsC) Set of presetsD) Sound of products

10. mSummation notation with the prefix m is used to indicate _______expression.A) POSB) SOPC) MaxtermD) None of the above

11. To realize AND gate using only NAND gates, we require____NAND gatesA) 2B) 3C) 4D) 5

12. Advantage of simplifying an expression is _____________A) Time savingB) Easy to rememberC) Simple gate network.D) Simple procedure

13. Karnaugh Map consists of an arrangement of ___________A) GatesB) BoxesC) Cells.D) None of the above

14. The cells in a __________are arranged in such a way that there is only a one bit or one variable change between any two adjacent cells.A) Karnaugh MapB) Quine McClusky methodC) Truth tableD) None of the above

15. While simplifying the expression in Karnaugh Map, Variables that appear in both uncomplemented and complemented are_____________.A) RetainedB) EliminatedC) addedD) None of the above

16. Simplification of a given logical expression with Quine McClusky method involves in the computation of _________from which minimal sum should be selected.A) CellsB) MaxtermsC) SubsetD) Prime implicants

17. _____________circuit accepts two binary digits as inputs and produces two outputs sum and carry.A) Full adderB) Half adderC) MultiplexerD) Decoder

18. __________is constructed using only one AND gate and an EX-OR gate.A) MultiplexerB) EncoderC) Half adderD) Full adder

19. Full adder can be realized using two_______A) MultiplexersB) DecodersC) Half subtractorsD) Half adders

20. A logic circuit called__________ performs the subtraction of two bits with borrow generated if any, during the previous LSB subtraction.A) Full subtractor.B) Half subtractorC) DecoderD) Encoder

21. The fundamental components of shift registers and counters are_________A) Flip-flopsB) SubtractorsC) AddersD) None of the above

22. The difference between a latch and a flip-flop lies in the method used for changing their_________A) Input stateB) Output stateC) Circuit elementsD) None of the above

23. When S=1 and R=0, the output of a SR latch is____________A) InvalidB) ResetC) SetD) None of the above

24. When a HIGH voltage level on the EN pin enables or controls the output of the latch, then gated latches are also known as __________latchesA) Edge triggeredB) Level triggeredC) TransparentD) None of the above

25. Flip-flops are used in____________A) Adder

B) MultiplexerC) Priority encoderD) Digital counter

26. Asynchronous counters are also known as ____________A) Ripple counters.B) Parallel countersC) System countersD) None of the above

27. A single flip-flop can be treated as a ____________A) mod-2 counterB) mod-1 counterC) mod-3 counterD) None of the above

28. Which of the following statements is true?A) The counting sequence of Mod-6 counter is 001 010 011 100 101 000110.B) The number of flip-flops required to design a decade counter is 3.C) In ripple counters all the flip-flops are made to change the states exactly at the same time.D) With two flip-flops four output states can be counted. Hence it is referred to as mod-4 counter.

29. In synchronous counters, all the flip-flops are connected to a same clock signal and changes state at the ___________A) Same time.B) Different timeC) Irregular intervals of timeD) None of the above

30. An up/down counter is also referred as a ___________counter.A) DoubleB) SystematicC) BidirectionalD) Universal

31. A synchronous counter has the ____________of counting as that of a ripple counter.A) Same time

B) Same sequenceC) Different sequenceD) Different sets

32. Most often in synchronous counter design, __________are usedA) S-R flip-flopsB) D flip-flopsC) J-K flip-flopsD) None of the above

33. Shift registers is an example of ___________ type of logic circuitsA) MathematicalB) CombinationalC) SequentialD) Analog

34. Serial-in, serial-out shift registers delay data by ______ clock time for each stage.A) FourB) ThreeC) TwoD) One

35. 74LS395 is a ________registerA) Serial in-Serial outB) UniversalC) Parallel in –Serial outD) Serial in Parallel out

36. In ________ the output of a shift register is fed back to the input.A) Ring CounterB) Parallel in –Serial out RegisterC) Serial in Parallel out RegisterD) Johnson Counter

37. The main disadvantage of the Binary weighted DAC is thatA) It requires more spaceB) It is difficult to understandC) It requires a wide range of binary weighted resistors that may not be practically available.D) Sometimes it will not give the expected results.

38. Flash type of ADC is also called as the ____________A) Serial ADCB) Parallel ADCC) Lash ADCD) None of the above

39. __________is the disadvantage of a single slope integrator ADC.A) Conversion timeB) SpeedC) Calibration driftD) Presence of an op-amp

40. If an ADC circuit has a sample frequency of 5000 Hz, the highest-frequency waveform it can successfully resolve isA) 10000 HzB) 2500 HzC) 500 HzD) 1000 Hz

Part B (Two mark questions)

41. To convert a given octal number to_______, simply replace the octal digit by itsequivalent __________representation.A) Binary, 4-bit binaryB) Binary, 3-bit binaryC) Decimal, 4-bit binaryD) Decimal, 3-bit binary

42. The _________Number System uses base 16 and the value of D is equal to______ indecimal.A) Octal, 13B) Binary, 12C) Hexadecimal, 13D) Hexadecimal, 14

43. If a and b are the inputs and x is the output, then the NOR gate output is equal to ________and XOR gate output is given by _____________A) x a b , x abB) x ab , x ab

C) x a b , x a bD) x a b , x ab

44. Associative law of addition is given by_______________ and Distributive law is givenby________________A) a . (b + c) = (a + b) + c , a . b . c = (a . b) . (a . c)B) a + (b . c) = (a + b) + c , a . (b + c) = (a . b) + (a . c)C) a + (b + c) = (a + b) + c , a . (b + c) = (a . b) + (a . c)D) None of the above

45. _________and __________ gates are called universal gates.A) NAND and ORB) NAND and NORC) AND and NORD) NAND and NOT

46. In Boolean algebra the product of two variables can be represented with _______functionand sum of any two variables can be represented with _________function.A) AND, NORB) NAND, ORC) AND, NANDD) AND, OR

47. A more systematic method of minimizing expressions of larger number of variables is____________method and is also known as ____________A) Karnaugh Map, tabular methodB) Quine McClusky, cells methodC) Karnaugh Map, cells methodD) Quine McClusky, tabular method,

48. Which of the following statements are correct?i. Karnaugh map can be used to simplify the expressions consisting of more than 6variables.ii. The simplified expression for a given logic function consists of all essential primeimplicants and one or more prime implicants.iii. A three variable Karnaugh Map map consists of 8 cells and a four variable KarnaughMap map consists of 16 cells.iv. In prime implicant chart all prime implicants found in column wise and all minterms in

row wise.A) i and iiB) ii and ivC) ii and iiiD) i, ii and iv

49. Half subtractor circuit accepts two binary digits as inputs and produces twooutputs _________ and ________A) Sum ab , Carry ab .B) Sum ab , Borrow abC) Diff ab,Carry abD) Diff ab, Borrow ab

50. ____________is an un weighted code and exhibits only a _________change from one code number to the next.A) Gray code, single bitB) Gray code, two bitC) BCD code, single bitD) BCD code, two bit

51. A ________can be thought of a ________ as it stores 1 bit of information over a specific time.A) Combinational circuit, shift registerB) Multiplexer, shift registerC) Decoder, memory unitD) Flip-flop, Memory unit

52. The _______existed in SR latch is avoided in D latch because ______ gate is connected between S and R inputs.A) Valid condition, ANDB) Invalid condition, ORC) SET condition, NOTD) Invalid condition, NOT

53. __________is a 4-bit Binary Counter and it consists of one single flip-flop and a 3-bit__________counter.A) IC 7497, asynchronousB) IC 7493, asynchronousC) IC 7493, synchronousD) IC 7496, synchronous

54. __________consists of one single flip-flop ______and a ________asynchronous counter.A) IC 7493, mod-5B) IC 7490, mod-5C) IC 7493, mod-4D) IC 7490, mod-8

55. Select the correct statements from the following.i. In synchronous counters, all flip-flops are driven by the different clock pulses.ii. The design complexity is more in synchronous counters than the asynchronous counters.iii. The sequence of states changes from a lower state to the upper state in up counters.iv. A three-bit synchronous binary up counter counts from 100 to 110 onlyA) i and ivB) i and iiiC) ii and ivD) ii and iii

56. A synchronous _________is one that is capable of counting in either direction through a certain__________.A) up-down counter, sequenceB) down counter, sequenceC) up counter, setD) None of the above

57.The binary number 1011 is serially shifted into an four-bit parallel out shift register that has an initial content of 1110.What are the Q outputs after two clock pulsesA) 1100B) 1011C) 1111D) 1010

58. The binary number 1011 is serially shifted into an four-bit serial out shift register that has an initial content of 1110.What is the content of the register after two clock pulsesA) 1100B) 1011C) 1010D) 1111

59. The important considerations of ADC circuitry are its ________and__________.

A) Resolution, sample frequencyB) Resolution, SpeedC) Conversion time, sample frequencyD) Conversion time, discrete steps

60. If an ADC is subjected to an analog input signal whose frequency exceeds the Nyquist frequency for that ADC, the converter will output a digitized signal of falsely________. This phenomenon is known as __________A) Low frequency, aliasing.B) High frequency, aliasing.C) Low frequency, acquisitionD) High frequency, acquisition

Part C (Four mark questions)

61. Match the followinga) BCD i. Fraction partb) Repeated multiplication ii. Subtraction c) Hexadecimal Number iii. Weighted code d) Complementary method iv. Alpha-numeric symbols A) a-iii, b-i, c-iv, d-ii B) a-ii, b-i, c-iv, d-iii C) a-iii, b-i, c-ii ,d-iv D) a-i, b-iii, c-iv, d-ii

62. State whether the following statements are True (T) or False (F) a. The Decimal Number System uses base 10 and represented by arranging the 9 symbols i.e. 1 through 9, where these symbols were known as digits. b. Counting with octal number system is analogous to the counting methodology used in decimal and in binary numbering system.c. There are totally 7 combinations with 3-bit binary representation from 001 to 111, which can be mapped octal symbols 0 to 6.d. 1‟s complement method is useful in the sense subtraction can be carried with addercircuits of ALU (Arithmetic logic unit) of a processor.A) a-T, b-F, c-T, d-FB) a-F, b-F, c-T, d-FC) a-F, b-T, c-F, d-TD) a-T, b-T, c-F, d-F

63. Match the followinga) a + b = b + a i. OR ruleb) a a 1 ii. Associative rule

c) a b c a b c iii. Commutative lawd) iv. Demorgan‟s TheoremA) a-iii, b-i, c-iv, d-iiB) a-ii, b-i, c-iv, d-iiiC) a-iii, b-i, c-ii ,d-ivD) a-i, b-iii, c-iv, d-ii

64. State whether the following statements are True (T) or False (F)a. NAND operation can be thought as NOT of the ORed inputs.b. Distributive law states that the net result remain same irrespective grouping of thevariables for OR operationc. NOT function represents a logical inversion or negation.d. Three input AND operation can be give by x = a. b. cA) a-T, b-F, c-T, d-F B) a-F, b-F, c-T, d-T C) a-F, b-T, c-F, d-T D) a-T, b-T, c-F, d-F

65. Match the following a) Clock waveform i. Gate circuitry b) Propagation delay ii. OR function.c) Product of two variables iii. Rectangular pulsed) Sum of any two variable iv. AND function A) a-iii, b-i, c-iv, d-ii B) a-ii, b-i, c-iv, d-iii C) a-iii, b-i, c-ii ,d-iv D) a-i, b-iii, c-iv, d-ii

66. State whether the following statements are True (T) or False (F) a) SOP and are OSP are the two representations of a given Boolean expressions.b) The forms of the Boolean expression doesnot determine how many logic gates are used and what types of gates are needed for the realization and their interconnection.c) Boolean rules and laws are used to simplify the logic function and realize the minimized function using basic gates. d) A most popular method of representation of SOP form is with the minterms. A) a-T, b-F, c-T, d-F B) a-F, b-F, c-T, d-T C) a-F, b-T, c-F, d-T D) a-T, b-T, c-F, d-F

67. Match the following a) Qunie McClusky method i. Arrangement of cellsb) Karnaugh Map ii. Not a systematic method

c) Two input variables iii. Hand computationd) Boolean algebra iv. Four cell map A) a-iii, b-i, c-iv, d-ii B) a-ii, b-i, c-iv, d-iii C) a-iii, b-i, c-ii ,d-iv D) a-i, b-iii, c-iv, d-ii

68. State whether the following statements are True (T) or False (F) a) A four variable map consists of 24 = 16 cells.b) For an „n‟ number of variables the total number of combinations possible are 2n, hence Karnaugh Map consists of 2n cells.c) Qunie McClusky method is not suitable for the soft program implementation.d) Qunie McClusky method cannot be used for more than 4 variables. A) a-T, b-F, c-T, d-F B) a-F, b-F, c-T, d-T C) a-F, b-T, c-F, d-T D) a-T, b-T, c-F, d-F

69. Match the following a) BCD code i. a > b b) Comparator ii. Data select linesc) Gray code iii. Weighted coded) Multiplexer iv. Un-weighted code A) a-iii, b-i, c-iv, d-ii B) a-ii, b-i, c-iv, d-iii C) a-iii, b-i, c-ii ,d-iv D) a-i, b-iii, c-iv, d-ii

70. State whether the following statements are True (T) or False (F)a) In Binary to Gray conversion, the most significant bit (MSB) in the Gray code is the same as the corresponding digit in the binary numberb) Decimal to BCD encoder is also known as 10 lines to 4 line encoder. c) A decoder accepts an active level on one of its inputs representing digit, such as decimal or octal and converts it to a coded output such as binary or BCD.d) Binary to octal encoder is also known as 3 lines to 8 line decoder; the output is activated upon the input on its 8 lines. A) a-T, b-F, c-T, d-F B) a-F, b-F, c-T, d-T C) a-F, b-T, c-F, d-T D) a-T, b-T, c-F, d-F

71. Match the following a) Latch i. SR latchb) Invalid condition ii. Negative edge triggering

c) A triangle with a bubble at the clock terminal iii. Bistable deviced) Edge triggering iv. Flip-flopA) a-iii, b-i, c-iv, d-iiB) a-ii, b-i, c-iv, d-iiiC) a-iii, b-i, c-ii, d-ivD) a-i, b-iii, c-iv, d-ii

72. Match the followinga) IC 7490 i. Mod 4 counterb) Two bit counter ii. 2 counter.c) Ripple counters iii. Decade counterd) Single flip-flop iv. Cascade connectionA) a-iii, b-i, c-iv, d-iiB) a-ii, b-i, c-iv, d-iiiC) a-iii, b-i, c-ii ,d-ivD) a-i, b-iii, c-iv, d-ii

73. State whether the following statements are True (T) or False (F)a) In a synchronous up-down counters, for the Up sequence, QB changes state on the nextclock pulse when QA = 1 where as for the Down sequence, QB changes state on the nextclock pulse when QA = 0.b) In a three-bit up/down synchronous counter, the output Q of the second flip-flop cannotbe directly connected to the J and K inputs of third flip-flop.c) In a three-bit up/down synchronous counter, up/down terminal is not required.d) In a two bit synchronous up counter with negative edge triggering, when the negativeedge of the first clock pulse is applied, output of first flip-flop does not toggle.A) a-T, b-F, c-T, d-F B) a-F, b-F, c-T, d-T C) a-F, b-T, c-F, d-T D) a-T, b-T, c-F, d-F

74. Match the followinga) Number of bits a flip-flop can store i. 7b) Number of clock pulses required to ii 2Shift a 4 bit data into and out of a fourBit serial in-serial out shift registerc) Number of stages we need for a divide iii 4By 2 ring counter?

d) Number of stages required to iv 1Implement divide by 8 Johnson counterA) a-iii, b-i, c-iv, d-ii B) a-ii, b-i, c-iv, d-iii C) a-iii, b-i, c-ii, d-iv D) a-iv, b-i, c-ii, d-iii

75. Which of the following are the typical applications of Analog to Digital Converters?i. Digital voltmeters,ii. Pen drive and CRT iii. Microprocessor interfacing iv. LED/LCD displaysv. Memory unit, and mouseA) i and iii only B) ii and v only C) i ,iii and iv only D) ii,iii and v only

Answer KeysPart – A Part – B Part - CQ. No.Ans. Q. No.Ans. Q. No.Ans. Q. No.Ans.1 D 21 A 41 B 61 A

2 B 22 B 42 C 62 C

3 A 23 C 43 A 63 C

4 C 24 B 44 C 64 B

5 B 25 D 45 B 65 A

6 B 26 A 46 D 66 B

7 C 27 A 47 D 67 A

8 D 28 D 48 C 68 D

9 A 29 A 49 D 69 A

10 B 30 C 50 A 70 D

11 A 31 B 51 D 71 C

12 C 32 C 52 D 72 A

13 C 33 C 53 B 73 D

14 A 34 D 54 B 74 D

15 B 35 B 55 D 75 C

16 D 36 A 56 A

17 B 37 C 57 C

18 C 38 B 58 D

19 D 39 C 59 A

20 A 40 B 60 A