M68K Assembly Language Programming

Bob Britton

Chapter 2

The M68K Architecture

Notice: Slides in this series originally, provided by B.Britton, have been modified by R.Renner to reflect Spring 2006 course content.

Program Counter (PC)

Instruction Register

ALU

Data In

Out

Rd Rs

Control

Logic

Memory

# Immediate

DataOut

AddressD0D1...D6D7A0A1A2...A6A7

XNZVC

M68K Datapath Diagram

The Basic Functional Components

• Control Unit

• Data Registers D0 through D7 and Address Registers A0 through A7

• Arithmetic and Logic Unit (ALU)

• Program Counter (PC)

• Memory

• Instruction Register (IR)

Buses & Data Selectors• A bus is nothing more than a set of electrical

conducting paths over which different sets of binary values are transmitted. (32 tiny wires)

• Every data selector with two input buses must have a single control wire connected to it. The control unit sends a control signal of zero or one to select which input bus should be routed to the output of the data selector.

Registers

The M68K architecture has a register file containing 16 registers. Each register has a capacity to hold a 32-bit value. The range of signed decimal values that can be represented in binary with 32 bits is -2,147,483,648 (-231) to +2,147,483,647 (231-1).

A 32-bit register is constructed from 32

flip-flops (a digital circuit containing feedback)

ALU

The ALU is a digital logic circuit designed to perform 32-bit binary integer addition & subtraction, as well as 32-bit binary logical operations such as AND, OR, NOT and XOR.

Which operation the ALU performs depends upon the operation code in the instruction that has been fetched from memory. (Combinational Circuit)

Multiplication, and division are accomplished by performing a sequence of 16 additions/subtractions.

Example Logical AND instruction

AND.B D0, D7

00011101 (D0)

00001110 (D7)00001100 (D7 new)

Example Logical OR instruction

OR.B D0, D7

00011101

0000111000011111

Example of Binary Addition

ADD.B D0, D7

Decimal Binary

29 00011101 (D0)

14 00001110 (D7)

Sum = 43 00101011 (D7 new)

Program Counter (Pointer)

The Program Counter (PC) is a register that is initialized by the operating system to the address of the first instruction of your program in memory. Notice that the address in the program counter is routed to the address input of the memory via a bus.

Memory• Memory can be thought of as a large array of

locations where binary information is stored and from which binary information can be fetched. The M68K defines three data types:– A byte refers to an 8-bit quantity– A word refers to a 16-bit quantity (two bytes)– A long-word refers to a 32-bit quantity (four

bytes)

• Each location in memory has a unique 32-bit address, so memory addresses range from 0 to 4,294,967,295 (232-1).

Fetch Execute Cycle1. Instruction Fetch Phase – An instruction is fetched from memory at

the location specified by the Program counter. The instruction is loaded into the Instruction Register. The Program Counter is incremented to point to the next sequential instruction.

2. Operand Fetch Phase – Fields within the instruction contain binary codes that specify which registers should be accessed and routed to the ALU. The code for size will control how many bits are sent to the ALU.

3. Execute Phase – The ALU performs the operation which is specified by the opcode in the instruction.

4. Write Back Phase – The result of the operation is placed back into the same register where Source#2 came from. Go to step 1.

Instruction Register• The Instruction Register (IR) holds a copy of the most

recently fetched instruction. The M68K architecture has many different instruction formats, at the hardware encoding level, but for the assembly language programmer most instructions have the following format:

Opcode.Size Source#1, Source#2/Destination *Comment

• Notice that the destination for the computed result, be it a register or a memory location, is the same location as the second operand. In other words, the original value is wiped out.

(this trade-off was used to conserve memory space for programs)

Example of M68K instruction

ADD.L (A2), D5 * Memory[A2] + D5 D5

• opcode mnemonic is: ADD

• The size of the values to be added together can be 8-bits (a byte) “.B”, 16-bits (a word) “.W”, or 32-bits (a long-word) “.L”, as in this example.

• In this example Source#1 is a 32-bit value in memory at a location pointed to by register A2. Here we are assuming that an address has been placed in address register A2 by some previous instruction. This is an example of an addressing mode call “address register indirect”.

• In this example, the second operand field specifies that the present contents of data register “D5” will be added to the value accessed from memory (Source#1) and the result of the addition will be placed back into data register D5.

• The last field contains a comment. The asterisk at the beginning of the comment field is optional. In this example, the pseudo-code equivalent of this assembly language instruction is provided to aid the reader in understanding the assembly language code. Comments are used to document a program.

Instruction Set• Arithmetic instructions to add, subtract, multiply and divide

• Instructions to MOVE a copy of information from a source to a destination

• Logical bit-wise instructions AND, OR, EOR (exclusive-or) and NOT

• A set of conditional branch instruction BCC to implement control structures

• Instructions to branch to a subroutine BSR, and return from a subroutine RTS

• The instruction LEA to Load an Effective Address into an address register

• Instructions CMP and CMPA that are used to compare two values for less than equal to or greater than

• A TRAP instruction that is used to request an input or output (I/O) service from the operating system, such as to display values in their decimal representation or to print a string of characters; as well as a system service that will take input

The Load Effective Address Instruction

Given that there is a place in memory that corresponds to the label “Message”, we can specify that when the program runs we want register A0 to be loaded with the binary address in memory of the first character of the string that we have labeled “Message”.

LEA Message, A0 * Address of “Message” A0

Assembler Directives

The following is an example of the define constant bytes DC.B directive that specifies that we want to initialize memory with the string of ASCII characters “Hello World” terminated with the ASCII null character zero, referenced with the label “Message”.

Message DC.B ‘Hello World’, 0

Addressing Modes

The six addressing modes we will initially discuss are:

• Dn Data register direct: Operand in Dn

• An Address register direct: Operand in An

• (An) Address Register Indirect: An is a pointer to a memory location

• (An)+ Address register indirect with post auto increment

• (d, An) Address register indirect with displacement

• #n Immediate -- Constant operand stored as an extension of the instruction

Appendix AQuick Reference to Fundamental M68K InstructionsOpcode Size Operands CCR Six Address Modes Operation

bwl xnzvc Dn An (An) (An)+ (d,An) #n ADDbwl sor, Dn ***** sor sor sor sor sor sor (sor + Dn) Dn

Dn, des ***** des --- des des des --- (Dn + des) desADDA wl sor, An ------- sor sor sor sor sor sor (sor + An) AnANDbwl sor, Dn -**00 sor --- sor sor sor sor (sor AND Dn) Dn

Dn, des -**00 des --- des des des --- (Dn AND ds) dsBcc bw label ------- --- --- --- --- --- --- If cc true then (PC + d) PCBSR bw label ------- --- --- --- --- --- --- PC- (SP); ( PC+d) PCCLR des -0100 des --- des des des --- 0 Dn CMP bwl sor, Dn -**** sor sor sor sor sor sor Set CCR with (sor - Dn)CMPA wl sor, An -**** sor sor sor sor sor sor Set CCR with (sor - An)DIVS w sor, Dn -***0 sor --- sor sor sor sor 32-bit Dn / 16-bit sor Dn (r:q)EOR bwl Dn, des -**00 des --- des des des --- (Dn XOR des) desLEA l sor, An ------ --- --- sor sor sor --- “sor” address AnMOVE* bwl sor, des -**00 s*d sor s*d s*d s*d sor sor desMOVEA wl sor, An ------ sor sor sor sor sor sor sor An

* For the MOVE instruction the notation “s*d” means that the addressing mode corresponding for this column can be used in both the source and destination. No other M68K instruction has such broad addressing flexibility. Most other instructions require that either the source or the destination be specified as a register.

Appendix A (Continued)Quick Reference to Fundamental M68K InstructionsOpcode Size Operands CCR Six Address Modes Operation

bwl xnzvc Dn An (An) (An)+ (d,An) #nMULS w sor, Dn -**00 sor --- sor sor sor sor 16-bitDn x 16-bit sor DnNOT bwl des -**00 des --- des des des --- !!!!!!!!!!( des) des OR bwl sor, Dn -**00 sor --- sor sor sor sor (sor OR Dn) Dn

Dn, des -**00 des --- des des des --- (Dn OR des) desRTS ----- --- --- --- --- --- --- (SP)+ PCSUB bwl sor, Dn ***** sor --- sor sor sor sor (sor - Dn) Dn

Dn, des ***** des --- des des des --- (Dn - des) desSUBA wl sor, An ------- sor sor sor sor sor sor (sor - An) AnTRAP #n ------- --- --- --- --- --- --- Request a system service TST bwl des -**00 des --- des des des --- N and Z Set to reflect des conditionThe following is a list of the more useful BRANCH instructions. The branch instructions use information in the Condition Code Register (CCR). In most cases the instruction immediately preceding the branch instruction will be the compare (CMP) instruction, or an arithmetic or logic instruction that affects the CCR.Mnemonic Name Mnemonic NameBRA Unconditional Branch BVS Branch if Overflow is SetBGT Branch if Greater Than BVC Branch if Overflow is ClearBGE Branch if Greater or Equal BNE Branch if Not EqualBLT Branch if Less Than BEQ Branch if EqualBLE Branch if Less or Equal BPL Branch if Plus (Positive)BCS Branch if Carry Set BMI Branch if Minus (Negative)BCC Branch if Carry Clear

EXAMPLELet us suppose we want to subtract the 16-bit contents of register D1 from the 16-bit contents of register D2, placing result in the lower half of register D3, without modifying either source operand. Since in this case we do not want the contents of register D2 modified, it is necessary to first move a copy of the value in register D2 into register D3:

move.w D2, D3 * D2 D3

sub.w D1, D3 * D3 - D1 D3

Note: The assembler is case insensitive.

Note: Source#1 is subtracted from Source#2.

MultiplicationThe mnemonic for the signed multiply instruction is

“MULS”. This instruction is only defined for 16-bit (word) operands. It multiplies two 16-bit binary values and produces a 32-bit product which is stored in the destination register. The Source#2/Destination field can only be a register. The following instruction would access 16-bits of data from memory at the location pointed to by address register A7, multiply it by the lower 16-bits of data in register D0 and store the 32-bit product back into register D0. This is an example of address register indirect addressing to get Source#1 from a memory location.

MULS (A5), D0 * D0 x Memory[A5] D0

DivisionThe mnemonic for the signed divide instruction is “DIVS”.

With this instruction there is no size field to specify. The dividend (Source#2) is always taken as 32-bits, and the divisor is always the lower 16-bits from Source#1. The resulting 16-bit remainder and 16-bit quotient will be put into the destination register. The following divide instruction divides the 32-bit binary value in register D3 by the 16-bit value in register D6. The quotient is stored in the lower 16-bits of register D3 and the remainder is stored in the upper 16-bits of register D3. DIVS D6, D3 * 32-bit D3 / 16-bit D6 (Remainder : Quotient) D3

• Note: Source#1 is the 16-bit divisor With the divide instruction two possible run time error conditions that could occur:

• (1) Overflow – which causes the “V” bit in the status register to be set.

• (2) Division by zero – which will cause and exception to be generated and the program will terminate with control passing back to the operating system.

Status Register (CCR)• You will notice there is a register associated with the ALU that has

the letters XNZVC inside. This is the status register, and each letter has the following meaning:

• X : Extend (similar to the carry bit)

• N: Negative

• Z: Zero

• V: Overflow

• C: CarryWhen certain instructions are executed certain bits in the status register are

either set to 1 (True) or cleared to zero (False) to provide information about the resulting value produced by the instruction that was just executed. You will notice in Appendix A there is a column in the table with the heading CCR (Condition Code Register) and below that we see “xnzvc”. You must refer to Appendix A to determine for sure which instructions affect which status bits. Below you see a portion of the table.

Branch InstructionsThe M68K provides instructions to implement control

structures such as:

“if (D6 < 0) then goto QUIT else D6 -1 D6 ”

The above pseudocode states that if the binary number of register D6 is a value less than zero, in other words negative, we want to branch to a location in the program labeled “QUIT.” Otherwise (else) we want to decrement the contents of register D6. The assembly language instructions to accomplish this are:

• TST.L D6 * Test D6• BMI Quit * If N bit is set then branch to Quit• SUB.L #1, D6 * (D6 – 1) D6

Immediate Mode• In the previous section the instruction “SUB.L #1,

D6” provides an example of immediate mode addressing. • Immediate mode addressing should always be used to

specify operands that are constants, because your program will run faster and use less memory space. At the assembly language level the sharp sign “#” indicates immediate mode addressing. At the machine language level the immediate binary value is stored in memory as part of the instruction.

• Notice in the datapath diagram there is a datapath from the right-hand portion of the instruction to the data selector that provides an operand input to the ALU. Immediate mode addressing may only be used to specify a Source#1 operand.

Auto Increment Addressing ModeHere we introduce address register indirect addressing with post-incrementing. This

addressing mode also references memory at the location pointed to by the specified address register, but in addition the contents of the address register, which is a pointer, is then incremented by the amount specified in the size field.

In other words, if the instruction is performing a long-word (4-bytes) operation then the address register is incremented by 4. If the instruction is performing a word (2-bytes) operation then the address register is incremented by 2, and if the instruction is performing a byte operation then the address register is incremented by 1.

Obviously this is a very convenient addressing mode to sequentially access array elements. The following provides an example of the syntax for this addressing mode. To specify this addressing mode you simply place a plus sign (+) after the address register specification.

move.b (A0)+, D6 * Memory[A0] D6 ; then (A0 + 1) A0

Below we have an example of storing a long-word into memory using this post-increment addressing mode.

move.l D2, (A6)+ * D2 Memory[A6]; then (A6 + 4) A6

An Example M68000 Program

STARTORG $1000 * Program origin in MemoryCLR.W D1 * Clear D1 to 0MOVE #12, D7 * Initialize loop counter to 12

LOOPADD.W D7, D1 * D1 + D7 D1SUBQ.W #1, D7 * Decrement loop counterBGT.S LOOP * If (D7 > 0) Branch to LOOPMOVEQ #3, D0 * Code to print an integer is 3TRAP #15 * PrintMOVE.B #9, D0 * The code to halt is 9TRAP #15 * Halt simulationEND START

Exercises

2.1 Explain the difference between a register and the ALU.

2.2 Explain the difference between assembly language and machine language.

2.3 Explain the difference between RAM Memory and the Register File.

2.4 Explain the difference between the Instruction Register and the Program Counter.

2.5 Explain the difference between a bus and a control line.

2.6 Identify a kitchen appliance that contains a control unit that issues control signals.

2.7 What is an algorithm?

2.8 Provide a step-by-step description of the sequence of operations that must take place within a M68K processor to fetch and execute the following instruction:

BEQ Loop

2.9 Provide a step-by-step description of the sequence of operations that must take place within a M68K processor to fetch and execute the following instruction:

MOVE.L (A0), D0

Quick Reference to Fundamental I/O Tasks

D0= Description

(2) Read in a string of characters from the keyboard. The string is terminated by a carrage return (CR) character. Store the characters into an array in memory starting at the location specified by the address in register A1. The number of characters read in, including the “CR” character, will be returned in register D1.W. A maximum of 80 characters can be read in.

(3) Display the value in register D1.L as a decimal number, using the least amount of space on the output display, in other words, left-justified.

D0= Description

(4) Read a decimal number from the keyboard and store the binary equivalent in register D1.L. Typing in any character other than a decimal digit will invoke the decimal to binary conversion, and all trailing characters will be ignored.

(9) Terminate the program

(13) Display the NULL terminated string pointed to by the address in register A1, with a carrage return (CR) and a line feed (LF). The maximum number of characters that will be displayed is 255, which includes the CR and LF.

(14) Display the NULL terminated string pointed to by the address in register A1, without a carrage return (CR) and a line feed (LF). The maximum number of characters that will be displayed is 255.

Quick Reference to Fundamental I/O Tasks

ASCII Codes

y79121Y598993957em1925

x78120X588883856can1824

w77119W578773755etb1723

v76118V568663654syn1622

u75117U558553553nak1521

t74116T548443452dc41420

s73115S538333351dc31319

r72114R528223250dc21218

q71113Q518113149dc11117

p70112P508003048dle1016

o6f111O4f79/2f47si0f15

n6e110N4e78.2e46so0e14

m6d109M4d77-2d45cr0d13

l6c108L4c76,2c44np0c12

k6b107K4b75+2b43vt0b11

j6a106J4a74*2a42nl0a10

i69105I4973)2941ht099

h68104H4872(2840bs088

g67103G4771'2739bel077

f66102F4670&2638ack066

e65101E4569%2537enq055

d64100D4468$2436eot044

c6399C4367#2335etx033

b6298B4266"2234stx022

a6197A4165!2133soh011

'6096@4064sp2032nul000

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