Machine Structures Lecture 19 CPU Design: Designing a Single-cycle CPU, pt 2 Halloween plans? Try the Castro, SF! Tomorrow

Machine Structures Lecture 19 –

CPU Design: Designing a Single-cycle CPU, pt 2

Halloween plans? Try the Castro, SF!

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Tomorrow 2005-10-31,runs until 11pm

…go at least once…Happy Halloween, everyone!

How to Design a Processor: step-by-step1. Analyze instruction set architecture (ISA)

=> datapath requirements•meaning of each instruction is given by the register transfers• datapath must include storage element for ISA registers• datapath must support each register transfer

2. Select set of datapath components and establish clocking methodology

3. Assemble datapath meeting requirements4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.

5. Assemble the control logic

Step 3: Assemble DataPath meeting requirements

• Register Transfer Requirements Datapath Assembly

• Instruction Fetch• Read Operands and Execute Operation

3a: Overview of the Instruction Fetch Unit• The common RTL operations• Fetch the Instruction: mem[PC]•Update the program counter:

Sequential Code: PC PC + 4 Branch and Jump: PC “something else”

32

Instruction WordAddressInstruction

Memory

PCclk

Next AddressLogic

3b: Add & Subtract• R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt

•Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields

•ALUctr and RegWr: control logic after decoding the instruction

32Result

ALUctr

clk

busW

RegWr

3232

busA

32busB

5 5 5

Rw Ra Rb32 32-bitRegisters

Rs RtRd

AL

U

op rs rt rd shamt funct061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits

Already defined the register file & ALU

Clocking Methodology

•存储单元由同样的边缘定时•物理设备 , flip-flops (FF)和组合逻辑会有一些延时•门电路 : 输入引起输出变化之间有延时•在 FF D输入端的信号必须稳定，然后，激发时钟边缘才允许信号 FF (set-up time)中通过 , 因此这里也会有 clock-to-Q延时

•“关键路径 Critical path” (通过逻辑电路的最长路径 ) 确定时钟周期的长度

Clk

.

.

.

.

.

.

.

.

.

.

.

.

Register-Register Timing: One complete cycleClk

PCRs, Rt, Rd,Op, Func

ALUctr

Instruction Memory Access Time

Old Value New Value

RegWr Old Value New Value

Delay through Control Logic

busA, BRegister File Access TimeOld Value New Value

busWALU Delay

Old Value New Value

Old Value New Value

New ValueOld Value

Register WriteOccurs Here

32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

AL

U

5Rd

3c: Logical Operations with Immediate• R[rt] = R[rs] op ZeroExt[imm16] ]

op rs rt immediate016212631

6 bits 16 bits5 bits5 bits

immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs RtA

LU

5Rd

3c: Logical Operations with Immediate• R[rt] = R[rs] op ZeroExt[imm16] ]



immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

• Already defined 32-bit MUX; Zero Ext?

What about Rt register read??

32

ALUctr

clk

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

Rd

ZeroE

xt 3216imm16

ALUSrc

01

0

1

AL

U

5

RegDst

3d: Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt,rs,imm16



32

ALUctr

clk

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

Rd

ZeroE

xt 3216imm16

ALUSrc

01

0

1

AL

U

5

RegDst

3d: Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt,rs,imm16



32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216

imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

AL

U 0

1WrEn Adr

DataMemory

5

?

3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]

Ex.: sw rt, rs, imm16



32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216

imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

AL

U 0

1WrEn Adr

DataMemory

5

3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]

Ex.: sw rt, rs, imm16



32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216

imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

AL

U 0

1WrEn Adr

DataMemory

5

3f: The Branch Instruction

beq rs, rt, imm16•mem[PC] Fetch the instruction from memory•Equal = R[rs] == R[rt] Calculate branch condition• if (Equal) Calculate the next instruction’s address PC = PC + 4 + ( SignExt(imm16) x 4 )

else PC = PC + 4



Datapath for Branch Operations• beq rs, rt, imm16

Datapath generates condition (equal)op rs rt immediate

016212631


Already have mux, adder, need special sign extender for PC, need equal compare (sub?)imm16

clk

PC

00

4 nPC_sel

PC E

xt

Adder

Adder

Mux

Inst Address

32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

AL

U

5

=

Equal

Putting it All Together:A Single Cycle Datapath

imm16

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender

3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWrEqual

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

clk

PC

00

4

nPC_sel

PC E

xt

Adr

InstMemory

Adder

Adder

Mux

01

0

1

=AL

U 0

1WrEn Adr

DataMemory

5

An Abstract View of the Implementation

DataOut

clk

5

Rw Ra Rb

RegisterFile

Rd

Data In

DataAddr Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

PC

5Rs

5Rt

32

323232A

B

Nex

t Add

ress

Control

Datapath

Control Signals Conditions

clk clk

AL

U

°5 steps to design a processor• 1. Analyze instruction set => datapath requirements• 2. Select set of datapath components & establish clock

methodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction to

determine setting of control points that effects the register transfer.• 5. Assemble the control logic

°Next time!

Summary: Single cycle datapath

Control

Datapath

Memory

ProcessorInput

Output

Documents

Machine Structures Lecture 19 CPU Design: Designing a Single-cycle CPU, pt 2 Halloween plans? Try the Castro, SF! Tomorrow