MAPS R&D program for SVT Layer0

G. Rizzo SuperB Workshop - Paris - May 9, 2007 1

MAPS R&D program for SVT Layer0

Giuliana Rizzo for the Pisa Group

V SuperB WorkShopV SuperB WorkShop

Paris – May 9, 2007Paris – May 9, 2007


Outline

• Recent results on deep nwell (DNW) CMOS MAPS

• R&D issues for CMOS MAPS:– Fast readout architecture – Sensor optimization– Radiation hardness– Mechanical issues covered in the next talk

• R&D strategy


CDR SVT Layer0

• CDR: 2 options for Layer0 design – Striplets option: mature technology, less

robust against background occupancy.– CMOS MAPS options: more challenging

technology, more robust against background occupancy.

• Both cases: 8 modules @ r=1.5 cm, 50 m pitch, material budget < 0.5% X0.

• Background rate expected ~ 5 MHz/cm2 (x5 safety to be included)


Layer0 MAPS R&D issues

• CMOS MAPS is an option for the ILC vertex detector many aspects of the R&D are common

• CMOS Monolithic Active Pixels (MAPS) are a very promising “new device” (granular, thin, quite rad hard), but so far never used in a real operating detector.

• Extensive R&D needed – Fast readout architecture – Sensor optimization– Radiation hardness – Mechanical issues: Sensor thinning, module design,

light cooling … see next talk by S. Bettarini

Design trade off with monolithic pixels


CMOS MAPSelectronics & interconnects

epitaxial layer

(~ 10 m thick)

substrate

(~ 300 m thick)

Principle of Operation:• Electrons generated by the incident

particle in the undepleted epitaxial layer move by thermal diffusion.– Q ~ 80 e-h/m -> Signal ~ 1000

e-• Signal collected by the n-well/p-epi

diode

Advantages:

• Same substrate for detector-readout:

less material in the detection region (thin down to ~ 50 um)

• Sensor faster and more rad hard than CCDs

• CMOS deep submicron process

– low power consumption and fabrication costs

– electronics intrinsically radiation hard

Developed for imaging applications, recently proven to work well also for charged particles: good efficiency & resolution performance measured

Lots of MAPS R&D in many places with a “conventional” approach:• Charge-to-voltage conversion provided by sensor capacitance

-> small collecting electrode-> small single pixel signal

• Extremely simple in-pixel readout configuration (3 NMOSFETs)

-> sequential readout-> readout speed limitation


Deep Nwell CMOS MAPS design

• Full in-pixel signal processing realized exploiting triple well CMOS process• Deep nwell (DNW) as collecting

electrodeGain independent of the sensor capacitance collecting electrode can be extended

• Area of the “competitive” nwells inside the pixel kept to a minimum:, they steel signal to the main DNW electrode.

• Fill factor = DNW/total n-well area 0.85 in the prototype test structures

• Pixel structure compatible with data sparsification architecture to improve redout speed.

PRE SHAPER DISC LATCH

New approach in CMOS MAPS design to improve the readout speed potential: APSEL chip series

• Proof of principle with the first prototypes realized in 130 nm triple well CMOS process (STMicrolectronics)

SLIM5 Collaboration - INFN & Italian

University

competitive nwellDeep nwell


APSEL series recent results

• Starting from the triple well MAPS design 6 test chips produced

3x3 matrix, full analog 4x4 matrix with sparsified readout

• Better optimization of the front-end: Noise ENC = 50 e-• Measurements with radioactive sources (90Sr , 55Fe)on 3x3

matrix with analog output:• Indications of small cluster size (1-4 pixels)• Cluster Signal for MIP (Landau MPV) 700 e- S/N = 14

• Measurements on 8x8 matrix with digital output and sequential readout:• Noise ENC = 50 e- • Threshold dispersion reduced to ~ 100 e- (still to be improved) • Differential spectra with radioactive sources OK.

• Residual capacitive coupling between the digital lines and the sensor (C~10 aF !!!) is an issue: crosstalk effects observed.

– Inserted shielding with metal planes to cure the problem in the next chips in productions.

8x8 matrixSequential readout


90Sr electrons

Landau

mV

S/N=14

Cluster signal (mV)

• Noise ENC = 50 e-

• Indications of small cluster size (1-2 pixels)

• Cluster Signal for MIP (Landau MPV) 700 e-

S/N = 14

Cluster Multiplicity

3x3 matrix, full analog outputAPSEL2 3x3 matrix: analog

output

Noise events properly normalized

12

Cluster seed

Hit pixels in 3x3 matrix


8x8 matrix digital outputSequential readout

Threshold dispersion ~ 100 e-

APSEL2 8x8 matrix: digital output

Average Noise ENC = 50 e-

Noise scan: hit rate vs discriminator threshold

Vthr

Noise

90Sr electrons: single pixel spectrum

Spectrum from analog output

Differential spectrum from digital output

Vth (mV)

Noise (mV)


Readout Architecture for MAPS

• Data-driven readout architecture with sparsification and timestamp information under development.

• Need to minimize in the active sensor area:– the logical blocks with pmos to minimize the competitive nwell area and preserve

the collection efficiency of the DNW sensor.

– digital lines for point to point connections scales with matrix dimensions

to reduce cross talk with the sensor underneath.

– Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the End Of Column

– Token pass logic scans for hits in the EOCs (stored list of hit MPs and relative timestamp) to start the redout of the corresponding MP.

– Pixel data from each read out MP are sent to the End Of Row and to the sparsification logic.

– Data output interface formats the output of the sparsification, associates the TS and sends data to output lines

– First small chip submitted in Nov 2006 (4x4 pixels). – Larger prototypes (up to ~4k pixels) in production in the next 6 months.– Simulation under way to evaluate performance with the SuperB background

rates.

MP

MP MP

End Of Columns- EOC -

En

d O

f R

ows

- E

OR

-

Sparsification


Pixel Cell optimization: Noise/Power

• Noise dominated by sensor capacitance

1. Changes in the design of the analog part help reduce the DNW sensor area and capacitance substantially (about a factor 3)

2. To keep the efficiency high extend DNW electrode with smaller capacitance nwell collecting electrodes (smaller total capacitance)

• DNW has higher specific Cap w.r.t. standard nwell• Cdnpw ~ 7x Cnwpe

Equivalent noise charge (ENC)

0

10

20

30

40

50

60

0 200 400 600 800

EN

C [

e- rm

s]

Capacitance shunting the preamplifier input, CT [fF]

tP=1 s

measurement

simulationseries contribution from the input device

series contribution from the PMOS current source biasing the input device

parallel contribution from the feedback network

MAPS with N-well extension

standalone ROC

reference MAPS

•Optimization Goal: High signal efficiency = large collection electrode area but with small capacitance (small noise).


Noise/power trade-off in Apsel3

APSEL2 I II III

Detector capacitance

[fF]

460 140 140 140

Analog power

dissipation [W]

60 8 17 30

Input device drain current

[A]

30 5 12 20

Input device dimensions

[m/m]

16/0.25 4/0.25 4/0.25 10/0.25

ENC@200 ns [electrons

rms]

42 40 30 25

schematic simulations

•Noise/power trade-off can take advantage of the substantial reduction in the sensor capacitance

Final design sensor capacitance ~ 150 – 300 fF

50 m

50

m

DEEP NWELL

(digital and MIM capacitors section

not present)

DEEP NWELL

Collecting electrode

NWELL NWELL

PWELL

Shaper inputMiM cap.

Shaper

feedbackMiM cap.

APSEL2

50

m

50 m

Layout not completed

APSEL3


Pixel Cell optimization: Signal

• Developed a fast simulation of the device (ionization and diffusion) to optimize the sensor geometry (E. Paoloni)

- APSEL2 data+ Fast Simulation

90Sr electrons– Detailed device simulation (ISE-TCAD) gives similar results

– Fair agreement among data and Fast Simulation

– Need further tuning of the sensible parameters

Fast Simulation identifies low efficiency regions inside pixel– Improve efficiency adding in these areas small satellite nwells

connected to the main DNW electrode (low contribution to the total sensor capacitance)

– Satellite nwells in the surroundings of the competitive nwell very effective to increase the efficiency


An example of sensor optimization

DNW collecting electrode

Competitive Nwells

3x3 MATRIX APSEL2 pixel Satellite

nwells connected to the DNW electrode

3x3 MATRIX pixel optimized

• With APSEL2 cell (left) Efficiency ~ 96% from simulation (pixel threshold @ 250 e- = 5xNoise)

• Inefficient regions shown in red (pixel signal < 250 e-)• Cell optimized with satellite nwells (right) Efficiency ~ 99.5%


MAPS Radiation Hardness

• Expected Background @ Layer0:– Dose = 6Mrad/yr – Equivalent fluence = 6x1012 neq/cm2/yr

• CMOS redout electronics (deep submicron) rad hard• MAPS sensor - Radiation damage affects S/N

• Non-ionizing radiation: bulk damage cause charge collection reduction, due to lower minority carrier lifetime (trapping)

fluences 1012 neq/cm2 affordable, 1013 neq/cm2 possible

• Ionizing radiation: noise increase, due to higher diode leakage current (surface damage)

OK up to 20 Mrad with low integration time (10 s) or

T operation < 0o C, or modified pixel design to improve it • Irradiation test performed on several MAPS prototypes, with

standard nwell sensor, indicate application for SuperB is viable.• DNW design could be even more rad hard • APSEL chips will be irradiated by the end of 2007

Results from standard nwell MAPS prototypes


SLIM5 Collaboration

• The SLIM5 Collaboration has a quite detailed project plan to build a prototype of a thin silicon tracker (MAPS and thin silicon striplets modules) with LV1 trigger capabilities (based on Associative Memories).– Important aspect of the project is to develop light mechanical

and cooling structures for thin silicon modules to benefit of the very low material budget of the sensor itself.

• Test of the prototype tracker in a test beam in 2008/2009

• Several Italian Institutes involved in the project:– Pisa (coordination), Pavia, Bergamo,Trieste, Torino, Trento,

Bologna

• R&D project supported by the INFN and the Italian Ministry for Education, University and Research.


CMOS MAPS R&D Strategy

• Reasonable S/N performance achieved with present pixel design

• Need to demonstrate fast readout architecture implementation is possible with this technology:– Cure digital crosstalk (test structures in production)– Scalability of the architecture to large matrix (by end

of 2007) – Chip Performance measurement with test beam

(2008/2009)• Optmize S/N and power dissipation • Investigate Radiation tolerance• Explore new possibilities to improve MAPS

performance, based on Vertical Integration (3D Electronics) industrial process.


MAPS chips production in 2007

• July ’07: APSEL3 series In test from Nov 07– Analog 3x3 matrices with new pixel design

(Signal/Noise/Power optimized)– Digital 8x8 matrix with sequential readout– Digital 256 pixels matrix with data driven

architecture (no sensor connected/sensor connected )

• May ’07: APSEL2_CT In test from Sett ‘07– Test structures with metal shield to cure

residual digital crosstalk.– Sensor geometry improved

• Nov ’07: 1k/4k pixel matrix with data driven architecture – pixel as in APSEL3 series– Use feedback from May ‘07 test chip to cure crosstalk– MAPS sensor for 2008/2009 testbeams

Matrix 32 x 8, 256 pixels, 5050µm2


Explore new pixel technology

• Time to explore new pixel technology for SVT Layer0.– Vertical Integration of thin chips is commercially

available.

• Can use MAPS readout electronics on a thin chip connected to high resistivity thin pixel sensor: – 3D interconnection technology could be adopted – Improve S/N w.r.t. to CMOS MAPS:

• pixels on high resistivity substrate are fully depleted• Signal proportional to sensor thickness• Noise reduced with the lower detector capacitance

– Reduce power dissipation (trade off with noise reduction)

– Sensor can be extremely radiation hard


Backup


Layer0 striplets R&D issues

• Technology for Layer0 baseline striplet design well estabilshed

– Double sided Si strip detector 200 m thick– Existent redout chip (FSSR2 - BteV) match the requirements for

striplets redout with good S/N ~ 25.– Redout speed and efficiency not an issue with the expected

background rate (safety factor x5 included)

– Reduction in L0 material budget (from 0.45% 0.35% X0) with R&D on the connection between the silicon sensor and the redout electronics:• Interconnection critical given the high number of readout

channels/module (~3000). Possible choices:– Multiple layers of Upilex with Cu/gold traces with microbonding (as in SVT) – Kapton/Al microcables with Tape Automated Bonding (as in ALICE

experiment)

• Mechanical details worked out in some detail: from module assembling up to final mounting on the beam pipe. See nex talk (S.Bettarini)


Final Layer 0 (striplets) structure

r-cross section

3-D view

• Mechanical details worked out in some detail: from module assembling up to final mounting on the beam pipe.


Module Layer0 (striplets): 3D-view

Hybrids

Striplets Si detector(fanout cut-away)

Upilexfanout

Carbon-Kevlar ribs End

piece

chip

Buttons(coupling HDI to flanges)


Placing the Layer0 module on the flanges

Semi-circularflanges(cooling circuitinside)

Thermal Conductive wings

Places forButtons


The whole SVT: Layer 0 inside the BaBar SVT


Power: 20000 watt/m2

on each Silicon surfaceTemperature (FEA results)• Inlet cooling liquid @ 10 °C

• Tmax= 8°C (H20 Flow=0.094 l / min2.5

m/sec)

AlN-AlN Interface: 50 m of Conductive Glue (4 watt/mK)

Layer0 MAPS module

Two silicon layers (up/down) placed on the mechanical support forming a ladder.

Each chip:12.8mm x 12.8mm.


APSEL series recent results

• Better optimization of the frontend: Noise ENC = 50 e-• Measurements with radioactive sources (90Sr source,

55Fesource)on 3x3 matrix with full analog output:• Indications of small cluster size (1-4 pixels)• Cluster Signal for MIP (Landau MPV) 700 e- S/N = 14

• Measurements on a 8x8 matrix with digital output and sequential readout. Layout modifications in the APSEL2 chip to cure the main source of the digital iterference with the analog circuit• Noise ENC = 50 e- • Threshold dispersion reduced to ~ 100 e- (300 e- in the first

chip, but still to be improved) • Differential spectra with radioactive sources similar to

spectra obtained with the full analog information. • Residual capacitive coupling between the digital lines and the

sensor (C~10 aF !!!) is an issue: crosstalk effects observed. – Shielding with metal planes inserted to cure the problem in the

next chips in productions.


Readout Architecture for MAPS• Data-driven readout architecture with sparsification and timestamp

information under development. No external trigger needed; suitable for LV1 trigger system based on associative memories.

– Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the End Of Column

– Logical OR of pixels inside the MP sent to End Of Column, which has the following functionality:

– Associates relative TimeStamp to each hit MP– Freeze the hit MP until readout is completed– Retains the list of hit MPs and the relative TS – Selects which MP to read

– Token pass logic scans for hits in the EOCs to start the redout of the corresponding MP.

– Pixel data from each read out MP are sent to the End Of Row and to the sparsification logic.

– Data output interface formats the output of the sparsification, associates the TS and sends data to output lines

MP

MP MP

End Of Columns- EOC -

En

d O

f R

ows

- E

OR

-

Sparsification

– First small chip in production (4x4 pixels, with MP=2x2). Medium size prototype (~1k pixels) in production by the end of 2007.

– Simulation under way to evaluate performance with the expected SuperB background rates.

Need to minimize in the active area (pixel and MP)

• the logical blocks (to minimize the competitive nwell area)

• digital lines (to avoid cross talk)


APSEL series

• Starting from the triple well MAPS design 6 test chips produced

• Readout Architecture data driven with sparsification and timestamp information is under development:– Simulation under way to evaluate performance with the

expected SuperB background rates.– First small chip in production, medium size prototype in

production by the end of 2007. • Residual capacitive coupling between the digital lines

and the sensor (C~10 aF !!!) is an issue: crosstalk observed. – Shielding with metal planes inserted to cure the problem in

the next chips in productions.

3x3 matrix, full analog

8x8 matrixSequential readout

4x4 matrix with sparsified readout


Documents

MAPS R&D program for SVT Layer0