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    Makenoise Maths

    Manual Patch Ideas illustrated

    by Demonam

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    Index

    01. . . Voltage Controlled Transient Generator (Attack/ Decay EG)02. . . Voltage Controlled Sustained Function Generator (A/S/R EG)

    03. . . Typical Voltage Controlled Triangle Function04. . . Typical Voltage Controlled Ramp Function

    05. . . Typical Voltage Controlled Pulse06. . . Voltage Controlled ADSR (East Coast Envelope done West Coast style)

    07. . . Voltage Comparator/ Gate Extraction w/ variable width08. . . Gate Controlled CYCLE

    09. . . Toggled Delayed CYCLING10. . . Envelope Follower

    11. . . 281 Quadrature Mode (West Coast Swirly Bird)12. . . VC LAG/ Slew Processor13. . . East Coast Portamento

    14. . . Arcade Trill15. . . Chaotic Trill ( r equi r es QMMG or ot her Di r ect Coupl ed LP f i l t er )

    16. . . Independent Contours17. . . Bouncing Ball ( r equi r es QMMG or Dual VCA)

    18. . . FLIP-FLOP (1-Bit Memory)19. . . Voltage Controlled Pulse Delay Processor

    20. . . Voltage Controlled Clock Divider21. . . Logic Invertor

    22. . . Half Wave Rectification23. . . Full Wave Rectification24. . . ADD, Subtract Control Signals

    25. . . Peak Detector26. . . Voltage Mirror27. . . Multiplication

    28. . . Patch Tips #1 - Maths Slope Control ( f r om navs. modul ar . l ab)

    http://navsmodularlab.blogspot.fr/2010/01/patch-tips-1-maths-slope-control.htmlhttp://navsmodularlab.blogspot.fr/2010/01/patch-tips-1-maths-slope-control.html
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    Voltage Controlled Transient Generator (Attack/ Decay EG)

    At t ack

    Decay

    EG scal e/ i nver si on

    Response

    pul se or gat e

    EG Out

    A pul se or gat e appl i ed t o t he Tr iCH. 1 or 4 wi l l st ar t t he t r ansi en

    whi ch r i ses f r om 0V t o 10V at

    det ermi ned by t he Ri se par amet er Fal l s f r om 10V t o 0V at a rat e dett he Fal l par amet er . Thi s f unct i ot r i gger - abl e dur i ng t he Fal l i ng Ri se and Fal l are i ndependent l y

    cont r ol l abl e, wi t h var i abl e respoLog t hr u Li near t o Exponent i al , a

    t he Var i - Response panel Cont r o

    r esul t i ng f unct i on may be f ur t her wi t h at t enuat i on and/ or i nver si oScal e/ I nver si on Panel Cont r

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    Voltage Controlled Sustained Function Generator (A/S/R EG)

    At t ack

    Rel ease

    EG scal e/ i nver si on

    Response

    gat e

    EG Out

    A gat e appl i ed t o the Si gnal I N of4 wi l l st ar t t he f uncti on whi ch r0V t o t he l evel of t he appl i ed Ga

    r ate determi ned by t he Ri se parSust ai ns at t hat l evel unt i l t he Gends, and t hen Fal l s f r om t hat l eat a rat e det er mi ned by t he Fal l p

    Ri se and Fal l are i ndependent l y cont r ol l abl e, wi t h var i abl e r espon

    by t he Var i - Response panel Cont rr esul t i ng f unct i on may be f ur t her

    wi t h at t enuat i on and/ or i nver si oScal e/ I nver si on Panel Cont r

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    Typical Voltage Controlled Triangle Function

    Fr equency

    Out scal e/ i nver si on

    desi r at ed modul at i on

    Out

    Fr equency

    Fr equency

    Set CH. 1 ( or 4) t o sel f Cycl e. SeFal l Panel Cont r ol t o NOON. Appl y

    modul at i on t o CH. 3 Si gnal I nput .

    Scal e/ I nver si on Panel Cont r ol tAppl y Vol t age Of f set and modul aSUMmed, by pat chi ng SUM OUT t o Bot

    I nput . CH. 2 Scal e/ I nver si on wFrequency. OUTput i s t aken f r om S

    of associ at ed channel . Set t i ng Ri spar amet er s f ur t her CW wi l l pr ovi d

    cycl es. Set t i ng t hese par amet ers f

    wi l l pr ovi de shor t cycl es, up t o aThe r esul t i ng f unct i on may be fpr ocessed wi t h at t enuat i on and/ or

    by t he Scal e/ I nver si on Panel C

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    Fr equency

    Typical Voltage Controlled Ramp Function

    Fr equency

    Out scal e/ i nver si on

    desi r at ed modul at i on

    Out

    As above, onl y the Ri se parameteFULL CCW, Fal l paramet er i s set t o

    NOON.

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    pul se wi dt h

    Typical Voltage Controlled Pulse

    Fr equency

    desi r at ed modul at i on

    Out

    Fr equency

    Out

    Same as above, onl y t he OUTput i s EOC or EOR. CH. 1, Ri se par ameter ef f ect i vel y adj ust f r equency, and par amet er wi l l adj ust pul se wi dt h.4, t he opposi t e i s t r ue wher e Ri s

    mor e ef f ect i vel y Wi dt h and Fal l f r equency. I n bot h channel s al l a

    t o Ri se and Fal l par amet er s wi l lf r equency.

    l ll d ( l d l )

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    Voltage Controlled ADSR (East Coast Envelope done West Coast style)

    At t ack st age 1

    Rel ease

    Sust ai n

    Response

    gat e

    ADSR Out

    At t ack st age 2

    Response

    Decay

    Appl y Gate si gnal t o CH. 1 Si gnal I n. Set CH. I nver si on Panel Cont r ol t o l ess t hen Ful l CW. End of Ri se to CH. 4 Tr i gger I N. Set CH. 4 Scal

    Panel Cont r ol t o Ful l CW. Take OUTput f r omOR busur e t hat CH. 2, 3 are set t o NOON i f not i n uspatch CH. 1 and 4 Ri se wi l l cont r ol t he At t ack

    t ypi cal ADSR adj ust t hese parameter s t o be si miCH. 1 Ri se to be l onger t hen CH. 4 wi l l or vi cepr oduce t wo at t ack st ages) . CH. 4 Fal l parametert he Decay st age of t he envel ope. CH. 1 Scal e/ I nvCont r ol wi l l set t he Sust ai n l evel , whi ch MUST b

    t hat same parameter on CH. 4. Fi nal l y CH. 1 Fat he Rel ease Ti me.

    V lt C t / G t E t ti / i bl idth

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    Voltage Comparator/ Gate Extraction w/ variable width

    der i vat e gat e Del ay

    der i vat e gat e Wi dt h

    si gnal t o becompar ed

    t hr eshol d

    ext r act ed gat e

    Appl y si gnal t o be compar at ed tSi gnal I N. Pat ch CH. 2 OUT t o CH. I N. Set CH. 1 Ri se and Fal l t o f

    Take ext r act ed Gat e f r om EOR. CH. I nver si on acts as t he Thr eshhol dappl i cabl e val ues bei ng bet ween Ful l CW. Val ues cl oser t o NOON

    HI GHER t hr eshol ds. Set t i ng the RiCW, you wi l l be abl e to Del ay t hegat e. Set t i ng Fal l t i mes CW you w

    t he wi dt h of t he der i ved Gate. Use

    Envel ope Fol l ower , and CH. 2 & 1 ext r act i on, and you have a ver y pat ch f or ext er nal si gnal pr oce

    Gate Controlled CYCLE

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    Gate Controlled CYCLE

    t r i gger del ayt i me

    gat e

    Out

    f i ne t une/ shape f i ne t une/ shape

    Appl y Gat e t o CH. 2, set CH. 2 Scat o 3 o' cl ock. Pat ch CH. 1 EoR t o set Scal e cont r ol t o Ful l CW. Usi nst ack- cabl e, pat ch OR OUT t o bot h Tr i gger I N. Take output f or m CH.

    OUT mul t i pl e ( bot t om r ow) . Pat ch dt o CH. 1 Si gnal OUT ( t op r ow) , or si gnal el se wher e i n t he pat ch. Ccont r ol s t he t r i gger del ay t i me. Cmust al ways be shor t er t hen CH. 1 Response knob acts as a f i ne t une

    l engt hs as wel l as set t i ng t he shawi l l CYCLE so l ong as Gate i s Speci al t hanx t o Don Ki m f or t hi

    i dea.

    Toggled Delayed CYCLING

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    Toggled Delayed CYCLING

    t r i gger del ayt i me

    gat e

    Out

    f i ne t une/ shape f i ne t une/ shape

    Thi s i s t he pat ch t hat f r om whi chf or t he above Gat e Cont r ol l ed CYC

    or i gi nated. Set up t he above patcht he SUM OUT and mul t t o bot h CH

    Tr i gger I N. i nst ead of t he OR OUT. be l onger i n dur atat i on t hen t he Cas set by Ri se and Fal l of CH. 1 a

    Thi s pat ch wor ks great wi t h Pr essuut i l i zi ng on of Gate OUTs on t hat

    Speci al t hanx t o Don Ki m f or t huni que pat ch i dea.

    Envelope Follower

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    Envelope Follower

    posi t i ve onl y Out

    r esponse

    si gnal t o bef ol l owed

    posi t i ve/ negat i ve Out

    scal e/ i nver si on

    Appl y Si gnal t o be f ol l owed t o Si g1 or 4. Set Ri se t o NOON. Set

    modul ate FALL Ti me to achi eve dir esponses. Take out put f r om ass

    channel Si gnal OUT f or posi t i ve anPeak Detect i on. Take out put f r om O

    t o achi eve mor e t ypi cal Posi t i vEnvel ope Fol l ower f uncti on. I f

    needed, pat hc si gnal t o CH. 2 or 3Scal e/ I nver si on t o f ul l CW. Tak

    f r om associ ated channel OU

    281 Quadrature Mode (West Coast Swirly Bird)

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    281 Quadrature Mode (West Coast Swirly Bird)

    modul at i on

    dest i nat i on

    modul at i on

    dest i nat i on

    I n t hi s pat ch, CH. 1, 4 wor k i n tpr ovi de f unct i ons shi f t ed by ni netWi t h bot h Cycl e Swi t ches UN- ENGAGEnd of Ri se ( CH. 1) t o Tr i gger I

    Pat ch End of Cycl e (CH. 4) t o Tr i g1. I f bot h CH. 1 and 4 do not begi n

    engage CH. 1 Cycl e Br i ef l y. Wi tchannel s cycl i ng, appl y thei r r e

    Si gnal OUTput s t o t wo di f f er ent mdest i nat i ons, f or exampl e t wo cha

    t he QMMG.

    VC LAG/ Slew Processor

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    VC LAG/ Slew Processor

    si gnal t o besl ewed

    scal e/ i nver si on

    s l ew RI SE

    sl ew FALL

    r esponse

    Out

    A si gnal appl i ed t o t he Si gnal I N, accordi ng t o t he RI SE and FALL paVar i abl e r esponse f r om Log t hr u L

    Exponent i al , i s as set by t he Var ipanel Cont r ol . The r esul t i ng f unctf ur t her pr ocessed wi t h at t enuat i o

    i nver si on by t he Scal e/ I nver si oCont r ol .

    East Coast Portamento

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    si gnal t o besl ewed

    scal e/ i nver si on

    Out

    ext r emeness of t heLOG r esponse

    por t ament o r at e

    Set CH. 1 Ri se and Fal l t o NOONResponse to Ful l CCW. Patch CH. 1

    ( t op r ow) t o CH. 2 Si gnal I N, seScal e t o Ful l CCW, pat ch SUM OUT

    BOTH Cont r ol I N. Set CH. 3 Scalcont r ol t o NOON. Pat ch CV t o be slan Obi e l i ke por t ament o t o CH. 1 S

    Take output f r om CH. 1 Si gnal OUTr ow. I n t hi s pat ch CH. 2 Scal e pan

    wi l l set t he ext r emeness of t hr esponse, Ful l CCW bei ng t he most CH. 3 Scal e panel cont r ol wi l l se

    t he por t ament o, CW bei ng f ast er bei ng sl ower .

    I f you want ed to get even f anci er ,

    pat ch t he mod- wheel f r om your CV ( or Pr ess CV f r om Pr essur e Poi nt s)Si gnal I N, and use mod- wheel or Pri nf l uence and cont r ol t he por t ame( j ust be sur e nothi ng i s pat ched

    OUT, t op r ow, so that t he si gnal it he SUM BUSS, and i f you use CH

    somethi ng el se, be sur e t o ut i l i zRow out put t o br eak t he normal i

    cont r ol si gnal

    Arcade Trill

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    scal e/ i nver si on

    Out

    t r i l l

    t r i l l

    t r i l l

    Set CH. 4 Ri se and Fal l t o NOON,I nver si on t o 9 o' cl ock. Pat ch EOC

    Tr i gger I N. Pat ch CH. 4 Si gnal OUTBoth I N. Set CH. 1 Ri se t o NOON,

    f ul l CCW. Engage CH. 4 Cycl e swi tSi gnal OUT CH. 1 t o modul at i on des

    CH. 4 Scal e/ I nver si on, Ri se anRsponse Par amet er s var y t r i

    Chaotic Trill ( r equi r es QMMG or ot her Di r ect Coupl ed LP f i l t er )

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    scal e/ i nver si on

    LPG CV i n

    t r i l l

    t r i l l

    t r i l l

    LPG si gnal i n/ LPG si gnal out

    chaos

    Begi n wi t h Ar cade Tr i l l patch. ApCH. 1 Si gnal OUT t o MATHS CH. 2,

    Scal e/ I nver si on t o 1 o' cl ock. ApSi gnal OUT QMMG CH. 1 Cont r ol I N.

    t o to QMMG CH. 1 Si gnal I N, set t ono f eedback, st ar t i ng wi t h Of f set

    CCW. Appl y QMMG CH. 1 Si gnal OUTpuCH. 4 Bot h I N. QMMG Of f set and MAScal e/ I nver si on panel cont r ol s w

    i nt er est .

    Independent Contours

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    scal e/ i nver si on

    Out

    scal e/ i nver si on

    Out

    By pr ocessi ng t he Si gnal OUT of wi t h CH. 2, 3 and f eedi ng t hat si gi nt o CH. 1, 4 at RI SE or FALL Coni ndependent cont r ol of t he cor r e

    sl ope i s achi eved. Best t o have thpanel cont r ol set t o NOON

    Bouncing Ball ( r equi r es QMMG or Dual VCA)

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    gat e/ t r i gger

    VCA 1 CV I NVCA 1 si gnal I N

    VCA 1 si gnal OUT

    VCA 2 si gnal OUTVCA 2 si gnal I N

    VCA 2 CV I N

    Out

    Gr avi t y Gr avi t y

    Rest i t ut i on

    si gnal t o bebounced

    Appl y same t r i gger or Gate t o CH. 1 CH. 4 TrSet Ri se t o f ul l CCW and Fal l t o 3 o' cl ock

    I nver si on t o f ul l CW. Pat ch CH. 1 Si gnal OUTSi gnal I N. Set Ch. 2 Scal e/ I nver si on t o 10

    Appl y CH. 2 si gnal out t o CH. 4 Both I N. Set f ul l CCW, Fal l set t o NOON, Scal e/ I nver si on and engage Cycl e Swi t ch. Pat ch CH. 4 Si gnal oCH. 1 Si gnal I N. Pat ch MATHS CH. 1 Si gnal OUt o QMMG CH. 1 Cont r ol Si gnal I N. Set QMMG CHt o f ul l CCW, Feedback t o 9 o' cl ock, set mod

    Appl y Si gnal t o be bounced t o QMMG CH. 2 Si gnOf f set i s set t o f ul l CCW and f eedback i s

    o' cl ock, mode i s Bot h. Patch QMMG CH. 1 Si gn

    QMMG CH. 2 Cont r ol Si gnal I N. Moni t or QMMG CHOUT. MATHS Var i - Response panel cont r ol s wi l lsor t of Gr avi t y parameter, where bot h shoulsi mi l ar and more Logari t hmi c response wi l l gr avi t y. MATHS CH. 1 Fal l parameter i s a

    Rest i t ut i on cont r ol . I ncr easi ng Fal l par amet ebal l wi l l bounce mor e t i mes. Shor t er Fal l s tbr i ng f ewer bounces. Set t i ng Fal l t o bef ore r esul t i n no bounci ng. Hi gh Gr avi t y set t i ngs

    wi t h f ewer bounces yi el ds a r ever b l i ke souwi t h QMMG.

    FLIP-FLOP (1-Bit Memory)

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    Reset

    Gat e/ l ogi c

    "NOT Q" Out"Q" Out

    I n t hi s pat ch CH. 1 Tr i gger I N acSet i nput , and CH. 1 BOTH Cont ras t he Reset i nput . Appl y Reset CH. 1 BOTH Cont r ol I N. Appl y Gate

    si gnal t o CH. 1 Tr i gger I N. Set RiCCW, Fal l t o Ful l CW, Var i - Resp

    Li near . Take Q out put f r om EOC. t o CH. 4 Si gnal t o achi eve NOT QEOC OUT. Thi s pat ch has a memory

    about 3 mi nut es, af t er whi ch i t f oone t hi ng you t ol d i t t o

    r emember .

    Voltage Controlled Pulse Delay Processor

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    del ay

    wi dth ofdel ayed pul se

    Tr i gger or Gat e

    Out

    Appl y Tr i gger or Gat e t o Tr i gger 1. Take out put f r om End Of Ri separ amet er wi l l set t he del ay an

    par amet er wi l l adj ust wi dt h of t he

    del ayed pul se.

    Voltage Controlled Clock Divider

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    di vi sor

    wi dth ofresul t i ng cl ock

    Cl ock

    cl ock Out cl ock Out

    di vi sor

    wi dth ofresul t i ng cl ock

    Cl ock si gnal appl i ed t o Tr i gger I N4 i s pr ocessed by a di vi sor as se

    par amet er . I ncr easi ng Ri se set s hi gher , r esul t i ng i n l ar ger di vi s i

    t i me wi l l adj ust t he wi dt h of t he cl ock. I f t he Wi dt h i s adj ust ed

    gr eat er t he t he t ot al t i me of t het he out put wi l l r emai n hi gh. Ta

    f r om EOR or EOC.

    Logic Invertor

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    l ogi c gat e

    Out

    Appl y l ogi c gat e t o CH. 4 Si gnal out put f r om CH. 4 EOC.

    Half Wave Rectification

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    bi - pol ar si gnal

    Out

    Appl y bi - pol ar si gnal t o CH. 1, 2,Take output f r om OR out . Mi nd

    normal i zat i ons t o t he OR bu

    Full Wave Rectification

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    si gnal t o be

    r ect i f i ed

    Out

    Mul t si gnal t o be r ecti f i ed t o boand 3 I N. CH 2 Scal i ng/ I nver si oFul l CW, CH. 3 Scal i ng/ I nver si o

    Ful l CCW. Take out put f r om OR Out .

    Scal i ng.

    ADD, Subtract Control Signals

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    si gnal ( s) t o besubst r act ed

    Out

    si gnal ( s) t o beadded

    Appl y si gnal s t o be added/ subt r accombi nat i on of Si gnal I N CH. 1, 2,usi ng CH. 1, 4 Ri se and Fal l must

    f ul l CCW, and Cycl e swi t ch not eng

    Scal e/ I nver si on panel cont r ol s f ot o be added, t o f ul l CW. Set S

    I nver si on panel cont r ol s f or channsubt r act ed t o f ul l CCW. Take out pu

    OUT.

    Peak Detector

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    Out

    si gnal t o bedet ect ed

    Gat e Out

    Pat ch si gnal t o be det ect ed t o CH.I N. Set Ri se and Fal l t o 3 ' o' Clout put f r om Si gnal OUT. Gat e out

    OUT.

    Voltage Mirror

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    cont r ol s i gnalt o be mi r r or ed

    Out

    Appl y Cont r ol Si gnal t o be mi r r or eSi gnal I N. Set CH. 2 Scal e/ I nver scont r ol t o Ful l CCW. Wi t h not hi ngat CH. 3 Si gnal I N ( so as t o gen

    of f set ) , set CH. 3 Scal e/ I nver sicont r ol t o f ul l CW. Take out put OUT. Thi s pat ch wi l l al so wor k as

    I nver t or .

    Multiplication

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    posi t i ve cont r olsi gnal t o be

    mul t i pl i ed

    posi t i ve mul t i pl i ercont r ol si gnal

    Out Out

    Appl y posi t i ve goi ng Cont r ol Si gnmul t i pl i ed t o CH1 or 4 Si gnal I N.

    t o f ul l CW, Fal l t o Ful l CCW. Applgoi ng, mul t i pl i er Cont r ol Si gnal

    Cont r ol I N. Take out put f r om cor rSi gnal OUT.

    Patch Tips #1 - Maths Slope Control (from navs.modular.lab)

    http://navsmodularlab.blogspot.fr/2010/01/patch-tips-1-maths-slope-control.htmlhttp://navsmodularlab.blogspot.fr/2010/01/patch-tips-1-maths-slope-control.html
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    gat e/ t r i gger

    EG Out

    At t ack

    Decay

    sever i t y/ pol ar i t yof t he At t ack

    r esponse

    sever i t y/ pol ar i t yof t he Decayr esponse

    Set Mat hs' r esponse knob t o l i neaTake t wo mul t s of t he envel ope ou

    patch one t o Maths' channel 2, t hechannel 3. Set channel 2' s out put

    t wo o' cl ock ( +) and pat ch i t t o thi n, set channel 3 t o ca. t en o' cl opat ch t o t he f al l CV. Thi s wi l l g

    l ogar i t hmi c ri se and exponent i aI ncr easi ng t he amount of posi t

    negat i ve f eedback wi l l i ncr ease t h

    of t he r esponse, f l i ppi ng t he polt he CV- i ns wi l l yi el d an exponentand l ogar i t hmi c f al l . I f you wan

    r eal l y mad, use Doepf er ' s A- 13Pol ar i zer i nst ead of Mat hs' ' at t en

    t o gai n vol t age cont r ol over par amet ers.

    Thanks

    f l f i f i i d l l i f i i i l l i

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    radiokoala f or "Hal f Wave Rect i f i cat i on" and "Ful l Wave Rect i f i cat i on" i l l ustr at i onsNavs f or "Pat ch Ti ps #1 - Mat hs Sl ope Cont r ol "