Maximum Efficiency Point Tracking (MEPT) Method and Digital Dead Time Control Implementation

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 5, SEPTEMBER 2006 1273

Maximum Efficiency Point Tracking (MEPT) Methodand Digital Dead Time Control Implementation

Jaber A. Abu-Qahouq, Member, IEEE, Hong Mao, Hussam J. Al-Atrash, and Issa Batarseh, Fellow, IEEE

Abstract—An adaptive control method, to be called maximumefficiency point tracking (MEPT), is presented in this paper.This method tracks system efficiency, which is dc–dc converterefficiency in this paper, and adaptively optimizes system param-eters to maximize efficiency. The MEPT method is used in thispaper to optimize the primary-to-secondary switches’ dead-timeparameter in an isolated topology to reduce the switches’ bodydiodes conduction during commutation periods and to reducebody diodes conduction and reverse-recovery related losses inorder to improve efficiency. MEPT tracks converter efficiencywhile changing the dead-time and detects the optimized dead-timevalue at the maximum efficiency point at different load and lineconditions. In this paper, the MEPT method is discussed andanalyzed, and its digital control algorithm and experimentalimplementation are presented.

Index Terms—Adaptive, converter, dead time, digital control,efficiency, isolated, maximum efficiency point tracking (MEPT)method, non-isolated, tracking.

I. INTRODUCTION

I N DESIGNING power electronics converter systems such asdc–dc converters, several design parameters need to be opti-

mized to improve efficiency and converter performance. Someof these parameters are load dependent, input voltage depen-dent, component dependent, and temperature dependent. De-signing such parameters for a specific load, input, output, com-ponent, and temperature may improve single design point ef-ficiency but will not result in maximum efficiency and perfor-mance at different load and line conditions and will not guar-antee optimality at that design point because of the componentand temperature variations.

Digital controllers are increasingly being used, especially incomplex systems including power electronics systems, becauseof their advantages that include the ability to perform sophis-ticated and enhanced control schemes, low power consump-tion, reliability, reconfiguration flexibility, elimination of com-ponent tolerances and ageing, and ease of integration and inter-

Manuscript received July 14, 2004; revised February 4, 2005. This work wassupported by Astec Power and the National Science Foundation. Recommendedby Associate Editor Z. Chen.

J. A. Abu Qahouq was with the Department of Electrical and Computer En-gineering, University of Central Florida, Orlando, FL 32816 USA. He is nowwith Intel Corporation, Hillsboro, OR 97124 USA (e-mail: [email protected]).

H. Mao is with the Advanced Technology Department, Astec Power (Divisionof Emerson Network Power), Andover, MA 01810 USA.

H. J. Al-Atrash and I. Batarseh are with the Department of Electrical andComputer Engineering, University of Central Florida, Orlando, FL 32816 USA(e-mail: [email protected]).

Digital Object Identifier 10.1109/TPEL.2006.880244

face with other digital systems [1]–[3], [7]. Of course, there arestill some disadvantages/challenges in using digital controllersfor analog systems, such as dc–dc converters in power elec-tronics, including the required high resolution from the digitalcontroller to satisfy the converter tight regulation requirementsand the required high speed to satisfy the converter dynamic re-quirements, which result in an increase in cost. Fortunately, thedigital controllers industry is rapidly advancing, allowing for theavailability of faster and higher resolution digital controllers ata lower cost [1]–[3].

The ability of a digital controller to perform sophisticatedalgorithms makes it easy to apply adaptive control algorithmswhere system parameters can be adaptively adjusted in responseto system behavior to achieve better performance and stability.An adaptive controller is therefore intuitively a controller thatcan modify its behavior after changes in the controlled plant orin the environment.

One important parameter that needs to be optimized inisolated and non-isolated converters is the dead time betweenthe switches turn ON and turn OFF to avoid switch body diodeconduction [4]–[6], [11]. For example, synchronous rectifier(SR) MOSFET’s body-diodes conduction of the secondary sidetopology, such as current doubler, should be avoided for betterefficiency, especially in low-output voltage, high-output currentapplications where the body-diodes conduction and reverserecovery losses become more severe [4]–[6]. This scenariorequires to design for the smallest possible dead time (delaytime) between turning ON and OFF the primary-side switchesand turning OFF and ON the corresponding secondary-sideSR switches. At the same time, this dead time should be longenough to avoid the two secondary switches’ short circuitwhen the two of them are ON at the same instant the voltage isapplied from the primary side.

The selection and optimization of this dead time is not an easytask and is difficult to achieve at all load/input conditions andfor different component parasitics and temperatures. One wayto accomplish this is to fix the dead time to a constant value thatsatisfies the worst condition. This can be achieved by a simpleresistive–capacitive (RC) delay circuitry to set the dead time be-tween turning ON and OFF the corresponding switches. Thismethod is simple but unfortunately results in lower efficiencysince the dead time has to be set long enough to cover the wholeload/input range and to cover other variations such as compo-nent and temperature variations. Another way is to set the deadtime by detecting the switch-body diode conduction [4]–[6] andmodifying the dead time accordingly. This method reduces bodydiode losses and therefore improves efficiency. However, thebody diodes still conduct, and losses are still considerable—es-

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1274 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 5, SEPTEMBER 2006

pecially at higher switching frequencies and higher output cur-rents. Also, it is difficult to be implemented in isolated topolo-gies because of the delays caused by driving signals isolatorsand transformer leakage inductance that vary at different loadand line conditions. Efficiency is one of the most important pa-rameters being targeted for optimization and maximization. Ef-fectively controlling converter parameters, such as dead time,can greatly contribute to efficiency.

An adaptive control method, to be called maximum effi-ciency point tracking (MEPT), is presented in this paper. TheMEPT method adaptively changes the parameter to be opti-mized, which is the dead time in this paper, while tracking theefficiency for maximum efficiency point detection that existsfor certain optimized dead-time value. It must be noted thatwhile the maximum power point tracking (MPPT) methods [8],[9] track the maximum power point of the solar arrays (con-verter input power), the proposed MEPT tracks the minimumconverter input power/current point in order to maximize theconverter efficiency.

The next section presents the concept of the proposed MEPTmethod and its application to control switches’ dead time.Section III discusses practical implementation considerationsand solutions and Section IV presents further theoretical anal-ysis. Section V presents experimental work and the conclusionis given in Section VI.

II. MEPT METHOD AND DEAD TIME CONTROL

MEPT tracks the efficiency of the converter to find the op-timized value of the parameter(s) to be adjusted adaptively bytracking the direction of change of the efficiency , in-crease or decrease, and the direction of change of the controlledparameter , increment or decrement. Fig. 1(a) showsa general efficiency curve under different values, whileFig. 1(b) shows a basic single cycle algorithm flowchart forMEPT for operation demonstration. A practical and detailedflowchart is shown in the next section. It must be noted that thecurve of Fig. 1(a) shape may vary depending on the nature ofthe controlled parameter . As shown in Fig. 1, if bothand are moving in the same direction (have same signs),this means that the efficiency is moving toward the maximumpoint [Fig. 1(a)], and the controller will change the in thesame direction as it was in the previous step change. Otherwise,if and are moving in opposite direction (have op-posite signs), it means that the efficiency is moving far fromthe maximum point [Fig. 1(a)], and the controller will change

in the opposite direction of the previous step to correct this.and are given by

(1)

(2)

(3)

where is the current efficiency value under the currentcontrolled parameter value , and 1 is the pre-vious efficiency value under the previous controlled parametervalue 1 .

Fig. 1. Basic single cycle algorithm flowchart for MEPT.

Fig. 2 shows an isolated half-bridge dc–dc converter withcurrent-doubler secondary side, which will be taken as a con-verter example here with MEPT to be applied to it to opti-mize its secondary-to-primary SR switches’ dead time. Con-ventional symmetric control, asymmetric (complementary) con-trol, or duty-cycle-shifted (DCS) control can be applied to thehalf-bridge topology of Fig. 2 [10], [12]. In this paper, DCS-con-trolled half-bridge is taken as an example and not for limitation.

Fig. 3 shows the main switching waveforms of the DCS-con-trolled half-bridge of Fig. 2. Each primary side switch ( and

) has a corresponding dead time at its rising edge andfalling edge relative to the secondary side SR switches( and ). It is desired to optimize the value of andto reduce the corresponding losses of and body diodes.

ABU-QAHOUQ et al.: MAXIMUM EFFICIENCY POINT TRACKING METHOD 1275

Fig. 2. Isolated half-bridge dc–dc converter taken as a converter example herefor MEPT to be applied to it to optimize dead time.

Fig. 3. Main switching waveforms of DCS-controlled half-bridge of Fig. 2.

For simplicity and discussion purposes, it is assumed that.

Fig. 4 shows efficiency versus dead time tentative curvethat illustrates how MEPT can be used to optimize dead timevalue when the control variable to be optimized is the dead time

. In Fig. 4, is the optimum dead time value thatresults in maximum efficiency. As becomes larger than ,the efficiency tends to decrease, up to the point where the SRswitches’ body diodes conduct for the whole period when thevoltage is applied and the efficiency drop stops. While asbecomes smaller than , the efficiency drops rapidly becauseof the resulting over-current condition.

Fig. 5 shows efficiency versus dead time tentative curves thatpresent how MEPT is used to optimize dead time at differentload and input voltage conditions. The MEPT keeps tracking

Fig. 4. Efficiency versus dead time curve that presents how MEPT is used tooptimize dead time.

Fig. 5. Efficiency versus dead time tentative curves that present how MEPT isused to optimize dead time: (a) at different load conditions and (b) at differentinput voltages.

the efficiency to keep the converter under updated and opti-mized dead time value under variable conditions. This will re-sult in efficiency improvement especially at lower output volt-ages, higher load currents, and higher switching frequencieswith wide load and line variation ranges.

III. PRACTICAL IMPLEMENTATION CONSIDERATIONS

AND ISSUES WITH SOLUTIONS

Calculating the efficiency of a converter requires accuratesensing and the use of four values, i.e., , , , and , the


output voltage, output current, input voltage, and input currentof the converter, respectively. It also requires three multiplica-tions, which use large controller resources and calculation time.Moreover, the error resulted in the efficiency value may be mag-nified since it is affected by the sensing error of four values.

A closer look at these four values indicates that for certainline and load point at a fixed regulated output voltage

, the input current is a sufficient parameter to indi-cate the change in the converter efficiency, increase or decrease,over a certain period of time when the converter operates atsteady-state. Even though the input voltage and output currentmay change, after passing the transient period the converter willsettle to constant , , and . The maximum efficiency pointoccurs at the minimum input current point, i.e., for fixed ,

, and , the efficiency is higher when is smaller, sincethe converter input power will be minimized for a fixed outputpower. Therefore, will be used to implement MEPT here.Note that using means that the MEPT implementation didnot require additional sensed signals, since is usually sensedanyway for protection and/or control purposes.

Fig. 6 shows an implementation program flowchart for MEPTto control dead time. samples of , taken by an analog-to-digital converter (ADC), are stored, then averaged and possiblyfiltered by a low-pass digital filter difference equation

1 2 if necessary to eliminate noiseand generate . In the implementation of this paper, 6samples of are digitally averaged andno difference equation is used. is compared to a max-imum current value for over current protection. This pro-tection is added in case is set too small by mistake and causesa short circuit. If , the controller will set to aworst case value and then will restart the process.

is equal or larger than the largest dead time valuethat is expected during the converter operation at differentconditions including line and load conditions

. The next section discusses the theoretical selection andvalue of .

If , the program will continue to calculate thedifference between the previous value and the new value ofand the difference between the current value and the previousvalue of as follows:

(4)

(5)

A check will be performed to see if has sufficient valueto update or not. If this value is sufficient, the program

will proceed to the next step; otherwise, it will start from thebeginning by sampling again.

If the signs (positive or negative) of (4) and (5) are identical(equations results have the same signs, either both positive orboth negative), this means that the current efficiency-dead timepoint is located on the left side of as shown in Fig. 4 and that

should be incremented by to move toward the maximumefficiency point. Otherwise, if the signs of (4) and (5) are notidentical, this means that the current efficiency-dead time pointis located on the right side of as shown in Fig. 4 and that

Fig. 6. Implementation program flowchart for MEPT to control dead time.

should be decremented by to move toward the maximumefficiency point.

After storing the current values of and , the programwill decrement or increment and update it. Then, after sev-eral switching cycles, is sampled again, and the MEPTprocess is repeated.

IV. FURTHER THEORATICAL ANALYSIS

The SRs dead-time value is related to many converter pa-rameters and components’ non-idealities including the SR(MOSFET) gate characteristics and other SR characteristics.This relationship is also highly non-linear. Therefore, the math-ematical modeling and analysis accuracy of such a relationshipand how it is related to the converter efficiency is complicated


and is linked to many components and system non-idealities.In fact, this is a very strong reason why the proposed adaptivedigital dead time control method is so important.

The following are further theoretical analysis and design con-siderations for the presented MEPT dead-time control:

A. Using the Input Current to Indicate the Efficiency

For a fixed operating point and output power, the converterefficiency is higher when the input power is lower since the ef-ficiency is given by

(6)

The smaller the input current is, the smaller the input power,and the higher the efficiency. The output voltage is fixed andregulated by the fast closed-loop feedback. Since the outputpower changes when the output current changes or/and the inputpower changes when the input voltages changes, the input cur-rent will change. However, for the new power condition and forany power level, the converter will have higher efficiency at alower input current value. Each time the power level changes,there is a new minimum input current value that will result innew maximum efficiency point when this minimum input cur-rent point is continuously tracked and updated by the MEPTcontroller.

B. Value Selection

is equal to or larger than the largest dead-timevalue that is expected during the converter operationat different conditions including line and load conditions

.For the converter of Fig. 2, this value will occur at the

operation point of minimum input voltage and light load cur-rent, since the transformer voltage/current slope applied to thesecondary-side is smaller at this condition and needs more timeto switch to the other direction as can be seen from the wave-forms of Fig. 3. For the half-bridge converter example here, thisdead-time value can be approximated by the following equation:

(7)

where 2 for the half-bridge converter of Fig. 2, isthe isolation transformer leakage inductance and is the isola-tion transformer turns ratio as shown in Fig. 2.

can be then calculated considering worst-caseconditions and selected with some error margin as follows:

(8)

Fig. 7. Controller block diagram.

C. Dead-Time Increment/Decrement Selection

While the smaller is, the better the MEPT controller per-formance is and the higher the efficiency improvement is, hard-ware or digital controller with smaller usually has a highercost.

However, some design guidelines can be used to select .The first guideline condition is set by the desired minimum per-centage efficiency change for a given changein dead time. Each SR body-diode power loss change for a given

change can be approximated by

(9)

where is the SR body-diode forward voltage.Considering the power stage specifications of the exper-

imental section and required 0.35%, whereis the desired minimum percentage efficiency

change for a given change , the total required powerloss change of the two SRs of the current-doubler at full load is2 40 0.35 100 0.14 W. Using 0.6 Vand 1/400 kHz in (9), 8 ns. Smaller canbe targeted, however, smaller will be required. Becauseof the hardware limitation available in the laboratory,10 ns is used for experimental evaluation in Section V.

D. Selection

is defined as the minimum input current change required toupdate (increment or decrement) the dead time . value actsas a hysteresis window to eliminate or reduce switching betweentwo values when there is no converter parameters change thatrequires updating , and it also reduces the measurement noiseeffect. The selection of value depends on the converter ratedpower and the desired minimum efficiency change. Since theconverter efficiency is , thefollowing equation can be used as a guide to select the value of

:

or

(10)


Fig. 8. (a) Transformer voltage and rectified sensed current, and (b) through (e) captured rising edge primary-to-secondary switches dead time t while theMEPT is trying to optimize t through several switching cycles starting from a large value of t .

can be solved for using (10) at the nominal and rated systemvalues. For example, at rated output power 40 W withnominal 48 V and expected efficiency around82%, 1.016 A. Targeting 0.25%, can besolved from (10) to be 4.4 mA.

It is important that the ADC used to sample the current beable to detect a variation of input current less than . The 10-bADC used in the experimental work has a resolution of lessthan 3.5 mV with a 3.3-V bias voltage, which is sufficient fordetecting from the current sensor.

E. Selection

It is important to have a delay time of switching cyclesevery time is updated by MEPT dead-time controller beforemeasuring the input current again to calculate the newto ensure that the converter input current is in its new steady-

state value again. The value of (or delay) selectiondepends on the converter settling time decided by the powerstage and the closed-loop regulation loop. should beselected to be slightly larger than the converter settling time,which was 25 s or 10 in the experimentalwork of this paper.

F. System Stability With MEPT

To insure that the proposed MEPT method will not affectsystem stability, the MEPT dead-time control loop is designedto be much slower compared to the high speed voltage regula-tion loop. The fast regulation loop will take care of the systemstability and regulation. The switches duty cycle is controlledby the fast regulation loop, not by the slow MEPT dead-timecontrol loop. Future further study, analysis, and modeling canbe done especially if the adaptive optimization loop is requiredto be designed with faster speed.


V. EXPERIMENTAL WORK

Even though the MEPT can be implemented as an integratedpart or a program subroutine in a fully digital controller, inthis experimental verification work, the MEPT part was imple-mented as a digital control part while the output voltage regula-tion was achieved using a conventional analog voltage closed-loop compensator.

The DCS-controlled half-bridge topology with current-dou-bler of Fig. 2, with its main waveforms shown in Fig. 3, waschosen as a power stage in this experimental work to implementMEPT in order to control dead time between its primary-sideand secondary-side switches. The half-bridge experimental pro-totype was with 1 V/40 A output, 36 V 75 V input voltagerange, and with synchronous rectifiers used for the current-dou-bler switches. The switching frequency used was 400 kHz. Thepower stage isolation transformer turns ratio is 6 witha leakage inductance of about 200 nH, primary sideswitches and are Si7454, and the SRs ( and ) areSi7868 (three paralleled in each channel). The output induc-tors are 180 nH and the output capacitance is

500 F.Fig. 7 shows the controller block diagram. The analog com-

pensator decides the PWM duty-cycle , which is read by theMEPT digital controller block. Using and , the MEPTblock generates the required switches control signals for ,

, , and with optimized dead time using an algo-rithm like the one shown in Fig. 6. TLV1562 ADC was usedto sample the input current . C8051 8-b micro-controller wasused to implement the MEPT algorithm, and a 100-MHz Alterafield-programmable gate array (FPGA) was used to generate thefinal switches control signals. The MEPT algorithm was imple-mented using 10 ns. 80 ns, 4.4 mA,

6 and 10.At 48 V, Fig. 8(a) shows the transformer voltage and

rectified current. Fig. 8(b) through Fig. 8(e) show capturedrising edge primary-to-secondary switches dead time (is not shown since it is similar), while the MEPT is trying tooptimize through several switching cycles starting from largevalue of .

The efficiency of the converter was measured at different con-ditions with and without the proposed MEPT digital dead-timecontroller. Fig. 9 shows percentage efficiency improvementcurves (the percentage difference between the new converterefficiency with MEPT dead-time control and theconverter efficiency without MEPT dead-time control:

100%) at differentinput voltage and output load currents that resulted from usingthe proposed digital dead-time control method compared tousing worst-case constant dead-time value. The efficiency im-provement of Fig. 9 was measured while varying both the inputvoltage and output current, and the proposed MEPT dead-timecontroller is able to detect the optimized dead time value at allconditions. In Fig. 9, efficiency improvement data is given atthree different input voltages (38 V, 48 V, and 65 V) while theinput current varies from 5 A to 40 A.

The efficiency improvement can be noticed from Fig. 9. How-ever, this improvement was limited by the large step size of

10 ns and the variation of the efficiency improvement

Fig. 9. Measured percentage efficiency improvement curves while inputvoltage and output current vary.

Fig. 10. Measured percentage efficiency at different dead-time values whileinput voltage and output current vary. (a) Output current varies. (b) Input voltagevaries.

amount at different operating points. As indicated in previoussection, the reason for using 10 ns is because of thehardware limitation available in the laboratory is with10 ns. In fact, the smaller is, the better the MEPT con-troller performance is. However, hardware or digital controllerwith smaller usually has a higher cost.

It must be noted that when the converter efficiency withoutMEPT dead-time control is measured, the dead timewas fixed to the worst case dead time value requiredat the maximum output current (40 A) with minimum inputvoltage (36 V). Using Equations (7) and (12), this value is about


80 ns. This dead-time value was used in order tocompare and evaluate the experimental results of the MEPT op-eration and results in Fig. 9.

During experimental evaluation, periodic input voltage andoutput current transients (changes) were applied to the con-verter power stage while under closed-loop regulation with theMEPT dead-time control. The controller could always detect thenew optimized dead-time value. Of course, these transients wereslow enough for the converter to settle, i.e., the transients oc-cured at a periodic time that is larger than the converter settlingtime that decides the value of , which is a logical requirementfor any converter. If any transient occurs during the MEPT cur-rent measurements and dead time modification, the next deadtime updated value may not be the optimized value. However,in the next MEPT loop/cycle, this value will be corrected andthe dead time will start to move toward the optimized value.

Fig. 9 efficiency measurements are taken by directly mea-suring the actual output power and the actual input power fromthe power stage, and hence, they are not affected by the sensing,ADC, and other digital control effects of the digital MEPT con-troller. The ADC sampling and averaging errors have slight ef-fect on the MEPT tracking performance once the ADC and dig-ital system precision is sufficient to detect . This is becausethe tracking depends on the difference between two measuredaverage input current values and does not rely on one single cur-rent measurement. Therefore, if the sensing has a shift in one ofthe values, all measurements will have the same shift.

Fig. 10 shows the efficiency versus dead time at different op-erating points of the input voltage and output current, while deadtime is varied within its allowed range, which will not causethe power stage protection circuitry to be triggered nor causea thermal problem or possible system malfunction. Fig. 10(a)shows how the optimized dead-time value changes from 20 nsto 30 ns to 40 ns, while the output current changes from 10 A to20 A to 30 A. Fig. 10(b) shows how the optimized dead-timevalue changes from 40 ns to 30 ns to 20 ns while the inputvoltage changes from 38 V to 48 V to 65 V. The curves of Fig. 10agree with the tentative curves of Figs. 4 and 5 and with the the-oretical analysis of Section IV. The time step 10 ns ofthe digital controller used in this experimental work limited theefficiency improvement, and a smaller will lead to betterresults. For example when the MEPT controller detects an opti-mized dead-time value of 40 ns, the actual optimized value maybe 37 ns, which could not be detected using 10 ns. More-over, different converter topologies, different converter specifi-cations, different components with different design optimiza-tion and different test conditions will also result in different ef-ficiency improvements and different efficiency curves.

VI. CONCLUSION

An adaptive control method to maximize converter efficiencyby optimizing system parameters, namely, the MEPT method ispresented in this paper and used to optimize converter switches’dead time. This method tracks converter efficiency to optimizeparameters such as switches’ dead time for performance opti-mization, which results in efficiency improvement—especiallyat higher switching frequencies and load currents with wide loadand line variation range.

In this paper, the MEPT method’s principle is discussedand an MEPT algorithm is presented to control switches’ deadtime. Moreover, practical implementation considerations arediscussed and solutions are proposed. Experimental structureand results are presented for verification. Smaller step size isrequired for better results and further improvement.

MEPT algorithm to control dead time can work, can be usedin both isolated and non-isolated topologies and does not dependon body-diode conduction detection. These topologies include,but are not limited to: non-isolated synchronous buck converter,and any isolated topology that uses synchronous rectificationsuch as half-bridge (with its different control schemes), full-bridge (with its different control schemes), and active-clamp,which uses output topology with synchronous rectification suchas forward, center-tapped, and current-doubler.

Moreover, MEPT algorithm to control dead time could beimplemented as a part of a fully digitized controller or couldbe integrated in a dedicated chip for optimal performance. Thepresented MEPT concept can be also used to adaptively trackand optimize other converter system parameters.

ACKNOWLEDGMENT

The authors would like to thank G. Potter and B. Higgins,Astec Power, for their helpful discussion and thoughtful insight.

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Jaber A. Abu-Qahouq (M’98) received the B.Sc.degree (with first class honors) from PrincessSumaya University/Royal Scientific Society,Amman, Jordan, in 1998, and the M.S. and Ph.D.degrees from the University of Central Florida(UCF), Orlando, in 2000 and 2003, respectively, allin electrical engineering/electronics.

He is currently a Senior Power Electronics/PowerManagement Engineer with Intel Corporation, Hills-boro, OR. From January 2004 to August 2005, he wasa Faculty Member of the School of Electrical Engi-

neering and Computer Science, UCF, and from January 2002 to December 2003,and was a member of the Adjunct Faculty. He was a Research Assistant/As-sociate with the Florida Power Electronics Center, UCF, from 1999 to 2003.From 1998 to 1999, he was with the Royal Scientific Society (RSS), ElectronicServices and Training Center (ESTC), Amman. He led and worked on sev-eral projects funded by the Florida Space Consortium, NASA, NSF, ASTECPower, INTEL, and the University of Central Florida. He has many journaland conference publications and holds several patents. His research interestsinclude soft-switching power conversion, low-profile high-density low-voltagehigh-current fast-transient dc–dc converters, power factor correction converters,digital control in power electronics, dc–ac inverters, system/platform power de-livery architecture, power management, and renewable energy systems.

Dr. Abu-Qahouq received the Division Recognition Award from the SystemsTechnology Lab, Corporate Technology Group, Intel Corporation, in 2006, theIEEE Outstanding Graduate Student Award in 2002, and the King of JordanRoyal Watch in 1998. He is a member of the IEEE Power Electronics Society,Eta Kappa Nu, and Phi Kappa Phi.

Hong Mao received the B.S. degree from the SichuanUniversity of Science and Technology, Chengdu,China, in 1992, M.S. degree from ChongqingUniversity, Chongqing, China, in 1997, and Ph.D.degree from Zhejiang University, Hangzhou, China,in 2000, all in electrical engineering.

He is currently a Senior Design Engineer withAstec Power, Andover, MA. From 1992 to 1994,he was an Assistant Professor with the Departmentof Electrical Engineering, Sichuan University ofScience and Technology. From 1999 to 2000, he

was a Project Leader with Zhongxing (ZTE) Telecom Corporation, China.From 2000 to 2001, he was a Senior Engineer and Division Manager with PIElectronics, China, where he led a team to develop adaptors for SONY laptopcomputers. From 2001 to 2002, he was with the Center for Power ElectronicsSystems, Virginia Polytechnic Institute and State University, Blacksburg,focusing on high-efficiency front-end dc–dc converters. In 2002, he joined theUniversity of Central Florida, Orlando, working on low-profile low-voltagedc–dc converters. He was an Assistant Director with the Florida Power Elec-tronics Center, University of Central Florida. His current research interestsinclude soft-switching dc–dc power conversion, power factor correction, andmodeling of power electronics systems.

Hussam J. Al-Atrash received the B.S. degree (withhonors) from the University of Jordan (UJ), Amman,in 2003 and the M.S.E.E. degree from the Universityof Central Florida (UCF), Orlando, in 2005, where heis currently pursuing the PhD degree, all in electricalengineering.

He is currently a Graduate Research Assistant withthe Florida Power Electronics Center, UCF. His re-search interests are converter topologies and controltechniques for power systems with renewable energysources.

Issa Batarseh (SM’91–F’05) received the B.S. de-gree in computer engineering and the M.S. and Ph.D.degrees in electrical engineering from the Universityof Illinois, Chicago, in 1983, 1985, and 1990, respec-tively.

He is a Professor and Director of the School ofElectrical Engineering and Computer Science, Uni-versity of Central Florida (UCF), Orlando. He was aVisiting Assistant Professor of Electrical Engineeringat Purdue University, Calumet City, IN, from 1989 to1990 before joining the Department of Electrical and

Computer Engineering, UCF, in 1991. He has more than 14 U.S. patents, andmore than 50 refereed journal and 200 conference publications. His researchwork has been sponsored by Federal agencies and private sector. He publishedPower Electronic Circuits (New York: Wiley, 2003). His major research in-terests are power electronics, focusing on high frequency dc–dc conversion,soft-switching and dynamic modeling of dc-to-dc converters, harmonic anal-ysis, power factor correction, and renewable energy systems.

Dr. Batarseh received many national and international teaching, research, andservice awards. He served as Session Chair and Committee Member for APECand PESC conferences. He will be the general chair for PESC’07 conference inOrlando. Dr. Batarseh has served as a Chairman of the IEEE Orlando Power En-gineering Chapter, Chairman of the IEEE Orlando Section, and Faculty Advisorfor IEEE Student Branch, and Eta Kappa Nu. He is a Registered ProfessionalEngineer in Florida.

Documents

Maximum Efficiency Point Tracking (MEPT) Method and Digital Dead Time Control Implementation