MB91590 series GDC macro specifications - Fujitsu...Sapphire GDC macro specifications FUJITSU SEMICONDUCTOR CONFIDENTIAL ･The content of the description of this material might change

FUJITSU SEMICONDUCTOR

CONFIDENTIAL

MB91590 series

GDC macro specifications

August, 2011 the 3.0th edition

Sapphire GDC macro specifications

FUJITSU SEMICONDUCTOR CONFIDENTIAL

･The content of the description of this material might change without a previous notice, and confirm it to the brokerage department in the order, please.

･The outline of operation and the example of applied circuit described in this material are showing standard operation and the usage of the semiconductor device, and no one to guarantee operation by the equipment actually used. Therefore, please design the equipment in customer's responsibility when you use these. Our company doesn't assume the responsibility about the damage etc. that originate in these use.

･The technical intelligence including the outline of operation and the circuit chart described in this material doesn't mean the permission of the use right of intellectual property rights of our or third party's patent and the copyright, etc. and other rights or the execution rights. Moreover, it is not the one that guarantees to be able to execute third party's intellectual property right and other rights of these use. Therefore, our company doesn't assume the responsibility of the intellectual property right of the third party who originates in these use and the violation of other rights.

･The product described in this material is intended to be used for usual industrial use and a general usage for general clerical work and for personal domestic etc. , and it is designed and it is manufactured. Extremely advanced safety is demanded. On condition that..concerned..safety..secure..social..important..influence..give..directly..life..body..grave danger..with..usage..nuclear installation..nuclear reaction..control..aircraft..automatic..flight..control..air-traffic control..mass transportation..system..operation..control..life..maintenance..medical equipment..arms..system..missile launch..control..say..extremely..high..reliability..demand..usage..bottom of the sea..transponder..space..satellite..say..use..design..manufacture..one.Therefore, please consult about use in these usages and consult the brokerage department about the customer of the idea beforehand. Please acknowledge being not able to assume the responsibility about the damage etc. that occur by having been used without the consultation.

･The breakdown occurs in the semiconductor device at a certain probability. The customer must design safety of a tedious design of the device, the spreading measures design, the overcurrent prevention measures design, and the malfunction prevention design, etc. to cause neither an accident resulting in injury or death, a fire accident nor social damage consequentially even if our semiconductor device breaks down.

･Please give a necessary procedure to me decoying after confirming the restrictions of the foreign currency exchange, Foreign Trade Law, and the United States export management relevant statute, etc. when the product described in this material is exported or is offered.

･The name of the company described in this book and the proper noun of the product name etc. are the trademarks or registered trademarks of each company. Copyright c 2008 -2011 FUJITSU SEMICONDUCTOR CONFIDENTIAL All rights reserved.

Sapphire GDC macro specifications

FUJITSU SEMICONDUCTOR CONFIDENTIAL

Revision history

Date Number of versions

Content of revision

2008/10/24 0.1 First edition

2009/05/18 0.2 ･The chapter of the display list, the video capture, the line engine, and Run-Length Decompression is added. ･The chapter of the sprite engine is updated to a Japanese version.

2009/10/01 0.8 ･The chapter of command sequencer, SIG, DMAC, and FLASHIF is added. ･The chapter of the display list is moved under the line engine. ･"BltCopy * and DrawBitmap *" is added to the display list. ･Display cursor function deletion. ･The display output is added in the whole composition chart and passing that does capture is added. ･Enhancing and display capture selection addition of VCCC register C0sel to 2bit. ･Additionally, error correction.

2010/2/07 0.9 ･Chapter 2 "Display controller" update. ･Chapter 3 "Video capture" update ･Chapter 6 "Command list" update ･Chapter 11 "NTSC/PAL decoder" addition. ･Additionally, error correction.

2010/2/28 0.99 ･The video capture resolution limitation is released. ･Chapter 5 "Sprite engine" update ･Additionally, error correction.

2010/4/13 1.00 ･Chapter 2.9.3"Display controller register" Field name LnAL is united to LnAF. LnAF=11 is deleted. Amplification addition of L3BLD register alpha blend. Note addition at Bit31 (display output enable) setting change of DCM1 register.

･Additionally, error correction.

2011/3/23 2.00 ･Refer to the attached paper.

2011/8/30 3.00 ･Refer to the attached paper.

FUJITSU SEMICONDUCTOR LIMITED

Contents FUJITSU SEMICONDUCTOR CONFIDENTIAL 3

Contents CONTENTS......................................................................................................................................... 3

1. OUTLINE..................................................................................................................................... 9

2. FEATURE................................................................................................................................... 10

3. BLOCK DIAGRAM .....................................................................................................................11

4. MEMORY MAP .......................................................................................................................... 12

5. OPERATION EXPLANATION .................................................................................................. 14

5.1. BASIC SETTING ........................................................................................................................ 14 5.1.1. GDC access sequence ..................................................................................................... 14 5.1.2. GDC external memory maximum capacity .................................................................. 17 5.1.3. External bus memory interface mode setting .............................................................. 17 5.1.4. External bus memory interface exclusive operation.................................................... 17 5.1.5. Endian............................................................................................................................. 18 5.1.6. Access size....................................................................................................................... 18 5.1.7. Arrangement of command list for reset start ............................................................... 19

5.2. DIRECTIONS ............................................................................................................................ 20 5.2.1. External terminal sharing............................................................................................. 20 5.2.2. Data transfer to RLD ..................................................................................................... 21 5.2.3. Lock forwarding of AHB Bus ......................................................................................... 21 5.2.4. Address boundary........................................................................................................... 21

6. DISPLAY CONTROLLER (DISPLAY) ...................................................................................... 22

6.1. OUTLINE.................................................................................................................................. 22 6.2. FEATURE ................................................................................................................................. 22 6.3. COMPOSITION.......................................................................................................................... 23

6.3.1. Location by composition of the entire GDC macro....................................................... 23 6.4. REGISTER ................................................................................................................................ 24

6.4.1. Description form of register........................................................................................... 24 6.4.2. Register list..................................................................................................................... 25 6.4.3. The register is detailed. ................................................................................................. 30

6.5. OPERATION EXPLANATION....................................................................................................... 72 6.5.1. Display function ............................................................................................................. 72 6.5.2. Display timing ................................................................................................................ 81 6.5.3. Data form........................................................................................................................ 84 6.5.4. Display scanning control................................................................................................ 87 6.5.5. External synchronization............................................................................................... 89 6.5.6. Changeable parameter of L1 layer YCbCr/RGB conversion........................................ 91 6.5.7. L1 color element level conversion.................................................................................. 93 6.5.8. Dual display.................................................................................................................... 94 6.5.9. Interrupt ......................................................................................................................... 98

7. CAPTURE CONTROLLER (CAPTURE) .................................................................................. 99

7.1. OUTLINE.................................................................................................................................. 99 7.2. FEATURE ................................................................................................................................. 99 7.3. LOCATION BY COMPOSITION OF THE ENTIRE GDC MACRO .................................................... 100 7.4. REGISTER .............................................................................................................................. 101

7.4.1. Description form of register......................................................................................... 101 7.4.2. Register list................................................................................................................... 102 7.4.3. The register is detailed. ............................................................................................... 105

7.5. OPERATION EXPLANATION..................................................................................................... 131 7.5.1. Capture controller function ......................................................................................... 131 7.5.2. Video buffer................................................................................................................... 133



7.5.3. Capture image rotation write ...................................................................................... 137 7.5.4. Scaling........................................................................................................................... 141 7.5.5. Interrupt ....................................................................................................................... 146 7.5.6. External video signal input ......................................................................................... 148

8. DRAW ENGINE (DRAW)......................................................................................................... 159

8.1. OUTLINE................................................................................................................................ 159 8.2. FEATURE ............................................................................................................................... 159 8.3. COMPOSITION........................................................................................................................ 159 8.4. REGISTER .............................................................................................................................. 160

8.4.1. Description form of register......................................................................................... 160 8.4.2. Register list................................................................................................................... 160 8.4.3. Drawing control register.............................................................................................. 164 8.4.4. Drawing mode register................................................................................................. 168 8.4.5. Drawing configuration register ................................................................................... 172 8.4.6. Rectangular drawing register...................................................................................... 177 8.4.7. Blt register.................................................................................................................... 178 8.4.8. 2D high-speed line drawing register........................................................................... 179 8.4.9. Display list FIFO.......................................................................................................... 180

8.5. OPERATION EXPLANATION..................................................................................................... 181 8.5.1. Coordinate system........................................................................................................ 181 8.5.2. Graphic depiction ......................................................................................................... 182 8.5.3. Graphic depiction attribute ......................................................................................... 184 8.5.4. Display list.................................................................................................................... 185

9. SPRITEENGINE (SPE) ........................................................................................................... 197

9.1. OUTLINE................................................................................................................................ 197 9.2. FEATURE ............................................................................................................................... 197 9.3. COMPOSITION........................................................................................................................ 198

9.3.1. Block diagram............................................................................................................... 198 9.4. REGISTER .............................................................................................................................. 199

9.4.1. Description form of register......................................................................................... 199 9.4.2. Register list................................................................................................................... 200 9.4.3. The register is detailed. ............................................................................................... 202

9.5. OPERATION EXPLANATION..................................................................................................... 221 9.5.1. Outline of processing.................................................................................................... 221 9.5.2. Sprite............................................................................................................................. 223 9.5.3. Monochrome sprite(rectangular drawing) .................................................................. 223 9.5.4. Font mode sprite........................................................................................................... 223 9.5.5. Sprite number............................................................................................................... 224 9.5.6. Priority level ................................................................................................................. 224 9.5.7. Display area of sprite ................................................................................................... 226 9.5.8. Pattern data format ..................................................................................................... 227 9.5.9. Transparent color function .......................................................................................... 230 9.5.10. Background color function ....................................................................................... 230 9.5.11. Color palette table .................................................................................................... 231 9.5.12. Reversing function.................................................................................................... 233 9.5.13. Alpha blend ............................................................................................................... 234 9.5.14. Special sprite............................................................................................................. 235

9.6. INTERRUPT ............................................................................................................................ 242 9.7. NOTES ................................................................................................................................... 242

9.7.1. Limitations ................................................................................................................... 242

10. GRAPHICS MEMORY (VRAM)........................................................................................... 243

10.1. OUTLINE ............................................................................................................................ 243 10.1.1. Block diagram ........................................................................................................... 243

10.2. OPERATION EXPLANATION ..................................................................................................... 244 10.2.1. Memory composition..................................................................................................... 244 10.2.2. Kind of data ................................................................................................................. 244



10.2.3. Data format.................................................................................................................. 245 10.2.4. Frame control............................................................................................................... 247

11. COMMAND SEQUENCER (CMDSEQ) .............................................................................. 248

11.1. OUTLINE ............................................................................................................................ 248 11.2. FEATURE............................................................................................................................ 248 11.3. COMPOSITION .......................................................................................................................... 249 11.4. REGISTER............................................................................................................................... 250

11.4.1. Description form of register ..................................................................................... 250 11.4.2. Register list ............................................................................................................... 250 11.4.3. The register is detailed. ...................................................................................... 251

11.5. OPERATION EXPLANATION ............................................................................................................ 270 11.5.1. Outline of operation.................................................................................................. 270 11.5.2. Various starts............................................................................................................ 272 11.5.3. Priority ...................................................................................................................... 279 11.5.4. Command list ............................................................................................................ 280 11.5.5. Slave module access error response ........................................................................ 289 11.5.6. Forced ending............................................................................................................ 289 11.5.7. Forwarding status .................................................................................................... 289 11.5.8. Interrupt.................................................................................................................... 290 11.5.9. Interrupt is enable.................................................................................................... 293 11.5.10. Interrupt clearness ................................................................................................... 293

11.6. NOTES................................................................................................................................ 293 11.6.1. Limitations................................................................................................................ 293

11.7. USE EXAMPLE .................................................................................................................... 294 11.7.1. Reset start ................................................................................................................. 294 11.7.2. Trigger start .............................................................................................................. 295 11.7.3. Register start ............................................................................................................ 298

12. RUN-LENGTH DECOMPRESSION (RLD) ........................................................................ 299

12.1. OUTLINE ............................................................................................................................ 299 12.2. FEATURE............................................................................................................................ 299 12.3. LIMITATIONS ...................................................................................................................... 299 12.4. COMPOSITION .................................................................................................................... 300

12.4.1. Block diagram ........................................................................................................... 300 12.5. REGISTER........................................................................................................................... 301

12.5.1. Description form of register ..................................................................................... 301 12.5.2. Register list ............................................................................................................... 302 12.5.3. The register is detailed............................................................................................. 303

12.6. OPERATION EXPLANATION ................................................................................................. 312 12.6.1. Data form .................................................................................................................. 312 12.6.2. Processing flow.......................................................................................................... 316 12.6.3. Control flow............................................................................................................... 316

13. SIGNATURE GENERATOR (SIG) ...................................................................................... 317

13.1. OUTLINE ............................................................................................................................ 317 13.2. FEATURE............................................................................................................................ 317 13.3. COMPOSITION .................................................................................................................... 318



13.5. OPERATION EXPLANATION ................................................................................................. 333 13.5.1. Signature A:CRC-32 signature ................................................................................ 333 13.5.2. Signature B: Sum total signature............................................................................ 333 13.5.3. Programmable evaluation window(position and size)............................................ 334 13.5.4. Mask of programmable evaluation window ............................................................ 334



13.5.5. Automatic monitor and interruption....................................................................... 334 13.5.6. Self-restoration error counter .................................................................................. 335 13.5.7. Interruption control flow.......................................................................................... 335 13.5.8. Limitations................................................................................................................ 335 13.5.9. Processing mode........................................................................................................ 336 13.5.10. Control flow............................................................................................................... 337

14. DMA CONTROLLER (DMAC)............................................................................................. 339



14.4.1. Mark form of register ............................................................................................... 341 14.4.2. Register list ............................................................................................................... 342 14.4.3. The register is detailed............................................................................................. 343

14.5. OPERATION EXPLANATION ................................................................................................. 353 14.5.1. Forwarding mode...................................................................................................... 353 14.5.2. Beat forwarding ........................................................................................................ 357 14.5.3. Error .......................................................................................................................... 357

14.6. USE EXAMPLE .................................................................................................................... 358 14.6.1. DMA beginning with single channel ....................................................................... 358

15. MEMORY CONTROLLER (MEMC).................................................................................... 359

15.1. OUTLINE ............................................................................................................................ 359 15.1.1. Feature ...................................................................................................................... 359 15.1.2. Limitations................................................................................................................ 359

15.2. COMPOSITION .................................................................................................................... 360 15.2.1. Block diagram ........................................................................................................... 360 15.2.2. External terminal ..................................................................................................... 360

15.3. REGISTER........................................................................................................................... 362 15.3.1. Description form of register ..................................................................................... 362 15.3.2. Register list ............................................................................................................... 362 15.3.3. MCFMODE0/1(Memory Controller Flash MODE 0/1)........................................... 363 15.3.4. MCFTIM0/1(Memory Controller Flash TIMming 0/1) ........................................... 364 15.3.5. MCFAREA0/1(Memory Controller Flash AREA 0/1).............................................. 367 15.3.6. MCERR(Memory Controller ERRor)....................................................................... 369

15.4. OPERATION EXPLANATION ................................................................................................. 370 15.4.1. Endian ....................................................................................................................... 370 15.4.2. External bus memory mode ..................................................................................... 371 15.4.3. External bus memory timing control ...................................................................... 374 15.4.4. External bus memory area....................................................................................... 382 15.4.5. Error interruption..................................................................................................... 387 15.4.6. External bus memory access.................................................................................... 388 15.4.7. Trigger start of GDC macro...................................................................................... 389

15.5. CONNECTION EXAMPLE ..................................................................................................... 390 15.5.1. Eight bit 32M Byte SRAM/NOR Flash ................................................................... 390 15.5.2. 16 bit 32M Byte SRAM/NOR Flash x2.................................................................... 391 15.5.3. 16 bit 64M Byte SRAM/NOR Flash......................................................................... 392 15.5.4. Low Speed Peripheral .............................................................................................. 393

16. SPI CONTROLLER (SPICNT)............................................................................................. 394

16.1. OUTLINE ............................................................................................................................ 394 16.2. FEATURE.............................................................................................................................. 394 16.3. COMPOSITION ...................................................................................................................... 395

16.3.1. Block diagram ........................................................................................................... 395 16.4. REGISTER ............................................................................................................................ 396

16.4.1. Description form of register ..................................................................................... 396 16.4.2. Register list .................................................................................................................. 396



16.4.3. The register is detailed. ................................................................................................. 397 16.5. OPERATION EXPLANATION ..................................................................................................... 406

16.5.1. Slave read mode ........................................................................................................... 406 16.5.2. Manual mode ............................................................................................................... 407 16.5.3. Master forwarding mode ............................................................................................... 416

16.6. NOTES ................................................................................................................................. 422 16.6.1. Limitations ................................................................................................................... 422

17. NTSC DECODER ................................................................................................................. 423

17.1. OUTLINE ............................................................................................................................ 423 17.2. FEATURE............................................................................................................................ 423 17.3. COMPOSITION .................................................................................................................... 424 17.4. REGISTER........................................................................................................................... 425

17.4.1. Description form of register ..................................................................................... 425 17.4.2. Register list ............................................................................................................ 426 17.4.3. The register is detailed............................................................................................. 427

17.5. OPERATION EXPLANATION ................................................................................................. 436 17.5.1. Analog clamping internal ADC circuit .................................................................. 436 17.5.2. Y / C separation ........................................................................................................ 437 17.5.3. ACC............................................................................................................................ 437 17.5.4. AGC ........................................................................................................................... 437 17.5.5. For macro vision ...................................................................................................... 437 17.5.6. Automatic judgment function(no signal judgment) .............................................. 437 17.5.7. Other adjustments.................................................................................................... 437 17.5.8. Flow figure of register and data ......................................................................... 438 17.5.9. BPF characteristic for Y/C separation..................................................................... 439

18. COMMAND RAM (CMDRAM)............................................................................................. 440



18.5. OPERATION EXPLANATION ................................................................................................. 444 18.5.1. ECC mode switch...................................................................................................... 444 18.5.2. ECC mode(effective) ................................................................................................. 445 18.5.3. ECC mode(invalidity) ............................................................................................... 448

19. MODULE CONTROLLER (MCNT)..................................................................................... 451



19.5. OPERATION EXPLANATION ................................................................................................. 472 19.5.1. GDC information (GINFO)....................................................................................... 472 19.5.2. Interrupt control ....................................................................................................... 473 19.5.3. GDC control............................................................................................................... 476 19.5.4. Limitations................................................................................................................ 476

20. LOCAL BUS BRIDGE.......................................................................................................... 478




20.3.1. Block diagram ........................................................................................................... 479 20.4. OPERATION EXPLANATION ................................................................................................. 480

20.4.1. GDC Local Bus Bridge ............................................................................................. 480 20.4.2. GDC AHB-Local Bus Bridge .................................................................................... 480

21. GDC BUS BRIDGE .............................................................................................................. 481


21.4.1. List of register related to display list DMA ............................................................ 482 21.4.2. Register related to GDC interruption ..................................................................... 485

1


Outline FUJITSU SEMICONDUCTOR CONFIDENTIAL 9

1. Outline In the Graphic Display Controller(GDC) macro, automatic execution of the GDC macro according to the graphic engine (drawing and sprite), the image inputs, the display outputs, and the command lists, the memory interfaces, the data decompressions, and DMA, etc. are supported.

2


Feature FUJITSU SEMICONDUCTOR CONFIDENTIAL 10

2. Feature The feature of the GDC macro is as follows.

Maximum operation frequency 81MHz For GDC AHB BUS round robin Alfabrending and direct execution -8bpp indirect color- ARGB1555 color-Antieirias by drawing

engine line drawing-BitBlt function-display list ARGB1555, RGB565, and vertical reverse ..the horizontal reversing..-direct color ..ARGB8888..--

..can setting of color format of each sprite.. Alfabrending image input-analog video input (NTSC/PAL) Rotation expansion/reduction/function of - digital video

input (RGB666/555)-ITU-R BT.656 input-video image is supported. Display..output..maximum..resolution..sprite..layer..contain..layer..simultaneous..screen

overlay..window..color..format..correspondence..resolution..size..change..RGB..digital..output.(6bit×3) Command automatic operation execution by command automatic operation execution-register setting

by command list GDC macro BOOT by each command automatic operation execution- Trigger It corresponds to with built-in the memory interface (Effective/invalidity of ECC can be selected) the

memory 800KB ･8KB-8bit of external memory and NOR Flash/SRAM or 16bit (64MByte or less) Correspond to ..-.. cereal Flash (16MByte or less) NOR Flash/SRAM and ..-.. cereal Flash are exclusively controlled.

Data decompression Run-Length Decompression is supported. DMA of DMA2ch is installed.

3


Block diagram FUJITSU SEMICONDUCTOR CONFIDENTIAL 11

3. Block diagram The block diagram of the GDC macro is shown as follows. It explains since this chapter by abridging being written in parentheses of each module described in the block diagram.

Figure3-1Block diagram

(*1) Command RAM (CMDRAM) : 8KB RAM is built into. (*2) Graphics RAM (VRAM) : 800KB RAM is built into. (*3) DMA Controller (DMAC) : 2CH is built into.

4


Memory map FUJITSU SEMICONDUCTOR CONFIDENTIAL 12

4. Memory map The memory map of the GDC macro is shown as follows.

Figure4-1Memory map

4


Memory map FUJITSU SEMICONDUCTOR CONFIDENTIAL 13

(*1) CMD RAM : When ECC function is not used, it becomes a booking area. It is 'MB91590 Series hardware manual for the mode setting. Please refer to CHAPTER:44 GDC external control GDCCR register'. This hardware manual for the function. “Please refer to chapter 18 Command RAM”. (*2) MEMC/SPICNT: The content of the register changes by the selected external memory interface. It is 'MB91590 Series hardware manual for the memory selection. Please refer to CHAPTER:44 GDC external control GDCCR register'. This hardware manual for a detailed register. “Chapter 15 Memory Controller”

Please refer to chapter 16 SPI Controller'. Two kinds of addresses described in the memory map show the following.

GDC address The address in the GDC macro is shown. Please use this address in the access from each master module in the GDC macro.

It is written by the right record in this hardware manual. Example) 0000_0000H

On Chip BUS Layer 1/2 Address The address from CPU side is shown. It is 40_0000 in GDC address It becomes an address where H was added. Please use this address in the access from CPU side to the GDC macro. Please refer to 'MB91590 Series hardware manual' for the On Chip BUS Layer 1/2 Address memory map. It is written by the right record in this hardware manual. Example) 0000_0000H

5


Operation explanation FUJITSU SEMICONDUCTOR CONFIDENTIAL 14

5. Operation explanation

5.1. Basic setting

5.1.1. GDC access sequence Please do the following settings needed in the GRST bit of GDCCR register (0000_0F65H) using the GDC macro for the period of "1" (reset period).

Port setting Please set interactive and unused and use/input/output/pull-up/pull-down of the port. Please refer to 'MB91590 Series hardware manual CHAPTER11:I/O port' for the setting method.

Clock setting

Please set clock frequency and SSCG oscillation/stop etc. Please refer to 'MB91590 Series hardware manual CHAPTER5: the clock' for the setting method.

GDC macro operation mode setting

Please set various operation modes of the GDC macro. Please refer to 'MB91590 Series hardware manual CHAPTER44:GDC external control' for the setting method.

The command list by the reset start is executed automatically immediately after "0" was written in the GRST bit of GDCCR register (0000_0F65H) (Reset is released) (*). (* The command list automatic operation execution by the reset start can set "Use/unused of the reset start" by the BOOT bit setting of GDCCR register (0000_0F65H). ) Please ..GRST bit of GDCCR register (0000_0F65H).. access GDC "0" after confirming the interruption without fail by the GDC bit of IRPR6H register (0000_0424H) after writing (After releasing reset). When it accesses GDC without doing this confirmation, the operation of GDC is not guaranteed. Please follow the following sequences about the access to GDC.

5



Figure5-1GDC access sequence

5



5



5.1.2. GDC external memory maximum capacity The maximum memory capacity that can be connected with the external bus memory interface becomes it as follows. Please set 0200_0000H to the address area setting of CS0 of MEMC.

16MB or less × when SPICNT is selected 1 piece 32MB or less × when 'CS1' is selected by MEMC selection and MCNT module GCONT register 2

pieces 64MB or less × when 'Address25' is selected by MEMC selection and MCNT module GCONT

register 1 piece notes: Please set both same values to CS0/CS1 excluding the MFCAREA0/1 register of

MEMC when you select Address25. Please set 0200_0000H-03FF_FFFFH to the address area setting of CS0. Please set 0400_0000H-05FF_FFFFH to the address area setting of CS1.

Please refer to the chapter of '15.Memory Controller' for details.

5.1.3. External bus memory interface mode setting Please write "0" in MSB of the MEMMD bit of GDC control register (GDCCR) described in 'MB91590 Series hardware manual CHAPTER:44 GDC external control'. When "1" is written, the operation of the external bus memory interface is not warrantable.

5.1.4. External bus memory interface exclusive operation Both interfaces operate exclusively by a set value of 'MB91590 Series hardware manual CHAPTER:44 GDC external control GDCCR register' though MEMC and SPICNT are built into the GDC macro as an external bus memory interface. Limitations:

Please execute it while resetting the GDC macro when you switch the external bus memory interface. When the external bus memory interface switch is executed excluding while resetting it, the operation of the external bus memory interface is not warrantable.

5



5.1.5. Endian The endian supported by the GDC macro is a little endian. All this macro specifications are written by the little endian. Notes:

Please write the data of the device connected with the external bus memory interface (data used in the GDC macro) in the little endian.

5.1.6. Access size The register access to the GDC macro is limited to four byte access (word). Two byte access (half word) and one byte access (byte) are prohibited. Notes:

Writing in NOR Flash from MEMC becomes the following access sizes. Data cannot be correctly written in NOR Flash when writing it in a size outside the following regulations. It becomes correspondence only of NOR Flash2 byte 16 bit access. It becomes correspondence only of NOR Flash1 byte eight bit access.

Reading to NOR Flash can normally read any access size.

5



5.1.7. Arrangement of command list for reset start It is necessary to arrange it at the address where NOR Flash was decided in the GDC macro to execute the command list though the command list can be executed automatically by the reset start. Please refer to the following figures for arrangement in NOR Flash.

Figure5-2Arrangement of command list

Limitations:

In the command list for the reset start, the setting of MEMC is needed as the first command processing. The command list might not operate normally if the MEMC setting is not executed in the beginning.

5



5.2. Directions

5.2.1. External terminal sharing The terminal PG0 of the MB91F590 series (terminal number 200) : with standard clock input (DCLKIN) used with Display as shown in the figure below. Trigger input (CMDTRG) for the trigger start used with CMDSEQ is shared. Therefore, the following attention is necessary for using of each.

Please set it to T-SET register (01FB_7018H Bit19-Bit16) of CMDSEQ excluding FH when using it as a standard clock of Display. Please set 1H to CKS register (01FD_0000H Bit15) of Display.

Please set FH to T-SET register (01FB_7018H Bit19-Bit16) of CMDSEQ when using it as a trigger

input of CMDSEQ. Please set 0H to CKS register (01FD_0000H Bit15) of Display.

Figure5-3External terminal sharing

5



5.2.2. Data transfer to RLD The data transfer using DMAC is needed so that RLD should input the compression data to fixed address (SAHBData: 01FB_5030H).

Figure5-4Data transfer to RLD

GDC macro

Ext-Flash

RLD

DMAC

GDC AHB BUS

MEMC/SPICNT

MB91590 Series

Notes:

'Mastering forwarding mode' installed in SPINCT cannot be used for the data transfer to RLD because it doesn't correspond to fixed addressing though the data reading from external cereal Flash uses SPICNT. Therefore, the data transfer using DMAC that shows the data transfer from external cereal Flash in the above-mentioned is needed.

5.2.3. Lock forwarding of AHB Bus The GDC macro doesn't support the Lock forwarding. When the Lock forwarding is executed to the GDC macro, the operation guarantee cannot be done.

5.2.4. Address boundary The burst that exceeds the address boundary of one Kbyte cannot be accessed to the GDC macro.

6.1. Outline


Display Controller (Display) FUJITSU SEMICONDUCTOR CONFIDENTIAL 22

6. Display Controller (Display)

6.1. Outline

Display controller (Display) is a controller who displays data of the image in VRAM to the display device such as LCD panels by the layer structure.

6.2. Feature Display control The window of four layers can be displayed. Moreover, screen scrolling can be processed. Lower interchangeability It is compatible with four high-ranking layers of our company LSI MB86276. The subordinate position layer doesn't correspond. Dual display by single display controller Two different screens can be output as a single display controller. An arbitrary layer can be selectively output to two screens. Video timing generation circuit 320 × 800 from 240 × The video timing is generated corresponding to screen resolution up to 480. Color look-up Three color look-up tables with palette RAM are built into for the frame display of indirect color mode (8bit/pixel).

6.3. Composition



6.3. Composition

6.3.1. Location by composition of the entire GDC macro

Figure6-1Block diagram of Display

Note: Analog NTSC corresponds to external terminal VIN. Digital RGB corresponds to external terminal PA2-PA7, PB2-PB7, and PC2-PC7. ITU-R.BT656 corresponds to external terminal PA2-PA7, PB2, and PB3. CSYNC corresponds to external terminal PG3. DCLKO corresponds to external terminal PG4. VSYNC corresponds to external terminal PG5. HSYNC corresponds to external terminal PG6. DE corresponds to external terminal PG7. DRi corresponds to external terminal P011, P012, and PD2-PD7. DGi corresponds to external terminal P013, P014, and PE2-PE7. DGi corresponds to external terminal P015, P016, and PF2-PF7.

6.4. Register



6.4. Register

6.4.1. Description form of register The register of the endian this module corresponds to the little endian. Please add Base Address(0040_0000H) when Base addressFR81S(CPU) accesses it. The bit number of the Bit register is shown. The bit field name of the Name register is shown. The attribute of read/write of the R/W each bit field is shown. R0: The read value is always "0. "R1:

The read value is always "1. "Please do W0 "0" in the write. When "1" is done in the write, the operation guarantee is not done. Please do W1 "1" in the write. When "0" is done in the write, the operation guarantee is not done. R: ReadW: Write

The value of each bit field immediately after Initial value reset is indicated. It becomes 0"0". It becomes one "1". X: It is irregular.

6.4. Register



6.4.2. Register list DisplayBaseAddress = 01FD_0000H

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VCCC ( Video/Capture Common Control) 0x7ff8

Csel C0s

r

V0s

r

0x7ffc VCSR( Video/Capture Soft Reset)

DisplayBaseAddress = 01FD_0000H

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DCM0 (Display Control Mode 0) 0x000

DE

N

L4E

L

23E

L

1E

L0E

C

KS

L

CS

SC

EE

Q

SC

SY

SF

E

SY

SYNC


DE

N

L4E

L

3E

L2E

L

1E

L0E

C

KS

L

CS

SC

EE

Q

SC

SY

S

F

ES

Y SY

NCDCM2 (Display Control Mode 2)

0x104

RU

F

RU

M0


RG

Brv

RG

Bsh

DC

Ked

DC

Kin

v

DCKD

0x004 HTP (H Total Pixels)

0x008 HDB (H Display Boundary) HDP (H Display Period)

0x00C

VS

WH

VSW HSW HSP (H Sync pulse Position)

0x010 VTR (V Total Rasters)

0x014 VDP (V Display Period) VSP (V Sync pulse Position)

0x018 L1WY (L1 Window Y) L1WX (L1 Window X)

0x01C L1WH (L1 Window Height) L1WW (L1 Window Width)

6.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

L0M (L0 Mode) 0x020

L0C

L0W (L0 width) L0H (L0 Height)

0x024 L0OA (L0 Origin Address )

0x028 L0DA (L0 Display Address )

0x02C L0D Y (L0 Display Y) L0DX (L0 Display X)

L0EM (L0 Extend Mode) 0x110

L0EC L0PB

L0W

P


0x118 L0WH (L0 Window Height) L0WW (L0 Window Width)

L1M (L1 Mode) 0x030

L1C

L1Y

C

L1C

S

L1I

M

L1W (L1 width)

0x034 L1DA(L1 layer Display Address) / CBDA0 (Capure Buffer Display Address 0)

0x038 CBDA1 ( Capture Buffer Display Address 1)


L1EC

VM

AG L1PB

L1L

CE

CAOFS (Capture Address Offset)



L2M (L2 Mode) 0x040

L2C

L2FLP


0x044 L2OA0 (L2 Origin Address 0)

0x048 L2DA0 (L2 Display Address 0)

0x04C L2OA1 (L2 Origin Address 1)


0x054 L2DY (L2 Display Y) L2DX (L2 Display X)


L2EC L2PB L

2OM

L2W

P



L3M (L3 Mode) 0x058

L3C

L3FLP


0x05C L3OA0 (L3 Origin Address 0)


0x064 L3OA1 (L3 Origin Address 1)


6.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x06C L3DY (L3 Display Y) L3DX (L3 Display X)

L3EM (L3 Extend Mode)

0x140 L3EC L3PB

L3O

M

L3W

P



MDC (Multi Display Control ) 0x170

MD

EN

SC1EN SC0EN

DLS (Display Layer Select) 0x180

DLS4 DLS3 DLS2 DLS1 DLS0

0x184 DBGC (Display Back Ground Color)

L0BLD (L0 Blend) 0x0B4

L0B

E

L0B

S

L0B

I

L0B

P

L0I

D

L0AF

L0BR

L1BLD (L1 Blend) 0x188

L1B

E

L1B

S

L1B

I

L1B

P

L1I

D

L1AF

L1BR

L2BLD (L2 Blend) 0x18C

L2B

E

L2B

S

L2B

I

L2B

P

L2I

D

L2AF

L2BR


L3B

E

L3B

S

L3B

I

L3B

P

L3I

D

L3AF

L3BR


L4B

E

L4B

S

L4B

I

L4B

P

L4I

D

L4AF

L4BR

6.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CKC (Chroma Key Control ) 0x0B8

KC

S

KY

EN

KEYC

L0TC (L0 Transparent Control) 0x0BC

L0Z

T

L0TC (L0 Transparent Color)

L2TC (L2 Transparent Control) L3TC (L3 Transparent Control) 0x0C0

L2Z

T


L3Z

T


L0ETC (L0 Extend Transparency Control) 0x1A0

L0E

ZT

L0ETC (L0 Extend Transparent Color)

L1ETC (L1 Transparent Extend Control) 0x1A4

L1E

ZT


L2ETC (L2 Transparent Extend Control) 0x1A8

L2E

ZT


L3ETC (L3 Transparent Extend Control) 0x1AC

L0E

ZT


L4ETC (L4 Extend Transparent Control) 0x1B0

L4E

ZT


L1YCR0 (L1 YC to Red Coefficient 0) 0x1E0

a12 a11

L1YCR1 (L1 YC to Red Coefficient 1) 0x1E4

b1 a13

L1YCG0 (L1 YC to Green Coefficient 0) 0x1E8

a22 a21

L1YCG1 (L1 YC to Green Coefficient 1) 0x1EC

b2 a23

L1YCB0 (L1 YC to Blue Coefficient 0) 0x1F0

a32 a31

L1YCB0 (L1 YC to Blue Coefficient 0) 0x1F4

b3 a33

6.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

L0PAL0 0x400

A R G B

0x404 L0PAL1

: :

0x7FC L0PAL255

L1PAL0 0x800

A R G B

0x804 L1PAL1

: :

0xBFC L1PAL255

L2PAL0 0x1000

A R G B

0x1004 L2PAL1

: :

0x13FC L2PAL255

L1LCT0 0x2000

R G B

0x2004 L1LCT1

: :

0x23FC L1LCT255

6.4. Register



6.4.3. The register is detailed.

6.4.3.1. Common control register

6.4.3.1.1. VCCC (Video display / Capture Common Control)

VCCC Register address 01FD_7ff8

Bit number 31 30 29 28 27 26 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit field name reserve Csel reserve C0sr resv V0srR/W R0W0 RW R0W0 RW RW RWInitial value 0 00 0 0 0 0

The overall control of Display and Capture is done.

[bit0] V0sr (Vdisp 0 software reset)

It is specified whether to reset the Display software. The reset operation is started by writing the VCSR register. Writing in here is only a selection to be reset.

0 Software is not reset. 1 Software is reset. [bit2] C0sr (Capture 0 software reset)

It is specified whether to reset the Capture software. The reset operation is started by writing the VCSR register. Writing in here is only a selection to be reset.

0 Software is not reset. 1 Software is reset. [bit13, bit12] Csel (Capture select) The input of Capture is selected. 00 External terminal 01 Built-in NTSC decoder 10 Display output 11 Booking

6.4.3.1.2. VCSR (Video display / Capture Software Reset)

VCSR Register address 01FD_7ffc

Bit number 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit field name VCSR R/W R0W Initial value 0

It is a register to execute software reset. The writing data is disregarded. The reset pulse of a single shot is generated by the writing operation internally. The target register for software reset is selected by the VCCC register.

6.4. Register



6.4.3.2. Display controller register

6.4.3.2.1. DCM0 (Display Control Mode 0)/ DCM1 (Display Control Mode1)

DCM0 Register address 01FD_0000

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name

DE

N

reserve L4E

L23E

L1E

L0E

CK

S

LCS

resr

eve

SC EE

Q

SC

SY

re-

serve

SF

ES

Y

SYNC

R/W RW

RW

0

R0

RX

W0

R0 RW0 RW RW

RW

R0

RW RW

RW

RW0 RW

RW

RW

Initial value 0 0 00000 X 00 000 1 0 0 11110 0 0 00 0 1 00

DCM1

Register address 01FD_0100H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name

DE

N

reserve L4E

L3E

L2E

L1E

L0E

CK

S

LCS

SC EE

Q

SC

SY

re-

serve

SF

ES

Y

SYNC

R/W RW

RW

0

R0 RW0 RW RW

RW

RW RW

RW

RW0 RW

RW

RW

Initial value 0 0 00 0000000 00000 1 0 111101 0 0 00 0 1 00

The display control mode is set. Part is divided by the difference of the form of the bit field though the substance of the DCM0 register and the DCM1 register is one register. The value with different two registers is never maintained. This register is not initialized by software reset.

[bit1, bit0] SYNC (Synchronize) The synchronous mode is set. 00 Non-interlace mode 01 Interlace mode 11 Interlace video mode [bit2] ESY (External Synchronize) An external synchronous mode is set. 0 External synchronous invalidity 1 Synchronization is external effective. [bit3] SF (Synchronize signal Format) The form of Synchronous Idle (VSYNC, HSYNC) is set. 0 Negative-true logic 1 Positive logic [bit6] SCSY (Select CSYNC output) What you output to the CSYNC output terminal is set. 0 The CSYNC signal is output to the CCYNC output terminal. 1 The GV signal is output to the CCYNC output terminal.

6.4. Register



[bit7] EEQ (Enable Equalizing pulse) The mode of the CCYNC signal is set. 0 The pulse of the change to Hitoshi is not inserted in the CCYNC signal. 1 The pulse of the change to Hitoshi is inserted in the CCYNC signal. [bit13～bit8] SC (Scaling)

Dividing frequency and the dot clock of the display standard clock are generated with the set ratio.

DCM0 DCM1

x00000 Frequency is not

divided. 000000

Frequency is not divided.

x00001 ..1/4.. dividing

frequency 000001

..1/2.. dividing frequency

x00010 ..1/6.. dividing

frequency 000010


x00011 ..1/8.. dividing

frequency 000011


: :

x11111 ..1/64.. dividing

frequency 111111


When n is set with DCM0, the ratio of dividing frequency is 1/(2n+2). When m is set with DCM1, the ratio of dividing frequency is 1/(m+1). Both are the basic configuration parameters of the same function, and 2n+2=m+1. It becomes the relation of m=2n+1 from it. When n is set to the SC field of DCM0 here, it becomes 2n+1 and it is reflected in DCM1.

[bit14] LCS (Lower frequency Clock Select) The frequency of built-in PLL clock is selected. 0 Standard frequency GDCPLLCLK(108MHz or less) 1 ..low.. frequency GDCSSCGCLK(81MHz or less) [bit15] CKS (Clock Source) A standard clock is selected. 0 A standard clock is made an output of built-in PLL. 1 A standard clock is made DCLKI signal input. [bit16] L0E (L0-layer Enable) The L0 layer display is effectively done. 0 The L0 layer is not displayed. 1 The L0 layer is displayed. [bit17] L1E (L1-layer Enable) The L1 layer display is effectively done. 0 The L1 layer is not displayed. 1 The L1 layer is displayed.

6.4. Register



[bit18] L23E (L2 & L3-layer Enable) -------- DCM0

The L2 layer and the L3 layer are made effective at the same time. It corresponds to M layer of the product so far.

0 Neither the L2 layer nor the L3 layer are displayed. 1 The L2 layer and the L3 layer are displayed. L2E(L2-layer Enable) ------- DCM1 The L2 layer display is effectively done. 0 The L2 layer is not displayed. 1 The L2 layer is displayed. [bit19] L4E (L4 layer Enable) -------- DCM0

The L4 layer is made efficacy. It corresponds to the BL layer of the product so far. It is only for Sprite.

0 The L4 layer is not displayed. 1 The L4 layer is displayed. L3E (L3-layer Enable) ------- DCM1 The L3 layer display is effectively done. 0 The L3 layer is not displayed. 1 The L3 layer is displayed. [bit20] L4E (L4-layer Enable) The L4 layer display is effectively done. 0 The L4 layer is not displayed. 1 The L4 layer is displayed. [bit31] DEN (Display Enable)

The display is enable. As for reading this bit, the value in which the DCLK clock is passed is read. (notes)Please note the following respect when you update this bit when the sprite display function is used. Please do the update of this bit (0 writing) for a vertical, synchronous period when you do the setting that doesn't output the display signal. The detection of a vertical, synchronous event must use the Wait Trigger function of a vertical, synchronous interruption or the command list. When the display output is restarted, sprite might not be appropriately displayed when this bit is not updated for a vertical, synchronous period.

0 The display signal is not output. 1 The display signal is output.

6.4. Register



6.4.3.2.2. DCM2 (Display Control Mode 2)


Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved RUF RUM

R/W R0 RW RW

Initial value 0 0 0

[bit0] RUM (Register Update Mode)

The mode that reflects the register value synchronizing with vertical synchronization is selected.

0 The register update is in real time reflected in the internal control circuit. The display falls into disorder when updating it for the display period.

1 The internal control circuit is told the value of the register synchronizing with vertical synchronization. The simultaneity is controlled with the following RUF flags.

[bit1] RUF (Register Update Flag)

The value is directed to be updated in the following vertical synchronization in writing one in this flag. If the update ends, it becomes 0.

0 Initial state or update end 1 Vertical, synchronous waiting

6.4. Register



6.4.3.2.3. DCM3 (Display Control Mode 3)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve

RG

Brv

R

GB

sh

reserve

DC

Ked

D

CK

inv

reserve DCKD

R/W R0 RW0 RW R0

RW0 R0

RW

0 R

0 R

W0

RW

RW

0

R0 RW

Initial value 0000 000000 00 0 000 000 0 0 0 00 0 00 00000

[bit5～bit0] DCKD ( Display Clock Delay) Additional DeLay is defined with each internal PLL clock. 00000 There is no addition DeLay. 00010 +2 PLL clock 00100 +3 PLL clock 00110 +4 PLL clock : : 11110 +17 PLL clock xxxx1 reserve

[bit8] DCKinv (Display Clock inversion ) 0: There is not DCLKO output signal reversing. 1: The DCLKO output signal is reversed.

[bit9] DCKed (Display clock edge ) The edge used is defined. 0: Single edge mode. RGB output is done by the Ta edge. 1: Both edge mode. RGB output is done by a positive edge and a negative edge.

[bit20] RGBsh (Display clock edge ) 0: Output usually 1: RGB output is shifted and only 2bit shifts to the LSB side.

[bit21] RGBrv (RGB reverse) 0: Output usually 1: RGB bit reversing output

6.4. Register



6.4.3.2.4. HTP (Horizontal Total Pixels)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Bit field name Reserved HTP

R/W R0 RW

Initial value 0 Irregularity

A horizontal total number of pixels is specified. Set value +1 becomes a total number of pixels.

6.4.3.2.5. HDP (Horizontal Display Period)


Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved HDP

R/W R0 RW


A horizontal display period is specified with each pixel clock. Set value +1 becomes a number of pixels at the display period.

6.4.3.2.6. HDB(Horizontal Display Boundary)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Bit field name Reserved HDB

R/W R0 RW


The display period of a left screen is specified with each pixel clock. Set value +1 becomes the number of pixels for a left screen at the display period. When the right and left division display is not done, the value equal to HDP is set.

6.4.3.2.7. HSP (Horizontal Synchronize pulse Position)

Register address 01FD_000CH

Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved HSP

R/W R0 RW


The pulse position of the horizontal synchronizing signal is specified with each pixel clock. When the number of clocks from the display period beginning (13 offset = clocks are included) reaches set value +1, the horizontal synchronizing signal is asserted.

6.4. Register



6.4.3.2.8. HSW (Horizontal Synchronize pulse Width)


Bit number 23 22 21 20 19 18 17 16

Bit field name HSW

R/W RW

Initial value Irregularity

The pulse width of the horizontal synchronizing signal is specified with each pixel clock. Set value +1 becomes the number of clocks of pulse widths.

6.4.3.2.9. VSW (Vertical Synchronize pulse Width)


Bit number 31 30 29 28 27 26 25 24

Bit field name VSWH Reserved VSW

R/W RW R0 RW

Initial value 0 0 Irregularity

[bit29～bit24] VSW ( Vertical Synchronize pulse Width )

The pulse width of the vertical synchronizing signal is specified in each lusterware. Set value +1 becomes the number of lusterwares of pulse widths.

[bit31] VSWH (VSW Half )

The pulse width of the vertical synchronizing signal is extended and only the half of one lusterware extends.

6.4.3.2.10. VTR (Vertical Total Rasters)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Bit field name Reserved VTR

R/W R0 RW


The number of vertical directions of total lusterwares is specified. Set value +1 becomes the number of total lusterwares. Set value +1.5 becomes the numbers of total lusterwares of one field at the interlace display, and 2 × set value +3 becomes the numbers of total lusterwares of one frame. (reference: "エラー! 参照元が見つか

りません。Interlace display")

6.4. Register



6.4.3.2.11. VSP (Vertical Synchronize pulse Position)


Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved VSP

R/W R0 RW


The pulse position of the vertical synchronizing signal is specified in each lusterware. A vertical synchronization pulse is asserted from set value + first lusterware based on the display beginning lusterware.

6.4.3.2.12. VDP (Vertical Display Period)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Bit field name Reserved VDP

R/W R0 RW


The display period in the vertical direction is specified in each lusterware. Set value +1 becomes the number of display lusterwares.

6.4. Register



6.4.3.2.13. L0M (L0-layer Mode)


Bit number 31 30 29 28 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L0C Reserve L0W Reserve L0H

R/W RW R0 RW R0 RW

Initial value 0 0 Irregularity 0 Irregularity

[bit11～bit0] L0H (L0-layer Height) The height of a logical frame of the L0 layer is specified in each pixel. Set value +1

becomes height. [bit23～bit16] L0W (L0-layer memory Width) The width of the memory of a logical frame of the L0 layer (stride) is set in 64 bytes. [bit31] L0C (L0-layer Color mode) The color mode of the L0 layer is set. 0 Indirect color (8bit/pixel) mode 1 Direct color (16bit/pixel) ARGB mode

6.4.3.2.14. L0EM (L0-layer Extended Mode)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----- 4 3 2 1 0

Bit field name L0EC Reserve L0PB Reserve L0W

P

R/W RW R0 RW R0 RW

Initial value 0 0 0 0

[bit0] L0WP (L0-layer Window Position enable)

The position where the L0 layer is displayed is selected. Old interchangeable kind (MB86290-292) display can be selected.

0 Interchangeable mode display(for C layer) 1 Window display

[bit23～bit20] L0PB (L0-layer Palette Base)

The value added to the index when the palette of the L0 layer is pulled is indicated. 16 times a set value are added.

[bit31～bit29] L0EC (L0-layer Extended Color mode) The enhancing color mode of the L0 layer is set. 000 It follows L0C. 010 Direct color (24bit/pixel) mode 011 Direct color (16bit/pixel) RGB565 mode 100 Direct color (16bit/pixel) RGBA mode 110 Direct color (24bit/pixel) RGBA mode

6.4. Register



6.4.3.2.15. L0OA (L0-layer Origin Address)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L0OA

R/W RW RW0


The logical frame starting point address of the L0 layer is set. Because four subordinate position bits are 0 fixation, it becomes 16 Baitoarain.

6.4.3.2.16. L0DA (L0-layer Display Address)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L0DA

R/W RW


The display starting point address of the L0 layer is set. One subordinate position bit is treated for direct color mode (16bit/pixel) assuming that the aryne is done by 0 by every two bytes.

6.4.3.2.17. L0DP (L0-layer Display Position)

Register address 01FD_002cH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved L0DY Reserved L0DX

R/W R0 RW R0 RW

Initial value 0 Irregularity 0 Irregularity

Display beginning position coordinates (DX, DY) of the L0 layer are set in each pixel based on the logical frame starting point.

[bit11～bit0] L0DX ( L0-layer Display Position X) X coordinates are specified. [bit27～bit16] L0DY ( L0-layer Display Position Y) Y coordinates are specified.

6.4. Register



6.4.3.2.18. L0WP (L0-layer Window Position)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved L0WY Reserved L0WX

R/W R0 RW R0 RW


Display position coordinates (WX, WY) of the L0 layer window are set. The starting point becomes on the left of the display.

[bit11～bit0] L0WX ( L0-layer Window Position X) X coordinates are specified. [bit27～bit16] L0WY ( L0-layer Window Position Y) Y coordinates are specified.

6.4.3.2.19. L0WS (L0-layer Window Size)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved L0WH Reserved L0WW

R/W R0 RW R0 RW


The size of the L0 layer window is set.

[bit11～bit0] L0WW ( L0-layer Window Width X) Width is specified in each pixel. Please do not set 0. [bit27～bit16] L0WH ( L0-layer Window Height Y) Height is specified. Set value +1 becomes height.

6.4. Register



6.4.3.2.20. L1M (L1-layer Mode)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ----- 5 4 3 2 1 0

Bit field name L1C L1YC L1CS L1IM Reserve L1W Reserve

R/W RW RW RW RW R0 RW R0

Initial value 0 0 0 0 0 Irregularity 0

[bit23～bit16] L1W (L1-layer memory Width) The width of the memory of a logical frame of the L1 layer (stride) is set in 64 bytes. [bit28] L1IM (L1-layer Interlace Mode) L1CS sets the video capture operation mode at the capture mode. 0 Normal mode

1 It displays it in the WEAVE mode at the non-interlace display. Each frame

(pair of the odd number field and the even number field) and the buffer controls are done at interlace & video display.

[bit29] L1CS (L1-layer Capture Syncronize)

Whether the L1 layer is assumed to be a usual display layer or it uses it for the video capture is set.

0 Normal mode 1 Capture mode [bit30] L1YC (L1-layer YC mode) The color format of the L1 layer is set. 0 RGB mode 1 YC mode [bit31] L1C (L1-layer Color mode) The color mode of the L1 layer is set. 0 Indirect color (8bit/pixel) mode 1 Direct color (16bit/pixel) RGB mode

6.4. Register





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 … 4 3 2 1 0

Bit field name L1EC resv Resv VMAG L1PB ReserveL1LC

E reserve CAOFS

R/W RW RW0 R0 RW RW R0 RW RW0 RW

Initial value 0 0 0 0 0 0 0 0

[bit12～bit0] CAOFS (Capture Offset) The capture image display position can be fine-tuned. Please specify 0 when unused. [bit16] L1LCE (L1-layer level conversion enable)

It is specified to do the L1 layer color element level conversion. The translation table is defined with L1LCT0-255.

0 The color element level conversion is not used. 1 The color element level conversion is used. [bit23～bit20] L1PB (L1-layer Palette Base)


[bit25, bit24] VMAG (Video Magnify) The expansion of the capture image is specified. 00 The expansion function is not used. 01 Booking 10 The expansion function is used. 11 Booking [bit31, bit30] L1EC (L1-layer Extended Color mode) The enhancing color mode of the L1 layer is set. 000 It follows L1C. 010 Direct color (24bit/pixel) mode 011 Direct color (16bit/pixel) RGB565 mode 100 Direct color (16bit/pixel) RGBA mode 110 Direct color (24bit/pixel) RGBA mode

6.4. Register



6.4.3.2.22. L1DA (L1-layer Display Address)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L1DA

R/W RW


The display starting point address of the L1 layer is set. One subordinate position bit is treated for direct color mode (16bit/pixel) assuming that the aryne is done by 0 by every two bytes. Because the L1 layer doesn't process the wraparound, XY coordinates at a frame starting point linear address and the display position are not specified. This register is allocated at the same address as the following CBDA0 registers. Deciding which register becomes effective becomes the L1CS bit of the L1M register.

L1CS=0 --- The L1DA register is effective. L1CS=1 --- The CBDA0 register is effective.

6.4.3.2.23. CBDA0 (Capture Buffer Display Address 0)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CBDA0

R/W R


It is a register only of reading that can be accessed for "1" the L1CS bit of the L1M register. The first address of the displayed capture image is shown. The L1CS bit shows the first address in the odd number field on the capture screen for "1" it and "1" further the L1IM bit.

6.4.3.2.24. CBDA1 (Capture Buffer Display Address 1)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CBDA1

R/W R


It is a register only for reading that the L1CS bit becomes effective for only "1" it and "1" further the L1IM bit. The first address in the even number field on the capture screen is shown.

6.4. Register




Register address 01FD_0124H (01FD_0018H)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW


Display position coordinates (WX, WY) of the L1 layer window are set. The starting point becomes on the left of the display. The map is done in two addresses.



Register address 01FD_0128H (01FD_001CH)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW


The size of the L1 layer window is set. The map is done in two addresses.


6.4. Register



6.4.3.2.27. L2M (L2-layer Mode)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 -- 4 3 2 1 0

Bit field name L2C L2FLP Reserve L2W Reserve L2H

R/W RW RW RW0 R0 RW R0 RW

Initial value 0 00 0 0000 Irregularity 0000 Irregularity

[bit11～bit0] L2H (L2-layer Height)

The height of a logical frame of the L2 layer is specified in each pixel. Set value +1 becomes height.

[bit23～bit16] L2W (L2-layer memory Width) The width of the memory of a logical frame of the L2 layer (stride) is set in 64 bytes. [bit30, bit29] L2FLP (L2-layer Flip mode) The flipping mode of the L2 layer is set. 00 Respect 0 is displayed. 01 Respect 1 is displayed. 10 Respect 0 and respect 1 of each frame are alternately displayed. 11 Booking [bit31] L2C (L2-layer Color mode) The color mode of the L2 layer is set. 0 Indirect color (8bit/pixel) mode 1 Direct color (16bit/pixel) ARGB mode

6.4. Register





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 4 3 2 1 0

Bit field name L2EC Reserve L2PB Reserve L2OM L2WP

R/W RW R0 RW R0 RW RW

Initial value 000 0 0 0 0 0

[bit0] L2 WP (L2-layer Window Position enable)

The position where the L2 layer is displayed is selected. Old interchangeable kind (MB86290-292) display can be selected. 0 Interchangeable mode display(for ML layer) 1 Window display

[bit1] L2OM (L2-layer Overlay Mode)

The overlapping mode of the L2 layer is selected. Old interchangeable kind (MB86290-292) display can be selected. 0 Interchangeable mode 1 Enhancing mode



[bit31～bit29] L2EC (L2-layer Extended Color mode) The enhancing color mode of the L2 layer is set. 000 It follows L2C. 010 Direct color (24bit/pixel) mode

011 Direct color (16bit/pixel) RGB565 mode 100 Direct color (16bit/pixel) RGBA mode 110 Direct color (24bit/pixel) RGBA mode

6.4.3.2.29. L2OA0 (L2-layer Origin Address 0)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L2OA0

R/W RW RW0


The logical frame starting point address in layer and L2 respect 0 is set. Because four subordinate position bits are 0 fixation, it becomes 16 Baitoarain.

6.4. Register



6.4.3.2.30. L2DA0 (L2-layer Display Address 0)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L2DA0

R/W RW


The display starting point address in layer and L2 respect 0 is set. One subordinate position bit is treated for direct color mode (16bit/pixel) assuming that the aryne is done by 0 by every two bytes.



Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW RW0





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW




6.4. Register





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW






Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW




6.4. Register



6.4.3.2.36. L3M (L3-layer Mode)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 -- 4 3 2 1 0

Bit field name L3C L3FLP Reserve L3W Reserve L3H

R/W RW RW RW0 R0 RW R0 RW

Initial value 0 00 0 0000 Irregularity 0000 Irregularity

[bit11～bit0] L3H (L3-layer Height)

The height of a logical frame of the L3 layer is specified in each pixel. Set value +1 becomes height.

[bit23～bit16] L3W (L3-layer memory Width) The width of the memory of a logical frame of the L3 layer (stride) is set in 64 bytes. [bit30～bit29] L3FLP (L3-layer Flip mode) The flipping mode of the L3 layer is set. 00 Respect 0 is displayed. 01 Respect 1 is displayed. 10 Respect 0 and respect 1 of each frame are alternately displayed. 11 Booking [bit31] L3C (L3-layer Color mode) The color mode of the L3 layer is set. 0 Indirect color (8bit/pixel) mode 1 Direct color (16bit/pixel) ARGB mode

6.4. Register





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 4 3 2 1 0

Bit field name L3EC Reserve L3PB Reserve L3OM L3WP

R/W RW R0 RW R0 RW RW

Initial value 000 0 0 0 0 0

[bit0] L3 WP (L3-layer Window Position enable)

The position where the L3 layer is displayed is selected. Old interchangeable kind (MB86290-292) display can be selected.

0 Interchangeable mode display(for MR layer) 1 Window display

[bit1] L3OM (L3-layer Overlay Mode)

The overlapping mode of the L3 layer is selected. Old interchangeable kind (MB86290-292) display can be selected.

0 Interchangeable mode 1 Enhancing mode



[bit31～bit29] L3EC (L3-layer Extended Color mode) The enhancing color mode of the L3 layer is set.

000 It follows L3C.

011 Direct color (24bit/pixel) ARGB mode 011 Direct color (16bit/pixel) RGB565 mode 100 Direct color (16bit/pixel) RGBA mode 110 Direct color (24bit/pixel) RGBA mode



Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW RW0



6.4. Register





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW RW0





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW




6.4. Register





Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW






Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW




6.4. Register



6.4.3.2.45. DLS (Display Layer Select)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve DLS4 DLS3 DLS2 DLS1 DLS0

R/W R0W0 R0W0 R0W0 RW RW RW RW RW

Initial value 0111 0110 0101 0100 0011 0010 0001 0000

The order by which the layer is overlapped is defined.

[bit3～bit0] DLS0 (Display Layer Select 0) The layer of most significant is selected. 0000 L0 layer 0001 L1 layer : : 0111 L7 layer 1000 Booking : : 1110 Booking 1111 Non-selection [bit7～bit4] DLS1 (Display Layer Select 1)

The second layer is selected. The correspondence of the value is the same as DSL0.

[bit11～bit8] DLS2 (Display Layer Select 2)

The third layer is selected. The correspondence of the value is the same as DSL0.


The fourth layer is selected. The correspondence of the value is the same as DSL0.


The fifth layer is selected. The correspondence of the value is the same as DSL0.

6.4. Register



6.4.3.2.46. MDC (Multi Display Control)


Bit number 31 30 29 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name MDen reserve reserve SC1en SC0en

R/W RW R0 R0W0 RW RW

Initial value 0 0 Irregularity Irregularity Irregularity

A dual display is controlled. The correspondence of effective invalidity, the display screen, and the display layer is set. (reference: 6.5.8. dual display)

[bit0] SC0en0 ( screen 0 enable 0) 0: L0 is not included in screen 0. 1: L0 is included in screen 0. [bit1] SC0en1 ( screen 0 enable 1) 0: L1 is not included in screen 0. 1: L1 is included in screen 0. [bit4] SC0en4 ( screen 0 enable 4) 0: L4 is not included in screen 0. 1: L4 is included in screen 0. [bit8] SC1en0 ( screen 1 enable 0) 0: L0 is not included in screen 1. 1: L0 is included in screen 1. [bit9] SC1en1 ( screen 1 enable 1) 0: L1 is not included in screen 1. 1: L1 is included in screen 1. [bit12] SC1en4 ( screen 1 enable 4) 0: L4 is not included in screen 1. 1: L4 is included in screen 1. [bit31] MDen ( multi display enable ) A dual (multi) display mode is made effective. 0: Single display mode 1: Dual display mode

6.4. Register



6.4.3.2.47. DBGC (Display Background Color)


Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserve DBGR DBGG DBGB

R/W

RW

0

R0 RW RW RW

Initial value 0 0 0 0 0

The color displayed in the area that comes off from the display area of each layer on the screen is specified.

[bit7～bit0] DBGB (Display Background Blue) A blue level of the background color is specified. [bit15～bit8] DBGG (Display Background Green) A green level of the background color is specified. [bit23～bit16] DBGR (Display Background Red) A red level of the background color is specified.

6.4. Register



6.4.3.2.48. L0BLD (L0 Blend)

Register address 01FD_00B4H

Bit number 31 30 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserve L0BE L0BS L0BI L0BP L0ID L0AF resv resv L0BR

R/W R0 RW RW RW RW RW RW R0W0 R0 RW

Initial value 0 0 0 0 0 0 0 0 0 0

It blends about the L0 layer and it specifies parameters. It corresponds to BRATIO of old kind (MB86290-292) and BMODE.

[bit7～bit0] L0BR (L0-layer Blend Ratio) The blend ratio is set. Set value/256 basically becomes blend ratios. [bit11, bit10] L0AF (L0-layer Alpha Field) The bit field of the alpha layer is selected. 00 Bit7-bit0 is treated as an alpha layer. 01 Bit15-bit8 is treated as an alpha layer. 10 Bit23-bit16 is treated as an alpha layer. [bit12] L0ID (L0-layer Ignore Data) It is specified whether to receive the influence of A field of the displayed data. 0 Only when A field of the displayed data is one, the blend is done. 1 A field of the displayed data is disregarded. [bit13] L0BP (L0-layer Blend Plane )

Whether the alpha layer is assumed to be a blend ratio whether to assume the constant value to be a blend ratio is selected.

0 The value of L0BR is assumed to be a blend ratio. 1 The pixel of the L3 layer is assumed to be a blend ratio. [bit14] L0BI (L0-layer Blend Increment) It is selected whether to add 1/256 when the blend ratio is not 0. 0 The blend ratio is calculated as it is. 1 When the blend ratio is not 0, 1/256 is added. [bit15] L0BS (L0-layer Brend Select) The blend calculation type is selected.

0 High-ranking image × blend ratio + subordinate position image ×(ratio of one-blend)

1 (ratio of one-blend) High-ranking image × Ratio of + subordinate position image × blend

[bit16] L0BE (L0-layer Blend Enable) The blend is made effective. 0 Overlapping by transparent color 1 Overlapping by blend

When the blend is done, the blend mode is specified with L0BE, and it should be the L0 layer displayed data and, in addition, A field be, 1. A field of the displayed data is disregarded for L0ID=1.

6.4. Register



6.4.3.2.49. L1BLD (L1 Blend)


Bit number 31 30 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



Initial value 0 0 0 0 0 0 0 0 0 0

It blends about the L1 layer and it specifies parameters.








6.4. Register



6.4.3.2.50. L2BLD (L2 Blend)


Bit number 31 30 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



Initial value 0 0 0 0 0 0 0 0 0 0









6.4. Register



6.4.3.2.51. L3BLD (L3 Blend)


Bit number 31 30 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



Initial value 0 0 0 0 0 0 0 0 0 0

It blends about the L3 layer and it specifies parameters. [bit7～bit0] L3BR (L3-layer Blend Ratio) The blend ratio is set. Set value/256 basically becomes blend ratios. [bit11, bit10] L3AF (L3-layer Alpha Field)

The bit field of the alpha layer is selected. There is no usage in the L3 layer to refer to oneself as an alpha value.

00 Bit7-bit0 is treated as an alpha layer. 01 Bit15-bit8 is treated as an alpha layer. 10 Bit23-bit16 is treated as an alpha layer. [bit12] L3ID (L3-layer Ignore Data) It is specified whether to receive the influence of A field of the displayed data. 0 Only when A field of the displayed data is one, the blend is done. 1 A field of the displayed data is disregarded. [bit13] L3BP (L3-layer Blend Plane )






When the blend is done, the blend mode is specified with L3BE, and it should be the L3 layer displayed data and, in addition, A field be, 1. A field of the displayed data is disregarded for L3ID=1. Oneself will be referred to as an alpha coefficient when using it with L3BP=1. It becomes a significant display only for L3AF=00 by 32bit/pixel of the RGBA form. In this case, it should be L3BI=1. Because the color element is used as a blend coefficient, a meaningless image will be displayed though it is possible to set excluding L3AF=00.

6.4. Register



6.4.3.2.52. L4BLD (L4 Blend)


Bit number 31 30 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



Initial value 0 0 0 0 0 0 0 0 0 0


[bit7～bit0] L4BR (L4-layer Blend Ratio) The blend ratio is set. Set value/256 basically becomes blend ratios. [bit11～bit10] L4AF (L4-layer Alpha Field) The bit field of the alpha layer is selected. 00 Bit7-bit0 is treated as an alpha layer. 01 Bit15-bit8 is treated as an alpha layer. 10 Bit23-bit16 is treated as an alpha layer. [bit12] L4ID (L4-layer Ignore Data)

It is specified whether to receive the influence of A field of the displayed data. Sprite A field doesn't exist in the image, and use it with L4ID=1, please.

0 Only when A field of the displayed data is one, the blend is done. 1 A field of the displayed data is disregarded. (recommended value) [bit13] L4BP (L4-layer Blend Plane )







6.4. Register



6.4.3.2.53. L0TC (L0-layer Transparency Control)

Register address 01FD_00BCH

Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L0ZT L0TC

R/W RW RW

Initial value 0 0

The transparent color of the L0 layer is set. The color set by this register for the blend mode becomes transparent. Color 0 is displayed for L0TC=0 and L0ZT=0 as a black (opacity). It corresponds to the CTC register of old kind (MB86290-292).

[bit14～bit0] L0TC (L0-layer Transparent Color)

The color value (code) assumed to be a transparent color in the L0 layer is set. Bit7-bit0 is used for indirect color mode (8bit/pixel).

[bit15] L0ZT (L0-layer Zero Transparency) The color value (code) in C layer The treatment of 0 is set. 0 Code 0 is not assumed to be transparent. 1 Code 0 is assumed to be transparent.


Register address 01FD_00C2H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


R/W RW RW

Initial value 0 0

The transparent color of the L2 layer is set. Color 0 is displayed for L2TC=0 and L2ZT=0 as a black (opacity). It corresponds to the MLTC register of old kind (MB86290-292).



[bit31] L2ZT (L2-layer Zero Transparency) The color value (code) in the L2 layer The treatment of 0 is set. 0 Code 0 is not assumed to be transparent. 1 Code 0 is assumed to be transparent.

6.4. Register





Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW RW

Initial value 0 0

The transparent color of the L3 layer is set. Color 0 is displayed for L3TC=0 and L3ZT=0 as a black (opacity). Old kind (MB86290-292)It corresponds to ..MRTC.. register drinking.



[bit15] L3ZT (L3-layer Zero Transparency) The color value (code) in the L3 layer The treatment of 0 is set. 0 Code 0 is not assumed to be transparent. 1 Code 0 is assumed to be transparent.

6.4.3.2.56. L0ETC (L0-layer Extend Transparency Control)

Register address 01FD_01A0H

Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L0EZT Reserve L0TEC

R/W RW R0 RW

Initial value 0 0 0

The transparent color of the L0 layer is set. The transparent color of 24bit/pixel is done by this register. Subordinate position 15bit physically becomes the same register with L0TC. Moreover, L0EZT physically becomes the same register with L0ZT. Color 0 is displayed for L0ETC=0 and L0EZT=0 as a black (opacity).

[bit23～bit0] L0ETC (L0-layer Extend Transparent Color)


[bitt31] L0EZT (L0-layer Extend Zero Transparency) The color value (code) in the L0 layer The treatment of 0 is set. 0 Code 0 is not assumed to be transparent. 1 Code 0 is assumed to be transparent.

6.4. Register





Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name L1EZT Reserve L1ETC

R/W RW R0 RW

Initial value 0 0 0

The transparent color of the L1 layer is set. Color 0 is displayed for L1ETC=0 and L1EZT=0 as a black (opacity). The transparent color judgment assumes it doesn't do, and it is not transparent and is processed at the YCbCr display.



[bit31] L1EZT (L1-layer Extend Zero Transparency) The color value (code) in the L1 layer The treatment of 0 is set. 0 Code 0 is not assumed to be transparent. 1 Code 0 is assumed to be transparent.



Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW R0 RW

Initial value 0 0 0





6.4. Register




Register address 01FD_01ACH

Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW R0 RW

Initial value 0 0 0







Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W RW R0 RW

Initial value 0 0 0

The transparent color of the L4 layer is set. Color 0 is displayed for L4ETC=0 and L4EZT=0 as a black (opacity).


The color value assumed to be a transparent color in the L4 layer is set by RGB form 24bit. It is general to set the same color value as the background color of the sprite screen.


6.4. Register



6.4.3.2.61. CKC (Chroma Key Control)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved KC

S

KY

EN

KYC

R/W R0 RW RW RW

Initial value 0 0 0 Irregularity

[bit14～bit0] KYC (Key Color) The key color that processes the chroma-key is set. When indirect color mode

(8bit/pixel) and the chroma-key mode are set to C Rayacarar, bit7-bit0 is used. [bit15] KYEN (chroma-Key Enable) Right or wrong of the chroma-key processing is set. 0 The chroma-key is not processed. (The terminal GV always outputs H. ) 1 The chroma-key is processed. [bit16] KCS (Key Color Select) The key color of the chroma-key processing is assumed to be a display color or it is

assumed the color of C layer or selects it. 0 The key color is assumed to be a display color. 1 The key color is made C Rayacarar.

6.4.3.2.62. L1YCR0 (L1 layer YC to Red coefficient 0)

Register address 01FD_01E0H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved a12 Reserved a11

R/W R0 RW R0 RW

Bit number 0 000 0000 0000 0 001 0010 1011

This register defines the parameter concerning a red element in the YCbCr/RGB conversion. [bit10～bit0] a11

It is a fixed decimal with 11bit sign. Subordinate position 8bit becomes below the decimal point. It is an one's complement expression.

[bit26～bit16] a12


6.4. Register



6.4.3.2.63. L1YCR1 (L1 layer YC to Red coefficient 1)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved b1 Reserved a13

R/W R0 RW R0 RW

Bit number 0 1 1111 0000 0 001 1001 1000

This register defines the parameter concerning a red element in the YCbCr/RGB conversion.

[bit10～bit0] a13


[bit24～bit16] b1 It is 9bit sign addition integer. It is an one's complement expression.

6.4.3.2.64. L1YCG0 (L1 layer YC to Green coefficient 0)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW

Bit number 0 111 1001 1100 0 001 0010 1011

This register defines the parameter concerning a green element in the YCbCr/RGB conversion. [bit10～bit0] a21


[bit26～bit16] a22


6.4.3.2.65. L1YCG1 (L1 layer YC to Green coefficient 1)

Register address 01FD_01ECH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW

Bit number 0 1 1111 0000 0 111 0010 1111

This register defines the parameter concerning a green element in the YCbCr/RGB conversion. [bit10～bit0] a23



6.4. Register



6.4.3.2.66. L1YCB0 (L1 layer YC to Blue coefficient 0)

Register address 01FD_01F0H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW

Bit number 0 010 0000 0100 0 001 0010 1011

This register defines the parameter concerning a blue element in the YCbCr/RGB conversion. [bit10～bit0] a31


[bit26～bit16] a32


6.4.3.2.67. L1YCB1 (L1 layer YC to Blue coefficient 1)

Register address 01FD_01F4H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


R/W R0 RW R0 RW

Bit number 0 1 1111 0000 0 000 0000 0000

This register defines the parameter concerning a blue element in the YCbCr/RGB conversion.

[bit10～bit0] a33



6.4. Register



6.4.3.2.68. L0PAL0-255 (L0-layer Palette 0-255)

Register address 01FD_0400H -- 01FD_07FCH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name A R G B

R/W RW R0 RW R0 RW R0 RW R0

Initial value Irreg

ulari

ty

0000000 Irregularity 00 Irregularity 00 Irregularity 00

It is a color palette register of the L0 layer. As for the color code of the display frame, when displaying it by an indirect color mode, the color that is used as a palette register number, and set to the register becomes the display color of the pixel. It corresponds to CPALn of old kind (MB86290-292).

[bit7～bit2] B (Blue) A blue element of the color is set. [bit15～bit10] G (Green) A green element of the color is set. [bit23～bit18] R (Red) A red element of the color is set. [bit31] A (Alpha)

It is specified whether to do the blend with the subordinate position layer when the blend mode is effective.

0 Even if the blend mode is effective, the blend is not done. It overlaps it by the transparent color.

1 The blend is done.

6.4. Register




Register address 01FD_0800H ? 01FD_0BFCH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



Initial value Irreg

ulari

ty


It is a color palette register of the L1 layer. As for the color code of the display frame, when displaying it by an indirect color mode, the color that is used as a palette register number, and set to the register becomes the display color of the pixel. It corresponds to MBPALn of old kind (MB86290-292).





6.4. Register




Register address 01FD_1000H -- 01FD_13FCH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



Initial value Irreg

ulari

ty


It is a color palette register of the L2 layer. As for the color code of the display frame, when displaying it by an indirect color mode, the color that is used as a palette register number, and set to the register becomes the display color of the pixel.





6.4.3.2.71. L1LCT0-255 (L1 Level Conversion table 0-255)

Register address 01FD_2000H ～ 01FD_23FCH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name R G B

R/W R0 RW R0 RW R0 RW R0

Initial value 0 Irregularity 0 Irregularity 0 Irregularity 0

The color element level of the L1 layer is converted. It is conversion from 256 levels to 256 levels.

[bit9～bit2] B (Blue) When value x is set to B field of L1LCTn, level n of B element is converted into x. [bit19～bit12] G (Green) When value y is set to G field of L1LCTn, level n of G element is converted into y. [bit29～bit22] R (Red) When value z is set to R field of L1LCTn, level n of R element is converted into z.

6.5. Operation explanation




6.5.1. Display function

6.5.1.1. Screen structure The window is displayed by four hierarchy display. The order of overlapping the layer can be arbitrarily set. Four high-ranking layers are more interchangeable than old goods kind (MB86290-296). The sprite screen is overlapped and displayed on the screen of the old goods kind. The sprite screen is treated as L4.

Figure6-2Composition of display

L1 (L1WX,L1WY)

L0 (L0WX,L0WY)L3 (L3WX,L3WY)

L2 (L2WX,L2WY)

(a) full window mode

L0,L2(0,0)L3 (HDB+1,0) L1 (WX,WY)

(b) partial window mode

background color

L4 (0,0) : sprite L4 (0,0) : sprite

The correspondence of the layer of ..old goods kind (MB86290-296).. display is as follows.

Beginning point coordinates Width and height Existing kind layer

GDC macro (a)Window

(b)Interchangeability

(a)Window (b)Interchangeability

L0 L1 L2 L3

C W ML MR

L0 L1 L2 L3 (aplha)

(L0WX,L0WY) (L1WX,L1WY) (L2WX,L2WY) (L3WX,L3WY)

(0,0) (WX,WY) (0,0) (HDB,0)

(L0WW,L0WH+1) (L1WW,L1WH+1) (L2WW,L2WH+1) (L3WW,L3WH+1)

(HDP+1,VDP+1) (WW,WH+1) (HDB+1,VDP+1) (HDP-HDB,VDP+1)

L4 BL L4 sprite (0,0) (HDP+1,VDP+1)

L5 (alpha)

BR -----

L6 L7

--- ----- There is no correspondence.

C, W, ML, MR, BL, and BR mean the layer in old kind (MB86290-292) here. The selection of full window mode/partial window mode of each layer can be selected. The new feature can be used by the minor change of the program that operates by an old kind by the display mode is not completely divided but allowing existing together. When a high resolution is displayed, the number of layers and pixel data that can be displayed simultaneously might be limited by the ability of the supply of the data of VRAM.




6.5.1.2. Overlapping

6.5.1.2.1. Outline

The image data of (L0-L3) + four layer sprite is processed as follows.

Figure6-3Structure of display layer

Pallet-1

YUV/RGB

Pallet-2 Laye

r S

elec

tor

L0(C) data

L2(ML) data

L2 data

L3 data

Ble

nder

Ove

rlay

L1(W) data

L4 data (sprite)

L3(MR) data

L4 data (sprite)

alpha

L1LCT

Pallet-0

L1 only

A basic flow is palette → layer selection → blend. The palette converts eight bit color codes into RGB form. The layer selection arbitrarily replaces the overlapping order. Brenda does blend by the defined blend coefficient of each layer or overlaps and processes it according to the transparent color definition. The L0 layer is equivalent in C layer of old kind (MB86290-292). The L1 layer corresponds to W layer of old kind (MB86290-292). It overlaps it with the subordinate position layer to achieve lower interchangeability with an old kind before the blend is operated. Moreover, the L1 layer is possible the level conversion of the color element like the gamma control. The L2-L4 layer has two kinds of the route input to Brenda the processing route, L1 individually input to Brenda, and after it piles it up. When the same processing as former and old kind (MB86290-292) is done when processing it in the enhancing mode, the latter is selected. Which of each layer is selected can be specified.




6.5.1.2.2. Overlapping mode

There are two modes when the image layer is overlapped. It is a simple priority mode and a blend mode. The value of the subordinate position layer is assumed to be an image value of the next stage for the transparent color in the simple priority mode according to the defined transparent color of each layer, and when it is not a transparent color, own value is assumed to be a value of the next stage.

Dview = Dnew (When Dnew is not corresponding to the transparent color. ) = Dlower (When Dnew is corresponding to the transparent color. )

When the L1 layer is YCbCr mode, the transparent color judgment of L1 assumes it doesn't do, and it is not transparent and is processed. Defined blend ratio r of each layer is specified by 8bit accuracy in the blend mode, and the following operation is done.

Dview = Dnew×r + Dlower×(1-r)

The blend becomes effective because of the setting of the mode of each layer. Besides, one should stand in the A(alpha) field of the pixel. In MSB of palette RAM data and 16bit/pixel, it becomes a bit for which MSB of the word specifies an effective blend for 8bit/pixel in MSB and 24bit/pixel of own data. This bit position is different for the RGBA form in case of the ARGB form. (Refer to → data form. ) The mode always assumed to be an effective blend disregarding A field on the pixel side in the GDC macro was added. It selects it with LnID (Ln Ignore bit of blended Data).

A field of the LnID=0 blend object data is effective. A field of the LnID=1 blend object data is disregarded.

6.5.1.2.3. Blend coefficient layer

It ..L3 layer.. comes in the blend coefficient layer though the blend coefficient in a usual blend mode is fixation of each layer. The blend coefficient of each pixel can be specified in this mode and ,for instance, the gradation can be put. When this function is used, the L3 layer is set to 8bit/pixel window display mode and overlapping enhancing mode. It is 32 as for the L3 layer It is possible to use it as four worth of an alpha side when setting it to bit/pixel.




6.5.1.2.4. Synthesis of sprite

As for the L4 layer, RGB image from the sprite engine is input. The data structure in sprite is not individually recognized at the stage of overlapping among the display controllers. It processes it as an image of Shinglraya at RGB = 8:8:8. Please set the background color of sprite as 24bit transparent color of the L4 layer when selectively synthesizing it between the subordinate position layers. The subordinate position layer is displayed in the background color area. It is also possible that another who can specify it for a register setting value and the transparent color of the L4 layer transparent color is 0x000000 at the same time.

sprite sprite screen display screen

back ground color = yellow transparent color = gray

lower display layer

L4 display layer

L4 transparent color = yellow

Sprite Engine

24bit

RGB




6.5.1.3. Display parameter The display area is defined according to the following parameters. Each parameter sets the value to the register severally.

Figure6-4Display parameter

< notes > The above-mentioned and some settings of the display parameter are actually different.

Please refer to the display timing for details.

HTP Horizontal Total Pixels Horizontal total number of pixels

HSP Horizontal Synchronize pulse Position The horizontal synchronization pulse position

HSW Horizontal Synchronize pulse Width Width of the horizontal synchronization pulse

HDP Horizontal Display Period The horizontal display period

HDB Horizontal Display Boundary The horizontal division display boundary position

VTR Vertical Total Raster Number of vertical direction total lusterwares

VSP Vertical Synchronize pulse Position Vertical synchronization pulse position

VSW Vertical Synchronize pulse Width Width of vertical synchronization pulse

VDP Vertical Display Period Vertical display period

LnWX Layer n Window position X Ln layer window X coordinates

LnWY Layer n Window position Y Ln layer window Y coordinates

LnWW Layer n Window Width Ln layer and window width

LnWH Layer n Window Height Ln layer window amount

HTP

HSP

HDB

HDP

LnWY

LnWX LnWW

LnWH

VD

P

VS

P

VT

R

VSW

HSW




HDP when screen separation is not done = It is set as HDB, and displays only the left side. Moreover, a set value should fill the following big and small relation.

0 < HDB ≦ HDP < HSP < HSP+HSW+1 < HTP 0 < VDP < VSP < VSP+VSW+1 < VTR




6.5.1.4. Control of display position The displayed image data is arranged in logical two dimension coordinates space (logical image space) in VRAM. The space that maintains the display image includes the following four logical image spaces.

L0 layer, L1 layer, L2 layer, and L3 layer The relation between the logical image space and the display position is defined as follows.

Figure6-5Display position and setting parameters

Origin Address (OA) Display Address (DA) Display Position X,Y (DX,DY)

Stride (W)

Hei

ght

(H)

Logical Frame

Display Frame

VDP+1

HDP+1

OA Origin Address Logical space starting point address Memory address of pixel that becomes logical frame starting point (on the left)

W Stride Width of logical frame in every 64 bytes in logical space (memory) width

H Height Number of lusterwares (pixel) of logical space height logical spaces.

DA Display Address The address in the display starting point address display frame starting point (on the left) is shown.

DXDY Display Position Coordinates on logical frame space in display starting point coordinates display frame starting point.




A logical space does the display scanning as connected with horizontal direction and the vertical direction cyclic. They can scroll smoothly by adding and drawing in the figure that continues to the part that began to be seen from the boundary when displaying it by this function exceeding the boundary of a logical space.

Figure6-6Wraparound processing of display

64w

L

Logical Frame Origin

Additionally drawn area New display origin

Previos display origin

The relational expression of a linear address (unit of the byte) that corresponds to xy coordinates in the intraframe becomes as follows.

A(x,y)= x × bpp / 8+64wy (bpp=8, 16, 32)

The display coordinate origin should be in the intraframe. The following set restriction conditions concretely adhere to the parameter.

0 ≦ DX < w × 64 × 8 / bpp (bpp=8, 16, 32) 0 ≦ DY < H

DX, DY, and DA should show the same point in the intraframe. That is, it is necessary to have approved the following relation.

DA = OA+DX × bpp / 8+64w × DY (bpp=8, 16, 32)

Notes: A wraparound function is not provided in the L1 layer.




The L3 layer can be used as an alpha coefficient when the display blend is done. As for the alpha value, each pixel is operated as an absolute position on the display corresponding to the layer. When a corresponding window to the display is defined, the alpha value in which the pixel in four corners in the display is read from the memory is applied. As for the inside of the window, when a window that is smaller than the display is defined, the value read from VRAM is applied to the alpha value. As for the outside, alpha value =0 is applied.

LxWW

LxW

H+

1

(LxWX,LxWY)

alpha=0

alpha read from memory

Screen




6.5.2. Display timing

6.5.2.1. Non-interlace

VDP+1 rasters

VSYNCi

HSYNCi

VSP+1 rasters

VTR+1 rasters

VSW+1 rasters

HDP+1 clocks

HSP+1 clocks

HTP+1 clocks

HSW+1 clocks

HSYNCi

RiGiBi

Assert Frame Interrupt

Assert Vsync Interrupt

Latency＝ 15 clocks

DISPEi

Ri/Gi/Bi

DISPEi

DCLKOi

0 1 2 n1n2 n=HDP+1

RiGiBi

VTR and HDP, etc. indicate a set value of the corresponding register here. When the display of the last lusterware ends, VSYNC/frame interruption is asserted. The display doesn't fall into disorder when doing synchronizing with the frame interruption when the display parameter is updated. Because the calculation of the next frame is begun immediately after a vertical synchronization pulse ..asserting.., it will be necessary to update the parameter till then.




6.5.2.2. Interlace video

VDP+1 rasters

VSYNCi

HSYNCi

VSP+1 rasters

VTR+1 rasters (odd field)

VSW+1 rasters

VTR+1 rasters (even field)

VSW+1 rasters

VSYNCi

HSYNCi

VDP+1 rasters

VSP+1 rasters



Assert Frame Interrupt

Ri/Gi/Bi

Ri/Gi/Bi

VTR and HDP, etc. indicate a set value of the corresponding register here. It operates according to timing as which the interlace mode is the same. The output image data is only different.




6.5.2.3. Compound synchronous signal

When the EEQ bit of the DCM register is "0", the CSYNC signal output becomes the following shapes of waves.

CSYNCi

VSYNCi

CSYNCi

VSYNCi

odd field

even field odd field

even field

The pulse of the change to Hitoshi is inserted in the CSYNC signal when the EEQ bit of the DCM register is "1" and it becomes the following shapes of waves.

CSYNCi

VSYNC

CSYNCi

VSYNCi

odd field

even field odd field

even field

When beginning at a vertical fly back time, the pulse of the change to Hitoshi is inserted. Moreover, after it ends for a vertical, synchronous period, it is inserted three times.




6.5.3. Data form There are the following form of data treated with Display.

6.5.3.1. Indirect color(8bit/pixel) It is an index of palette RAM. It converts into the image data of each RGB 6bit with palette RAM and it displays it. The palette that can be used by the layer is different.

A

8bit

R G Bi-th entry

i

1bit 6bit 6bit 6bit

Palette RAM

256

entries

When pixel value is i, RGB output value is decided by entering i turn eyes of the palette. The accuracy of each color element of the palette becomes 6bit. Display..output..basic..accuracy..RGB..each..palette..color..element..side..shift..display..output.




6.5.3.2. Direct color(16bit/pixel) The level of RGB is expressed with 5bit or 6bit. Display..output..basic..accuracy..RGB..each..color..element..value..side..shift..display..output. There are three forms.

format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ARGB R G B

RGBA R G B

RGB565 R G B

A bit decides effective invalidity of the display blend. Accuracy rises only as for G RGB565. A field is not included and always considered to be A=1.

6.5.3.3. Direct color(24bit/pixel) The level of RGB is expressed with each 8bit. It is actually 32 one pixel = bit. There are ARGB form and RGBA form.

format 31 30 … 25 24 23 22 … 17 16 15 14 … 9 8 7 6 … 1 0

ARGB A R G B

RGBA R G B A

In the ARGB form, the effective blend invalidity is decided. MSB of A field is 0 or 1The effective blend invalidity is decided with A=0 A≠0 as an integral value of 8bit in the RGBA form.

6.5.3.4. YCbCr color(16bit/pixel) It is image data of the form at YCbCr = 4:2:2. It converts into the image data of each RGB 8bit by the operationed circuit and it displays it. Two pixels of RGB 24bit/pixel are expressed with 32bit. It is possible to treat consequentially as 16bit/pixel.

format 31 30 … 25 24 23 22 … 17 16 15 14 … 9 8 7 6 … 1 0

YCbCr Y Cr Y Cb




6.5.3.5. Alpha coefficient(8bit/pixel) The coefficient of the display blend is maintained. When the value is t, t/256 is expressed as a binary decimal. The display blend does the following operation in each color element of each pixel.

c' = c0 × t / 256 + c1 (1-t/256)

6.5.3.6. Alpha coefficient(16bit/pixel) The coefficient of the display blend is maintained. It maintains it by the form that packs two worth of an alpha value.

format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

format A1 A0

It selects it on the side by the LnAF parameter.

6.5.3.7. Alpha coefficient(24bit/pixel) The coefficient of the display blend is maintained. It maintains it by the form that packs three worth of an alpha value.

format 31 30 … 25 24 23 22 … 17 16 15 14 … 9 8 7 6 … 1 0

Alpha A2 A1 A0

It selects it on the side by the LnAF parameter.




6.5.3.8. Layer dependency The display color that can be used in each layer is as follows.

Layer Interchangeable mode Enhancing mode

L0 It is direct (16,24), and indirect. (P0) It is direct (16,24), and indirect. (P0)

L1 (16,24) and indirectly (P1) and YCbCr directly

(16,24) and indirectly (P1) and YCbCr directly

L2 It is direct (16,24), and indirect. (P1) It is direct (16,24), and indirect. (P2)

L3 It is direct (16,24), and indirect. (P1) (16,24) and direct alpha(8,32)

L4 Sprite(24)

Pn means corresponding palette RAM here. Three palettes are used as follows. Palette 0 (P0): It corresponds to C layer palette of old kind (MB86290-292). It becomes the palette of L0. Palette 1 (P1): It corresponds to the MB layer palette of old kind (MB86290-292). It becomes a common palette of L1-L3 in an interchangeable mode. It becomes L1 exclusive use palette in the enhancing mode. Palette 2 (P2): It is L2 exclusive use palette. It is possible to use it only in the enhancing mode.

6.5.4. Display scanning control

6.5.4.1. Correspondence display A typical resolution on the display that can be used and the frequency of the Synchronous Idle are shown. The pixel clock frequency is decided by setting the ratio of dividing frequency of the display standard clock. The display standard clock becomes a clock given to built-in PLL base (108MHz or 81MHz) or the DCLKI input terminal here. Various setting examples are shown in the following.

Table6.5-1Resolution and display frequency

Resolution

Ratio of standard frequency/dividing frequency =Pixel frequency

Horizontal total Pi Number of Csel

The horizontal Frequency

Vertical total Ra Number of Sta

Vertical Frequency

320 × 240 108/17=6.35MHz 403 15.75 kHz 263 59.9Hz 400 × 240 108/13=8.31MHz 538 15.73 kHz 263 59.8Hz 480 × 240 108/11=9.82MHz 624 15.76 kHz 263 59.8Hz 640 × 480 25MHz (DCLKI) 800 31.25 kHz 525 59.5Hz 640 × 480 108/4=27MHz 858 31.47kHz 525 59.5Hz

800 × 480 108/3=36MHz 1143 31.5 kHz 525 60.0Hz Standard pixel frequency = frequency /standard ratio of dividing frequency = frequency/(SC+1) Horizontal frequency = pixel frequency /horizontal total number of pixels = pixel frequency/(HTP+1) The horizontal vertical frequency = frequency /the horizontal the number of of vertical total lusterware = frequency/(VTR+1)




6.5.4.2. Interlace display The GDC macro is another and can display interlace of the non-interlace display. When the setting of the synchronous mode of the DCM0 register is interlace video (11), the image on VRAM is displayed, and the odd number lusterware and the even number lusterware of each field are alternately output, and one screen is displayed by one frame (odd number field + even number field). When the setting of the synchronous mode of the DCM0 register is interlace (01), the image on VRAM is output in order of the lusterware. The same image data as the odd number field and the even number field is output. Therefore, the number of the lusterware on the screen becomes half compared with the interlace video. However, the distinction between the odd number field and the even number field exists unlike the non-interlace mode because of the phase relation between the horizontal synchronizing signal and the vertical synchronizing signal.

Figure6-7Difference of display by synchronous mode

Odd

Even

Non-Interlace Interlace Video Interlace




6.5.5. External synchronization The display scanning can be done by synchronizing it with horizontal/vertical synchronizing signal from the outside. When an external synchronous mode is selected by the register, the GDC macro does the display that samples the HSYNC signal and synchronizes with the external video signal. The sampling clock can select built-in PLL clock or the DCLKI signal input. Moreover, superimpose can be done by the chroma-key processing. A synchronous external example of the circuit is shown as follows.

Figure6-8External synchronous use example

MB91590 series chip

GDC macro

HSYNC

VSYNC

Video SW

Analog

RGB

Analog

RGB In

Superimposed

Analog

RGB Out

Hsync In

Vsync In

GV

(Pedestal Clump Input)

Compare

3 states

KEYC

External Sync

Enable

Hsync Out

Vsync Out

L0buffer

register

CKM bit

ESY bit

Display TimingGenerator

Ove

rlap

DA

C

L0L1

L4

D-FF

An external synchronous mode is set by the ESY bit of the DCM0(1) register. If an external synchronous mode is set, HSYNC and the terminal VSYNC of the GDC macro become input modes. Afterwards, please supply Synchronous Idle from the outside in three state buffer. Moreover, please turn off the ESY in GDC macro bit after cutting a synchronous input from the outside when coming off an external synchronous mode. It is necessary to evade turning on the buffer of external Synchronous Idle with the output of a synchronous signal of the GDC macro turned on. Please control so as not to cause the period of simultaneous ON according to the above-mentioned procedure. When the external synchronizes with the display clock of built-in PLL base, the GDC macro extends the clock cycle immediately after the input of the horizontal synchronization pulse and does the phase match with the horizontal synchronizing signal. It is necessary to note it here. When the high-speed serial transfer transmitter such as LVDS is connected with digital RGB output, PLL with built-in high-speed serial transfer transmitter temporarily becomes unstable by this operation. Therefore, the external of built-in PLL base must not synchronize with the high-speed cereal transmitter.




The synchronization of horizontal direction is controlled by the following state transition.

Figure6-9Synchronous horizontal state transition chart

Horizo

nta

l pi

xel counte

r

reac

hed

HTP

.

Disp

Sync

Horizontal pixel counter

reached HDP. otherwise otherwise

otherwise

When horizontal pixel counter

reaches HTP, the counter is

initialized.

External horizontal, synchronous

detection, or

the horizontal synchronization

pulse counter reached HSW.

otherwise

Horizontal pixel counter is

stopped temporarily, and the start

of counting of the horizontal

synchronization pulse counter. H

orizo

nta

l pi

xel counte

r

reac

hed

HSP

.

Fporch

Bporch

The state transition is chiefly controlled by the count value of horizontal pixel counter. The display period corresponds in the state of Disp. It becomes an end at the display period when the value of horizontal pixel counter reaches the HDP register setting value, and it changes from the state of Disp to the state of Fporch (reception desk porch). It enters in the state of Sync when the count value of horizontal pixel counter reaches a set value of the HSP register in the state of Fporch. Under such a condition, an outside horizontal synchronizing signal is waited for. The GDC macro synchronizes detecting negating edge of an external horizontal synchronization pulse. It changes to the state of Bporch (back porch) when an external horizontal synchronizing signal is detected. Horizontal pixel counter stops in the state of Sync. 0 the horizontal synchronization pulse counter, it counts. It changes to the state of Bporch without detecting an external horizontal synchronizing signal when this count value reaches a set value of the HSW register. Horizontal pixel counter is reset when the value of horizontal pixel counter reaches the HTP register setting value in the state of Bporch, it changes to the state of Disp, and the display of the next lusterware begins. Moreover, the synchronization of the vertical direction is controlled by the following state transition.

Figure6-10Synchronous state transition chart in vertical direction

The r

aste

r counte

r

reac

hed

VTR

.

Disp

The raster counter

reached VDP. otherwise otherwise

otherwise When the raster counter

reaches VTP, the counter is

initialized.

Negate detection of

external vertical

synchronization pulse

otherwise

Ass

ert

ing.

. de

tection

of

ext

ern

al v

ert

ical

synchro

niz

atio

n p

uls

e

Fporch

Bporch Sync




In the control of the vertical direction, the count value of the lusterware counter is basic of the state transition. The display period corresponds in the state of Disp. It becomes an end at the display period when the value of the lusterware counter reaches the VDP register setting value, and it changes from the state of Disp to the state of Fporch (reception desk porch). It is waited that an external vertical synchronization pulse is asserted in the state of Fporch. It changes to the state of Sync when asserting of an external vertical synchronization pulse is detected. Under such a condition, negating of an external vertical synchronizing signal is waited for. It changes to the state of Bporch (back porch) when negating is detected. The lusterware counter is reset when the value of the lusterware counter reaches VTR register setting value in the state of Bporch, it changes to the state of Disp, and the display of the next field begins.

6.5.6. Changeable parameter of L1 layer YCbCr/RGB conversion The L1 layer can be displayed by converting the data of the YCbCr form into RGB, and the conversion parameter is changeable. The YCbCr data is converted by the next expression.

R = a11×Y + a12 × (Cb?128) + a13 × (Cr?128) + b1 G = a21×Y + a22 × (Cb?128) + a23 × (Cr?128) + b2 B = a31×Y + a32 × (Cb?128) + a33 × (Cr?128) + b3 aij ---- 11bit signed real ( lower 8bit is fraction, two's complement ) bi ----- 9bit signed integer ( two's complement )

It is expressible as follows as the operation of the procession.

R G B

a11

a21

a31

a12

a22

a32

a13

a23

a33

Y Cb-128 Cr-128

where , b =

b1

b2

b3

= A + b A =

These parameters are set to the register shown as follows.

L1YCR0 (a12, a11), L1YCR1 (b1, a13) L1YCG0 (a22, a21), L1YCG1 (b2, a23) L1YCB0 (a32, a31), L1YCB1 (b3, a33)

The same conversion as product (MB86290-296) is done so far by the first stage value set to the register immediately after reset. The register value immediately after reset is as follows.

a11 = 0x12b (299/256) , a12 = 0x0, a13 = 0x198 (408/256) a21 = 0x12b (299/256), a22 = 0x79c (-100/256), a23 = 0x72f (-209/256) a31 = 0x12b (299/256), a32 = 0x204 (516/256), a33 = 0x0 b1= b2= b3= 0x1f0 (-16)




Brightness, the contrast, hue, and the color saturation level can be controlled by changing these conversion parameters.

Adding the constant to b means an increase in brightness. Multiplying a scalar constant that is larger than one by A means an increase in the contrast. The rotation of two dimensions of Cb-128 and Cr-128 means the change in hue. The color saturation level is relative color compared with brightness strength.

A new coefficient of transformation in which these changes are reflected becomes like the next expression.

100

0 cos(t) -sin(t)

0 sin(t) cos(t)

A = c1 A0

b = bo + c3 c3 c3

100

0c2

0

00c2

= A0

c1

00

0cos(t)c1c2

-sin(t)c1c2

0sin(t)c1c2 cos(t)c1c2

A0 and b0: Initial value c1: Contrast parameter. One is a standard value. For instance, 1.2 is strengthened. c2: Color saturation level parameter. One becomes a monochrome image a standard value and 0. c3: Brightness parameter. 0 is a standard value. t : Hue rotation parameter. 0 degrees are standard values.

Notes: Please newly do the clip within the range of effective and the numerical value of the corresponding register when you calculate bi and set as aij.




6.5.7. L1 color element level conversion The level conversion can be done to color element RGB about the L1 layer image. The brightness of the entire image can be adjusted by this conversion (gamma control). It does with the table in which conversion from 256 levels to 256 levels is defined with RAM for RGB form in each element. After it converts it into RGB form, the level conversion is done for the YCbCr form.

255

0 2550

output

input

Conversion for R

255

0 2550

output

input

Conversion for G

255

02550

output

input

Conversion for B

It becomes effective by making the L1LCE bit of the L1EM register "1". The translation table is set to L1LCT0-255(0x2000-0x23fc).

The example of brightly converting the area where the image is dark is shown.

255

0 2550

output

input(80,120)

(160,160)




6.5.8. Dual display

6.5.8.1. Outline A different content can be displayed in two display devices by the dual display function of interchangeable MB86276. Two screens are multiplexed and output. Which layer to which screen is put out can be controlled. It is assumed that screen 0 is output to display device 0 here, and screen 1 is output to display device 1.

screen"1"

screen"0"display device"0"

display device"1"

GDC Macro

display

controller

6.5.8.2. Layer destination control An arbitrary layer can be included in a screen that both or the other. The layer not included in the screen is treated as a transparency. When the output is an entire turning off, the background color is displayed. It can be thought that this destination control is virtual with the following crossing point switches.

SC0en4

SC1en4

SC0en1

SC1en1

SC0en0

SC1en0

screen 0

layer 0

screen 1

background

color layer 1 layer 4

The MDen (multi display enable) bit is in the MDC(multi display control) register, and does this dual display operation effectively. The SC0en (screen"0" enable) field is in the MDC register, and specifies to which screen 0 the layer is output. The SC1en (screeen"1" enable) field is in the MDC register, and specifies to which screen 0 the layer is output.

bit0 ---- L0 is included bit1 ---- L1 is included bit2 ---- L2 is included bit3 ---- L3 is included bit4 ---- L4 is included




6.5.8.3. Output signal control Only the multiplex mode is used in the GDC macro though there are two output modes of a parallel mode and the multiplex mode. Two screens are multiplexed and output to RGB output.

sc1 sc0 sc1 sc0 sc1sc0 Rn/Gn/Bn

DCLKOn (BE)

DCLKOn (SE)

DEn

There are two modes in the clock output. BE (bi-edge) In the DCLKO mode, two output phases can be identified by both edges. SE (single-edge) In the DCLKO mode, two output phases are identified with HSYNCn or DEn.

sc0 sc1Digital RGB

DCLKO (SE)

HSYNC

even clocks

DE

ref edge

sc0 is first

The CKed( clock edge) bit is in the DCM3 register, and selects the DCLKO mode. CKed=0 becomes in the SE(single edge) mode and CKed=1 becomes BE(bi-edge) mode.




6.5.8.4. Example of output circuit (1) SE mode It is an example that separates with low-priced CPLD by using the DCLKOn clock and the DEn output of the SE mode.

DCKi

VSi

HSi

Di[18]

DCK0

VS0

HS0

D0[18]

D0[17:0]Di[17:0]

Rn[7:2]

Gn[7:2]

Bn[7:2]

DCLKOn

HSYNCn

VSYNCn

DEn

XC9572XL-TQ100

R0,G0,B0

DCLK0HSYNC0VSYNC0DE0

R1,G1,B1

DCLK1HSYNC1VSYNC1DE1

(SE mode)

GDC Macro

display device "0"

display device "1"

D1[17:0]

DCK1

VS1

HS1

D1[18]

(DCKed=0)

module XC9572XL ( DCKi, HSi,VSi,Di, DCK0,HS0,VS0,D0, DCK1,HS1,VS1,D1 );input DCKi,HSi,VSi;input[18:0] Di;output DCK0,HS0,VS0, DCK1,HS1,VS1;output[18:0] D0,D1;reg HS0,HS1, VS0,VS1, DCK0,DCK1;reg[18:0] D0,D1;

always @(posedge DCKi) begin HS0 <= HSi; HS1 <= HS0; VS0 <= VSi; VS1 <= VS0; DCK0 <= (HS0&!HSi)? 0: !DCK0; // sync to ref edge : flip DCK1 <= DCK0; if(DCK0) D0 <= Di; if(DCK1) D1 <= Di;end

endmodule




Di

DCLKi

HSi

even clocks

ref edge

sc0 sc1 sc0 sc1 sc1

sc0 sc0

sc1 sc1

DCK0

D0[18:0]

DCK1

D1[18:0]

read point

read point

(2) BE mode The data of two screens can be individually received with the DCLKO clock of the BE mode for the device that can select a positive edge and a negative edge as an active edge of the clock.

0

1 pos edge mode

(BE mode) mode

display device"0"

display device"1"

(POM=0,DCKed=1) neg edge mode

mode

GDC Macro

Rn[7:2]

Gn[7:2]

Bn[7:2]

DCLKOn

HSYNCn

VSYNCn

DEn




6.5.8.5. Display clock and timing It is necessary to supply twice the frequency compared with dual displaying or usually. The display clock of 25MHz is used for the VGA display, and the display clock of 50MHz is necessary when using it in the dual display mode. The timing settings such as HTP other than the SC(scaling ratio) parameter become the same. The maximum resolution for which the maximum display clock frequency can be used is decided. It is possible to use by the resolution of SVGA(800 × 600), and the display clock at that time becomes 80MHz.

6.5.8.6. Limitations 1) The scanning speed and the resolution of two display devices should be the same in the origin of common Synchronous Idle. 2) It is not possible to use it at the same time as the external's synchronizing. 3) When the DCLKI clock input is used as a display clock, the BE mode cannot be used.

6.5.9. Interrupt

The interrupt event that the display controller generates is as follows. There is a status flag corresponding to the INTST register in MCNT, and synchronization with each event can be managed.

Event For MCNT/INTST

VSYNC When beginning for the period of a vertical blank, it is generated.

INT2 (bit1)

FSYNC

VSYNC and in case of non-interlace display. It is generated by beginning the period of a vertical blank immediately after the end of the even number field at the interlace display and the interlace video display.

INT3 (bit3)

SYNCERR When HSYNC is cut off in an external synchronous mode, it is generated.

INT4 (bit4)

RUPDATE When the update by a register synchronous update mode ends, it is generated.

INT5 (bit5)

7.1. Outline


Capture Controller (Capture) FUJITSU SEMICONDUCTOR CONFIDENTIAL 99

7. Capture Controller (Capture)

7.1. Outline The capture controller is a controller who takes the video signal from the outside as image data. The image data can be displayed by synthesizing it to another image data. Moreover, it is possible to make it to the processing object of host CPU as a still picture.

7.2. Feature Video input

･The entry format is ITU RBT-656 or RGB666. ･After it is stored once in graphics memory (VRAM), the video format is displayed on the screen synchronizing

with the display scanning. ･The video in two systems can be input.

Scaling

･1~2 can be used for the scale-up factor. PAL or the NTSC image can be displayed in the wide screen. ･1~1/32 can be used for the scale-down factor. ･The picture Inn picture can display the drawing image and the video image on the same screen.

7.3. Location by composition of the entire GDC macro



7.3. Location by composition of the entire GDC macro


7.4. Register



7.4. Register




7.4. Register



7.4.2. Register list CaptureBaseAddress = 01FD_8000H

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VCM (Video Capture Mode) 000(h)

VIE

V

IS

V

ICE

CM

VI

NR

GB

VS

CSC(Capture SCale) 004(h)

VSCI VSCF HSCI HSCF

VCS(Video Capture Status 0) 008(h)

CE0

CBM0 (Capture Buffer Mode 0) 010(h)

OO

S

BU

F

CR

GB

CBW (stride)

BL

EN

C24

R

GB

A

CS

W

CB

ST

CBM1 (Capture Buffer Mode 1) 320(h)

C56

5

Hre

v V

rev

Rro

t

TB

UF

014(h) CBA0 (Capture Buffer Address 0 )

018(h) CBA1 (Capture Buffer Address 1 )

324(h) CBA2 (Capture Buffer Address 2)

328(h) CBOFS (Capture Buffer Offset) CISTR(Capture Image Start)

01c(h) CIVSTR CIHSTR

CIEND(Capture Image End) 020(h)

CIVEND CIHEND

7.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHP(Capture Horizontal Pixel) 028(h)

CHP

CLPF(Capture Low Pass Filter) 040(h)

CVLPF CHLPF

CMSS(Capture Magnify Source Size) 048(h)

CMSHP CMSVL CMDS(Capture Magnify Display Size)

04c(h) CMDHP CMDVL

RGBHC(RGB input HSYNC Cycle) 080(h)

RGBHC

RGBHEN(RGB input Horizontal Enable Area) 084(h)

RGBHST RGBHEN RGBVEN(RGB input Vertical Enable Area)

088(h)

RG

BV

ST

_T

RGBVST RGBVEN

VIN_VSAMP

08c(h)

VJI

TF

LT

FL

DR

EV

RGBS(RGB input SYNC) 090(h)

RM

HP

V

P

RGBCMY(RGB Color convert Matrix Y coefficient) 0c0(h)

a11 a12 a13 RGBCMCb(RGB Color convert Matrix Cb coefficient)

0c4(h) a21 a22 a23 RGBCMCr(RGB Color convert Matrix Cr coefficient)

0c8(h) a31 a32 a33 RGBCMb(RGB Color convert Matrix b coefficient)

0cc(h) b1 b2 b3

7.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CINT 178(h)

VS

CIMSK 17c(h)

VS

SYNC_err

180(h)

VS

L_e

rr

VS

S_e

rr

VS_

err

HS

L_e

rr

HS

S_e

rr

HS_

err

SYNC_error_MSK

184(h)

MV

SL

_err

MV

SS

_err

MV

S_e

rr

MH

SL

_err

MH

SS

_err

MH

S_e

rr

300(h) CVCNT

CDCN(Capture Data Count for NTSC) 4000(h)

BDCN VDCN CDCP(Capture Data Count for PAL)

4004(h) BDCP VDCP

MDS

4014(h)

YC

MI

M

VINLC 404c(h)

VIN_LINE_NO_kep VHSLS (Video Input HSYNC Long/Short)

4054(h) VIN_HS_LONG VIN_HS_SHORT

VHSDC (Video HSYNC Down Count) 4058(h)

VIN_HDOWN_CNT

VVSLS (Video VSYNC long/short) 4060(h)

VIN_HS_LONG VIN_HS_SHORT VVSDC (Video VSYNC Down Count)

4064(h) VIN_VDOWN_CNT

7.4. Register




7.4.3.1. General

7.4.3.1.1. VCM (Video Capture Mode)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 12 11 10 4 3 2 1 0

Bit field name VIE VIS resv VICE resv CM reserve VI reserve resv reserve NRGB VS resv

R/W RW RW RX RW RX RW RX RW RX RW0 RX RW RW RX

Initial value 0 0 X 0 X 0 X 0 X 0 X 0 0 X

The mode of the video capture is set. This register is not initialized by software reset.

[bit1] VS (Video Select) NTSC or PAL is selected for the code error detection. (R.BT656 is only input. ) 0 NTSC 1 PAL [bit2] NRGB (Native RGB input on). Native RGB mode is set.

0 YUV 4:2:2 1 Native RGB

[bit20] VI (Vertical Interpolation) The interpolation processing in the vertical direction is set. 0 The interpolation processing is done to the vertical direction.

The image is expanded to twice in the vertical direction. 1 The interpolation processing is not done to the vertical direction. [bit25, bit24] CM (Capture Mode) The mode of the video capture is set. Please set 11 when you do capture. 00 Initial value 01 Booking 10 Booking 11 Capture use [bit28] VICE(Video Input Clock Enable) The capture clock is made effective. 0 Effective 1 Invalidity [bit30] VIS(Video Input Select) 0 RBT656 1 RGB

7.4. Register



[bit31] VIE (Video Input Enable) The video capture function is made effective. 0 The video capture is not done. 1 The video capture is done.

-Procedure of video capture clock stop- ① "0" is written in bit31(VIE) of the VCM register, and the video capture function is invalidated. ② "1" is written in bit28(VICE) of the VCM register, and the video capture clock is stopped.

-Procedure of video capture clock beginning- ① "0" is written in bit28(VICE) of the VCM register, and the video capture clock is made effective. ② "1" is written in bit31(VIE) of the VCM register, and the video capture function is made effective.

7.4. Register



7.4.3.1.2. CSC (Capture SCale)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name VSCI VSCF HSCI HSCF

R/W RW RW RW RW

Initial value 00001 00000000000 00001 00000000000

The expansion reduction rate of the video capture is set.

[bit10～bit0] HSCF (Vertical SCale Fraction) The fraction part of a horizontal expansion reduction rate is set. [bit15～bit11] HSCI (Horizontal Scale Integer) The integer part of a horizontal expansion reduction rate is set. [bit26～bit16] VSCF (Vertical SCale Fraction) The fraction part of the expansion reduction rate in the vertical direction is set. [bit31～bit27] VSCI (Vertical SCale Integer) The integer part of the expansion reduction rate in the vertical direction is set.

7.4. Register



7.4.3.1.3. CBM0 (video Capture Buffer Mode 0)


Bit number 31 30 29 28 27 … 24 23 22 … 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name OO

SB

UF

CR

GB

reserve CBW

BLE

N

C24

RG

BA

CS

W

reserve

CB

ST

R/W RW

RW

RW

RW

0

R0 RW RW

RW

RW

RW

R0 RW0 R0 RW

Initial value 0 0 0 0 0 X 0 0 0 0 0000 0000 0 0

[bit0] CBST(Capture Burst)

The burst length at the capture write is specified. Because the access efficiency improves, long one recommends setting it to one. 0 Standard burst write(4word)

1 Long burst write(8word) [bit12] CSW (Color Swap) Byte position of the color element is replaced when writing it in the YCbCr form. 0 Replacement none 1 It replaces it. [bit13] RGBA (RGBA format) When writing it in RGB form, the ARGB/RGBA form is selected. 0 ARGB form 1 RGBA form [bit14] C24 ( Color 24bit/pixel ) When RGB input capture is done, 24bit/pixel or 16bit/pixel is selected.

When converted RGB capture(CRGB=1) is set, whether this function is Native RGB capture (NRGB=1) it is effective.

0 16bit/pixel 1 24bit/pixel [bit15] BLEN (Blend Enable) When writing it in RGB form, the value of A field (blend bit) is specified. 0 A=0 1 A=1 [bit23～bit16] CBW (Capture Buffer memory Width) The width of the memory of the capture buffer (stride) is set in 64 bytes. [bit29] CRGB (Capture RGB write) The data of the YCbCr form at RGB = 5:5:5 It is specified to convert into

(16bit/pixel) and to write it. 0 YCbCr form(There is no conversion. ) 1 RGB form

7.4. Register



[bit30] SBUF (Single Buffer) It is specified to manage the capture buffer by the single buffer method. 0 The ordinary mode(ring buffer) 1 Single buffer mode [bit31] OO (Odd Only mode) It is specified that only the odd number field does capture. 0 The ordinary mode 1 Odd number only mode

Notes: This register is not initialized in soft reset.

7.4. Register



7.4.3.1.4. CBM1 (video Capture Buffer Mode 1)


Bit number 31 30 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve C565 reserve resv Hrev Vrev Rrot reserve Tbuf

R/W R0 RW R0 RW0 RW RW RW R0 RW

Initial value 0 0 0 0 0 0 0 0 0

[bit0] Tbuf (Triple buffer mode)

It is specified to use the capture buffer in a triple buffer. 0 A triple buffer is not used.

1 A triple buffer is used. [bit4] Rrot (Rectanguler rotate )

It is specified to rotate every 90 degrees. 0 It doesn't rotate.

1 It rotates. [bit5] Vrev (Vertical reverse mode)

Reversing the vertical direction is specified. 0 The vertical direction is not reversed.

1 The vertical direction is reversed. [bit6] Hrev (Horizontal reverse mode)

Reversing horizontal direction is specified. 0 Horizontal direction is not reversed.

1 Horizontal direction is reversed. [bit12] C565 (Color 565 )

It is specified to use the form at RGB = 5:6:5 when 16bit/pixel is used by RGB form. 0 It uses it excluding the form at RGB = 5:6:5.

1 The form at RGB = 5:6:5 is used.

7.4. Register



7.4.3.1.5. CBA0 (video Capture Buffer Address 0)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CBA0

R/W RW R0

Initial value Irregularity 0

The first address in the video capture buffer is specified. It corresponds to CBOA of old goods kind (MB86296).



Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CBA1

R/W RW R0


The final address of the video capture buffer is specified. It corresponds to CBLA of old goods kind (MB86296). CBA1 > Please set to become CBA0.



Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CBA2

R/W RW R0


When a triple buffer is used, the first address in the third buffer is specified.

7.4.3.1.8. CBOFS (video Capture Offset)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CBOFS

R/W R0 RW R0

Initial value 0 0 0

When the image is written in the capture buffer, writing beginning point of the frame is specified in the address of each byte.

7.4. Register



7.4.3.1.9. CISTR (Capture Image STaRt)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CIVSTR reserve CIHSTR

R/W RX RW RX RW

Initial value Irregularity Irregularity Irregularity Irregularity

The range of the image written in the video capture buffer is set. Coordinates (CIHSTR, CIVSTR) on the left within the written range are specified based on on the left of the image. It applies to the image coordinates after it reduces when reducing.

[bit11～bit0] CIHSTR (Capture Image Horizontal STaRt) X coordinates are specified. [bit27～bit16] CIVSTR (Capture Image Vertical STaRt) Y coordinates are specified.

7.4.3.1.10. CIEND (Capture Image END)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CIVEND reserve CIHEND

R/W RX RW RX RW

Initial value Irregularity Irregularity Irregularity Irregularity

The range of the image written in the video capture buffer is set. Lower right coordinates (CIHEND, CIVEND) within the written range are specified based on on the left of the image. It applies to the image coordinates after it reduces when reducing. It only writes it for the input image size when the number of lusterwares of input images is smaller than that of this setting range.

[bit11～bit0] CIHEND (Capture Image Horizontal END) X coordinates are specified. [bit27～bit16] CIVEND (Capture Image Vertical END) Y coordinates are specified.

7.4. Register



7.4.3.1.11. CVCNT (Capture Vertical Count)


Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CVCNT

R/W R0 R


Y coordinates of the lusterware that does capture are shown now. Only reading is possible.

7.4.3.1.12. CHP (Capture Horizontal Pixel)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CHP

R/W RX RW

Initial value X 0x168 (360)

The number of horizontal pixels of images output to the capture buffer is set. The value is specified by every two pixels. The maximum values are 840 pixels (set value 0x1A4).

7.4. Register



7.4.3.1.13. CLPF (Capture Low Pass Filter)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CVLPF reserve CHLPF reserve

R/W RX R/W RX R/W RX

Initial value 0 0 0 0 X

The coefficient of the low-pass filter is set. A vertical low-pass filter composes three taps and the horizontal low-pass filters of the FIR filter of five taps. The coefficient code in two bits is specified independently by brightness (Y) signal and difference (C) of the color signals. The low-pass filter becomes turning off (through) because of the setting of each coefficient code "00".

[bit17, bit16] CHLPF_C (Capture Horizontal LPF coefficient C) CHLPF_C K0 K1 K2 K3 K4 00 0 0 1 0 0 01 0 1/4 2/4 1/4 0 10 0 3/16 10/16 3/16 0 11 3/32 8/32 10/32 8/32 3/32

[bit19, bit18] CHLPF_Y(Capture Horizontal LPF coefficient Y) CHLPF_Y K0 K1 K2 K3 K4 00 0 0 1 0 0 01 0 1/4 2/4 1/4 0 10 0 3/16 10/16 3/16 0 11 3/32 8/32 10/32 8/32 3/32 [bit25, bit24] CVLPF_C (Capture Vertical LPF coefficient C) CVLPF_C K0 K1 K2 00 0 1 0 01 1/4 2/4 1/4 10 3/16 10/16 3/16 11 Set

prohibition

[bit27, bit26] CVLPF_Y (Capture Vertical LPF coefficient Y) CVLPF_Y K0 K1 K2 00 0 1 0 01 1/4 2/4 1/4 10 3/16 10/16 3/16 11 Set

prohibition

7.4. Register



7.4.3.1.14. CMSS (Capture Magnify Source Size)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CMSHP reserve CMSVL

R/W RX RW RX RW

Initial value X X X X

[bit9～bit0] CMSVL(Capture Magnify Source Vertical Line) The number of vertical lines of images before the expansion scaling is processed is

set. [bit25～bit16] CMSHP(Capture Magnify Source Horizontal Pixel) The number of horizontal pixels of images before the expansion scaling is processed

is set. The value is specified by every two pixels.

7.4.3.1.15. CMDS (Capture Magnify Display Size)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CMDHP reserve CMDVL

R/W RX RW RX RW


[bit9～bit0] CMDVL(Capture Magnify Display Vertical Line) The number of vertical lines of images after the expansion scaling is processed is set. [bit26～bit16] CMDHP(Capture Magnify Display Horizontal Pixel) The number of horizontal pixels of images after the expansion scaling is processed is

set. The value is specified by every two pixels.

7.4. Register



7.4.3.1.16. RGBHC (RGB input Hsync Cycle)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve RGBHC

R/W RX RW

Initial value X X

[bit13～bit0] RGBHC The horizontal cycle when the video is input is input. It is used for the HSYNC

determination detection when RGB/R.BT656 is input as the time that changed to the setting to sample VSYNC by the VIN_VLSAMP register. Set value -1 becomes the horizontal cycle.

7.4.3.1.17. RGBHEN (RGB input Horizontal Enable area)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve RGBHST reserve RGBHEN

R/W RX RW RX RW


It is a parameter to decide effective pixel horizontal data. [bit12～bit0] RGBHEN

Effective pixel data size is set by every two pixels.

[bit25～bit16] RGBHST The starting position of effective pixel data is set. Set value +4 becomes the starting positions.

7.4. Register



7.4.3.1.18. RGBVEN (RGB input Vertical Enable area)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name

rese

rve

RG

BV

ST

_T

rese

rve

RGBVST

rese

rve

RGBVEN

R/W RX RW RX RX RX RX

Initial value X 1 X X X X

It is a parameter to decide effective pixel data of the vertical direction. When RGB input is formatted, it uses it.

[bit12～bit0] RGBVEN(RGB input Vertical Enable area Size) The effective line size in the vertical direction is set. [bit24～bit16] RGBVST (RGB input Vertical Enable area Start position)

The starting position of the effective line data is set. Set value +1 becomes a starting position.

[bit29, bit28] RGBVST_T (RGB input Vertical Enable area Start position for Top field)

It is 2bit signed integer.

Effective line beginning position = RGBVST_O + It becomes RGBVST_BOTTOM. It drinks, only RGB input of progressive is supported in this Capchacontorra, and use it with RGBVST_O=0, please.

7.4. Register



7.4.3.1.19. VIN_VSAMP (Video INput Vsync SAMPling mode)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


VJI

TF

LT

reserve

FLD

RE

V

R/W RX RW RX RW

Initial value X 00 X 0

[bit0] FLDREV(FieLD REVerse )

The field identification is reversed. 0 It doesn't reverse.

1 It reverses. [bit9, bit8] VJITFLT(Vsync JITter FiLTer) The method of sampling the vertical synchronizing signal is set. Please select 00. 00 It samples it with HSYNC. 01 Booking 10 Booking 11 Booking

7.4.3.1.20. RGBS (RGB input Sync)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve RM

reserve HP

VP

R/W RX RW

RX RW

RW

Initial value X 1 X 0 0

The edge detection of Synchronous Idle is set. When RGB is input, it uses it.

[bit0] VP(VSYNC Polarity) 0 Taori of the VSIN signal is assumed to be VSYNC. 1 Ta of the VSIN signal is assumed to be VSYNC.

[bit1] HP(HSYNC Polarity)

0 Taori of the HSIN signal is assumed to be HSYNC. 1 Ta of the HSIN signal is assumed to be HSYNC.

[bit16] RM(RGB input Mode select) RGB666 direct input mode is set.

0 Reserved 1 RGB666 direct input mode

7.4. Register



7.4.3.2. Color space change RGB input data is converted into the YCbCr form by the following matrix type.

Y = a11*R + a12*G + a13*B + b1 Cb = a21*R + a22*G + a23*B + b2 aij 10bit signed real ( lower 8bit is fraction ) Cr = a31*R + a32*G + a33*B + b3 bi 8bit unsigned integer

Each coefficient is set by the following register. 2-4 conversion filter processing is done before the color space is changed, and color-difference signal Cb and Cr are formatted at YCbCr 4:2:2.

7.4.3.2.1. RGBCMY (RGB Color convert Matrix Y coefficient)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name a11

rese

rve

a12

rese

rve

a13

R/W RW RX

RW RX

RW

Initial value 0001000010 x 0010000000 x 0000011001

The coefficient of Y signal calculation of the RGB/YCbCr conversions is set.

[bit9～bit0] a13 10bit signed real (lower 8bit is fraction) [bit20～bit11] a12

10bit signed real (lower 8bit is fraction)

[bit31～bit22] a11 10bit signed real (lower 8bit is fraction)

7.4. Register



7.4.3.2.2. RGBCMCb (RGB Color convert Matrix Cb coefficient)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name a21

rese

rve

a22

rese

rve

a23

R/W RW RX

RW RX

RW

Initial value 1111011010 X 1110110110 X 0001110000

The coefficient of the Cb signal calculation of the RGB→YCbCr conversions is set.




7.4.3.2.3. RGBCMCr (RGB Color convert Matrix Cr coefficient)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name a31

rese

rve

a32 re

serv

e a33

R/W RW RX

RW RX

RW

Initial value 0001110000 X 1110100010 X 1111101110

The coefficient of the Cr signal calculation of the RGB→YCbCr conversions is set.




7.4. Register



7.4.3.2.4. RGBCMb (RGB Color convert Matrix b coefficient)

Register address 01FD_80CCH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name

rese

rve

b1

rese

rve

b2

rese

rve

b3

R/W RX

RW RX RW RX RW

Initial value X 000010000 X 010000000 X 010000000

The numerical value of the addition paragraph of the RGB/YCbCr conversion is set.

[bit8～bit0] b3 9bit unsigned integer [bit19～bit11] b2

9bit unsigned integer

[bit19～bit22] b1 9bit unsigned integer

7.4.3.2.5. MDS (MoDe Select)

Register address 01FD_C014H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve YCMI

M reserve

R/W RX RW RX

Initial value X 00 X

[bit5, bit4] YCMIM(YC Multiplex video Input Mode) Please use it by the default value.

00 Fixation 01 Reserved 10 Reserved

11 Set prohibition

7.4. Register



7.4.3.3. Synchronous error detection < RGB/ R.BT656 commonness >

7.4.3.3.1. VINLC (Video INput Line Count)

Register address 01FD_C04CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve VIN_LINE_NO_kep

R/W RX R

Initial value X 0

[bit12～bit0] VIN_LINE_NO_kep

King Blanc period is contained ..showing the number of lines of one frame (field).. ..(... Display value +1 is a number of lines.

7.4.3.3.2. VHSLS (Video Input HSYNC Long/Short)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reser

veVIN_HS_LONG

reser

veVIN_HS_SHORT

R/W RX RW RX RW


[bit13～bit0] VIN_HS_SHORT HSYNC watch setting at video input short intervals

HSS_err becomes one following the interval that the input HSIN signal set. Set value +1 becomes a cycle.

[bit29～bit16] VIN_HS_LONG HSYNC watch setting of video input of of long time

When the interval that the input VSIN signal set is exceeded, HSL_err becomes one. Set value +1 becomes a cycle.

7.4. Register



7.4.3.3.3. VHSDC (Video input HSync Down Count)


Bit number 31 30 29 28 27 26 25 24 23 22 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve VIN_HDOWN_CNT

R/W RW0 RX RW0 RX RW

Initial value 0 X 0 X 0

[bit7～bit0] VIN_HDOWN_CNT Setting at video input HSYNC determination watch cycle

When the cycle that the VSYNC determination set is exceeded, HS_err becomes one. Set value +1 becomes a cycle.

7.4.3.3.4. VVSLS (Video input VSync Long/Short)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve VIN_VS_LONG reserve VIN_VS_SHORT

R/W RX RW RX RW


[bit12～bit0] VIN_VS_SHORT VSYNC watch setting at video input short intervals

VSS_err becomes one following the interval that the input VSIN signal set. Set value +1 becomes a cycle.

[bit28～bit16] VIN_VS_LONG VSYNC watch setting of video input of of long time

When the interval that the input VSIN signal set is exceeded, VSL_err becomes one. Set value +1 becomes a cycle.

7.4. Register



7.4.3.3.5. VVSDC (Video Input VSync Down Count)


Bit number 31 30 29 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve VIN_VDOWN_CNT

R/W RW0 R RW

Initial value 0 0 0

[bit7～bit0] VIN_VDOWN_CNT Setting at video input VSYNC determination watch cycle

When the cycle that the VSYNC determination set is exceeded, VS_err becomes one. Set value +1 becomes a cycle.

7.4.3.3.6. CINT (Capture Interrupt)


Bit number 31 30 29 28 27 26 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve VS resv

R/W R0 RW0 R0

Initial value 0

It is an interruption status register of a video synchronous signal. It is cleared with "0" write.

[bit1] VS (VSYNC) 1: VSYNC generation 0:There is no generation.

7.4.3.3.7. CIMSK (Capture Interrupt Mask)


Bit number 31 30 29 28 27 26 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve VS resv

R/W RW0 RW RW0

Initial value 0

The mask does the interruption of a video synchronous signal.

[bit1] VS (VSYNC) 1: Mask none 0:Mask

7.4. Register



7.4.3.3.8. SYNC_err (SYNC error)


Bit number 31 30 29 26 25 24 23 21 18 17 16 15 14 11 10 9 8 7 3 2 1 0


VS

L_er

r

VS

S_e

rr

reserve

VS

_err

reserve

HS

L_er

r

HS

S_e

rr

reserve

HS

_err

R/W RX RW0 RW0 RX RW0 RX RW0 RW0 RX RW0

Initial value X 0 0 X 0 X 0 0 X 0

It is an error system interruption status register of a video synchronous signal. It is cleared with "0" write.

[bit0] HS_err (Hsync error) 1:Video input HSYNC determination error 0:There is no error. [bit8] HSS_err (HSync Short error) 1:HSYNC error at video input short intervals 0:There is no error. [bit9] HSL_err (Hsync Long error) 1:HSYNC error of video input of of long time 0:There is no error. [bit16] VS_err (Vsync down error) 1:Video input VSYNC determination error 0:There is no error. [bit24] VSS_err (Vsync Short error) 1:VSYNC error at video input short intervals 0:There is no error. [bit25] VSL_err (Vsync Long error) 1:VSYNC error of video input of of long time 0:There is no error.

7.4. Register



7.4.3.3.9. SYNC_err_MSK (SYNC error MaSK)


Bit number 31 30 29 26 25 24 23 21 18 17 16 15 14 11 10 9 8 7 3 2 1 0


MV

SL_

err

MV

SS

_err

reserve

MV

S_e

rr

reserve

MH

SL_

err

MH

SS

_err

reserve

MH

S_e

rr

R/W RX RW RW RX RW RX RW RW RX RW

Initial value X 0 0 X 0 X 0 0 X 0

The mask does the interruption of a video synchronous signal.

[bit0] MHS_err (Mask HSync error) 1:Mask none 0:Mask [bit8] MHSS_err (Mask HSync Short error) 1:Mask none 0:Mask [bit9] MHSL_err (Mask HSync Long error) 1:Mask none 0:Mask [bit16] MVS_err (Mask VSync error) 1:Mask none 0:Mask [bit24] MVSS_err (Mask VSync Short error) 1:Mask none 0:Mask [bit25] MVSL_err (Mask VSync Long error) 1:Mask none 0:Mask

7.4. Register



7.4.3.4. Code error detection >

7.4.3.4.1. CDCN (Capture Data Count for NTSC)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve BDCN reserve VDCN

R/W RX RW RX RW

Initial value X 0x10f(271) X 0x5A3(1443)

The number of data of input video streams when the NTSC format is used is set. (It is effective only to format R.BT656. )

[bit12～bit0] VDCN (Valid Data Count for NTSC) The number of data during the validity term when the NTSC format is used is set. Set

value +1 is a number of data. [bit28～bit16] BDCN (Blanking Data Count for NTSC) The number of data in king Blanc period when the NTSC format is used is set. Set

value +1 is a number of data.

The range of VDCN and BDCN is shown in following figure.

SAVEAV Multip lexed video data

Cb,Y,Cr,Y,Cb,Y,Cr,Y,….. VI[7:0]

4T

H-BLANK 276T ［525］

ACTIVE-VIDEO1440T [525]

EAV

4T

Blanking data

80,10,80,10,80,.

4T

288T ［625］

272T(BDCN:271T) 284T(BDCP:283T)

1444T(VDCN:1443T) 1444T(VDCP:1443T)

1440T [625]

SAV: start of active video timing reference code EAV: end of active video timing reference code T: clock period 37 ns nom.

7.4. Register



7.4.3.4.2. CDCP (Capture Data Count for PAL)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve BDCP reserve VDCP

R/W RX RW RX RW

Initial value X 0x11B(283) X 0x5A3(1443)

The number of data of input video streams when PAL format is used is set. (It is effective only to format R.BT656. )

[bit12～bit0] VDCP (Valid Data Count for PAL) The number of data during the validity term when PAL format is used is set. Set value

+1 is a number of data. [bit28～bit16] BDCP (Blanking Data Count for PAL) The number of data in king Blanc period when PAL format is used is set. Set value +1

is a number of data.

7.4.3.4.3. CDCNS (Capture Data Count for NTSC Short)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve BDCN_S reserve VDCN_S

R/W RX RW RX RW

Initial value X 0x10f(271) X 0x5A3(1443)

The number of data of short input video streams at intervals when the NTSC format is used is set. (It is effective only to format R.BT656. )

[bit12～bit0] VDCN_S (Valid Data Count for NTSC Short) The number of data during the validity term when the NTSC format is used is set. Set

value +1 is a number of data. [bit28～bit16] BDCN_S (Blanking Data Count for NTSC Short) The number of data in king Blanc period when the NTSC format is used is set. Set

value +1 is a number of data.

7.4. Register



7.4.3.4.4. CDCPS (Capture Data Count for PAL Short)

Register address 01FD_C01CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve BDCP_S reserve VDCP_S

R/W RX RW RX RW

Initial value X 0x11B(283) X 0x5A3(1443)

The number of data of short input video streams at intervals when PAL format is used is set. (It is effective only to format R.BT656. )

[bit12～bit0] VDCP_S (Valid Data Count for PAL Short) The number of data during the validity term when PAL format is used is set. Set value

+1 is a number of data. [bit28～bit16] BDCP_S (Blanking Data Count for PAL Short) The number of data for king Blanc period when PAL format is used is set. Set value

+1 is a number of data.

7.4.3.4.5. VCS (Video Capture Status)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve CE0

R/W RX RW0

Initial value X 0000000

It is a status register that shows that there was an error in the code of input RBT.656. Please set NTSC/PAL to VS-bit of the VCM register for there is an error in the code to detect it. When NTSC is set, and PAL of capture data count register (CDCN, CDCN_S) is set, bit6-bit0 of video capture status register VCS is as follows when it doesn't agree with the stream data and an undefined code is detected in Fourth word of SAV/EAV referring to the number of data of capture data count registers (CDCP, CDCP_S). ..(.. about the code definition7.5.6Refer to chapter R.BT656YUV422 input format. )

[bit0] CE0 1 : RBT.656 undefinition error( Code Bit7 ) 0 :There is no error. [bit1] CE0 1 : RBT.656 undefinition error( Code Bit7-4 ) 0 :There is no error. [bit2] CE0 1 : RBT.656 undefinition error( Code Bit7-0 ) 0 :There is no error. [bit3] CE0 1 : H error in the code of RBT.656 of of long

time(SAV) 0 :There is no error.

[bit4] CE0 1 : H error in the code of RBT.656 of of long

time(EAV) 0 :There is no error.

[bit5] CE0 1 : H error in the code at RBT.656 short

intervals(SAV) 0 :There is no error.

[bit6] CE0 1 : H error in the code at RBT.656 short

intervals(EAV) 0 :There is no error.

7.4. Register



7.4.3.4.6. VCS_MSK (Video Capture Status MaSK)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name reserve MSK_CE0

R/W RX RW

Initial value X 0000000

It is specified whether to do each interrupt event masking. When the interruption event without the mask is generated, the interruption output is generated in host CPU. Even if the event that the mask is done is generated, the interruption output to host CPU is not generated.

[bit0] MSK_CE0 RBT.656 undefinition error mask 0: Mask 1: Mask none

[bit1] MSK_CE0 RBT.656 undefinition error ( Code bit7-bit4 ) mask 0: Mask 1: Mask none [bit2] MSK_CE0 RBT.656 undefinition error ( Code bit7-bit0 ) mask 0: Mask 1: Mask none [bit3] MSK_CE0 H error in the code (SAV) mask of RBT.656 of of long time 0: Mask 1: Mask none [bit4] MSK_CE0 H error in the code (EAV) mask of RBT.656 of of long time 0: Mask 1: Mask none [bit5] MSK_CE0 H error in the code (SAV) mask at RBT.656 short intervals 0: Mask 1: Mask none [bit6] MSK_CE0 H error in the code (EAV) mask at RBT.656 short intervals 0: Mask 1: Mask none





7.5.1. Capture controller function

7.5.1.1. Input data format

・ Details are conforming the ITU RBT-656 format ("エラー! 参照元が見つかりません。Refer to the external video signal input". )The signal method corresponds to NTSC and PAL.

・ It corresponds to digital RGB666 an input.

7.5.1.2. Taking of video signal The capture controller becomes effective when VIE of video capture mode register (VCM) is one, and takes the video stream data from the video data input pin synchronizing with the CCLK clock.




7.5.1.3. Non-interlace conversion(progressive conversion) The non-interlace of the video image that does capture can be displayed. The non-interlace conversion can select two kinds (the BOB mode and the WEAVE mode).

7.5.1.3.1. BOB mode

The lusterware of the even number field is generated with the average interpolation in the odd number field, it adds, and it makes it to one frame. Moreover, the lusterware of the odd number field is generated with the average interpolation in the even number field, it adds, and it makes it to one frame. A vertical interpolation is effectively done by the VI bit of the VCM(Video CaptureMode) register to select the BOB mode, and the L1IM bit of the L1M(L1-layer Mode) register is set to "0".

7.5.1.3.2. WEAVE mode

The even number field is merged with the odd number field on the video capture buffer and it makes it to one frame. The gap of the lusterware might be seen in the scene with movement though a vertical resolution rises compared with BOB.

Stop

Moving

A vertical interpolation is invalidated by the VI bit of the VCM(Video CaptureMode) register to select the WEAVE mode, and the L1IM bit of the L1M(L1-layer Mode) register is set to "1".

7.5.1.3.3. Progressive mode

The case where non-interlace is not converted is called a progressive mode. The case used with VCM=0 and L1IM=0 becomes a progressive mode.




7.5.2. Video buffer

7.5.2.1. Data form

It basically memorizes it in the capture buffer with 16bit/pixel. Two color elements (Cb, Cr) are half the horizontal direction resolutions, and are consequentially expressed by 16bit/pixel for the brightness data (Y element). It converts into RGB form in the L1 layer and it is displayed.

format 31 30 … 25 24 23 22 … 17 16 15 14 … 9 8 7 6 … 1 0

YCbCr 16bit/pixel Y Cr Y Cb

It is also possible to memorize it by RGB form. The following form exists.

format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ARGB 16bit/pixel A R G B

RGBA 16bit/pixel R G B A

RGB565 16bit/pixel R G B

format 31 30 … 25 24 23 22 … 17 16 15 14 … 9 8 7 6 … 1 0

ARGB 24bit/pixel A R G B

RGBA 24bit/pixel R G B A




The relation to the data form control bit in the register is as follows.

NRGB CRGB C24 RGBA C565 Capture data form Expansion display

0 0 0 0 0 YCbCr 16bit/pixel -

0 1 0 0 0 ARGB 16bit/pixel (YCbCr → RGB conversion)

0 1 0 0 1 RGB565 16bit/pixel (YCbCr → RGB conversion)

0 1 0 1 0 RGBA 16bit/pixel (YCbCr → RGB conversion)

0 1 1 0 0 ARGB 24bit/pixel (YCbCr → RGB conversion)

0 1 1 1 0 RGBA 24bit/pixel (YCbCr → RGB conversion)

1 0 0 0 0 ARGB 16bit/pixel -

1 0 0 0 1 RGB565 16bit/pixel -

1 0 0 1 0 RGBA 16bit/pixel -

1 0 1 0 0 ARGB 24bit/pixel -

1 0 1 1 0 RGBA 24bit/pixel -

As for the capture expansion display, only the form of * is possible by a right column. Data without the meaning as image data in a setting other than the above is written. The NRGB bit is bit2 of the VCM register. Other bit values exist in the CBM register.

When the selection of the data form of the capture image is shown in the figure, it becomes the following.

RGB to

YCbCr

VIS-bit

0

1 YCbCr

to RGB

CRGB-bit

0

1

NRGB-bit

RI/GI/BI input

VI input

RGB

24 to16

C24-bit

1

0

0

1

ARGB

to RGBA

RGBA-bit

YCbCr-16bpp

ARGB-16bpp

ARGB-24bpp

RGBA-16bpp

RGBA-24bpp

0

1

It can select whether for ARGB or the RGBA form to adjust the blend bit to one at pixel write or to make it to 0 by the BLEN bit of the CBM register.

BLEN=0 blend bit =0(It is LSB in ARGB in MSB and RGBA. ) BLEN=1 blend bit =1(It is LSB in ARGB in MSB and RGBA. )




7.5.2.2. Frame management Three management modes exist. 1) Single buffer mode The display read and the capture write are executed without synchronization by using the area for one frame. The (n+1) frame exists together to n frame at the top and bottom and it is displayed. When movement in the horizontal direction of the content of the screen is large, the boundary of the frame might look momentary.

Stop

Moving

The area of use can be small though the display quality in the phase with movement is not good. The buffer space secures one frame, and sets the first address to the CBA0/1 register. Please set the same value as two registers. CBA0=CBA1

2) Ring buffer mode The area of 2.2-2.5 frame corresponding is secured, and the ring buffer is composed of each lusterware. To display the frame that completes the capture operation for one frame, the frame boundary is never seen. When the speed of the frame of capture is more high-speed than the speed of the frame of the display, the skip of the frame is generated. Moreover, when the speed of capture of the frame is slower oppositely than that of the display, the display of the same frame is done two times. The area that corresponds to the lusterware of 2.2-2.5 frame corresponding is secured. CBA0

CBA1

(2.2~2.5)*(ras/frame)

The first address is set to CBA0. The upper bound of the area is set to CBA1. When the area of n lusterware is secured, the value of the next expression is set. CBA1=CBA0+64(n-2) × CBW The area secured as a capture buffer becomes it within the following range.




CBA0 ≦ capture buffer < CBA0+64n × CBW Please note that it is not an upper bound address in the capture buffer here about CBA1. When the reduced display is done, the buffer space is secured by the size of the frame after it reduces. 3)Triple buffer mode The area of three frame corresponding is secured, and three areas are used going it. The following description is used 90 times by capture with a rotation. It becomes it as well as As for the absorption of a relative difference of the speed of the frame of capture and the display, it is 2). The first address in each area is specified for the CBA0/1/2 each register.

CBA0 CBA1 CBA2

The following description is used 90 times by capture including the rotation. 1)-3) is selected by the following bit.

CBM0/Sbuf-bit CBM1/Tbuf-bit Single buffer 1 0 Ring buffer 0 0 Triple buffer 1 1

7.5.2.3. Window display The video image that capture is done uses and displays the L1 layer. The whole of the image that capture is done or a part is whole of the screen or can be displayed as a window. When capture is displayed, the L1 layer is set to the capture synchronous mode (L1CS=1). In this mode, the L1 layer display displays the latest frame in the video capture buffer. The display address used in the ordinary mode is disregarded. The stride of the L1 layer should be corresponding to the stride in the video capture buffer. The image diagonally distorted is displayed when not matching. The display size of the L1 layer is matched to the image size after the video capture is reduced. When the display size of the L1 layer is set more greatly than the capture image size, invalid data will be displayed. The L1 layer can select RGB display and the YCbCr display, and when the video capture is done, the YcbCr form is selected (L1YC=1).

7.5.2.4. Interlace display The image taken into the video capture buffer in the WEAVE mode can be displayed by interlace. The setting makes the WEAVE mode effective and selects interlace & video display by the display scanning. However, the flicker goes out in the scene with movement when the display scanning is an asynchronous system. To prevent this, the OO(Odd Only) bit of the CBM0(Capture Buffer Mode 0) register is set to "1".




7.5.3. Capture image rotation write

7.5.3.1. Outline The right and left of an upper and lower rotation can rotate by 90 degrees when writing it in the capture buffer. This image conversion can convert seven kinds of excluding the identical transformation.

There is not

reversing. Right and left reversing

Upper and lower reversing

Right and left, upper and lower reversing

Axis of coordinate Changing insertion

none

Axis of coordinate Insertion changing

However, the following limitation exists. 1) It uses it in a single buffer or a triple buffer. It is not possible to use it in the ring buffer. 2) It uses it with BOB or progressive. It is not possible to use it with WEAVE. 3) X axis or Y axis alone cannot be used in the mode of the expansion. 4) The capture operation is stopped and the parameter is changed. There is a possibility of overwriting the data of another data area on VRAM when the parameter change is done while operating. The rotation is specified with RRot-bit described later, Hrev-bit, and Vrev-bit. When those bits are all 0, quite the same operation as past GDC (MB86296) is done.

7.5.3.2. Various reversing modes

It specifies it by the following parameter.

Y=x symmetry reversing(xy coordinates axis insertion changing) It selects it by CBM1 register RRot-bit.

The horizontal reversing It selects it by CBM1 register Hrev-bit.

Vertical reversing It selects it by CBM1 register Vrev-bit.







7.5.3.3. Writing beginning point offset It is necessary to specify the beginning point offset to write the image after the rotation is processed at an appropriate position of the capture buffer. It is input on the left to the input image of capture as a beginning point in order of raster scan. It is writing beginning point offset to specify where in the writing destination the input beginning point corresponds. It becomes a starting point on the left. The starting point is a starting point of each frame in a single buffer or a triple buffer here at the writing destination. On VRAM, it becomes a point specified by the CBA0/1/2 register. It sets it to the CBOFS(capture buffer offset) register in a linear address based on the respect. CBOFS corresponds to the address of each byte. It makes it to offset 0 for the identical transformation.

capture source

w

h

(CIHSTR,CIVSTR)

(CIHEND,CIVEND)

CBAn

VRAM

stride

display screen

(L1WX,L1WY)

wr start

offset

L1W

H+

1

L1WW

The source image frame (CIHSTR, CIVSTR)- (CIHEND, CIVEND)It becomes a frame after clip is done. That is, height h and width w of the area become the following relations. w = CIHEND - CIHSTR+1h = CIVEND - CIVSTR+1 Writing beginning point offset according to each reversing mode is as follows.

source origin, wr start

stride

h

w w

RectRot=0, Hrev=0, Vrev=0 CBOFS=0 The register setting value is actually disregarded and it treats compulsorily as 0.

source

w

origin wr start

stridew

h h

RectRot=0, Hrev=1, Vrev=0 CBOFS= (w-1)*bpp/8 (bpp=16,32)

source origin

wr start

h

stride

h

w w

RectRot=0, Hrev=0, Vrev=1 CBOFS=(h-1)*stride

(stride=64*CBW)

source origin

wr

star

t

strideww

hh

RectRot=0, Hrev=1, Vrev=1 CBOFS= (w-1)*bpp/8+ (h-1)*stride (bpp=16,32; stride=64*CBW)




source origin, wr start

w

h

hstride

w

RectRot=1, Hrev=0, Vrev=0 CBOFS=0

source origin wr start

hstridew

h w

RectRot=1, Hrev=1, Vrev=0 CBOFS = (h-1)*bpp/8 (bpp=16,32)

source origin

stride

wr start

w

w

h

h

RectRot=1, Hrev=0, Vrev=1 CBOFS= (w-1)*stride (stride=64*CBW)

source origin

wr

star

t

hstridew

wh

RectRot=1, Hrev=1, Vrev=1 CBOFS= (h-1)*bpp/8+(w-1)*stride

(bpp=16,32; stride=64*CBW)

7.5.3.4. Display position fine-tuning The following restriction is in a set value of writing beginning point offset CBOFS. If it is CBOFS subordinate position 3bit=100 16bit/pixel if it is 32bit/pixel for RectRot=0 and Hrev=1, it is CBOFS subordinate position 3bit=110. There is a possibility that a surplus pixel is displayed at the left of the L1 display window when this restriction exists. To evade it, the CAOFS field of the L1EM register is set on the display side. To disregard a surplus pixel for left side n-pixel, CAOFS=n*bpp/8 (bpp=16, 32) is set.




7.5.4. Scaling

7.5.4.1. Reduction function of video When CM of video capture mode register (VCM) is 11, the capture controller reduces the video screen. The unit of one line and horizontal direction are every two pixels in the vertical direction, and the scale of the reduction can be independently set respectively. A set value of the scale defines by the value of input/output, and is a fixed decimal of 16bit shown in integer part 5bit and fraction part 11bit. An effective set value becomes 0x0800-0xFFFF. Please set in bit31-bit16 of capture scale register (CSC) and set horizontal direction to the vertical direction and bit15-bit0. An initial value of this register is 0x08000800 (one time). The example of the set calculation type is shown as follows.

Reduction of vertical direction 576 → 490lines 576/490=1.1761.176×2048=2408 → 0x0968 Reduction of horizontal direction 720 → 648pixels 720/648=1.1111.111×2048=2275 → 0x08E3

As a result, the setting to CSC becomes 0x096808E3. Capture horizontal pixel register (CHP) is the one to limit the number of pixels for the scaling processing, and no set value of scaling. It is the one to do the clamping processing to the video streaming data that exceeds the value set with CHP. This register can be used like the first stage value usually.




7.5.4.2. Expansion function of video The capture controller can independently expand the video screen horizontal direction and each vertical direction. When full-screen is displayed, the function of can use the video stream input that doesn't come up to the display resolution to display. Moreover, the usage said then is ..part of the video stream input.. expanding (zoom) possible. The initialization procedure is shown as follows.

・ Magnify flag of the L1-layer mode register of Display Controller is set. ・ The source image size before it expands is set to CMSHP and CMSVL. ・ The expansion further output image size is set to CMDHP and CMDVL.

As a setting example Input image size: 480 × 360 pixel display image size: 640 × 480 pixels It is time when set drinking in each register and it shows.

HSCALE = (480/640) × 2048 = 0x0600 VSCALE = (360/480) × 2048 = 0x0600 CMSHP = 0x00f0 CMSVL = 0x0168 CMDHP = 0x0140 CMDVL = 0x01e0 L1WW = 0x0280 L1WH = 0x01df

(notes 1) Please place the setting that becomes period (vertical synchronization of the display)2V twice (CSC=0x08000800) such as the above between those when switching from the expansion to the reduction by the display size change. This is a restriction because the interpolation filter for the reduction and the expansion is sharing. There is no restriction when changing from the reduction into the expansion. (notes 2) The scale rate is continuously operated and the image falls into disorder somewhat when the reduction scale and the expansion scale are displayed. This is due to the method of this Capchacontorra function. (notes 3) When an external synchronous function is used, the expansion display cannot be used. There is a possibility that the display becomes unstable because the internal control circuit doesn't correspond.




7.5.4.3. Flow of image data processing As for the capture image displayed in L1 Rayawindou, the image processing is done by the following flow. Figure7.5-1Flow of image data processing

Non-interlace interpolation processing

The interlace screen is vertically interpolated by using data in the same field when VI of video capture mode register (VCM) is "0". Two screens are multiplied in the vertical direction. When VI is "1", it doesn't vertically interpolate it.

Scaler

Video- Input

(656/RGB)

Video Output

GDC Macro

horizontal

LPF horizontal

down scaling

vertical

down scaling

vertical

LPF

vertical

up scaling horizontal

up scaling

Display Controller

Non-interlace

interpolation

On / Off

Ca

ptu

re b

uff

er

con

tro

ller

VR

AM

Color conversion

matrix

YUV / RGB RGB(Native RGB)

RGB

656(YUV422)

YUV422




7.5.4.3.1. The horizontal low-pass filter processing

The low-pass filter can be horizontally put as a preprocessing when the image is horizontally reduced. Horizontal low-pass filter (LPF) can be turned on and off regardless of the expansion or the reduction of the image. The horizontal low-pass filter is composed of the FIR filter of five taps. The coefficient is specified by the following register.

CHLPF_Y The horizontal LPF brightness element coefficient code CHLPF_C The horizontal LPF color difference element coefficient code

The coefficient is specified by the coefficient code in two bits independently by brightness (Y) signal and difference (C) of the color signals. The coefficient is a symmetric coefficient.

CHLPF_x K0 K1 K2 K3 K4 00 0 0 1 0 0

01 0 1/4 2/4 1/4 0

10 0 3/16 10/16 3/16 0

11 3/32 8/32 10/32 10/32 3/32

Horizontal LPF becomes turning off (through) because of the setting of the coefficient code "00".

(notes) In Native RGB mode (NRGB=1), only the coefficient code of CHLPF_Y becomes effective.

7.5.4.3.2. Reduction and expansion processing of horizontal direction

Please set it to bit15-bit0 of capture scale register (CSC) to do the reduction and the expansion processing of horizontal direction. Horizontal direction is reduced before VRAM ..writing... After reading from VRAM, horizontal direction is expanded. The interpolation filter processing of brightness (Y) signal does the interpolation filter processing of cubic interpolation (Cubic Interpolation ) method and difference (C) of the color signals by Bairinia interpolation (Bilinear Interpolation) method.




7.5.4.3.3. Vertical low-pass filter processing

The low-pass filter can be put on the vertical direction as a preprocessing when the image is reduced to the vertical direction. Vertical low-pass filter (LPF) can be set to turning on regardless of the expansion or the reduction of the vertical direction. A vertical low-pass filter is composed of the FIR filter of three taps. The coefficient is specified by the following register.

CVLPF_Y Vertical LPF brightness element coefficient code

CVLPF_C Vertical LPF color difference element coefficient code

It specifies it by the coefficient code in two bits independently by brightness (Y) signal and difference (C) of the color signals. The coefficient is a symmetric coefficient.

CVLPF_x K0 K1 K2

00 0 1 0

01 1/4 2/4 1/4

10 3/16 10/16 3/16

11 Set

prohibition

Vertical LPF becomes turning off (through) because of the setting of the coefficient code "00".

(notes) In Native RGB mode (NRGB=1), only the coefficient code of CVLPF_Y becomes effective.

7.5.4.3.4. Reduction and expansion processing in vertical direction

Please set it to bit31-bit16 of capture scale register (CSC) to do the reduction and the expansion processing in the vertical direction. The vertical direction is reduced before VRAM ..writing... After reading from VRAM, the vertical direction is expanded. The interpolation filter processing of brightness (Y) signal does the interpolation filter processing of cubic interpolation (Cubic Interpolation) method and difference (C) of the color signals by Bairinia interpolation (Bilinear Interpolation) method.




7.5.5. Interrupt

7.5.5.1. Outline The interruption event generated from the capture controller is as follows.

It is generated by the error of the error detection video input. It is generated synchronizing with the vertical synchronizing signal of capture VSYNC video input.

7.5.5.2. Interruption status The capture controller's interruption is transmitted to MCNT.

7.5.5.3. Error detection In the input video data, when expected control code and Synchronous Idle cannot be detected, it becomes an error. The status register among the corresponding capture controllers becomes SYNC_err register.




7.5.5.4. Capture VSYNC interruption It can know the VSYNC timing of capture because of this interruption. The status register among the corresponding capture controllers becomes CINT register. The following usage is assumed. 1) Detection 2 of effective image input) Frame management by host CPU When host CPU manages the frame, it does in the single buffer mode. The CBA0 register and the CBA1 register to specify the first address in the buffer according to timing where the VSYNC interruption is generated can be rewritten. The frame immediately after generation of the interruption is written in the address before it updates it. A new address becomes effective from the next frame. That is, the capture image of an old address can be used as a still picture. The state written in area 0 is shown. The CBA0 register maintains the first address in area 0.

CBA0

area0

WriteAdr

area1

write

The writing address moves to the first address in area 0 synchronizing with VSYNC. The VSYNC interruption is generated.

CBA0

area0

WriteAdr

area1

write

VSYNC

After it interrupts of VSYNC, CBA0 is changed to the head of area 1 by host CPU. Even the following VSYNC doesn't influence writing.

CBA0

area0

WriteAdr

area1

write

Host CPU

Writing in area 1 is begun later, and the image of area 0 is preserved about the following VSYNC.

CBA0

area0

WriteAdr

area1

remain write

next VSYNC

Notes:Please set it to CBA0=CBA1 when a single buffer operates.




7.5.6. External video signal input

7.5.6.1. R.BT656 YUV422 input format

The ITU R.BT-656 format is widely used for digital transmission of NTSC and PAL. The format corresponds to YUV422. Capture to convert the input interlace video signal into non-interlace by a linear interpolation is possible in Capchaconrorra. The capture controller becomes effective capture when VIE of video capture mode register (VCM) is "1", and takes the video stream data from the terminal VI of 8bit synchronizing with the CCLK clock. Because the video stream that can be processed is limited to the digital video stream in accordance with ITU-RBT656, it becomes a format at Y to which Taimingrefanrenscord is added, Cb, and Cr 4:2:2. Please set NTSC/PAL to VS of VCM for there is an error in the code to detect it though it corresponds automatically any of NTSC/PAL for the stream taking by the timing Reference code. When NTSC is set, and PAL of capture data count register (CDCN) is set, bit4-bit0 of video capture status register (VCS) reaches the values other than 00000 when not agreeing with the stream data referring to the number of data of capture data count registers (CDCP).

7.5.6.1.1. R.BT656 input format

Synchronous code and image data ( Cb, Y, Cr, Y ) are input as data of eight multiple bits synchronizing with 27MHz clock, and an effective pixel is transmitted while placed between a synchronous code named SAV and EAV.

SAVEAV Multiplex Video data

Cb,Y,Cr,Y,Cb,Y,Cr,Y,….. 8 bit

VI[7:0]

4T

H-BLANK 276T ［288T］

ACTIVE-VIDEO 1440T [1440T]

EAV

4T

Blanking data

80,10,80,10,80,.

ACTIVE-VIDEO -LINE 1716T ［1728T］

SAV: Beginning code EAV of active video data (four bytes): End code T of active video data (four bytes): 27MHz: 625/50 factions(PAL)

BLANKING PERIOD

TIMING REF-CODE

720 PIXELS YUV4:2:2 DATA TIMING

REF-CODE BLANKINGPERIOD

… 80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 … Cr718 Y719 FF 00 00 EAV 80 10 …




7.5.6.1.2. Format of R.BT656 synchronous code (four bytes)

SYNC code(fixation) EAV/SAV Word

Bit

The first

The secon

d

The third

The fourth

7 1 0 0 1 (fixation) 6 1 0 0 F 0: The first field 1: Second field 5 1 0 0 V 0:ACTIVE-VIDEO1:VBI 4 1 0 0 H 0:SAV1:EAV 3 1 0 0 P3 protection bit 2 1 0 0 P2 protection bit 1 1 0 0 P1 protection bit 0 1 0 0 P0 protection bit

7.5.6.1.3. SAV/EAV timing standard signal

Bit 7 6 5 4 3 2 1 0 Function Fixation F V H P3 P2 P1 P0

80 1 0 0 0 0 0 0 0 9D 1 0 0 1 1 1 0 1 AB 1 0 1 0 1 0 1 1 B6 1 0 1 1 0 1 1 0 C7 1 1 0 0 0 1 1 1 DA 1 1 0 1 1 0 1 0 EC 1 1 1 0 1 1 0 0 F1 1 1 1 1 0 0 0 1

80: SAV code at the first field effective pixel period (Active-video) 9D: EAV code at the first field effective pixel period (Active-video) AB: SAV code at the first field vertical fly back time B6: EAV code at the first field vertical fly back time C7: SAV code at the second field effective pixel period (Active-video) DA: EAV code at the second field effective pixel period (Active-video) EC: SAV code at the second field vertical fly back time F1: EAV code at the second field vertical fly back time




7.5.6.1.4. R.BT656 synchronous code (EAV) timing(525/60 factions)

522 523 524 525 1 2 3 4 5 6 7 8 9 line-no, 1st field Active video equalizing pluse vertical sync equalizing pluse

EAV DA DA DA DA F1 F1 F1 B6 B6 B6 B6 B6 B6

F 1 1 1 1 1 1 1 0 0 0 0 0 0

V 0 0 0 0 1 1 1 1 1 1 1 1 1

260 261 262 263 264 265 266 267 268 269 270 271 272line-no, 2nd field Active video equalizing pluse vertical sync equalizing pluse

EAV 9D 9D 9D 9D B6 B6 F1 F1 F1 F1 F1 F1 F1

F 1 1 1 1 1 1 1 0 0 0 0 0 0

V 0 0 0 0 1 1 1 1 1 1 1 1 1

10 11 12 13 14 15 16 17 18 19 20 21 22 line-no,

1st field VBI-lines 1st field Act-video

EAV B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 9D 9D 9D

F 0 0 0 0 0 0 0 0 0 0 0 0 0

V 1 1 1 1 1 1 1 1 1 1 0 0 0

273 274 275 276 277 278 279 280 281 282 283 284 285line-no, 2nd field VBI-lines 2nd field Act-video

EAV F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 DA DA DA

F 1 1 1 1 1 1 1 1 1 1 1 1 1

V 1 1 1 1 1 1 1 1 1 1 0 0 0




7.5.6.1.5. R.BT656 synchronous code (EAV) timing(625/50 factions)

620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 line-no, 1st field Active video equalizing pluse vertical sync equalizing pluse VBI-lines 1st field

EAV DA DA DA DA F1 F1 B6 B6 B6 B6 B6 B6 B6 B6 B6

F 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0

V 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

323 324 325 326 327 328 329 330 331 332 333 334 335 336 337line-no, 2nd field Active video equalizing pluse vertical sync equalizing pluse VBI-lines 2nd field

EAV F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 DA DA

F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

V 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24line-no,

1st field VBI-lines 1st field Act-video

EAV B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 9D 9D

F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

V 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0

323 324 325 326 327 328 329 330 331 332 333 334 335 336 337line-no, 2nd field VBI-lines 2nd field Active-video

EAV F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 F1 DA DA

F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

V 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0




7.5.6.2. R.BT656 frame format

7.5.6.2.1. 525/60 R.BT656 format input factions

276CK

D1_HBLK D1_FP

D1_VSYNC

D1_FEILD

1440CK

B6 AB

720 pixel

TOP field

BOTTOM field

16 line 18ﾗ line

244 line

525ﾗｲﾝ

243 line

3 line

17 line

F1 EC

F1 EC

B6 AB2 line

240 line

240 line

D1_HSYNC

D1_F

D1_V

19 line

9D 80

DA C7

Note 1) CCLK_RGB=27MHz Note 2) Written SAV and EAV are "FF 00 00 XX actually. " by four bytes Note 3) D1_FP, D1_F, D1_FEILD, D1_V, D1_VSYNC, D1_HSYNC, and D1HBLK are images of the internal

signal generated from SAV and EAV.




7.5.6.2.2. 625/50 R.BT656 format input factions

276CK

D1_HBLK D1_FP

D1_VSYNC

D1_FEILD

1440CK

B6 AB

720 pixel

TOP field

BOTTOM field

22 line 22 line

288 line

625 line

288 line

2 line

23 line

F1 EC

F1 EC

B6 AB2 line

288 line

288 line

D1_HSYNC

D1_F

D1_V

23 line

9D 80

DA C7

Note 1) CCLK_RGB=27MHz Note 2) Written SAV and EAV are "FF 00 00 XX actually. " by four bytes Note 3) D1_FP, D1_F, D1_FEILD, D1_V, D1_VSYNC, D1_HSYNC, and D1HBLK are internal signal images

generated from SAV and EAV.




7.5.6.3. RGB input format

Two data processing modes are provided as RGB input video capture function. On the other hand, it is a processing mode as NativeRGB, and a mode that converts RGB into YUV422 on the other hand with an internal RGB pre-processor and processes it. It corresponds to the progressive video input in RGB input function. It doesn't correspond to the interlace progressive conversion function. It corresponds to the input of 66Mpixel/sec or less. RGB component data is six bits.

< notes > Please set NRGB=1 to change to the Native RGB mode.

7.5.6.3.1. RGB input signal

Name I/O Function CCLK_RGB Input Clock for RGB input CAP0R0-5 Input Red component value CAP0G0-5 Input Green component value CAP0BI0-5 Input Blue component value VSIN Input Vertical sync for RGB capture HSIN Input Horizontal sync for RGB capture

< notes > YUV422 input (R.BT656) and RGB input are selected by the VIS bit of the VCM(video capture mode) register.




7.5.6.3.2. Capture range setting

The following register is set in RGB input function. RGB input mode setting

・ RGB666 input flag(VIS) of the VCM register is set. ・ The NRGB bit of the VCM register is set to "1" in the Native RGB mode.

Setting at HSYNC cycle The HSYNC cycle is set to RGBHC. Horizontal, effective pixel range setting The start position and effective pixel size of an effective pixel are set to RGBHST and RGBHEN. Vertical, effective pixel range setting The start position and effective pixel size of an effective pixel are set to RGBVST and RGBVEN. The range of the video capture is defined as follows.

RGBHC RGB input Hsync Cycle

RGBHST RGB input Horizontal enable area STart position

RGBHEN RGB input Horizontal enable area size

RGBVST RGB input Vertical ENable area STart position

RGBVEN RGB input Vertical ENable area size (notes 1) The above-mentioned and some settings of the display parameter are actually different. "..detailed... 7.4.3Please refer to the video capture register".

(notes 2) Horizontal valid pixel settings (RGBHEN) become it up to 840. This is a restriction by the size of the line buffer in the video capture module.

VSYNC

HS

YN

C

RGBHST

RGBVST

RGBHEN(~840)

RGBVEN

(~4096) captured

RGBHC




7.5.6.3.3. RGB input timing

When RGB is input, the synchronization of data is taken with VSIN input with data RI, GI, and BI and HSIN.

Input regulations of HSIN Ta or the Taori edge of the HSIN signal is assumed to be the horizontal synchronization by setting the HP register. The input signal is assumed more than one clock (CCLK_RGB).

(notes 1) Horizontal valid pixel settings (RGBHEN) become it up to 840. This is a restriction by the size of the line buffer in the video capture module. (notes 2) RGB_HSYNC is an internal signal generated from the HSIN signal.

Effective pixel data input regulations to HSYNC The effective image data input regulations to HSYNC are shown. Input data is input synchronizing with HSYNC of each line. The distance from HSYNC to the head of an effective pixel of data can be done in changeability by the RGBHST register setting.

CCLK_RGB

HSIN

RI5-0

GI5-0

BI5-0

RGBHST captured

CCLK_RGB

HSIN ∬

~840RGBCLK+α(HBLANK)

More than 1 RGBCLK ∬

∬∬

RGB_HSYNC ∬ ∬




Input regulations of VSYNC The VSIN signal is sampled with HSYNC by the register setting and it is assumed internal VSYNC signal. At this time, the width of the VSIN signal signal input from the outside is assumed more than one line or more. It stands up or Taori of the VSIN signal is assumed to be VSYNC signal by setting the VP register.

(notes 1) Internal signal image to RGB_HSYNC generated from HSIN signal

Effective pixel data input regulations to VSYNC

Effective pixel data input regulations to VSYNC are shown below.

VSIN

HSIN

start to capture RGBVST

(notes 1) The input of the interlace video is not supported in RGB input mode. Please set RGBVST_T_O to "00".

7.5.6.3.4. Color space change

The RGB → YCbCr conversion is done by the following matrix type.

Y = a11*R + a12*G + a13*B + b1 Cb = a21*R + a22*G + a23*B + b2 aij : 10bit signed real ( lower 8bit is fraction ) Cr = a31*R + a32*G + a33*B + b3 bi: 8bit unsigned integer

Please set RGBCMY, RGBCMCb, and RGBCMCr and RGBCMb to the coefficient of the color conversion matrix.

(notes 1) Each coefficient can be defined by the register setting. (notes 2) The format conversion is done further as for the converted YCbCr signal at 4:2:2, and the internal image processing is done.

More than 1 line

1CCLK_RGB

RGB_HSYNC

VSIN

~840CCLK_RGB+αCCLK_RGB




7.5.6.4. RGB video input parameter setting chart

A necessary register to set the parameter is different depending on the video input mode. Please refer to the following chart.

Register setting chart according to RGB video input mode

VIS?

RGBHC RGBHST RGBHEN RGBVST RGBVEN RM VP HP RGBCMY RGBCMCbRGBCMCrRGBCMb

RGBHC RGBHST RGBHEN RGBVST RGBVEN RM VP HP RGBCMY

VS

ITU-R.BT656

NRGB?

Native RGB

0

1

0 1

RGB 656

8.1. Outline


Draw Engine (Draw) FUJITSU SEMICONDUCTOR CONFIDENTIAL 159

8. Draw Engine (Draw)

8.1. Outline The GDC macro has our company LSI MB86276 and an interchangeable line drawing function and the BitBlt function.

8.2. Feature

・ The line drawing (1-32 pixel width line, broken line, and Antieiriasrain) is supported. ・ The BitBlt function (rectangular painting out and copy and character pattern) is supported. ・ The display list execution is supported. ・ 8bpp indirect color ・ Direct ARGB-1555 color ・ Binary bit map(Only the BitBlt function :. ) ・ The Alfabrending function is supported.

8.3. Composition

Display ControllerNTSC

MB91590 Series

GDC Macro

ADCNTSC

decoder

CaptureController

Video dataprocessor

Video timingcontroller

SpriteEngine

CSYNCDCLKOVSYNCHSYNCDE

DRiDGiDBi

GD

C L

ocal

Bus

DrawEngine

GraphicsMemory(VRAM)

GDCAHB-LocalBus Bridge

GD

C A

HB

Bus

Analog NTSC

Digital RGBor

ITU-R BT656

8.4. Register



8.4. Register




8.4.2. Register list

In ( ) of the Offset field, the absolute address used by the SetRegister command is shown. DrawBase = 01FF_0000H

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPN 140H (050H) 0 0 0 0 Int 0

LXs 144H (051H) S S S S Int Frac

LXde 148H (052H) S S S S S S S S S S S S S S S In

t

Frac

LYs 14CH (053H) S S S S Int Frac

LYde 150H (054H) S S S S S S S S S S S S S S S In

t

Frac

8.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXs 200H (080H) 0 0 0 0 Int 0

RYs 204H (081H) 0 0 0 0 Int 0

RsizeX 208H (082H) 0 0 0 0 Int 0

RsizeY 20CH (083H) 0 0 0 0 Int 0

SADDR 240H (090H) 0 0 0 0 0 0 0 Address

SStride 244H (091H) 0 0 0 0 Int 0

SRXs 248H (092H) 0 0 0 0 Int 0

SRYs 24CH (093H) 0 0 0 0 Int 0

DADDR 250H (094H) 0 0 0 0 0 0 0 Address

DStride 254H (095H) 0 0 0 0 Int 0

DRXs 258H (096H) 0 0 0 0 Int 0

DRYs 25CH (097H) 0 0 0 0 Int 0

BRsizeX 260H (098H) 0 0 0 0 Int 0

BRsizeY 264H (099H) 0 0 0 0 Int 0

TColor 280H (0A0H) 0 Color

8.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLPO 3E0H (0F8H) BCR

CTR 400H (100H)

FD

CE FCNT NF

FF

FE

SS DS PS

IFSR 404H (-)

NF

FF

FE

IFCNT 408H (-) FCNT

SST 40CH (-) SS

DS 410H (-) DS

PST 414H (-) PS

EST 418H (-)

FD

CE

MDR0 420H (108H)

ZP

CF

CY

CX

BSV BSH

MDR1 424H (109H) LW

BP

BL LOG BM

MDR4 430H (10CH) LOG BM

TE

8.4. Register



Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FBR 440H (110H) FBASE

XRES 444H (111H) XRES

CXMIN 454H (115H) CLIPXMIN

CXMAX 458H (116H) CLIPXMAX

CYMIN 45CH (117H) CLIPYMIN

CYMAX 460H (118H) CLIPYMAX

FC 480H (120H) FGC8/16

BC 484H (121H) BGC8/16

ALF 488H (122H) A

48CH (123H) BLP

TBC 494H (125H) BC8/16

LX0dc 540H (150H) 0 0 0 0 Int 0

LY0dc 544H (151H) 0 0 0 0 Int 0

LX1dc 548H (152H) 0 0 0 0 Int 0

LY1dc 54CH (153H) 0 0 0 0 Int 0

8.4. Register



8.4.3. Drawing control register

8.4.3.1. CTR (Control Register)

Register address 01FF_0400H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name FO CE FCNT NF FF FE SS DS PS

R/W RW RW R R R R R R R

Initial value 0 00 10000 0 0 1 00 00 00

It is a register in which the flag and status information on the drawing part are reflected. The flag of bit24-bit22 is not cleared until "0" is written.

[bit24] FO (FIFO Overflow)

The FIFO overflow is generated and it is shown the kite.

0 Normality

1 Overflow detection

[bit23, bit22] CE (Display List Command Error)

The command error occurs and it is shown the kite. There is a part of kind of error that cannot be detected, too. It is necessary to reset it for the return.

00 Normality

11 Error detection

[bit19～bit15] FCNT (FIFO Counter)

Number (0~10000b) of empty steps of display lists FIFO is shown.

[bit14] NF (FIFO Near Full)

It is shown that becoming empty of display list FIFO is below the half.

0 Becoming empty of FIFO is more than the half.

1 ..FIFO's becoming empty.. half.

[bit13] FF (FIFO Full)

It is shown that display list FIFO is full.

0 It is not full.

1 Full

[bit12] FE (FIFO Empty)

It is shown that there is no data in display list FIFO.

0 There is data.

1 Data none

8.4. Register



[bit9, bit8] SS (Setup Status)

The status of the setup unit is shown.

00 Idol

01 It is processing it.

10 Reservation

11 Reservation

[bit5, bit4] DS (DDA Status)

The status of the DDA unit is shown.

00 Idol



11 Reservation

[bit1, bit0] PS (Pixel engine Status )

The status of the pixel engine unit is shown.

00 Idol


10 Reservation

11 Reservation

8.4. Register



8.4.3.2. IFSR (Input FIFO Status Register)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name NF FF FE

R/W R R R

Initial value 0 0 1

This register is a mirror register of bit14-bit12 of CTR.

8.4.3.3. IFCNT (Input FIFO Counter)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name FCNT

R/W R

Initial value 10000


8.4.3.4. SST (Setup engine Status)

Register address 01FF_040CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name SS

R/W R

Initial value 00

This register is a mirror register of bit9 of CTR and bit8.

8.4.3.5. DST (DDA Status)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name DS

R/W R

Initial value 00


8.4. Register



8.4.3.6. PST (Pixel engine Status)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name PS

R/W R

Initial value 00


8.4.3.7. EST (Error Status)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name FO CE

R/W RW RW

Initial value 0 00


8.4. Register



8.4.4. Drawing mode register Writing the value in the register uses the SetRegister command. CPU cannot access it.

8.4.4.1. MDR0 (Mode Register for miscellaneous)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name ZP CF CY CX BSV BSH

R/W RW RW RW RW RW RW

Initial value 0 00 00000000 0 000 00 00000 0 0 0000 00 00

[bit20] ZP (Z Precision)

The accuracy of Z value used by the hidden surface removal is set. (It doesn't have the meaning in this macro. )

0 16 bits/pixel

1 Eight bits/pixel

[bit16, bit15] CF (Color Format)

The format of the drawing color is set.

00 Indirect color mode(eight bits/pixel)

01 Direct color mode(16 bits/pixel)

10-11 Reservation

[bit9] CY (Clip Y enable)

The Crippingg processing in the direction of Y is set.

0 The clipping is not done.

1 The clipping is done.

[bit8] CX (Clip X enable)

The Crippingg processing in the direction of X is set.

0 The clipping is not done.

1 The clipping is done.

[bit3, bit2] BSV (Bitmap Scale Vertical)

The magnification in the vertical direction of the bit map drawing is set.

00 One time

01 Two times

10 1/2 times

11 Reservation

[bit1, bit0] BSH (Bitmap Scale Horizontal)

The magnification in the horizontal direction of the bit map drawing is set.

00 One time

01 Two times

10 1/2 times

11 Reservation

8.4. Register



8.4.4.2. MDR1 (Mode Register for LINE)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name LW BP BL LOG BM

R/W RW RW RW RW RW

Initial value 000 00000 000 0 0 000000 0011 00 0000000

The mode of the line and the sketch picture is set.

[bit28～bit24] LW (Line Width)

The stroke width when the line drawing is set.

00000 One pixel in width

00001 Two pixels in width

: :

11111 32 pixels in width

[bit20] BP (Broken line Period)

It tears and the cycle of Sen pattern is selected.

0 32 bits

1 24 bits

[bit19] BL (Broken Line)

The solid line or the broken line is selected.

0 Solid line

1 Broken line

[bit12～bit9] LOG (Logical operation)

The logical operation mode when drawing is set.

0000 CLEAR

0001 AND

0010 AND REVERSE

0011 COPY

0100 AND INVERTED

0101 NOP

0110 XOR

0111 OR

1000 NOR

1001 EQUIV

1010 INVERT

1011 OR REVERSE

1100 COPY INVERTED

1101 OR INVERTED

1110 NAND

1111 SET

[bit8, bit7] BM (Blend Mode)

The blend mode is set.

8.4. Register



00 Normality(source copy)

01 Alfabrending

10 Drawing with logical operation

11 Reservation

8.4. Register



8.4.4.3. MDR4 (Mode Register for BLT)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name LOG BM TE

R/W RW RW RW

Initial value 0011 00 0

The BLT mode is set.

[bit12～bit9] LOG (Logical operation)

The logical operation mode when drawing is set.

0000 CLEAR

0001 AND

0010 AND REVERSE

0011 COPY

0100 AND INVERTED

0101 NOP

0110 XOR

0111 OR

1000 NOR

1001 EQUIV

1010 INVERT

1011 OR REVERSE

1100 COPY INVERTED

1101 OR INVERTED

1110 NAND

1111 SET

[bit8, bit7] BM (Blend Mode)

The blend mode is set.

00 Normality(source copy)

01 Reservation

10 Drawing with logical operation

11 Reservation

[bit1] TE (Transparent Enable)

The transparent mode is set.

0 The penetration processing is not done.

1 At BLT, it doesn't draw in a corresponding pixel to the set transparent color. (penetration copy) (note)Please give blend mode (BM) to me normally.

8.4. Register



8.4.5. Drawing configuration register

8.4.5.1. FBR (Frame buffer Base)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name Reserved FBASE

R/W RW0 RW R0

Initial value X X 0

The base address of the drawing frame is stored.

[bit31～bit26] Reserved

[bit25～bit0] FBASE (Frame Base Address)

This field shows the frame base address of interchangeable MB86276.

8.4.5.2. XRES (X Resolution)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name XRES

R/W RW

Initial value X

The resolution X axially on the drawing side is set.

8.4.5.3. CXMIN (Clip X minimum)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CLIPXMIN

R/W RW

Initial value X

The minimum value of X of the clip frame is set.

8.4.5.4. CXMAX (Clip X maximum)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CLIPXMAX

R/W RW

Initial value X X maximum value of the clip frame is set.

8.4.5.5. CYMIN (Clip Y minimum)


8.4. Register



Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CLIPYMIN

R/W RW

Initial value X

The minimum value of Y of the clip frame is set.

8.4.5.6. CYMAX (Clip Y maximum)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name CLIPYMAX

R/W RW

Initial value X

Y maximum value of the clip frame is set.

8.4.5.7. FC (Foreground Color)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name FGC8/16

R/W RW

Initial value 0

The foreground color for drawing is set. The object color or it draws the bit map about the flat shading, and it ..tear.. becomes the foreground color when Sen drawing. It draws in the pixel where one is set by the color of this register.

Eight bit color mode: It is bit31-bit8 unused bit.

[bit7～bit0] FGC8 (Foreground 8 bit Color)

An indirect color of foreground (color index code) is set.

16 bit color mode: It is bit31-bit16 unused bit.

[bit15～bit0] FGC16 (Foreground 16 bit Color)

The color of foreground is set directly by 16 bits. A set value of bit15 is reflected in the memory as it is.

8.4. Register



8.4.5.8. BC (Background Color)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name BGC8/16

R/W RW

Initial value 0

The background color for drawing is set. It becomes a background color of Sen ..tear.. drawing. It draws in the pixel where 0 is set by the color of this register. It is also possible to make the background color transparent (Do not draw), and sets it by the BT bit of this register.

Eight bit color mode: It is bit31-bit16 unused bit.

[bit15] BT (Background Transparency)

The background color transparent mode is set.

0 It draws in the background color by the BGC setting color.

1 It doesn't draw in the background. (transparency)

It is bit14-bit8 unused bit.

[bit7～bit0] BGC8 (Background 8 bit Color)

An indirect color of the background (color index code) is set.

16 bit color mode: It is bit31-bit16 unused bit.

[bit15] BT (Background Transparency)

The background color transparent mode is set.

0 It draws in the background color by the BGC setting color.

1 It doesn't draw in the background. (transparency)

[bit14～bit0] BGC16 (Background 16 bit Color)

RGB of the color of the background is set directly by 16 bits.

8.4.5.9. ALF (Alpha Factor)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name A

R/W RW

Initial value 0

The Alfabrending coefficient is set.

8.4. Register



8.4.5.10. BLP (Broken Line Pattern)


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name BLP

R/W RW

Initial value 0

It tears and Sen pattern is set. It tears and Sen pattern draws the bit of one and it is drawn to the bit of foreground and 0 as a background. It tears and Sen pattern returns to MSB corresponding to 1pixel of the line when it is allocated from MSB in the direction of LSB, and it reaches LSB. It tears and the bit number of Sen pattern is managed by the BLPO register. It tears and the repetition of Sen pattern can select 32 bits or 24 bits according to the BP register of the MDR1 register. It is use for 24 bits as for bit23-bit0 of the BLP register.

8.4. Register



8.4.5.11. BLPO (Broken Line Pattern Offset)

Register address 01FF_03E0H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name BCR

R/W RW

Initial value 11111

Broken line..draw..register..set..broken line..pattern..bit..number..store.This register is decreased draw one pixel. It tears and it is possible to draw from an arbitrary starting position in Sen pattern by setting the value to this register. When writing is not done, it tears and the position of Sen pattern is continued. Line drawing register XY coordinates setting register Each register is used by the drawing command. The access and the SetRegister command from CPU cannot be used. Register Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPN 0140H 0 0 0 0 Int 0

LXs 0144H S S S S Int Frac

LXde 0148H S S S S S S S S S S S S S S S Int Frac

LYs 014cH S S S S Int Frac

LYde 0150H S S S S S S S S S S S S S S S Int Frac

The coordinates parameter when the line drawing is set.

LPN The number of pixels in the direction of the main axis is set.

LXs X coordinates of the segment drawing beginning point are set. (For main axis X. )Integral value in which half-adjust of X coordinates (For main axis Y. )X coordinates of fixed decimal form

LXde Information on the inclination of X coordinates is set. (For main axis X. )It is 1 or -1 according to the direction of drawing. (For main axis Y. )Value of DX/DY(Only the decimal part :. )

LYs Y coordinates of the segment drawing beginning point are set. (For main axis X. )Y coordinates of fixed decimal form (For main axis Y. )Integral value in which half-adjust of YX coordinates

LYde Information on the inclination of Y coordinates is set. (For main axis X. )Value of DY/DX(Only the decimal part :. ) (For main axis Y. )It is 1 or -1 according to the direction of drawing.

8.4. Register



8.4.6. Rectangular drawing register Each register is used by the drawing command. The access and the SetRegister command from CPU cannot be used. Register Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXs 0200H 0 0 0 0 Int 0

RYs 0204H 0 0 0 0 Int 0

RsizeX 0208H 0 0 0 0 Int 0

RsizeY 020cH 0 0 0 0 Int 0

Address Offset value from DrawBaseAddress S Sign and sign extension 0 Unused or 0 enhancing Int Integer part of integer or fixed decimal form Frac Fraction part of fixed decimal form

The coordinates parameter of a rectangular drawing is set. The color becomes a foreground color.

RXs X coordinates on the left rectangular that does Phil are set.

RYs Y coordinates on the left rectangular that does Phil are set.

RsizeX A rectangular X direction size in which Phil is done is set.

RsizeY A rectangular Y direction size in which Phil is done is set.

8.4. Register



8.4.7. Blt register The setting of the parameter of each register is as follows. The Tcolor register is set by the SetRegister command.

Please it doesn't set it in the access and the drawing command from CPU. Each register other than the Tcolor register are set by executing the drawing command.

Please note that the access and the SetRegister command from CPU cannot be used.

Register

Address 31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9 8 7 6 5 4 3 2 1 0

SADDR 0240H 0 0 0 0 0 0 0 Address SStride 0244H 0 0 0 0 Int 0 SRXs 0248H 0 0 0 0 Int 0 SRYs 024CH 0 0 0 0 Int 0 DADDR 0250H 0 0 0 0 0 0 0 Address DStride 0254H 0 0 0 0 Int 0 DRXs 0258H 0 0 0 0 Int 0 DRYs 025CH 0 0 0 0 Int 0 BRsizeX 0260H 0 0 0 0 Int 0 BRsizeY 0264H 0 0 0 0 Int 0 TColor 0280H 0 Color


The parameter of the Blt processing is set.

SADDR The first address in a rectangular area of the source is specified. The address is specified in byte address.

SStride The stride of the source is specified.

SRXs Beginning X coordinates of a rectangular area of the source are specified.

SRYs Beginning Y coordinates of a rectangular area of the source are specified.

DADDR The first address in a rectangular area of the destination is specified. The address is specified in byte address.

DStride The stride of the destination is specified.

DRXs Beginning X coordinates of a rectangular area of the destination are specified.

DRYs Beginning Y coordinates of a rectangular area of the destination are specified.

BRsizeX A rectangular X size is specified.

BRsizeY A rectangular Y size is specified.

TColor The transparent color is set. The palette code is set to eight subordinate position bits for an indirect color.

8.4. Register



8.4.8. 2D high-speed line drawing register Each register is used by the drawing command. CPU cannot access it. Register Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LX0dc 0540H 0 0 0 0 Int 0

LY0dc 0544H 0 0 0 0 Int 0

LX1dc 0548H 0 0 0 0 Int 0

LY1dc 054cH 0 0 0 0 Int 0


Coordinates (V0,V1) in the top of the line endpoint are set when 2D high-speed line drawing.

LX0dc X coordinates in top V0 are set.

LY0dc Y coordinates in top V0 are set.

LX1dc X coordinates in top V1 are set.

LY1dc Y coordinates in top V1 are set.

8.4. Register



8.4.9. Display list FIFO

8.4.9.1. DFIFO (Displaylist FIFO)

Register address 01FF_04A0H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name DFIFO

R/W W

Initial value X

It is FIFO register for the display list forwarding. The GDC macro becomes a master by me, has data from memory (VRAM ,CMDRAM) in GDC memory to display list FIFO, and the function to forward DMA is possessed. Chapter 21 Reference.





8.5.1. Coordinate system

8.5.1.1. Drawing coordinates In Draw Engine, it draws to the drawing frame on VRAM using the drawing coordinates (device coordinates). It is treated as two dimension coordinates like the figure below drawing frame origin point on the left. Coordinates of 4096×4096 or less can be treated. The drawing frame is arranged on VRAM by setting the resolution (size) in the address and the direction of X of the drawing frame starting point to the register. When drawing, Y coordinates that become the maximum should make it not come in succession with other areas though there is no size in the direction of Y ..setting especially.. needing. Moreover, when drawing, it is possible not to draw outside of the clip frame. The clip frame specifies lower right on the left of the frame, coordinates.

X (Max.4096）

Y (

Max

.409

6)

Origin Frame size X for Drawing

Fra

me

size

Y fo

r D

raw

ing

(Xmin,Ymin)

(Xmax,Ymax)

Frame for Clipping




8.5.2. Graphic depiction

8.5.2.1. Drawing primitiveness A line drawing and a rectangular drawing (BitBlt function) interchangeable to our company LSI MB86276 graphics controller are possessed in Draw Engine. It is possible to draw to VRAM (drawing side) in the figure of two dimensions by a color mode and a direct indirect color mode. The line can draw the heavy line and the broken line with width. It is also possible to give anti-aliasing, and to draw a smooth slash.

Table8-12D graphic depiction primitiveness

Primitiveness Explanation

Line It draws in the line.

Rectangle It draws in the rectangle.

8.5.2.2. Drawing color Eight bit indirect color and direct 16 bit color are supported as drawing input data.

8.5.2.3. Anti-aliasing function Draw Engine can reed the jaggy unremarkable by the anti-aliasing processing in the line drawing. The burr in the hatched line is shown smoothly by processing the boundary in the line in each subpixel, and doing the pixel color and the color before it draws in blend. It is possible to set it as an attribute of the line and 2D high-speed line drawing (It is personally effective only for the drawing frame of the color mode).

8.5.2.4. Alfabrending function Alfabrending expresses the effect of penetration by mixing the color of two images. The transmission coefficient is set to the register. The set transmission coefficient is used while drawing in one primitiveness. The blend is not processed to the transparent color, and the transparency is maintained. (The alpha blend of drawing is personally effective only for the drawing frame of the color mode. )




8.5.2.5. Bit map processing

8.5.2.5.1. BitBlt

The rectangle of each pixel can be forwarded. There is the following kinds of forwarding. Forwarding from FR81S to drawing frame Forwarding between VRAM Clause 2 logical operation is done and the result can be written. Moreover, it is also possible to draw by setting the transparent color penetrating a specific pixel. It is necessary to do the beginning point setting of forwarding to the source correctly when there is an overlapping part in the destination.

8.5.2.5.2. Pattern form

In the bit map data that the GDC macro treats, there are indirect color mode (8bit/pixel) and color mode (16bit/pixel) and direct binary bit map (1bit/pixel). The character pattern draws the pixel of one of the bit map in using the binary bit map and it draws in the bit of the foreground color and 0 by BGCOLOR (It is also possible to make BGCOLOR transparent by the setting).

8.5.2.6. Logical operation The logical operation is done between pixels where it has already been drawn by the pixel and the frame buffer where it tries to draw, and it draws in the operation result. When this specification is done, Alfabrending cannot be specified.

Operation form ID Operation Operation form ID Operation

CLEAR 0000 0 AND 0001 S & D

COPY 0011 S OR 0111 S | D

NOP 0101 D NAND 1110 !(S & D)

SET 1111 1 NOR 1000 !(S | D)

COPY INVERTED 1100 !S XOR 0110 S xor D

INVERT 1010 !D EQUIV 1001 !(S xor D)

AND REVERSE 0010 S & !D AND INVERTED 0100 !S & D

OR REVERSE 1011 S | !D OR INVERTED 1101 !S | D




8.5.3. Graphic depiction attribute

8.5.3.1. Line drawing attribute It is possible to draw by specifying the following attributes when drawing in the line.

Table8-2Line drawing attribute

Drawing attribute Function

Stroke width The stroke width can be specified within the range of the width of 1~32pixel. The starting point and the terminal in the heavy line become vertical for the main axis.

Sen ..tear.. processing It tears and Sen pattern can be specified. It tears and Sen pattern of 32 bits is set. Sen ..tear.. pattern becomes Sen pattern ..vertical to the main axis.. ..the tear...

Antieirias processing When effective Antieirias is selected, a smooth line from which anti-aliasing is given can be drawn.

8.5.3.2. BitBlt attribute It is possible to draw by specifying the following attributes when BLT is processed. BitBlt attribute


Logical operation mode Clause 2 logical operation mode is specified.

Transparent mode The penetration copy mode and the penetration color are set.

8.5.3.3. Character pattern drawing attribute Character pattern drawing and attribute


Character pattern extension reduction Twice in length and breadth, twice in width, 1/2 times in length and breadth, and 1/2 times in width can be specified.

Character pattern color The character color (foreground color) and the background color are set.

Penetration Non-penetration/penetration of the background color is set.




8.5.4. Display list The set of the display list command, the parameter, and the pattern data is called a display list. The display list command stored in FIFO is executed and processed one by one.

The display list is transmitted to display list FIFO. Either of the forwarding method the following is used. Forwarding to VRAM→FIFO by register setting for local forwarding in forwarding GDC macro to memory →FIFO of FR81S by DMA controller of writing FR81S in FIFO by FR81S

Table8-3Display list

Displaylist Command-1

Data1-1

Data1-2

Data1-3

Displaylist Command-2

Data2-1

Data2-2

Data2-3

…




8.5.4.1. Header format The format of the display list header is shown as follows. Format list

Format 31 24 23 16 15 0

Format 1 Type Reserved Reserved

Format 2 Type Count Address

Format 5 Type Command Reserved

Format 7 Type Command Reserved Vertex

Format 9 Type Reserved Reserved Flag

Table8-4Explanation of each field

Type Display list type

Command Command

Count Numbers of data of parameters except header

Address Address value for data transfer etc.

Vertex The top number

Flag Peculiar attribute flag to display list command

Table8-5The top number specified by Vertex code

Vertex The top number(line) The top number(triangle)

00 V0 V0

01 V1 V1

10 Set prohibition V2

11 Set prohibition Set prohibition

8.5.4.2. Parameter format The parameter of the rendering command is a data of interchangeable MB86276 format.




8.5.4.3. Rendering command

8.5.4.3.1. Command list

The rendering command and each command code of Draw Engine is shown below.

Type Command Explanation

Nop - No operation

Interrupt - Interruption generation to host

Sync - Synchronization with event

SetRegister - Data set to register

Draw Flush_FB/Z Flash of drawing pipeline

Xvector Line drawing(main axis X)

Yvector Line drawing(main axis Y)

AntiXvector Line drawing with Antieirias(main axis X) DrawLine

AntiYvector Line drawing with Antieirias(main axis Y)

DrawLine2i ZeroVector 2D high-speed line drawing(0 top starting points)

DrawLine2iP OneVector 2D high-speed line drawing(one top starting point)

DrawRectP BltFill Rectangular drawing by single color

BltDraw Blt drawing(parameter number 16bit specification) DrawBitmapP

Bitmap Binary bit map (character) drawing

TopLeft Blt forwarding from left top seat signpost

TopRight Blt forwarding from coordinates on the right

BottomLeft Blt forwarding from left right-hand side of the stage signpost

BltCopyP BltCopy- AlternateP

BottomRight Blt forwarding from coordinates under the right

Type code table

Type Code

DrawLine 0000_0010

DrawLine2i 0000_0011

DrawLine2iP 0000_0100

DrawRectP 0000_1001

DrawBitmapP 0000_1011

BitCopyP 0000_1101

BitCopyAlternateP 0000_1111

Draw 1111_0000

SetRegister 1111_0001

Sync 1111_1100

Interrupt 1111_1101

Nop 1111_1111




Command code table(1)

Command Code

Xvector 001_00000

Yvector 001_00001

XvectorNoEnd 001_00010

YvectorNoEnd 001_00011

XvectorBlpClear 001_00100

YvectorBlpClear 001_00101

XvectorNoEndBlpClear 001_00110

YvectorNoEndBlpClear 001_00111

AntiXvector 001_01000

AntiYvector 001_01001

AntiXvectorNoEnd 001_01010

AntiYvectorNoEnd 001_01011

AntiXvectorBlpClear 001_01100

AntiYvectorBlpClear 001_01101

AntiXvectorNoEndBlpClear 001_01110

AntiYvectorNoEndBlpClear 001_01111

ZeroVector 001_10000

Onevector 001_10001

ZeroVectorNoEnd 001_10010

OnevectorNoEnd 001_10011

ZeroVectorBlpClear 001_10100

OnevectorBlpClear 001_10101

ZeroVectorNoEndBlpClear 001_10110

OnevectorNoEndBlpClear 001_10111

AntiZeroVector 001_11000

AntiOnevector 001_11001

AntiZeroVectorNoEnd 001_11010

AntiOnevectorNoEnd 001_11011

AntiZeroVectorBlpClear 001_11100

AntiOnevectorBlpClear 001_11101

AntiZeroVectorNoEndBlpClear 001_11110

AntiOnevectorNoEndBlpClear 001_11111

Command code table(2)

Command Code

BltFill 010_00001

Flush_FB 110_00001




8.5.4.3.2. Explanation of rendering command

The parameter attached to the command is stored in the corresponding register. Please refer to the explanation of each register for the meaning of the parameter.

8.5.4.3.3. Nop (Format 1)

31 24 23 16 15 0 Nop Reserved Reserved

No operation.

8.5.4.3.4. Interrupt (Format 1)

31 24 23 16 15 0 Interrupt Reserved Reserved

The interruption to host CPU is generated.

8.5.4.3.5. Sync (Format 9)

31 24 23 16 15 4 0 Sync Reserved Reserved Flag

The following display list processing is stopped until the event set with Flag is detected. Flag:

Bit number 4 3 2 1 0

Bit field name Reserved Reserved Reserved Reserved VBLANK

[bit0] VBLANK

VBLANK synchronization.

0 No operation

1

Processing is stopped until the vertical blank set in the FS field of the MDR0 register is detected.

8.5.4.3.6. SetRegister (Format 2)

31 24 23 16 15 0 SetRegister Count Address

(Val 0) (Val 1) …

(Val n)

Data is set in a consecutive register. Count: Number Address of data (unit of double word): Please set the value of the address for SetRegister of the register address register list. Please set a register address first in case of two data forwarding.




8.5.4.3.7. Draw (Format 5)

31 24 23 16 15 0 Draw Command Reserved

The drawing command is executed. It is necessary to set the parameter necessary for the command execution by using SetRegister etc.

Command:

Flush_FB The drawing data of the drawing pipeline inside is done and the flash is done to VRAM. Please insert this command at the end of the display list.




8.5.4.3.8. DrawLine (Format 5)

31 24 23 16 15 0 DrawLine Command Reserved

LPN LXs

LXde LYs

LYde

The line draws. Drawing begins after setting the parameter in the register for the line drawing. Command:

Xvector It draws in the line. (main axis X)

Yvector It draws in the line. (main axis Y)

XvectorNoEnd It draws in the line. (There are neither main axis Y nor drawing in the terminal. )

YvectorNoEnd It draws in the line. (There are neither main axis Y nor drawing in the terminal. )

XvectorBlpClear It draws in the line. (Sen pattern reference position ..tear.. clearness before it begins ..main axis X.. to draw)

YvectorBlpClear It draws in the line. (Sen pattern reference position ..tear.. clearness before it begins ..main axis Y.. to draw)

XvectorNoEndBlpClear It draws in the line. (Sen pattern reference position ..tear.. clearness before it begins to draw in there are neither main axis X nor drawing in terminal)

YvectorNoEndBlpClear It draws in the line. (Sen pattern reference position ..tear.. clearness before it begins to draw in there are neither main axis Y nor drawing in terminal)

AntiXvector It draws in the line with Antieirias. (main axis X)

AntiYvector It draws in the line with Antieirias. (main axis Y)

AntiXvectorNoEnd It draws in the line with Antieirias. (There are neither main axis Y nor drawing in the terminal. )

AntiYvectorNoEnd It draws in the line with Antieirias. (There are neither main axis Y nor drawing in the terminal. )

AntiXvectorBlpClear It draws in the line with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins ..main axis X.. to draw)

AntiYvectorBlpClear It draws in the line with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins ..main axis Y.. to draw)

AntiXvectorNoEndBlpClear It draws in the line with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw in there are neither main axis X nor drawing in terminal)

AntiYvectorNoEndBlpClear It draws in the line with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw in there are neither main axis Y nor drawing in terminal)




8.5.4.3.9. DrawLine2i (Format 7)

31 24 23 16 15 0

DrawLine2i Command Reserved Verte

x LFXs 0 LFYs 0

2D high-speed line draws. Drawing begins after setting the parameter in the register for 2D high-speed line drawing. Coordinates can use only the integer.

Command:

ZeroVector It draws in the line from top 0 to top 1.

OneVector It draws in the line from top 1 to top 0.

ZeroVectorNoEnd It draws in the line from top 0 to top 1. (There is not drawing in the terminal. )

OneVectorNoEnd It draws in the line from top 1 to top 0. (There is not drawing in the terminal. )

ZeroVectorBlpClear It draws in the line from top 0 to top 1. (Sen pattern reference position ..tear.. clearness before it begins to draw)

OneVectorBlpClear It draws in the line from top 1 to top 0. (Sen pattern reference position ..tear.. clearness before it begins to draw)

ZeroVectorNoEndBlpClear It draws in the line from top 0 to top 1. (Sen pattern reference position ..tear.. clearness before it begins to draw in there is not drawing in terminal)

OneVectorNoEndBlpClear It draws in the line from top 1 to top 0. (Sen pattern reference position ..tear.. clearness before it begins to draw in there is not drawing in terminal)

AntiZeroVector It draws in the line from top 0 to top 1 with Antieirias.

AntiOneVector It draws in the line from top 1 to top 0 with Antieirias.

AntiZeroVectorNoEnd It draws in the line from top 0 to top 1 with Antieirias. (There is not drawing in the terminal. )

AntiOneVectorNoEnd It draws in the line from top 1 to top 0 with Antieirias. (There is not drawing in the terminal. )

AntiZeroVectorBlpClear It draws in the line from top 0 to top 1 with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw)

AntiOneVectorBlpClear It draws in the line from top 1 to top 0 with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw)

AntiZeroVectorNoEndBlpClear It draws in the line from top 0 to top 1 with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw in there is not drawing in terminal)

AntiOneVectorNoEndBlpClear It draws in the line from top 1 to top 0 with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw in there is not drawing in terminal)




8.5.4.3.10. DrawLine2iP (Format 7)

31 24 23 16 15 0

DrawLine2iP Command Reserved Verte

x LFYs LFXs

2D high-speed line draws. Drawing begins after setting the parameter in the register for 2D high-speed line drawing. Coordinates can use only the integer (Paccd form).

Command:

ZeroVector It draws in the line from top 0 to top 1.

OneVector It draws in the line from top 1 to top 0.

ZeroVectorNoEnd It draws in the line from top 0 to top 1. (There is not drawing in the terminal. )

OneVectorNoEnd It draws in the line from top 1 to top 0. (There is not drawing in the terminal. )

ZeroVectorBlpClear It draws in the line from top 0 to top 1. (Sen pattern reference position ..tear.. clearness before it begins to draw)

OneVectorBlpClear It draws in the line from top 1 to top 0. (Sen pattern reference position ..tear.. clearness before it begins to draw)

ZeroVectorNoEndBlpClear It draws in the line from top 0 to top 1. (Sen pattern reference position ..tear.. clearness before it begins to draw in there is not drawing in terminal)

OneVectorNoEndBlpClear It draws in the line from top 1 to top 0. (Sen pattern reference position ..tear.. clearness before it begins to draw in there is not drawing in terminal)

AntiZeroVector It draws in the line from top 0 to top 1 with Antieirias.

AntiOneVector It draws in the line from top 1 to top 0 with Antieirias.

AntiZeroVectorNoEnd It draws in the line from top 0 to top 1 with Antieirias. (There is not drawing in the terminal. )

AntiOneVectorNoEnd It draws in the line from top 1 to top 0 with Antieirias. (There is not drawing in the terminal. )

AntiZeroVectorBlpClear It draws in the line from top 0 to top 1 with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw)

AntiOneVectorBlpClear It draws in the line from top 1 to top 0 with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw)

AntiZeroVectorNoEndBlpClear It draws in the line from top 0 to top 1 with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw in there is not drawing in terminal)

AntiOneVectorNoEndBlpClear It draws in the line from top 1 to top 0 with Antieirias. (Sen pattern reference position ..tear.. clearness before it begins to draw in there is not drawing in terminal)




8.5.4.3.11. DrawRectP (Format 5)

31 24 23 16 15 0 DrawRectP Command Reserved

RYs RXs RsizeY RsizeX

It rectangle draws. After the parameter is set in the register, a rectangular area is painted out with a current color. Please set the value of eight Baitoarain to XRES(X resolution) when you execute this command.

Command:

BltFill A rectangular area is painted out with a current color (single color).

8.5.4.3.12. DrawBitmapP (Format6)

31 24 23 16 15 0 DrawBitmapP Command Count

RYs RXs

RsizeY RsizeX

(Pattern 0)

(Pattern 1)

…

(Pattern n)

A rectangular pattern draws. Please set the value of eight Baitoarain to XRES when you execute this command.

Command: BltDraw It draws in patterns of eight bits or 16 bit pixels.

DrawBitmap It draws in the bit map character pattern of the binary. It is drawn to the transparency or the background color register and 1 in 0 by a set color of the foreground color register.

Parameter:

RXs X coordinates on the left rectangular that does Phil are set. It is possible to specify it within the range of 0-4095.

RYs Y coordinates on the left rectangular that does Phil are set. It is possible to specify it within the range of 0-4095.

RsizeX A rectangular X direction size in which Phil is done is set. It is possible to specify it within the range > ?? 00 1 time ??????????? 1-4095 of the BSH>< useful range < MDR0 register. ?? 01 It is possible to specify it in twice ??????????? 1-2047 the range. ?? 10 It is possible to specify it in 1/2 times ????????? 2-4095 the range.

RsizeY A rectangular Y direction size in which Phil is done is set. It is possible to specify it within the range > ?? 00 1 time ??????????? 1-4095 of the BSV>< useful range < MDR0 register. ?? 01 It is possible to specify it in twice ??????????? 1-2047 the range. ?? 10 It is possible to specify it in 1/2 times ????????? 2-4095 the range.




8.5.4.3.13. BltCopyP (Format5)

31 24 23 16 15 0 BltCopyP Command Reserved

SRYs SRXs DRYs DRXs

BRsizeY BRsizeX

A rectangular pattern is copied in the drawing intraframe. Please set the value of eight Baitoarain to XRES when you execute this command.

Command: TopLeft The BitBlt forwarding begins from the left top seat signpost. TopRight The BitBlt forwarding begins from coordinates on the right. BottomLeft The BitBlt forwarding begins from the left right-hand side of the

stage signpost. BottomRight The BitBlt forwarding begins from coordinates under the right.

Parameter:



SRXs Beginning X coordinates of a rectangular area of the source are specified. It is possible to specify it within the range of 0-4095.

SRYs Beginning Y coordinates of a rectangular area of the source are specified. It is possible to specify it within the range of 0-4095.



DRXs Beginning X coordinates of a rectangular area of the destination are specified. It is possible to specify it within the range of 0-4095.

DRYs Beginning Y coordinates of a rectangular area of the destination are specified. It is possible to specify it within the range of 0-4095.

BRsizeX A rectangular X size is specified. It is possible to specify it within the range of 1-4096.

BRsizeY A rectangular Y size is specified. It is possible to specify it within the range of 1-4096.





8.5.4.3.14. BltCopyAlternateP (Format5)

31 24 23 16 15 0 BltCopyAlternateP Command Reserved

SADDR SStride

SRYs SRXs DADDR DStride

DRYs DRXs BRsizeY BRsizeX

A rectangular pattern is copied between different drawing frames. Please set the value of eight Baitoarain to XRES when you execute this command. Please set the value of eight Baitoarain to the value of SStride and DStride. As for the real address of the destination of VRAM, DADDR is added and calculated in the address of FBR.

Command: TopLeft The BitBlt forwarding begins from the left top seat signpost. In this command, the drawing clip is not executed.

Parameter:



SRXs Beginning X coordinates of a rectangular area of the source are specified. It is possible to specify it within the range of 0-4095.

SRYs Beginning Y coordinates of a rectangular area of the source are specified. It is possible to specify it within the range of 0-4095.



DRXs Beginning X coordinates of a rectangular area of the destination are specified. It is possible to specify it within the range of 0-4095.

DRYs Beginning Y coordinates of a rectangular area of the destination are specified. It is possible to specify it within the range of 0-4095.

BRsizeX A rectangular X size is specified. It is possible to specify it within the range of 1-4096.

BRsizeY A rectangular Y size is specified. It is possible to specify it within the range of 1-4096.


9.1. Outline


SpriteEngine (SPE) FUJITSU SEMICONDUCTOR CONFIDENTIAL 197

9. SpriteEngine (SPE) This chapter explains sprite engine (SPE) of the GDC macro.

9.1. Outline SpriteEngine (henceforth SPE) is used to make the image by the GDC macro. The method of processing various images can be used according to various register settings with software.

9.2. Feature Sprite of 512 or less Monochrome sprite (rectangular drawing) and font mode sprite Special sprite of 32 for automatic animation 16,777,216 colors or less Two can be set the color palette mode individual: 16bpp (ARGB-4444/ARGB-1555/RGB565) and

32bpp. (ARGB-8888) Eight 8bpp color palette tables or less(ARGB-4444/ARGB-1555/RGB565) 1bpp, 2bpp, 4bpp, and 8bpp indirect color format ARGB-1555, RGB-565, and direct color format of ARGB-8888 The color format of each sprite can be individually set. Alfabrending(4/8bpp alpha) Image reversing function(length/side)

9.3. Composition



9.3. Composition

9.3.1. Block diagram Figure9-1The block diagram of SPE is shown.

Figure9-1Block diagram of SPE


MB91590 Series

GDC Macro

ADCNTSC

decoder

CaptureController

Video dataprocessor


SpriteEngine


DRiDGiDBi

GD

C L

ocal

Bus

DrawEngine



GD

C A

HB

Bus

Analog NTSC

Digital RGBor

ITU-R BT656

Note:

Analog NTSC corresponds to external terminal VIN. Digital RGB corresponds to external terminal PA2-PA7, PB2-PB7, and PC2-PC7. ITU-R.BT656 corresponds to external terminal PA2-PA7, PB2, and PB3. CSYNC corresponds to external terminal PG3. DCLKO corresponds to external terminal PG4. VSYNC corresponds to external terminal PG5. HSYNC corresponds to external terminal PG6. DE corresponds to external terminal PG7. DRi corresponds to external terminal P011, P012, and PD2-PD7. DGi corresponds to external terminal P013, P014, and PE2-PE7. DGi corresponds to external terminal P015, P016, and PF2-PF7.

9.4. Register



9.4. Register

9.4.1. Description form of register The register of the endian this module corresponds to the little endian. Please add Base Address(0040_0000H) when Base addressFR81S(CPU) accesses it. The bit number of the Bit register is shown. The bit field name of the Name register is shown. Reserved is shown by "-". The attribute of read/write of the R/W each bit field is shown. R0: The read value is always "0. "R1:



9.4. Register




Table9-1SPE register list

Address Register name Description

Function Register

01FB_8000H SPEBG (S) Background color definition register.

01FB_8004H SPETP0 (S) Transparent color definition register0 (indirect).

01FB_8008H SPETP1 (S) Transparent color definition register1 (direct).

01FB_800CH SPEABC (S) Alpha blend single color definition register.

01FB_8010H SPECTL Sprite Engine control register.

01FB_8014H SPEST Status of the sprite engine register.

01FB_8018H SPEILN Interrupt line (0 - 4095) specify register.

01FB_801CH SPESDN (S) Sprite number range for display.

01FB_8020H SPEDETC (S) Sprite display enable table clear register.

01FB_8024H SPEDPAR Display area setting register.

01FB_8028H SPEPBA Pattern memory base address register.

01FB_802CH SPERSC Resource FIFO enable register.

SDET (Sprite Display Enable Table)

01FB_8100H SPESDE0 (S) Sprite display enable (SPR0 - SPR31)

01FB_8104H SPESDE1 (S) Sprite display enable (SPR32 - SPR63)

... ... ...

01FB_813CH SPESDE15 (S) Sprite display enable (SPR480 - SPR511)

SSCR (Special Sprite Configure Register)

01FB_8200H SPESS0CR3 Special Sprite0 control register3



... ... ...



01FB_837CH SPESS31CR5 Special Sprite31 control register5

01FB_8400H SPESSN0 Special sprite specify register0

01FB_8404H SPESSN1 Special sprite specify register1

... ... ...

01FB_847CH SPESSN31 Special sprite specify register31

SPT (Sprite Priority Table)

01FB_9000H SPESPRI0 Priority 0 set register



... ... ...

01FB_97FCH SPESPRI511 Priority 511 set register

9.4. Register




SAT (Sprite Attribute Table)

01FB_A000H SPES0CR0 Sprite0 control register0



... ... ...

01FB_ABF0H SPES254CR2 Sprite254 control register2



01FB_ABFCH SPES255CR2 Sprite255 control register2

... ... ...

01FB_B7F4H SPES511CR0 Sprite511 control register0

01FB_B7F8H SPES511CR1 Sprite511 control register1

01FB_B7FCH SPES511CR2 Sprite511 control register2

LUT (Look-up Table)

01FB_E000H SPELUTS0 LUT Setting register0



... ... ...

01FB_EFFCH SPELUTS1023 LUT Setting register511

Notes: (S) described in Register name shows the shadow register. The shadow register is loaded according to

the timing of the following VSYNC. It cannot access all reservations or unused address positions.

9.4. Register




9.4.3.1. Background Color register (SPEBG)

Address 01FB_8000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - RVAL[7:0] R/W R/W R/W Initial 00H 00H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GVAL[7:0] BVAL[7:0] R/W R/W R/W Initial 00H 00H

bit field

No name Explanation

7-0 BVAL[7:0] Blue definition of background

15-8 GVAL[7:0] Green definition of background

23-16 RVAL[7:0] Red definition of background

Notes: When SPECTL:BGM is only "0", this register becomes active. This register is a shadow register. The shadow register is loaded according to the timing of the

following VSYNC.

9.4.3.2. Transparent Color register0 (SPETP0) (indirect color mode)

Address 01FB_8004H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W R/W Initial 0000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - TP1B TP2B[1:0] TP4B[3:0] TP8B[7:0] R/W R/W R/W R/W R/W R/W Initial 0B 0B 0H 0H 00H

bit field

No name Explanation

7-0 TP8B[7:0] Transparent color code definition at eight bit color mode

11-8 TP4B[3:0] Transparent color code definition at four bit color mode

13-12 TP2B[1:0] Transparent color code definition at two bit color mode

14 TP1B Transparent color code definition at one bit color mode

Notes:

This register is a shadow register. The shadow register is loaded according to the timing of the following VSYNC.

9.4. Register



9.4.3.3. Transparent Color register1 (SPETP1) (direct color mode)

Address 01FB_8008H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GVAL[7:0] BVAL[7:0] R/W R/W R/W Initial 00H 00H

bit field

No name Explanation

7-0 BVAL [7:0] Direct blue definition of transparent color at color mode

15-8 GVAL [7:0] Direct green definition of transparent color at color mode

23-16 RVAL [7:0] Direct red definition of transparent color at color mode

Notes: This register is a shadow register. The shadow register is loaded according to the timing of the

following VSYNC.

9.4.3.4. Alpha-Blending Color register (SPEABC)

Address 01FB_800CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Bit 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14Name GVAL[7:0] BVAL[7:0] R/W R/W R/W Initial 00H 00H

bit field

No name Explanation

7-0 BVAL [7:0] Blue definition of single color Alfabrending

15-8 GVAL [7:0] Green definition of single color Alfabrending

23-16 RVAL [7:0] Red definition of single color Alfabrending


following VSYNC. When Alfabrendingmord is set to the mode that does a single color and the blending, this register is

used.

9.4. Register



9.4.3.5. Control register (SPECTL)

Address 01FB_8010H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - EBCE BERE PERE ILNE LBKE - SRL SSPE BGM SRE PRI SENR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0H 0B 0B 0B 0B 0B 0H 0B 0B 0B 0B 0B 0B

bit field

No name Explanation

0 SEN Making of SPE processing effective 1:Effective 0:Invalidity

1 PRI

Selection of priority level mode of sprite display 1:SPT mode 0:Fixed mode It fixes by the sprite number: SPR0 < SPR1 <…< SPR511.

2 SRE Making of shadow register update effective 1:Effective 0:Invalidity

3 BGM Selection of background mode 1:000001H of fixed value 0:Data set to SPEBG register

4 SSPE Making of special sprite function effective 1:Effective 0:Invalidity

5 SRL Making of shadow register loading actively 1:The shadow register is loaded with the following VSYNC. 0:The shadow register is not loaded.

8 LBKE Making of interruption at line blank effective 1:Effective 0:Invalidity

9 ILNE Making of line interruption effective 1:Effective 0:Invalidity

10 PERE Making of processing error interruption flag effective 1:Effective 0:Invalidity

11 BERE Making of bus error interruption flag effective 1:Effective 0:Invalidity

12 EBCE Making of "Enable Bits Changed" interruption effective 1:Effective 0:Invalidity

9.4. Register



Notes:

Please set SEN when the initialization of other function registers is completed, and the preparation for the pattern data is complete.

When SRE is set to "1", only all the shadow registers are updated in the following.. VSYNC after SRL is set to "1".

"Enable Bits Changed" interruption is SPEDE0 according to the shadow register. - It is a timing flag to update the register of SPEDE15.

9.4. Register



9.4.3.6. Status register (SPEST)

Address 01FB_8014H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W R Initial 0000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - SSUP BSYR/W R R RInitial 0000H 0B 0B

bit field

No name Explanation

0 BSY Busy flag of sprite engine 1:SPE is busy. 0:SPE is in the state of the idol.

1 SSUP The attribute of special sprite indicates the period updated in SPE. 1:It is updated. 0:It is not updated.

9.4.3.7. Interrupt Line register (SPEILN)

Address 01FB_8018H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - ILIN[11:0] R/W R/W R/W Initial 0H 000H

bit field

No name Explanation

11-0 ILIN[11:0] Interruption line number(0 - 4095)

9.4. Register



9.4.3.8. Sprite Display Number (SPESDN)

Address 01FB_801CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - ESN[8:0] R/W R/W R/W Initial 00H 000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - BSN[8:0] R/W R/W R/W Initial 00H 000H

bit field

No name Explanation

8-0 BSN[8:0] Starting address of SPECTL.PRI=1:SPT(32 bit word address and 0 511-) Display..begin..sprite..number.(SPR0 - SPR511)

24-16 ESN[8:0] Ending address of SPECTL.PRI=1:SPT(32 bit word address and 0 511-) Display..end..sprite..number.(SPR0 - SPR511)

Notes:

When the SPECTL register is set, this register has a different function. Please set a value that is bigger than BSN to ESN. This register is a shadow register. The shadow register is loaded according to the timing of the

following VSYNC.

9.4. Register



9.4.3.9. Sprite Display Enable Table Clear register (SPEDETC)

Address 01FB_8020H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - ESN[8:0] R/W R/W R/W Initial 00H 000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GO DEV - BSN[8:0] R/W R/W R/W R/W R/W Initial 0B 0B 00H 000H

bit field

No name Explanation

8-0 BSN[8:0] Beginning sprite number(SPR0 - SPR511)

14 DEV Clear value of SDET(SpriteDisplayEnableTable) 1:It displays it. 0:It doesn't display it.

15 GO The clearness of SDET(SpriteDisplayEnableTable) starts. 1:Execution. (After it executes it, this bit changes automatically to 0. ) 0:There is no operation.

24-16 ESN[8:0] End sprite number(SPR0 - SPR511)


following VSYNC.

9.4.3.10. Display Area register (SPEDPAR)

Address 01FB_8024H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - DPWD[10:0] R/W R/W R/W Initial 00H 000H

bit field

No name Explanation

10-0 DPWD[10:0] (1 - 80) ×16 pixel in display width DPWD 3:0 is fixed to "0".

9.4. Register



9.4.3.11. Pattern Memory Base Address, SPEPBA

Address 01FB_8028H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - PBA[7:0] R/W R/W R/W Initial 00H 00H

bit field

No name Explanation

7-0 PBA Base address of pattern data: PBA 7:0 ×16MB.

9.4.3.12. Resource FIFO Enable register (SPERSC)

Address 01FB_802CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - SPTE SATE LUTER/W R/W R/W R/W R/WInitial 0000H 0B 0B 0B

bit field

No name Explanation

0 LUTE Resource FIFO of LUT setting 1:Effective 0:Invalidity

1 SATE Resource FIFO of SAT setting 1:Effective 0:Invalidity

2 SPTE Resource FIFO of SPT setting 1:Effective 0:Invalidity

Notes:

When SPE draws in the frame, resource FIFO can temporarily maintain the set up information of SPT, SAT, and LUT when the correlation register of each field is effective.

The corresponding register field is set the SPE processing overtime through resource FIFO. Only the register set up information of 512 all is maintained in resource FIFO in the SPE processing

time.

9.4. Register



9.4.3.13. SPT (Sprite Priority Table) In SPT, the programming of the display priority level of the sprite of 512 or less can be done. SPT is 512×9bit register table to set the display priority at 512 levels. When the priority level mode is only SPT mode, this table becomes effective. In SPT, the subordinate position address becomes lower priority. Please write the sprite of a high-ranking number from other sprite at a high-ranking address of SPT. A series of sprite switch function can be easily achieved by setting the register of BSN and ESN (SPESDN).

Figure9-2Structure of SPT

SPESPRI0SPESPRI1SPESPRI2SPESPRI3

9bit

01FB_9000H

SPESPRI4SPESPRI5SPESPRI6SPESPRI7

... ...

SPESPRI511

AddressSprite Number

Low

High

BSN

ESN

Sprites that will be displayed on screen.

01FB_9004H

01FB_9008H

01FB_900CH

01FB_9010H

01FB_9014H

01FB_9018H

01FB_901CH

01FB_97FCH

9.4.3.13.1. Sprite Priority register (0 - 511), SPESPRI (0 - 511)

Address 01FB_9000H + (n<<2)H , n=0 - 511 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - SPN[8:0] R/W R/W R/W Initial 00H X

bit field

No name Explanation

8-0 SPN[8:0] Sprite number(0 - 511)

9.4. Register



9.4.3.14. SAT (Sprite Attribute Table) In each sprite, there is an attribute register group. Therefore, the sprite attribute table of the GDC macro is composed of the group of the sprite attribute register of 512.

Table9-2Basic sprite attribute table

Name Width Attribute DY 12 Y coordinates of display region DX 12 X coordinates of display region PA 25 Pattern address that sprite uses(32 bit word address) SH 9 Y size of source pattern SW 7 X size of source pattern VR 1 Making of reversing length effective HR 1 Making of reversing side effective CF 3 Color format selection CP 10 Color palette selection CPF 2 Color palette format selection TE 1 Making of penetration effective ABM 1 Selection of alpha blend mode ATE 1 Making of alpha table effective ATS 1 Selection of alpha table AF 1 Alpha data format(Only the alpha table data of the pattern memory :. ) AV 8 Alpha blend value DE 1 Making of sprite display effective

Table9-3Special sprite attribute table

Name Width Attribute MY 8 The pixel is moved in the direction of Y. MX 8 The pixel is moved in the direction of X. YMV 3 Movement method to direction of Y XMV 3 Movement method to direction of X PAAL 1 Making of automatic loading function of pattern address effective BLINK 1 Making of blinking function effective AMV 1 Making of automatic movement function effective REPEAT 1 Repetition of action VCNT0 8 VSYNC counter 0 VCNT1/CNT1 8 VSYNC counter 1 or CNT1 CNT0 8 Execution frequency of animation function

9.4. Register



9.4.3.14.1. SDET (Sprite Display Enable Table)

This register is SPESDE0-15 (Sprite display enable) register.


Name DE[m31:m16] R/W R/W Initial 0000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DE[m15:m0] R/W R/W Initial 0000H

bit field

No Name Explanation

31-0 DE[m31:m0]

DE m31:m0 is a relation shown in the following. SPESDE0 (01FB_8100H) : DE[31:0] SPESDE1 (01FB_8104H) : DE[63:32] SPESDE2 (01FB_8108H) : DE[95::64] SPESDE3 (01FB_810CH) : DE[127:96] SPESDE4 (01FB_8110H) : DE[159:128] SPESDE5 (01FB_8114H) : DE[191:160] SPESDE6 (01FB_8118H) : DE[223:192] SPESDE7 (01FB_811CH) : DE[255:224] SPESDE8 (01FB_8120H) : DE[287:256] SPESDE9 (01FB_8124H) : DE[319:288] SPESDE10 (01FB_8128H) : DE[351:320] SPESDE11 (01FB_812CH) : DE[383:352] SPESDE12 (01FB_8130H) : DE[415:384] SPESDE13 (01FB_8134H) : DE[447:416] SPESDE14 (01FB_8138H) : DE[479:448] SPESDE15 (01FB_813CH) : DE[511:480]

Notes:

These registers are the shadow registers. The shadow register is loaded according to the timing of the following VSYNC.

A high-speed, clear function is provided in SPE. This table is set at once by setting the register of SPEDETC.

9.4. Register



9.4.3.14.2. Sprite Configuration Register0 (SPES (0 - 511) CR0)

Address 01FB_A000H + (n*3<<2)H , n=0 - 511 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AF TE CPF[1:0]Name CF[2:0]

FCF[1:0] FAF[1:0]PA[24:16]

R/W R/W R/W R/W R/W R/W R/W Initial X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PA[15:0] R/W R/W Initial X

bit field

No name Explanation

24-0 PA[24:0] Pattern data addresses except single color sprite format(32 bit word address) When sprite is single color sprite, PA 23:0 is used as 24 bit color.

26-25 FAF[1:0]

Setting of permeability of font mode sprite(Only the font mode is effective. ) 00B: 1 (There is no penetration. ) 01B: 1/2 10B: 1/4 11B: 1/8

26-25 CPF[1:0]

Color palette format 00B : 32bpp (ARGB8888) 01B : 16bpp (ARGB4444) 10B : 16bpp (RGB565) 11B : 16bpp (ARGB1555)

28-27 FCF[1:0]

Color format of font mode sprite(Only the font mode is effective. ) 00B: One bit 01B: Two bits 10B: Four bits 11B: Eight bits

27 TE Making of penetration effective 0:Invalidity 1:Effective(The pixel of the defined transparent color is not displayed. )

28 AF Alpha data format(Only the alpha table of the pattern memory :. ) 0:4 bits 1:8 bits

31-29 CF[2:0]

Color format 000B:1 bit 001B:2 bit 010B:4 bit 011B:8 bit 100B:16 bit(RGB565) 101B:16 bit(ARGB1555) 110B:32 bit(ARGB8888) 111B: Single color sprite (rectangular drawing) and 24 bits(RGB888) Notes: It becomes font mode sprite for CF=111B and ATE=1.

9.4. Register





CP[7:0] AV[7:0] Name

FCV[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name SW[6:0] SH[8:0] R/W R/W R/W Initial X X

bit field

No name Explanation

8-0 SH[8:0] Height (1 - 512) pixel of sprite:(SH+1)

15-9 SW[6:0] (1 - 128) ×4 pixel in sprite width: (SW+1) ×4

31-16 FCV[15:0]

Setting of color value of font mode sprite(Only the font mode is effective. ) Only 16 bit RGB565 format is supported. FCV[15:11]: Red FCV[10: 5]: Green FCV[4:0]: Blue

23-16 AV[7:0] Alpha value of sprite

31-24 CP[7:0] Selection of color palette (address of LUT indirect color mode): Seven bits-0 bits

9.4. Register





Name VR CP[9:8] - DY[11:0] R/W R/W R/W R/W R/W Initial X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name HR ATE ABM ATS DX[11:0] R/W R/W R/W R/W R/W R/W Initial X X X X X

bit field

No name Explanation

11-0 DX[11:0] Display X coordinates(-2048 - 2047)

12 ATS Selection of alpha table 0:Memory 1:LUT (Only an indirect color mode :. )

13 ABM Alpha blend mode 0:Alpha blend in Pre-layer where it has already been drawn 1:Alpha blend in single color(SPEABC)

14 ATE

Making of alpha table effective 0:Invalidity Alfabrendingmord of sprite 1:Effective Alfabrendingmord of pixel Notes: It becomes font mode sprite for CF=111B and ATE=1.

15 HR Sideways reversing 0:Invalidity 1:Effective

27-16 DY[11:0] Display Y coordinates(-2048 - 2047)

30-29 CP[9:8] Selection of color palette (address of LUT indirect color mode): Nine bits-eight bits

31 VR It reverses to length. 0:Invalidity 1:Effective

9.4. Register



9.4.3.14.5. Sprite Configuration Register3 (SPESS (0 - 31) CR3) (for special sprite)

Address 01FB_8200H + (n*3<<2)H , n=0 - 31 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VCNT1[7:0] Name

CNT1[7:0] VCNT0[7:0]

R/W R/W R/W Initial 00H 00H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PAAL BLINK AMV REPEAT - CNT0[7:0] R/W R/W R/W R/W R/W R/W R/W Initial 0B 0B 0B 0B 0H 00H

bit field

No name Explanation

7-0 CNT0 Frequency from which automatic animation function is executed(1 - 256) TIMES = CNT0 + 1

12 REPEAT Automatic animation is always repeated. Do not refer to the CNT0 setting. 1:Effective 0:Invalidity

13 AMV Making of automatic movement function effective 1:Effective 0:Invalidity

14 BLINK Making of blinking function effective 1:Effective 0:Invalidity

15 PAAL Making of automatic loading function of pattern address effective 1:Effective 0:Invalidity

23-16 VCNT0[7:0] VSYNC counter 0(1 - 256)

31-24 VCNT1[7:0]/ CNT1[7:0]

These bits define the parameter with a different different animation mode. VSYNC1: VSYNC Counter1 of blinking mode(1 - 256) CNT1: Definition of movement frequency in animation function mode or switch frequency of image switch mode (1 - 256)

9.4. Register





Name YMV[2:0] - MY[7:0] R/W R/W R/W R/W Initial 0H 00H 00H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name XMV[2:0] - MX[7:0] R/W R/W R/W R/W Initial 0H 00H 00H

bit field

No name Explanation

7-0 MX[7:0] Pixel where special sprite moves in direction of X(1 256- pixel)

15-13 XMV[2:0]

Move mode in direction of X Geostationary in the direction of 000B:X. 001B: Left 010B: Right 011B:Reserved 100B: Left → right → left 101B: Returning → left of left → 110B: Right → left of → right 111B: Right → is returning right of →.

23-16 MY[7:0] Pixel where special sprite moves in direction of Y(1 256- pixel)

31-29 YMV[2:0]

Move mode in direction of Y Geostationary in the direction of 000B:Y. 001B: 010B: Under 011B:Reserved 100B: → in case of →. 101B: → of return of → 110B: In case of → in → in the under 111B: In case of → where → in the under returns

Notes:

Sprite must not intersect with both X (-2048 - 2047) and Y (-2048 - 2047) sprite display regions even about an automatic move mode in which special sprite is set either.

9.4. Register





Name - ADTA[24:16] R/W R/W R/W Initial 00H 000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ADTA[15:0] R/W R/W Initial 0000H

bit field

No name Explanation

24-0 ADTA[24:0] Base address of pattern data address table(32 bit word address)

9.4.3.14.8. Special Sprite Number Specify Register (SPESSN (0 - 31)) (for special sprite)



Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - SPN[8:0] R/W R/W R/W Initial 00H 000H

bit field

No name Explanation

8-0 SPN[8:0] Sprite number(0 - 511) Special sprite N (0 - 31) is specified.

Notes:

The same value cannot be set to these registers. Please set these registers before using special sprite.

9.4. Register



9.4.3.15. LUT (Look-up Table) The LUT register is used to do writing alpha data/color data and reading from LUT. This register is specified for SPELUTS (0 - 1023), and is 000H. - The mapping is done by FFCH.

9.4.3.15.1. LUT Setting Register (0~1023), SPELUTS (0~1023)

(1) 32bit color palette mode (ARGB-8888)

Address 01FB_E000H + (n<<2)H , n=0-1023 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name AVAL[7:0] RVAL[7:0] R/W R/W R/W Initial X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GVAL[7:0] BVAL[7:0] R/W R/W R/W Initial X X

bit field

No name Explanation

7-0 BVAL[7:0] Definition of blue

15-8 GVAL[7:0] Definition of green

23-16 RVAL[7:0] Definition of red

31-24 AVAL[7:0] Specification of alpha value



Name AVAL[3:0] RVAL[3:0] GVAL[3:0] BVAL[3:0] R/W R/W R/W R/W R/W Initial X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name AVAL[3:0] RVAL[3:0] GVAL[3:0] BVAL[3:0] R/W R/W R/W R/W R/W Initial X X X X

bit field

No name Explanation









9.4. Register



(3) 16bit color palette mode (RGB-565)


Name RVAL[4:0] GVAL[5:0] BVAL[4:0] R/W R/W R/W R/W Initial X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name RVAL[4:0] GVAL[5:0] BVAL[4:0] R/W R/W R/W R/W Initial X X X

bit field

No name Explanation









Name AVAL RVAL[4:0] GVAL[4:0] BVAL[4:0] R/W R/W R/W R/W R/W Initial X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name AVAL RVAL[4:0] GVAL[4:0] BVAL[4:0] R/W R/W R/W R/W R/W Initial X X X X

bit field

No name Explanation




15 AVAL Specification of alpha value




31 AVAL Specification of alpha value





9.5.1. Outline of processing SPE is a unit of the processing of the core image of the GDC macro. The shift, reversing, Alfabrending, and other functions are provided. All these functions can be controlled by setting the correspondence register with software.

9.5.1.1. Sprite generation flow SPE mounts the scanning lines rendering hardware. In each scanning lines, SPE analyzes SAT (Sprite Attribute Table) and other registers, and detects the pixel position of sprite with the highest priority. Moreover, the result of the final color data is written in LineBuffer by reading the pattern data including the alpha value, and processing the image.




9.5.1.2. Frame generation flow

Figure9-3Outline of processing of frame

LineN

Line Processing Line Blank

Line Start

Line_blank_int(REG/SAT/LUT Refresh Enable)

Line0

vblank

FrameN

X

Frame(N+1)

vblank

Line_int(the interrupt of user definition)

Frame_blank_int(REG/SAT/LUT refresh Enable)

Frame(N+1) Confiuration

320～8000

Sprite Generation for LineN ( Alpha-Blending, Reverse)

Frame(N+2) Confiuration

Y

120～480

Line0

Please refresh SAT (Sprite Attribute Table) and other registers for the period of a vertical blank or the period of a specified line blank. However, some shadow registers can be set at any time.




9.5.2. Sprite Sprite displays the source image on the screen. Sprite can display the arbitrary pattern stored in the pattern memory. Moreover, it is processed according to the attribute of each sprite such as reversing. The position of sprite is defined from the upper left corner of the sprite pattern. The sprite of each pixel can be moved according to the setting of SAT (Sprite Attribute Table).

Figure9-4Definition of sprite

In the GDC macro, the sizes of sprite are from 4×1 pixels to 512×512 pixels. The direction of X and the direction of Y can be separately set (Four pixel step and Y are one ..X.. pixel). Figure9-4The sprite of, 4×4 pixels, and 16×8 pixels is shown.

9.5.3. Monochrome sprite(rectangular drawing) As for a monochrome 512×512 pixel rectangular figure, the sprite engine is easily generable from size 4×1. The color format is 24bpp(RGB-888). The pattern data is not necessary.

9.5.4. Font mode sprite To express the font by the small amount or more pattern data, the sprite engine provides the font mode sprite function. The font mode sprite does the alpha blend to the rhea below for the same color by the alpha value with a different each pixel, and generates a new color value. Because it is especially agreement to the achievement of the font, it is called the font mode sprite. The font mode sprite doesn't have the color value, and have only the alpha factor of the pattern data unlike usual sprite. The reference to and the color palette is not needed. "Color (alpha)" format of the font mode sprite supports 1bpp, 2bpp, 4bpp, and 8bpp.

1bpp 2bpp 4bpp 8bpp

The above-mentioned is an effect of each format of the font mode sprite of size 64×70.

Sprite (4x4)

pixel

Sprite (16 x8 )

pixel




9.5.5. Sprite number The serial number of each sprite is 0 It is fixed to 511-, and is SPR0, and is SPR1 … SPR511 and the name are applied.

9.5.6. Priority level In Spraitoraya, there is sprite of 512 or less. The position of sprite might overlap because it can freely define it anywhere. There are two of the SPT (Sprite Priority Table) modes, and the priority level of the sprite of 512 is decided a fixed mode to sprite. The mode used depends on the setting of the PRI register (Bit 1 of SPECTL).

9.5.6.1. Fixed mode In a fixed mode, the priority level of sprite is decided by the serial number (The example: 0 511-). In initialization, the priority level of each sprite is fixation. The larger the serial number is, the more the priority level rises. The higher the priority level is, the more the viewer is put to be nearer. As for each Spraitoraya, priority rises more than Baccgraundoraya.

Background < SPR0 < SPR1 <…< SPR31 <…< SPR511

Figure9-5Priority of sprite(fixed mode)

Figure9-5And four sprite displayed on the screen at the same time are shown. When they overlap mutually, the visible degree is decided by those priority levels. The color of the pixel excludes the case where it is equal to the transparent color (When the penetration function is effective), and the pixel with high priority is seen.

background

SPR 0

SPR 2

SPR1

SPR3

Image Layer Display on Screen

transparent

X

Y X

Y




9.5.6.2. SPT mode In the SPT mode, the priority level of the sprite of 512 is decided by setting not the sprite number but SPT. SPT is a register table in 512×9 bits that stores the sprite number. SPE decides the priority level according to the address of sprite. Priority lowers if the address is low. Please initialize SPT before processing of SPE when you use this mode.

Figure9-6Priority of sprite(SPT mode)

Priority

Figure9-6The priority level of the sprite at the SPT mode of is shown. The number written in SPT is "0, 3, 2, 1, …, 511" from a low address to a high address. The order of the display of sprite on the screen is "SPR0, SPR3, SPR2, SPR1, …, SPR511" from the back to the front side.




9.5.7. Display area of sprite All sprite can be displayed in the display area, and coordinates of sprite are related to coordinates of the display area. The part of sprite that exceeds the display area is not displayed on the screen. The display area is 320 in the direction of X It is 120 in 800 pixel and - direction of Y 600- pixel can be defined. Therefore, it is possible to correspond to the WVGA format in SPE.

Figure9-7Display area of sprite

Display Area

(0,0)

(XSPR0,YSPR0)

(XSPR1,YSPR1)

(XSPR2,YSPR2)

(XSPR3,YSPR3)

The display coordinates of SPRn are derived from DX and DY of SAT register SPESnCR2 (n=0 - 511). DX and DY are the addition of signs in 12 bits that can be defined up to -2048+2047 registers.




9.5.8. Pattern data format The pattern data is source image data of sprite. It is stored in the memory by a different color data format, and to raise the reading efficiency of the memory in LineBuffer, each line is arranged. Moreover, the alpha table exists in ATS (SAT) of the pattern memory if the color format of the pattern is ARGB-8888 or not ARGB-1555 when ATE (SAT) of the alpha table is effective. It is located under the pattern data as an alpha table that maintains the alpha data of all pixels of the pattern. The alpha data of each line is arranged in the memory for the pattern data. The start address of the pattern data and the alpha data table is 32 bit addresses. Please specify the base address of the pattern memory area by setting SPEPBA before processing of the access.

Figure9-8Structure of pattern memory

The color and the structure of the line data including the alpha are "Little endian. "That is, the pixel of smaller X coordinates becomes a smaller address and a bit number in the memory in the same line. Moreover, the color data or the alpha data of all pixels should be consecutive by gapless. The pattern data is unnecessary for the font mode sprite, and it becomes a composition only of the alpha table.




Figure9-9Pattern data format

Figure9-9The sprite pattern data of the memory of 8×8 pixels in the becoming it color data format of ..peel.. I is shown. In the alpha table, there are two modes of 4bpp and 8bpp, and it is decided depending on the register corresponding to SAT.




The structure of the alpha table is the same as the color value when the color of 4bpp and 8bpp is formatted. The data of the font mode color format is usually the same structure as 1bpp of sprite, 2bpp, 4bpp, and 8bpp. The data of one line queues up continuously ..the space none.. the line even when it is fewer than one word (four bytes) and between lines. For instance, the sprite of 1bpp is composed as follows.




9.5.9. Transparent color function The transparent color can be set to the color palette table. The pixel of the sprite of the transparent color is not displayed on the screen. In a color mode and a direct indirect color mode, there are different set registers (SPETP0 register and SPETP1 register). In an indirect color mode, SPETP0 register defines the transparent color of four color formats (1bpp,2bpp,4bpp,8bpp). The GDC macro supports the color format of three of RGB (565), ARGB (1555), and ARGB (8888) directly. The GDC macro decides the transparent color of each color format in the following ways.

Figure9-10Direct transparent color format of color mode

9.5.10. Background color function The background mode is BGM (SPECTL) It is set by register. In usual background mode (BGM="0"), sprite ..background color.. is displayed and the color ..no existence.. is displayed in the pixel of the screen of ..location.. ..no penetration... The background color can be set by using corresponding SPEBG register with single color 24bpp (RGB-888). Moreover, to optimize coming in succession with other layers, SPE supports another background mode in Display Controller. All transparent pixels are treated as fixed color data ("000001H") when SPE is BGM ="1" mode, and real color data ("000001H") is converted into "000000H".




9.5.11. Color palette table In SPE, color palette table (LUT_RAM) is and there is 4096 byte RAM (1024w×32bit). RAM of every 32 bit word shows two colors by 1 color of the ARGB-8888 format or 16 bit color of ARGB-4444/ ARGB-1555/ RGB565. It is composed of four palettes in 64 palettes and eight bit modes ..512 palettes and two bit modes.. ..256 palettes and four bit modes.. in one bit mode in case of ARGB-8888. It is possible to compose of the palette twice ARGB-8888 for ARGB-4444/ ARGB-1555/ RGB565. In a word, it is composed of eight palettes in 128 palettes and eight bit modes ..1024 palettes and modes by two bits.. ..512 palettes and four bit modes.. in the bit mode. The value of the color palette table can be set directly from CMDSEQ and external CPU or be forwarded from an external memory by DMAC.

Figure9-11Color palette table(ARGB-8888)

The address of RAM of the color palette that sprite uses is decided in CP 7:0 field of SPECnCR1. (n=0 - 511) of SAT register. The kind of the color palette is decided in CPF 1:0 field of SPECnCR0. (n=0 - 511) of SAT register.




Figure9-12Color palette table(ARGB-1555/RGB-565)

LUT_RAM(4096byte)

Address

+0H

+4H

CP[9:0]

CP[9:1],1'b0

2bit Mode

1bit Mode

+0H

CP[9:4],3'b0

4bit Mode

+0H

+4H

+8H

+CH

CP[9:7],7'b0

8bit Mode

+1FCH

32bit

1024Word

0781516232431

0781516232431

0781516232431

0781516232431

+4H

+8H

+CH+10H

+14H

+18H

+1CH

Color#0Color#1

Color#0Color#1Color#2Color#3


Color#4Color#5Color#6Color#7Color#8Color#9

Color#15 Color#14

Color#11 Color#10

Color#1３ Color#1２



Color#254Color#255

Address

+0H

+4H

CP[9:0]

CP[9:1],1'b0

+0H

CP[9:4],3'b0

+0H

+4H

+8H

+CH

CP[9:7],7'b0

+1FCH

0781516232431

0781516232431

0781516232431

0781516232431

+4H

+8H

+CH+10H

+14H

+18H

+1CH

Color#0Color#1



Color#4Color#5Color#6Color#7Color#8Color#9

Color#15 Color#14

Color#11 Color#10

Color#1３ Color#1２



Color#254Color#255

2bit Mode

1bit Mode

4bit Mode

8bit Mode

ARGB-1555

RGB-565




9.5.12. Reversing function SPE supports a vertical, horizontal reversing function. It is decided whether to reverse sprite when the screen is displayed according to register (HR,VR) that the sprite attribute table corresponds. A vertical, horizontal reversing function can be made effective at the same time.

Figure9-13Reversing function

(A) Original Image

(D) Vertical and Horizontal Reverse (C) Vertical Reverse

(B) Horizontal Reverse




9.5.13. Alpha blend SPE (Sprite Engine) supports the Alfabrending function. When the image data of the sprite drawing is written in LineBuffer, Alfabrending is done by image data or single color (RGB888) of sprite where it has already been drawn in the place where the register that corresponds by setting Alfabrendingmord is effective. The alpha value data is obtained from the sprite attribute table in the state of the alpha channel or Spraitoalfabrendingmord of LUT_RAM in the state of the alpha table and Picselalfabrendingmord that exists under the pattern data of the pattern memory.

Figure9-14Alfabrending function

Color Palette Table(Only Indirect Color Mode) ATE(SAT)

Alpha Table (Pattern Memory)

AV (SAT)

SPEABC

Drawn Layer

Drawing Layer

Alpha-Blending

ATS(SAT)

ABM(SAT)

alpha[7:0]

R[7:0],G[7:0],B[7:0]

R[7:0]=(R1[7:0]*(255-alpha[7:0])+R2[7:0]*alpha[7:0])/255G[7:0]=(G1[7:0]*(255-alpha[7:0])+G2[7:0]*alpha[7:0])/255B[7:0]=(B1[7:0]*(255-alpha[7:0])+B2[7:0]*alpha[7:0])/255

R,G,B

R,G,B

R2,G2,B2

R1,G1,B1

0

1

0

1

0

1

When alpha 7:0 is "00H" according to the calculation type, only the lower layer (single color or drawing layer) remains in the result of the blending. In a word, the drawing layer becomes transparent. When the alpha value is "FfH", the drawing layer is not transparent.




9.5.14. Special sprite In the GDC macro, there is special sprite of 32. SPESSN0 - The sprite of all 512 can be defined as special sprite by setting the register of SPESSN31. It is possible to use it for these sprite to blink, and to achieve a lot of 2D animation functions of an automatic movement and the image change, etc. by the automatic operation. All these functions are SPESS (0 - 31) CR3 and SPESS (0 - 31) CR4 and SPESS (0 - 31) It is controlled by the register of CR5. The blinking function cannot be used with special sprite simultaneously ..the movement function and the image change function... However, an automatic movement and the image change function can be executed at the same time.

9.5.14.1. Blinking function The blinking function of special sprite is executed by controlling the time of the display and non-display of sprite. The display period sets VCNT0 (SPESSnCR3) and non-display period by VCNT1 (SPESSnCR3), and uses the bit of BLINK (SPESSnCR3) for make to effective/nullification of this function. Moreover, the execution frequency of the blinking function is set with CNT0 (SPESSnCR3). Please set the initial state (display/non-display) by setting SDET before the blinking function of special sprite is used.

Figure9-15Blinking function

SPR0 SPR0

M frame

N frame

InvisibleVisible

VCNT0

VCNT1




9.5.14.2. Automatic movement function Special sprite supports a lot of movement methods. Corresponding SPESS (0 - 31) Not only a right and left and a simple movement by setting the register of CR4 up and down but a complex movement is executable. The interval of each movement of time is set by the register of VCNT0 (SPESSnCR3). One movement of an automatic move mode and all pixels can separately set the direction of X and the direction of Y. The movement of the pixel in the direction of X is set by the register of MX (SPESSnCR4), and the movement of the pixel in the direction of Y is set by the register of MY (SPESSnCR4). Both 1 It is possible to set it between -256 pixels. An automatic move mode in the direction of X is set by the register of XMV (SPESSnCR4), and an automatic move mode in the direction of Y is set by the register of YMV (SPESSnCR4). Automatic..move mode..register..setting..sprite..a series of..move..frequency..show.However, an actual frequency necessary for the movement of sprite is different according to the setting of an automatic move mode.

Figure9-16Basic movement of direction of X




Figure9-17Basic movement of direction of Y

Figure9-16 と Figure9-17A basic movement method in the direction of X and the direction of Y of and special sprite is shown. In this mode, sprite moves times of n (n=CNT1+1) in a certain specific direction (automatic movement unit).

Figure9-18Specific movement of direction of X




Figure9-19Specific movement of direction of Y

Figure9-18 と Figure9-19Two specific movement methods in the direction of X and the direction of Y of and special sprite are shown. Both laws and sprite are moved in time of n (n=CNT1+1), and it returns to former position. It is as for. times nTherefore, it is called STR (Single Time Return) and NTR (N Times Return). Moreover, the automatic movement unit of two methods is different from times and 2n times of (n+1). The automatic movement method of matching two can correspond because the automatic movement method can separately set the direction of X and the direction of Y. Some examples are shown as follows. In each combination, the automatic movement unit is different.

Figure9-20Movement that combines direction of X in direction of Y(1)

Figure9-20, direction STR of Y, direction STR of X, and the automatic movement unit show the method of moving times of n+1.





Figure9-21, direction NTR of Y, direction NTR of X, and the automatic movement unit show the method of moving 2n times.


Figure9-22, movement of the direction of X in a single direction, direction NTR of Y, and the automatic movement unit show the method of moving 2n times.





Figure9-23, movement of the direction of X in a single direction, direction STR of Y, and the automatic movement unit show the method of moving times of n+1.


Figure9-24The method of moving, direction STR of X, and direction NTR of Y(movement method of the special compound) is shown. The automatic movement unit is 2n+1 times. Please note that the same Y coordinates are used about 2n+1 and 2n at the sprite position.




9.5.14.3. Image switch function When PAAL is set to "1", special sprite can automatically load the following pattern data address from the address table of the pattern memory. The starting address of the address table that special sprite uses is ADTA (SPESSnCR5) It sets it by register. The interval of the image switch of time is VCNT0 (SPESSnCR3) It sets it with register. Moreover, the series image number that special sprite uses is CNT1 (SPESSnCR3) It sets by register, and the execution frequency of the function is CNT0 (SPESSnCR3) It sets it with register. When the single-unit image switch function execution end is done, it becomes the image of the first address of the address table. There is no set necessity before processing frame 0 because of being automatically loaded because the first image of sprite is special sprite ..PA (SPESnCR0) of sprite... When the image switch function is used by the automatic movement function of special sprite, the series image number becomes equal with the automatic movement unit. In a word, it depends on the setting of the automatic movement method.

Figure9-25Image switch function

9.6. Interrupt



9.6. Interrupt The interrupt event generated by SPE is as follows. There is a status flag corresponding to the INTST register in MCNT, and synchronization with each event can be managed.

Event For MCNT/INTST

1. ILN The line interruption: All ..the line specified with SPEILN.. the processing of sprite ends.

INT19 (bit19)

2. LBK Each the interruption at the line blank: The processing of all sprite in the line ends.

INT18 (bit18)

3. PER Processing error interruption: Processing error generation

INT17 (bit17)

4. BER The bus error interruption: The bus error responds when the pattern data is led with an internal bus.

INT16 (bit16)

5. EBC “Enable bits change" interruption: Automatic update completion of ShadowRegister.

INT15 (bit15)

9.7. Notes

9.7.1. Limitations The blinking function cannot be used with special sprite simultaneously ..the movement function and the image switch function... Please update an enable display for a vertical, synchronous period when you do not output the display signal when the sprite display function is used. (Refer to Chapter 2.9.3. )

10.1. Outline


Graphics Memory (VRAM) FUJITSU SEMICONDUCTOR CONFIDENTIAL 243

10. Graphics Memory (VRAM) This chapter explains the graphics memory of the GDC macro.

10.1. Outline RAM of 800K Byte is built into graphics memory (VRAM). Composition

10.1.1. Block diagram Figure10-1VRAM and a peripheral block diagram are shown.

Figure10-1VRAM and peripheral block diagram


MB91590 Series

GDC Macro

ADCNTSC

decoder

CaptureController

Video dataprocessor


SpriteEngine


DRiDGiDBi

GD

C L

ocal

Bus

DrawEngine



GD

C A

HB

Bus

Analog NTSC

Digital RGBor

ITU-R BT656

Note:

Analog NTSC corresponds to external terminal VIN. Digital RGB corresponds to external terminal PA2-PA7, PB2-PB7, and PC2-PC7. ITU-R.BT656 corresponds to external terminal PA2-PA7, PB2, and PB3. CSYNC corresponds to external terminal PG3. DCLKO corresponds to external terminal PG4. VSYNC corresponds to external terminal PG5. HSYNC corresponds to external terminal PG6. DE corresponds to external terminal PG7. DRi corresponds to external terminal P011, P012, and PD2-PD7. DGi corresponds to external terminal P013, P014, and PE2-PE7. DGi corresponds to external terminal P015, P016, and PF2-PF7.





10.2.1. Memory composition

The graphics memory is used to do the display management using Draw Engine, Display Controller, and Capture Controller. It explains the composition of the graphics memory as follows.

10.2.1.1. Drawing frame

It is an image data area of 2D rectangle to draw. It is also possible that the drawing frame displays the part by being able to use the plural and using a drawing frame that is bigger than the display frame. X resolution is set in the drawing frame within the range of the capacity of the graphics memory, and 4096 pixels or less and Y resolutions can be set and even 4096 pixels or less be set. The data form uses the color (16 bits/pixel) directly an indirect color (eight bits/pixel).

10.2.1.2. Display frame It is an image data area of the display rectangular to do. Four screens or less can be overlapped and the graphics can be displayed. Moreover, one layer can be used as a coefficient side of the alpha blend.

10.2.2. Kind of data

Draw Engine treats the following data. The display list in this is Command. It is also possible to arrange it in RAM. It is also possible that a texture Thai ring pattern uses and sets the display list. When signature is calculated, the programmable mask window permits the exclusion of the reception pixel. Display list buffer

It is a series of command and a parameter for Draw Engine to process it.




10.2.3. Data format

10.2.3.1. Direct color(16 bits/pixel)

It is a data format expressed in five RGB bits for each. Bit15 is used as an alpha bit when translucent of the layer is displayed. Please give bit15 to me for other layers as "0".

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A R G B

10.2.3.2. Indirect color(eight bits/pixel)

It is a color index code of the look-up table (palette).

7 6 5 4 3 2 1 0

Color Code

10.2.3.3. Video image data

At 4:2:2 It is stored in the memory by the YCbCr form by 16 bits a pixel.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Y0 Cb

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Y1 Cr It is stored in the memory by the RGB666 form by 24 bits a pixel. Data in the memory reaches and because the aryne is done by 32 bits, eight high rank bits of bit31-bit24 reach an irregular value.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

G B

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved R




10.2.3.4. Direct color(24 bits/pixel)

It is a data format expressed in eight RGB bits for each. Bit31 is used as an alpha bit when translucent of the layer is displayed. The drawing function of 24 bits/pixel color mode is not installed, and ..graphics memory with CPU.. draw directly with the write etc. , please.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

G B

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

A Reserved R




10.2.4. Frame control

10.2.4.1. Single buffer

The whole of the drawing frame or the part is made a display frame. The screen can be scrolled by moving every frame at the position of the display frame. When the display frame exceeds the boundary of the drawing frame, it displays it assuming that the top and bottom and the right and left on the drawing side are consecutive. The image data can be influencing transmitted to the display for king Blanc period.

10.2.4.2. Double buffer

Two drawing frames are made, the drawing processing is done to the other frame, and the other frame is displayed. The animation that doesn't flicker can be displayed by alternately switching this display frame and the drawing frame every one frame. The display frame is switched for king Blanc period. There is a mode that the mode and the user who switches every frame are controlled and switched.

11.1. Outline


Command Sequencer (CMDSEQ) FUJITSU SEMICONDUCTOR CONFIDENTIAL 248

11. Command Sequencer (CMDSEQ)

11.1. Outline Command Sequencer (following CMDSEQ) interprets the command list in the specified area, and processes the sequence. This module can be started by the reset release, the trigger signal, and the register setting.

11.2. Feature The following can operate by processing an original command list. Wait processing of data writing

register or memory to register or memory by signal that expected value comparison specification is done

As for this module, the method of starting the following is possible. Start by start register setting by reset release according to start trigger signal

It is possible to cancel while processing the command list. The processing of the command list is ended by detecting the following error. Error of access of

disagreement slave module of expected value by COMPREG and COMPREG2 command Interrupt to various processing can be notified to the IRPR6H register of FR81S via Module

Controller (following MCNT). This module can access only the address area in the GDC macro. Please set the address area in the

GDC macro when you process the command list.

11.3. Composition



11.3. Composition

Figure11-1CMDSEQ block chart

Note:PG0(CMDTRG) is an external input signal.

11.4. Register



11.4. Register

11.4.1. Description form of register The register of the endian this module corresponds to the little endian. Please add Bass Address(0040_0000H) when Base addressFR81S(CPU) accesses it. The bit number of the Bit register is shown. The bit field name of the Name register is shown. Reserved is shown by "-". The attribute of read/write of the R/W each bit field is shown. R0: The read value is always "0. "R1:

The read value is always "1. "Please do W0 "0" in the write. When "1" is done in the write, the operation guarantee is not done. Please do W1 "1" in the write. When "0" is done in the write, the operation guarantee is not done. The value of each bit field immediately after R: ReadW: WriteInitial value reset is indicated. It becomes 0"0". It becomes one "1". X: It is irregular.


Address Register Name Description 01FB_7000H Status CMDSEQ status register 01FB_7004H Status enable Enable/Disable of CMDSEQ interrupt signal 01FB_7008H Start Start of CMDSEQ 01FB_700CH CMDSEQ IDLE status Status confirmation of IDLE. 01FB_7010H REGISTER start address Addressing of register start setting 01FB_7014H Forced termination Forced termination 01FB_7018H TRIGGER start enable Enable/Disable TRIGGER start signal 01FB_701CH Transfer status1 Execution status of various starts 01FB_7020H Transfer status2 Value of header part 01FB_7024H Transfer status3 Value of the first address or base address 01FB_7028H COMPREG error address hold The address of comparison error is held. 01FB_702CH Slave access error address hold The address of slave access error address is held

11.4. Register




11.4.3.1. Status register

Address 01FB_7000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - BLANE CMDR CMDE -

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R/W1 R/W1 R/W1 R0Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name REGI TRIGI PRI3I RSTI ENDE WAITE EXTF EXTNB CMPE SERR FTERM REG TRIG PRI3 TWDP1 RESET

R/W R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

This register shows the status of this module. Information on each bit (RESET,TWDP1,PRI3,TRIG,REG,FTERM,SERR,CMPE,EXTNB,EXTF,WAITE,ENDE,RSTI,PRI3I,TRIGI,REGI,CMDE, CMDR,BLANE) logical harmonizes, and is output to the INTST register of MCNT as CMDSEQ interrupt signal by making the bit to which this register corresponds effective with Status enable register. Bit0 RESET(RESET start)

When reset starts, this bit displays "1" by the following either factor. The BOOT bit of GDCCR register (0000_0F65H) is "1. " The data value that the BOOT bit of GDCCR register (0000_0F65H) was set to "0" and

0200_0000H (Reference Address Area) was FFFF_FFFFH. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error

Please set the RESETE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit1 TWDP1(Trigger start by Priority1 signal)

When the trigger by signal (TRG_PRI1) of Priority1 starts, this bit displays "1" by the following factor.

The data value set to 0200_0004H (Reference Address Area) was FFFF_FFFFH. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error

Please set the TWDTSE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt.

11.4. Register



Bit2 PRI3(trigger start by PRIority3 signal)

When the trigger by signal (TRG_PRI2) of Priority3 starts, this bit displays "1" by the following factor.

The data value set to 0200_0008H (Reference Address Area) was FFFF_FFFFH. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error

Please set the PRI3E bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit3 TRIG(trigger start by various TRIGger)

When the trigger with various triggers (TRIGGER0-14) starts, this bit displays "1" by the following factor.

The data value set to 0200_000CH ?0200_005CH (Reference Address Area) was FFFF_FFFFH.

Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error

Please set the TRIGE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit4 REG(REGister start interrupt)

When the register starts, this bit displays "1" by the following factor. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error

Please set the REGE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit5 FTERM(Forced TERMination interrupt)

When the FTERM bit of Forced termination register is set to "1", this bit displays "1". Please set the FTERME bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".


11.4. Register



Bit6 SERR(module Slave access ERRor interrupt)

When the error reply is received from the slave module that this module accesses, this bit displays "1". Please set the SERRE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit7 CMPE(CoMParison Error interrupt)

This bit displays "1" when there is a disagreement of the expected value comparison when COMPREG or the COMPREG2 command list is being processed. Please set the CMPEE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit8 EXTNB(EXT_NonBoot interrupt)

At "1" the BOOT bit of GDCCR register (0000_0F65H), this bit shows "1" when reset starts. Please set the EXTNBE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit9 EXTF(the data of EXTernal Flash-if are all "F")

This bit displays "1" by the following factor. The data value that the BOOT bit of GDCCR register (0000_0F65H) was set to "0" and

0200_0000H (Reference Address Area) when reset started was All "F. " 0200_0004H accessed when the trigger started ~ The data value set to 0200_0044H

(Reference Address Area) was All "F. " Please set the EXTFE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit10 WAITE(WAIT trigger Error interrupt)

When the signal of invalid WAIT Trigger in the WAITEN14 bit or the WAITEN15 bit of command list or GDCTRGR register (0000_0F66H) of WAIT9 is selected by the command list, this bit shows "1". Please set the WAITE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".


11.4. Register



Bit11 ENDE(END command Error)

When the END command is not All "F", this bit displays "1". Please confirm whether there is problem in the processed command list when "1" is displayed in this bit. Please set the ENDEE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit12 RSTI(ReSeT start Interrupt)

When there is high start demand (TRG_PRI1) of the priority level while reset of Priority2 is starting, and the reset start is canceled, this bit shows "1". Please set the RSTIE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit13 PRI3I(PRIority3 signal start Interrupt)

When there is high start demand (TRG_PRI1) of the priority level while the trigger of Priority3 (TRG_PRI2) is starting, and the trigger start of Priority3 is canceled, this bit shows "1". Please set the PRI3IE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit14 TRIGI(various TRIGger start Interrupt)

When there is a high start demand of the priority level (trigger start by TRG_PRI1 or TRG_PRI2) while the trigger of Priority4(TRIGGER0-14) is starting, and the trigger start of Priority4 is canceled, this bit shows "1". Please set the TRIGIE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit15 REGI(REGister start Interrupt)

When there is a high start demand of the priority level (trigger start) while the register of Priority5 is starting, and the register start is canceled, this bit shows "1". Please set the REGIE bit of Status enable register to "1" to add information on this bit to the interrupt factor. This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit17 CMDE(CMDseq Error)

When the state that this inside of the module doesn't anticipate is generated, this bit becomes "1". The operation guarantee when this bit about becomes "1" cannot be done. Please start again after confirming this module is when this bit becomes "1" in the state of IDLE. This bit is cleared by writing "1".


11.4. Register



Bit18 CMDR(CMDseq individual Reset completion)

Reset is issued only to this module by the automatic operation when judged that the state that this inside of the module doesn't anticipate by the noise generation etc. is generated, and the self-restoration is impossible. When this module is reset by the automatic operation, and initialized, this bit becomes "1". When this bit becomes "1", it is not possible to guarantee to operation immediately before. Please initialize it again when this bit becomes "1". This bit is cleared by writing "1".

0: Interrupt none 1: There is interrupt. Bit19 BLANE(Byte LANE of compreg2 was all "0")

At All "0" Byte lane of the COMPREG2 command, this bit becomes "1". Byte lane of the COMPREG2 command must confirm it is unquestionable in All "0". This bit is cleared by writing "1".


11.4. Register



11.4.3.2. Status enable register

Address 01FB_7004H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - BLANEE CMDRE CMDEE -

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R/W R/W R/W R/W R0Initial 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name REGIE TRIGIE PRI3IE RSTIE ENDEE WAITEE EXTFE EXTNBE CMPEE SERRE FTERME REGE TRIGE PRI3E TWDP1E RESETE

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1

This register controls information on the bit to which Status register corresponds on whether output it as an interrupt signal. Bit information to which Status register corresponds logical harmonizes, and is output to MCNT as CMDSEQ interrupt signal. Bit0 RESETE(RESET start interrupt Enable)

Information on the RESET bit of Status register is output as an interrupt signal by writing "1" in this bit. Information on the RESET bit of Status register is not output as an interrupt signal by writing "0" in this bit.

0: Information on the RESET bit is invalid. 1: Information on the RESET bit is effective. Bit1 TWDTSE( interrupt enable of Trigger start by Priority1 signal)

Information in the TWDP1 bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information in the TWDP1 bit of Status register as an interrupt signal by writing "0".

0: Information on the TWDTS bit is invalid. 1: Information on the TWDTS bit is effective. Bit2 PRI3E(interrupt enable of trigger start by PRIority3 signal)

Information in the PRI3 bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information in the PRI3 bit of Status register as an interrupt signal by writing "0".

0: Information in the PRI3 bit is invalid. 1: Information in the PRI3 bit is effective. Bit3 TRIGE(interrupt enable of trigger start by various TRIGger)

Information on the TRIG bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the TRIG bit of Status register as an interrupt signal by writing "0".

0: Information on the TRIG bit is invalid. 1: Information on the TRIG bit is effective.

11.4. Register



Bit4 REGE(REGister start interrupt Enable)

Information on the REG bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the REG bit of Status register as an interrupt signal by writing "0".

0: Information on the REG bit is invalid. 1: Information on the REG bit is effective. Bit5 FTERME(Forced TERMination interrupt Enable)

Information on the FTERM bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the FTERM bit of Status register as an interrupt signal by writing "0".

0: Information on the FTERM bit is invalid. 1: Information on the FTERM bit is effective. Bit6 SERRE(module Slave access ERRor interrupt Enable)

Information on the SERR bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the SERR bit of Status register as an interrupt signal by writing "0".

0: Information on the SERR bit is invalid. 1: Information on the SERR bit is effective. Bit7 CMPEE(CoMParison Error interrupt Enable)

Information on the CMPE bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the CMPE bit of Status register as an interrupt signal by writing "0".

0: Information on the CMPE bit is invalid. 1: Information on the CMPE bit is effective. Bit8 EXTNBE(EXT_NonBoot interrupt Enable)

Information on the EXTNB bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the EXTNB bit of Status register as an interrupt signal by writing "0".

0: Information on the EXTNB bit is invalid. 1: Information on the EXTNB bit is effective. Bit9 EXTFE(the data of EXTenal Flash-if are all "F" Enable)

Information on the EXTF bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the EXTF bit of Status register as an interrupt signal by writing "0".

0: Information on the EXTF bit is invalid. 1: Information on the EXTF bit is effective. Bit10 WAITEE(WAIT trigger Error interrupt Enable)

Information on the WAITE bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the WAITE bit of Status register as an interrupt signal by writing "0".

0: Information on the WAITE bit is invalid. 1: Information on the WAITE bit is effective.

11.4. Register



Bit11 ENDEE(END command Error interrupt Enable)

Information on the ENDE bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the ENDE bit of Status register as an interrupt signal by writing "0".

0: Information on the ENDE bit is invalid. 1: Information on the ENDE bit is effective. Bit12 RSTIE(ReSeT start Interrupt Enable)

Information on the RSTI bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the RSTI bit of Status register as an interrupt signal by writing "0".

0: Information on the RSTI bit is invalid. 1: Information on the RSTI bit is effective. Bit13 PRI3IE(PRIority3 signal start Interrupt Enable)

Information on the PRI3I bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the PRI3I bit of Status register as an interrupt signal by writing "0".

0: Information on the PRI3I bit is invalid. 1: Information on the PRI3I bit is effective. Bit14 TRIGIE(various TRIGger start Interrupt Enable)

Information on the TRIGI bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the TRIGI bit of Status register as an interrupt signal by writing "0".

0: Information on the TRIGI bit is invalid. 1: Information on the TRIGI bit is effective. Bit15 REGIE(REGister start Interrupt Enable)

Information on the REGI bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the REGI bit of Status register as an interrupt signal by writing "0".

0: Information on the REGI bit is invalid. 1: Information on the REGI bit is effective. Bit17 CMDEE(CMDseq Error Enable)

Information on the CMDE bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the CMDE bit of Status register as an interrupt signal by writing "0".

0: Information on the CMDEE bit is invalid. 1: Information on the CMDEE bit is effective. Bit18 CMDRE(CMDseq individual Reset completion Enable)

Information on the CMDR bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the CMDR bit of Status register as an interrupt signal by writing "0".

0: Information on the CMDR bit is invalid. 1: Information on the CMDR bit is effective.

11.4. Register



Bit19 BLANEE(Byte LANE of compreg2 was all "0" Enable)

Information on the BLANE bit of Status register is output as an interrupt signal by writing "1" in this bit. This bit doesn't output information on the BLANE bit of Status register as an interrupt signal by writing "0".

0: Information on the BLANE bit is invalid. 1: Information on the BLANE bit is effective.

11.4. Register



11.4.3.3. Start register

Address 01FB_7008H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name -

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - START

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R/W1Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

As for this register, the beginning setting of the register start is possible. Bit0 START(register START)

When "1" is set to this bit, this module begins the processing of the command list on the register start. Even if this register is set again while processing the register start, it is disregarded. This bit automatically sets "0" according to the following either factor.

The END command is executed while the register is starting. Interrupt by the trigger start (Depended on Priority1 or Priority3 or Priority4) became

effective, and the register start was canceled. Detection of slave module access error Expected value error generation Execution of forced ending

Please set the REGADR bit of REGISTER start address register before setting this bit to "1". 0: No processing end of demand of processing by register start 1: Processing by the register start is executed, waited or is being executed.

11.4. Register



11.4.3.4. CMDSEQ IDLE status register

Address 01FB_700CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name -

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - IDLER/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

This register shows whether this module is IDLE. As for this register, only the read is possible. Bit0 IDLE(state of IDLE)

When this module is IDLE, this bit becomes "0". When it doesn't start by various starts (reset start, trigger start, and register start), this module becomes IDLE. As for this bit, only the read is possible.

0: State of IDLE 1: State of WORK

11.4. Register



11.4.3.5. REGISTER start address register

Address 01FB_7010H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name REGADR[31:16]

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name REGADR[15:0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R0 R0Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

The address setting to execute the register start according to this register is possible. Bit31-0 REGADR(REGister start ADdRess)

When the address for the register start to begin is specified, this bit is used. In reading the command list, two subordinate position bits of this register are "0" fixation only because of the word access. This bit cannot be rewritten while the START bit of Start register is being set to "1". After the register start is processed, the setting of this bit is not cleared.

11.4. Register



11.4.3.6. Forced termination register

Address 01FB_7014H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name -

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - FCTERM

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R/W1Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

When the command list is processing it, this register can set the forced ending. Bit0 FCTERM(ForCed TERMination)

After ending the command list executing it now, this module ends processing if "1" is set to this bit. After the forced ending is executed, this bit is automatically set to "0".

0: The forced ending is not demanded or the forced ending is completed.

R 1: It is canceling.

0: Don't care

W 1: Forced ending execution

11.4. Register



11.4.3.7. TRIGGER start enable register

Address 01FB_7018H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - TSET

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - PRI3ET PRI1ET -

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R/W R/W R0Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

This register makes each signal of Priority1 of the trigger start, Priority3, and Priority4 effective. Bit1 PRI1ET(PRIority1 trigger start Enable by TRG_PRI1)

When standing up of TRG_PRI1 is detected, this module starts the trigger by making this bit effective. After the start of Priority1 by TRG_PRI1 ends, this bit is not cleared.

0: The trigger start by TRG_PRI1 is invalid. 1: The trigger start by TRG_PRI1 is effective. Bit2 PRI3ET(PRIority3 trigger start Enable by TRG_PRI2)

When standing up of TRG_PRI2 is detected, this module starts the trigger by making this bit effective. After the trigger start in Priority3 ends, this bit is not cleared.

0: The trigger start by TRG_PRI2 is invalid. 1: The trigger start by TRG_PRI2 is effective.

Bit19-16 TSET(Trigger Start Enable by TRIGGER0-14)

Effective of this bit only by one is signal of Priority4 in the trigger start from among TRIGGER0-14. When standing up of the selected trigger signal is detected, this module starts the trigger by making this bit effective. After the trigger start in Priority4 ends, this bit is not cleared. Please set this bit after the start completion interrupt outputs it when you want to change this bit while the trigger in Priority4 is starting.

0: The signal of Priority4 is invalid. 1: TRIGGER0 is effective in the signal of Priority4. 2: TRIGGER1 is effective in the signal of Priority4. 3: TRIGGER2 is effective in the signal of Priority4. 4: TRIGGER3 is effective in the signal of Priority4. 5: TRIGGER4 is effective in the signal of Priority4. 6: TRIGGER5 is effective in the signal of Priority4. 7: TRIGGER6 is effective in the signal of Priority4. 8: TRIGGER7 is effective in the signal of Priority4. 9: TRIGGER8 is effective in the signal of Priority4. 10: TRIGGER9 is effective in the signal of Priority4. 11: TRIGGER10 is effective in the signal of Priority4. 12: TRIGGER11 is effective in the signal of Priority4. 13: TRIGGER12 is effective in the signal of Priority4. 14: TRIGGER13 is effective in the signal of Priority4. 15: TRIGGER14 is effective in the signal of Priority4.

11.4. Register



11.4.3.8. Transfer status register1 (Confirmation of start)

Address 01FB_701CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name -

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - REGS TTRIG TPRI3 WDTP1 RESETS

R/W R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

This register shows whether processing by which start of various starts is done. When this register is All "0", this module becomes IDLE. Bit0 RESETS(RESET Status)

Whether the reset start is done by this bit can be confirmed. As for this bit, only the read is possible.

0: Reset unstart 1: Reset is starting. Bit1 WDTP1(trigger start by TRG_PRI1)

Whether the trigger start on which TRG_PRI1 depends by this bit is done can be confirmed. As for this bit, only the read is possible.

0: Trigger unstart by TRG_PRI1 1: The trigger by TRG_PRI1 is starting. Bit2 TPRI3(Trigger start by TRG_PRI2)

Whether the trigger start by TRG_PRI2 is done by this bit can be confirmed. As for this bit, only the read is possible.

0: Trigger unstart by TRG_PRI2 1: The trigger by TRG_PRI2 is starting. Bit3 TTRIG(Trigger start by TRIGGER0-14)

Whether the trigger start by TRIGGER0-14 is done by this bit can be confirmed. As for this bit, only the read is possible.

0: Trigger unstart by TRIGGER0-14 1: The trigger by TRIGGER0-14 is starting. Bit4 REGS(REGister Status)

Whether the register start is done by this bit can be confirmed. As for this bit, only the read is possible.

0: Register unstart 1: The register is starting.

11.4. Register



11.4.3.9. Transfer status register2(Command Header part value)

Address 01FB_7020H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CMDLIST[31:16]

R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CMDLIST[15:0]

R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

This register can confirm the value of the header part of the command list executed now. Bit31-0 CMDLIST(CoMmanD LIST header part value)

This bit can confirm the value of the header part. This bit can be cleared to an initial value only by reset (The GRST bit of GDCCR register (0000_0F65H) is "1"). As for this bit, only the read is possible.

11.4. Register



11.4.3.10. Transfer status register3 (Access address)

Address 01FB_7024H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CMDADDR[31:16]

R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CMDADDR[15:0]


This register displays the first address or the base address set next to the header part of SETREG, OSETREG, COMPREG executed now, and the COMPREG2 command. Bit31-0 CMDADDR(CoMmanD list ADDRess)

This bit can confirm the value of a set address of the command list executed now. This bit is cleared when the executed command list ended normally or it is reset. As for this bit, only the read is possible.

11.4. Register



11.4.3.11. COMPREG error address hold register

Address 01FB_7028H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CMPEADDR[31:16]

R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CMPEADDR[15:0]


This register maintains the address the error of the expected value error by the COMPREG command ahead. Bit31-0 CMPEADDR(CoMParison Error ADDRess)

This bit maintains the address the error of the expected value error by COMPREG and the COMPREG2 command ahead. Variously starting maintains only the address where the errors happen most in the beginning in this register. This bit can be cleared to an initial value only by reset (The GRST bit of GDCCR register (0000_0F65H) is "1"). As for this bit, only the read is possible.

11.4. Register



11.4.3.12. Slave access error address hold register

Address 01FB_702CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name SEADDR[31:16]

R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name SEADDR[15:0]


This register maintains the address the error ahead when there is an error reply when the slave module is accessed. Bit31-0 SEADDR(Slave access Error ADDRess)

This bit maintains the address the error ahead when there is an error reply when the slave module is accessed. This register maintains only the address where the errors happen most in the beginning, and the address is maintained newly the error ahead when there is an error reply again after the SERR bit of Status register is cleared. This bit can be cleared to an initial value only by reset (The GRST bit of GDCCR register (0000_0F65H) is "1"). As for this bit, only the read is possible.





11.5.1. Outline of operation Here, it explains separately for processing that needs external Flash and processing that is not necessary.

11.5.1.1. Processing that needs external Flash Figure11-2One processing example using external Flash

) ..MEMC (Or, SPICNT) it after it starts.. ..doing the read access to address (Reference Address Area) where external Flash was decided.. ..(①..Led data value (Command list address) is recognized the address at the following access destination by ①, and the command list at the address is processed one by one (②). Processing that needs external Flash is shown below. Reset start Trigger start Command List Area of the trigger start can use VRAM and CMDRAM in the GDC macro besides external Flash. Notes: Reference Address Area is 0200_0000H ?. It becomes 0200_0044H. Command list address stored in Reference Address Area must use the address of the GDC memory

map. When Base Address (0040_0000H) from FR81S is added, CMDSEQ cannot normally execute Command List.

When the reset start is used, Command List Area becomes External Flash. Moreover, when NOR Flash is used, CS0 becomes Command List Area. The reset start cannot be normally executed when assuming Command List Area excluding the above-mentioned.




11.5.1.2. Processing that doesn't need external Flash Figure11-3One processing example that doesn't use external Flash

This module processes the command list at the address specified after it starts one by one (③). Processing that doesn't need external Flash is shown below. Register start




11.5.2. Various starts The method of starting this module has the reset start, the trigger start, and the register start, and has the execution method in of each. The execution trigger in various starts is shown in the following.

Reset start It starts by setting GDCCR register (0000_0F65H) Bit0 to "1". (Priority2)

Trigger start It starts when effective and enable register (TRIGGER start enable register) are effective signal

(TRG_PRI1) of Priority1. (Priority1) It starts when effective and enable register (TRIGGER start enable register) are effective signal

(TRG_PRI2) of Priority3. (Priority3) It starts when effective and an enable register are effective signal (TRIGGER0 ? TRIGGER14) of

Priority4. (Priority4) Register start It starts with Start register of this module. (Priority5) Next, it explains each start.




11.5.2.1. Reset start This start begins the processing of the command list by the reset release of the GDC macro (GDCCR register (0000_0F65H) Bit0 is set to "0"). When the BOOT mode is effective (Bit1 of GDCCR register (0000_0F65H) is "0"), the data set to 0200_0000H (Reference Address Area) through AHB Bus is led. The led data value is an address value with the command list, and this module processes the command list at the address one by one. When the BOOT mode is invalid (GDCCR register (0000_0F65H) Bit1 is "1"), this module maintains the completion notification in Status register and ends (RESET=1) and operation. Processing by this start notifies INTST register (bit0) of MCNT both then maintenance (RESET=1) Status register after it ends the completion notification. Figure11-4Outline of reset start

The output factor of the completion notification by this start is as follows. The RESET bit of Status register is set to "1" according to the following factor. The BOOT mode is invalid. (BOOT bit (Bit1) of GDCCR register (0000_0F65H) is "1". ) The data value set to 0200_0000H (Reference Address Area) is FFFF_FFFFH. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error When there is an operation demand by the start demand of Priority1 (TRG_PRI1 is "1") while processing the function, this processing is canceled, and the demand of Priority1 is accepted. After the processing of the list of all the commands by this processing is completed, other demands are accepted when there are operation demands other than Priority1 while processing the function.




11.5.2.2. Trigger start Because the trigger signal becomes effective, this start begins the processing of the command list. The kind of the trigger signal is as follows. When enable register (TRIGGER start enable register) detects standing up of signal (TRG_PRI1) of

effective and Priority1, it starts. (Priority1) When enable register (TRIGGER start enable register) detects standing up of signal (TRG_PRI2) of

effective and Priority3, it starts. (Priority3) When enable register (TRIGGER start enable register) detects standing up of signal (TRIGGER0-14)

of Priority4 to which effective and the user can arbitrarily set the signal by the register, it starts. (Priority4)

Enable should be made effective by the register of this module to assume this start to be effective before various trigger signals become effective. When enable is invalid, the trigger signal cannot be detected. The register that sets enable exists two kinds of the following, and has a different respectively function. Table11-1Trigger start enable register and function

Register name Operation when enable register is made effective TRIGGER start enable register CMDSEQ starts and processes the command list when the trigger

becomes effective. Note: When the start demand of the trigger is generated again when the start demand of the trigger is

accepted, the demand is annulled. When this start becomes effective, this module reads the data set to Reference address area of external Flash. The led data value is an address value with the command list, and this module processes the command list at the address one by one. Reference address area of external Flash accessed most in the beginning when this start becomes effective with each trigger is as follows. Table11-2Address list at external Flash access destination

External Flash access address Start factor 0200_0004H TRG_PRI1 (Priority1 signal) 0200_0008H TRG_PRI2 (Priority3 signal) 0200_000CH TRIGGER0 (Priority4 signal) 0200_0010H TRIGGER1 (Priority4 signal) 0200_0014H TRIGGER2 (Priority4 signal) 0200_0018H TRIGGER3 (Priority4 signal) 0200_001CH TRIGGER4 (Priority4 signal) 0200_0020H TRIGGER5 (Priority4 signal) 0200_0024H TRIGGER6 (Priority4 signal) 0200_0028H TRIGGER7 (Priority4 signal) 0200_002CH TRIGGER8 (Priority4 signal) 0200_0030H TRIGGER9 (Priority4 signal) 0200_0034H TRIGGER10 (Priority4 signal) 0200_0038H TRIGGER11 (Priority4 signal) 0200_003CH TRIGGER12 (Priority4 signal) 0200_0040H TRIGGER13 (Priority4 signal) 0200_0044H TRIGGER14 (Priority4 signal)

Note: Please do not set the addresses other than the GDC macro to Reference address area. This module

cannot be accessed besides the address area of the GDC macro.




The connected TRIGGER signal is as follows. Table11-3TRIGGER signal connection list

Trigger signal name Output module Trigger condition TRG_PRI1 SIG SIG error count reached interrupt TRG_PRI2 NTSC No signal detection TRIGGER0 SIG SIG error count reached interrupt TRIGGER1 Display FSYNC interrupt TRIGGER2 Display VSYNC interrupt TRIGGER3 SPE Specified line processing over TRIGGER4 SPE Line blank

TRIGGER5 RLD

Byte count achieved, AHB Slave Error, Input FIFO empty, Input FIFO full

TRIGGER6 DMAC DMAC ch0 interrupt TRIGGER7 DMAC DMAC ch1 interrupt TRIGGER8 Capture Frame sync TRIGGER9 Capture 656 stream error TRIGGER10 Draw DMA command execution TRIGGER11 Draw INT command execution TRIGGER12 GDCTRGR register in FR81s TRG12 bit(Bit0) TRIGGER13 GDCTRGR register in FR81s TRG13 bit(Bit1) TRIGGER14 External pin (PG0:CMDTRG) External trigger(*1)

Note (*1): Please input the High pulse of 160nsec or more though an external trigger of TRIGGER14

becomes detection of the rising edge. After processing by this start ends, the completion notification is maintained in Status register. The bit that shows the completion notification of Status register with the starting trigger is different. It is as follows for the bit of Status register with the starting trigger. Table11-4Correspondence of start factor and status register bit

Bit name of Status register Kind of trigger signal TWDP1 TRG_PRI1 (Priority1 signal) TPRI3 TRG_PRI2 (Priority3 signal) TRIG TRIGGER0-14 (Priority4 signal)

The output factor of the completion notification by this start is as follows. Each bit of Status register is set to "1" according to the following factor. 0200_0004H accessed when starting ~ The data value set to 0200_0044H (Reference Address Area)

was FFFF_FFFFH. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error




The trigger start example of the flow chart is shown in the following. To do the trigger start by signal (TRG_PRI1) of Priority1 effectively, an enable bit (PRI1ET bit of TRIGGER start enable register) is made effective. When signal (TRG_PRI1) of Priority1 becomes "1", the value of 0200_0004H (Reference Address Area) is led, and it recognizes the address with the command list ahead. After processing the command list one by one, this module outputs the interrupt signal when enable interrupt (TWDP1E of Status enable register) is effective. Figure11-5Trigger start flow

CMDSEQ Module or memory(Arbitrariness of user)

Trigger start signal is effective. (TRG_PRI1) CMDSEQ reads the data that

exists in 0200_0004H.

CMDSEQ reads command list.

Data of command list.

Example data 0006_0000H

Example Access address 0006_0000H


Data of command list.

CMDSEQ analyzes, and processes command list.

HOST CPU

HOST CPU makes enable bit of TRG_PRI1Effective. (PRI1ET bit of TRIGGER start enable register is set to “1”)

External Flash-IF


Command list is END command.

If interrupt enable bit (TWDP1E) is effective, interrupt signal is output.

The address where command list is stored




11.5.2.3. Register start This module executes the command list at the address set by setting start address register (REGISTER start address register). This function starts by setting start register (Start register) to "1". This start cannot be newly started until the processing of the command list ends. After processing by this start ends, the completion notification is maintained in Status register (REG=1). Figure11-6Outline of register start

The output factor of the completion notification by this start is as follows. The REG bit of Status register is set to "1" according to the following factor. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error




The flow chart of the register start is shown in the following. The command list is processed by setting the address value that there is a command list in start address register (REGISTER start address register), and setting start register (Start register) to "1". After processing the command list one by one, this module outputs the interrupt signal when enable interrupt (REGE of Status enable register) is effective. Figure11-7Register start flow




11.5.3. Priority The following priorities exist in this module, and it processes it from a high start of the priority sequentially. Priority1>Priority2>Priority3>Priority4>Pryority5 Table11-5Priority list

Priority Signal name or demand Priority1 TRG_PRI1 (Trigger start) Priority2 Reset start Priority3 TRG_PRI2 (Trigger start) Priority4 TRIGGER0-14 (Trigger start) Priority5 Register start

The processing table when there is an operation demand in the following when variously starting is shown. Table11-6Operation demand processing list when variously starting




11.5.4. Command list The set of various parameter settings and the pattern data is called a command list. Wait can operate by counting a setting, an expected value comparison, and various trigger signals of the register by executing the command list. The command list consists of Header part including Packet Code and the part Parameter parts following it.

Header part [31:0]

Parameter parts [31:0]

11.5.4.1. Header part The outline of Header part is shown in the following. Packet Code is shown in eight high rank bits in Header part. Other 23:0 part is different according to each command. Please refer to various command lists for details.

Packet Code [31:24] Other [23:0]

11.5.4.2. Parameter part Parameter parts exists only in SETREG, OSETREG, COMPREG, and COMPREG2. Please refer to the explanation of the list of each command of SETREG, OSETREG, COMPREG, and COMPREG2 paragraph for details of Parameter parts.

11.5.4.3. Packet Code The following are Packet Code tables. This module identifies the command list by Packet Code included in Header part. Please refer to the following chapters for details of the command list. Table11-7Command list and packet code

Packet code Packet Name Discription 0000_0001B WAIT Trigger WAIT by trigger 0000_0010B SETREG Set Register

0000_0011B OSETREG Offset Address Set Register

0000_0100B COMPREG Comparison Register 0000_0101B COMPREG2 Comparison Register Part 2 1111_1111B END Command End

Note: When Packet Code other than the above is detected, it is considered the end command.




11.5.4.4. Various command lists This chapter explains the list of each command of WAIT Trigger, SETREG, OSETREG, COMPREG, COMPREG2, and END.

11.5.4.4.1. WAIT Trigger

Only the set Count number counts the signal, and, meanwhile, this function is not processed. The signal and the Count number that becomes WAIT Trigger are specified in Header part that shows this function. A format and a set value of the WAIT Trigger command list are as follows.

Trigger [3:0] The synchronizing display trigger signal is selected. 0000B: WAIT0 0001B: WAIT1 0010B: WAIT2 ... ... 1111B: WAIT15 Count [23:16] The signal of ..specified frequency.. trigger is edging detected by the count value. 0H: The trigger signal is detected 256 times, and the following command

list is processed. 1H: The trigger signal is detected, and the following command list is

processed once. 2H: The trigger signal is detected, and the following command list is

processed twice. ... ... FFH: The trigger signal is detected 255 times, and the following command

list is processed. The connected WAIT Trigger signal is as follows. Table11-8WAIT Trigger signal connection list

WAIT Trigger signal name Output module WAIT Trigger condition WAIT0 - GSSCGCLK WAIT1 SIG SIG error count reached interrupt WAIT2 Display FSYNC interrupt WAIT3 Display VSYNC interrupt WAIT4 SPE Specified line processing over WAIT5 SPE Line blank

WAIT6 RLD

Byte count achieved, AHB Slave Error, Input FIFO empty, Input FIFO full

WAIT7 DMAC DMAC ch0 interrupt WAIT8 DMAC DMAC ch1 interrupt WAIT9 - Reserved WAIT10 Capture Frame sync WAIT11 Capture 656 stream error WAIT12 Draw DMA command execution WAIT13 Draw INT command execution WAIT14 GDCTRGR Register in FR81s WAIT14 bit(Bit4) WAIT15 GDCTRGR Register in FR81s WAIT15 bit(Bit5)

31 24 23 16 15 4 3 0Header part WAIT=01H Count Reserved Trigger




11.5.4.4.1.1. WAIT Trigger enable signal and error detection

Please make WAITEN14(Bit6) and the WAITEN15(Bit7) bit of GDCTRGR register (0000_0F66H) "1" when you execute the WAIT Trigger command with WAIT14 and WAIT15. This module is considered to be WAIT Trigger error when recognizing list (Trigger=EH, Trigger=FH) of the command of WAIT14 and WAIT15 setting neither WAITEN14 nor the WAITEN15 bit. This module is similarly considered to be WAIT Trigger error when recognizing list (Trigger=9H) of the command of WAIT9. The processing of the command list is canceled when this module detects WAIT Trigger error, and the WAITE bit of Status register is set to "1".




11.5.4.4.2. SETREG

This function sets data for the register and the memory allocated in the memory map. Moreover, the write can do data to a consecutive address by setting the count value. When data is set in the register and the memory, this function is used. A format and a set value of the SETREG command list are as follows.

31 24 23 16 15 0

Header part SETREG=02H Count [23:16] - Address (Data0) (Data1)

: Parameter parts

(Data255)

Number of registers in which register and memory are set 0H: Data is set 256 times. 1H: Data is set once. 2H: Data is set twice. ... ...

Count [23:16]

FFH: Data is set 255 times.

Address [31:0] The first address of register or memory that begins data set. Data [31:0] Data set in register or memory. It is possible to set it by 256 data or less.

It is an example of formatting the SETREG command as follows.

SETREG Count = 5 Address data set ahead Set data Address = 1000_0000H Address Data Data0 = 0000_0001H 1000_0000H 0000_0001H Data1 = 0000_0002H 1000_0004H 0000_0002H Data2 = 0000_0003H 1000_0008H 0000_0003H Data3 = 0000_0004H 1000_000CH 0000_0004H Data4 = 0000_0005H 1000_0010H 0000_0005H

Note: Please do not set the addresses other than the GDC macro to Address 31:0. This module cannot be

accessed besides the address area of the GDC macro.




11.5.4.4.3. OSETREG

This function sets data for the register and the memory allocated in the memory map. The address in the forwarding destination is Base Address + Can it jump in becoming Offset Address, and setting Offset Address with the data value and data be set at the address of the jump. Moreover, data can be continuously set by setting the count value, and the forwarding size can be set. When data is set in the register and the memory, this function is used. A format and a set value of the OSETREG command list are as follows. The address value does the carryout at the forwarding destination when the Base Address+Offset Address value exceeds 32 bits. Eight bit forwarding format

31 24 23 16 15 8 7 2 1 0

Header part OSETREG=03H Count [23:16] - Size=00Base Address [31:0]

Offset Address0 (Data0) Offset Address1 (Data1)

: Parameter parts

Offset Address255 (Data255) Note: The address is as follows at the destination of forwarding forwarding eight bits. Base Address[31:0]+ Offset Address[31:8] 16 bit forwarding format

31 24 23 17 16 15 8 7 2 1 0

Header part OSETREG=03H Count [23:16] - Size=01Base Address [31:1] -

Offset Address0 - (Data0) Offset Address1 - (Data1)

: Parameter parts

Offset Address255 - (Data255) Note: The address is as follows at the destination of forwarding forwarding 16 bits. One subordinate position bit of the address becomes "0" fixation at the forwarding destination. Base Address [31:1] + Offset Address [31:17] 24 bit forwarding format

31 26 25 24 23 16 15 8 7 2 1 0

Header part OSETREG=03H Count [23:16] - Size=10,11Base Address [31:2] -

Offset Address0 - (Data0) Offset Address1 - (Data1)

: Parameter parts

Offset Address255

- (Data255)

Note: The address is as follows at the destination of forwarding forwarding 24 bits. Two subordinate position bits of the address become "0" fixation at the forwarding destination. Base Address [31:2] + Offset Address [31:26] Note: Eight high rank bits of the transmitted data become "0" fixation.




The forwarded size is selected. 00B: Eight bit forwarding(Only one byte forwarding is supported. ) 01B: 16 bit forwarding(Only two byte forwarding is supported. ) 10B: 24 bit forwarding(Only four byte forwarding is supported. )

Size [1:0]

11B: 24 bit forwarding(Only four byte forwarding is supported. ) Number of registers in which register and memory are set 0H: Data is set 256 times. 1H: Data is set once. 2H: Data is set twice. ... ...

Count [23:16]

FFH: Data is set 255 times.

Base Address Base address of register or memory that does data set. Offset Address The offset address of the register or the memory that sets data is set. Data Data set in register or memory. As for high rank 31:24bit, whenever 24 bits are

forwarded, "0" is set. It is possible to set it by 256 data or less. It is an example of formatting the OSETREG command as follows.

OSETREG Count = 7 Size = 0 Address data set ahead Set data Base Address = 1000_0000H Address Data Offset Address0 = 00_0001H Data0 = 1H 1000_0001H 01H Offset Address1 = 00_0003H Data1 = 2H 1000_0003H 02H Offset Address2 = 02_0000H Data2 = 3H 1002_0000H 03H Offset Address3 = 24_0001H Data3 = 4H 1024_0001H 04H Offset Address4 = 00_2500H Data4 = 5H 1000_2500H 05H Offset Address5 = 00_c000H Data5 = 6H 1000_c000H 06H Offset Address6 = c4_0000H Data6 = 7H 10c4_0000H 07H

Note: Please do not set the addresses other than the GDC macro to Base Address and Offset Address. This

module cannot be accessed besides the address area of the GDC macro.




11.5.4.4.4. COMPREG

This function reads the register allocated in the memory map, and compares expected values in 32 bits compared with the value set by the command list. As for this function, use of processing the command list of the back is thought in case of the value in which the value of the register and the memory is compared, and expected. A format and a set value of the COMPREG command list are as follows.

31 24 23 16 15 0

Header part COMPREG=04H Count [23:16] - Address (Data0) (Data1)

… Parameter parts

(Data255)

The data values are compared for the register. 0H: The data values are compared 256 times. 1H: The data values are compared once. 2H: The data values are compared twice. ... ...

Count [23:16]

FFH: The data values are compared 255 times.

Address [31:0] The first address of register or memory that begins expected value comparison. Data [31:0] Expected value data. It is possible to set it by 256 data or less.

It is an example of formatting the COMPREG command as follows.

COMPREG Count = 5 Address where expected value comparison begins

Expected value data

Address = 1000_0000H Address Data Data0 = 1111_1111H 1000_0000H 1111_1111H Data1 = 2222_2222H 1000_0004H 2222_2222H Data2 = 3333_3333H 1000_0008H 3333_3333H Data3 = 4444_4444H 1000_000CH 4444_4444H Data4 = 5555_5555H 1000_0010H 5555_5555H






11.5.4.4.5. COMPREG2

This function reads the register allocated in the memory map, compares the values set by the command list by each bytes, and compares expected values. As for this function, use of processing the command list of the back is thought in case of the value in which the value of the register and the memory is compared by each byte, and expected. A format and a set value of the COMPREG2 command list are as follows.

31 24 23 16 15 4 3 0

Header part COMPREG2=05H Count [23:16] - Byte

lane[3:0]Address (Data0) (Data1)

… Parameter parts

(Data255)

The data values are compared for the register. 0H: The data values are compared 256 times. 1H: The data values are compared once. 2H: The data values are compared twice. ... ...

Count [23:16]

FFH: The data values are compared 255 times.

Byte lane [3:0] Expected value comparative effective byte lane. The values of the specified byte lane are compared by "1". Byte lane and data are the following correspondences. Byte lane[3] → Data[31:24] Byte lane[2] → Data[23:16] Byte lane[1] → Data[15:8] Byte lane[0] → Data[7:0]

Address [31:0] The first address of register or memory that begins expected value comparison. Data [31:0] Expected value data. It is possible to set it by 256 data or less.

Byte lane set to "0" with Byte lane 3:0 becomes don 't care. It is an example of formatting the COMPREG2 command as follows. X shows don 't care. COMPREG2 Count = 5 Byte lane = B Address where expected value

comparison begins Expected value data

Address = 1000_0000H Address Data Data0 = 11XX_1111H 1000_0000H 11XX_1111H Data1 = 22XX_2222H 1000_0004H 22XX_2222H Data2 = 33XX_3333H 1000_0008H 33XX_3333H Data3 = 44XX_4444H 1000_000CH 44XX_4444H Data4 = 55XX_5555H 1000_0010H 55XX_5555H






11.5.4.4.6. END

This function ends the processing of the command list. After processing the end command, this module maintains the completion notification in Status register. A format and a set value of the END command list are as follows. 31 0

Header part END = FFFF_FFFFH

Note: When Packet Code other than WAIT Trigger, SETREG, OSETREG, COMPREG, and COMPREG2

are detected, it is considered the end command. The following are examples of the flow chart of the END command.

START

Command1 Command2 Command3 Command4

Command5(END)

End

11.5.4.4.6.1. End command error

When the end command is the values other than All "F", "1" is set to the ENDE bit of Status register. When the ENDEE bit of Status enable register is effective, this module outputs information on the ENDE bit to the interrupt signal.




11.5.5. Slave module access error response Error information is maintained in Status register when there is an error reply when this module accesses the slave module and the address (SERR=1) and making an error ahead is maintained in Slave access error address hold register. When the SERRE bit of Status enable register is effective, this module outputs information on the SERR bit of Status register to the interrupt signal. This module ends the start without waiting for the completion of the transaction when there is an error reply from the slave module.

11.5.6. Forced ending It is possible to cancel by the register setting while processing the command list by the reset start, the trigger start, and the register start. After the transaction is completed, forwarding is discontinued when this function becomes effective. This function becomes effective because it sets the FTERM bit of Forced termination register to "1". After processing by this function ends, the completion notification is maintained in Status register (FTERM=1). When the FTERME bit of Status enable register is effective, this module outputs information on the FTERM bit of Status register to the interrupt signal.

11.5.7. Forwarding status Can it be set next to the header part and the command list header part of the start method (reset start, trigger start, and register start) that this module is executing now and the command lists, and the first address or the offset address be confirmed with Transfer status register1-3. Please refer to a detailed register for details.

Header part [31:0] → It is possible to confirm it with

Transfer status register2.

Parameter parts_0 [31:0] → It is possible to confirm it with

Transfer status register3. Parameter parts_1 [31:0] Parameter parts_2 [31:0]

:




11.5.8. Interrupt This module can ..interrupt signal.. do the logical harmony output to MCNT. Please refer to the interrupt signal and refer to the following for the factor to do the logical harmony output to MCNT.

Interrupt factor Status register

Bit name Explanation

End of reset start

RESET

The start is ended when reset starts by the following either factor, and "1" is displayed in the RESET bit. The BOOT bit of GDCCR register (0000_0F65H) is "1. " The data value that the BOOT bit of GDCCR register

(0000_0F65H) was set to "0" and 0200_0000H (Reference Address Area) was FFFF_FFFFH.

Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error

End of Priority1 trigger start

TWDP1

The start is ended when the trigger by signal (TRG_PRI1) of Priority1 starts by the following factor, and "1" is displayed in the TWDP1 bit. The data value set to 0200_0004H (Reference Address Area)



PRI3

The start is ended when the trigger by signal (TRG_PRI2) of Priority3 starts by the following factor, and "1" is displayed in the PRI3 bit. The data value set to 0200_0008H (Reference Address Area)



TRIG

The start is ended when the trigger with various triggers (TRIGGER0-14) starts by the following factor, and "1" is displayed in the TRIG bit. 0200_000CH ? The data value set to 0200_005CH

(Reference Address Area) was FFFF_FFFFH. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error

End of register start

REG

The start ends when the register starts by the following factor, and "1" is displayed in the REG bit. Execution of END command Expected value error generation Detection of slave module access error Execution of forced ending Detection of WAIT command error






Completion of forced ending

FTERM When the FCTERM bit of Forced termination register is set to "1", "1" is displayed in the FTERM bit.

Slave error response

SERR When the slave module that this module accesses or the error reply is received, "1" is displayed in the SERR bit.

Expected value error

CMPE "1" is displayed in the CMPE bit when there is a disagreement of the expected value comparison when COMPREG or the COMPREG2 command list is being processed.

When the BOOT start mode is set, reset of the GDC macro is released. (reset start)

EXTNB

When reset of the GDC macro is released to the BOOT start mode effective (Bit1 of GDCCR register (0000_0F65H) is "0")(GDCCR register (0000_0F65H) Bit0 is set to "0"), "1" is displayed in the EXTNB bit.

Reference Address = FFFF_FFFFH

EXTF

This bit displays "1" in the EXTF bit by the following factor. When reset of GDC macro was released, data value that

BOOT start mode was set to effective (Bit1 of GDCCR register (0000_0F65H) was "0") and 0200_0000H (Reference Address Area) was All "F. "

0200_0004H accessed when the trigger started ~ The data value set to 0200_0044H (Reference Address Area) was All "F. "

WAIT Trigger Command error

WAITE

This bit displays "1" in the WAITE bit by the following factor. The list of the command of WAIT9 is processed. When WAITEN14(Bit6) of GDCTRGR register

(0000_0F66H) is "0", ..command of WAIT14.. list is processed.

When WAITEN15(Bit7) of GDCTRGR register (0000_0F66H) is "0", ..command of WAIT15.. list is processed.

END command error

ENDE When the END command is not All "F", "1" is displayed in the ENDE bit.

Reset start forced ending by interrupt request

RSTI When there is high start demand (TRG_PRI1) of the priority level while reset of Priority2 is starting, and the reset start is canceled, "1" is displayed in the RST1 bit.

Priority3 trigger start forced ending by interrupt request

PRI3I

When there is high start demand (TRG_PRI1) of the priority level while the trigger of Priority3 (TRG_PRI) is starting, and the trigger start of Priority3 is canceled, "1" is displayed in the PRI3I bit.

Priority4 trigger start forced ending by interrupt request

PRI4I

When there is a high start demand of the priority level (trigger start by TRG_PRI1 or TRG_PRI2) while the trigger of Priority4(TRIGGER0-14) is starting, and the trigger start of Priority4 is canceled, "1" is displayed in the PRI4I bit.

Register start forced ending by interrupt request

REGI When there is a high start demand of the priority level (trigger start) while the register of Priority5 is starting, and the register start is canceled, "1" is displayed.

The internal state not anticipated while operating is generated.

CMDE

When entering the internal state not anticipated while this module is operating, "1" is displayed. Operation cannot be guaranteed and reactivate this module, please.






The internal state not anticipated while operating was generated, and reset was issued.

CMDR

When reset is issued to this module and initialization is completed, "1" is displayed because it enters the internal state not anticipated while this module is operating, and it was judged that it was not possible to self-restore it. The operation guarantee immediately before cannot be done, and execute operation again, please.

Byte lane specification of the COMPREG2 command was All "0. "

BLANE

"1" is displayed at Byte lane 3:0= unsetting (4'H0) the specification of byte lane that executes the expected value comparison when this module recognizes the COMPREG2 command. Please confirm whether there is problem in byte specified lane.

11.6. Notes



11.5.9. Interrupt is enable. Information on Status register ..interrupt signal.. does the logical harmony output to MCNT by effective the bit of corresponding Status enable register ("1") doing.

11.5.10. Interrupt clearness The interrupt signal is cleared in "0" by setting "1" to the bit to which Status register corresponds.

11.6. Notes

11.6.1. Limitations This module can access only the address area in the GDC macro. Please set the address area in the

GDC macro when you process the command list. When the address area outside the GDC macro is specified, operation cannot be guaranteed.

11.7. Use example



11.7. Use example

11.7.1. Reset start The procedure of the reset start is as follows.

(1) Please write Command list address and Command list in Extenal Flash (CS0 NOR Flash or Serial Flash). Please describe the setting that makes Status enablre register effective in the command list when you output the interrupt signal from this module.

Figure11-8External Flash image

Reference Address Area(0200_0000H - 0200_0044H)

Top of command list

0200_0000H Command list address

Command list address

External Flash(CS0 NOR Flash or Serial Flash)

End of command list

Command List Area

(2) Please make the BOOT mode effective (Bit1 of GDCCR register (0000_0F65H) is set to "0"). (3) Please release reset of the GDC macro (Bit0 of GDCCR register (0000_0F65H) is set to "0"). (4) After releasing reset of the GDC macro, this module processes the command list that exists at address

(Command List Address) at the command list storage destination one by one. Figure11-9CMDSEQ start image

(5)

11.7. Use example



11.7.2. Trigger start

11.7.2.1. Start by Priority1 The procedure of the trigger start by signal (TRG_PRI1) of Priority1 is as follows.

(1) Please store address value (Command List Address) in 0200_0004H (Reference Address Area) at the command list storage destination and store the command list from the address (External Flash or Internal RAM) sequentially beforehand respectively at the command list storage destination. Please describe the setting that makes Status enable register effective in the command list when you output the interrupt signal from this module.

Figure11-10Data storage image

(2) Please set "1" to the PRI1ET bit of TRIGGER start enable register. (3) When TRG_PRI1 is changed into "1", this module processes the command list that exists at address

(Command List Address) at the command list storage destination one by one. Figure11-11CMDSEQ start image

(4) After the processing of the command list ends, status information is displayed in Status register. When

Status enable register is effective, bit information on corresponding Status register is output to INTST Register as an interrupt signal.

11.7. Use example



11.7.2.2. Start by Priority3 The procedure of the trigger start by signal (TRG_PRI2) of Priority3 is as follows.

(1) Please write address value (Command List Address) in 0200_0008H at the command list storage destination and write the command list from the address sequentially beforehand respectively at the command list storage destination.


(2) Please set "1" to the PRI3ET bit of TRIGGER start enable register. Please make Status enable register

effective when you output the interrupt signal from this module. (3) When signal (TRG_PRI2) of Priority3 changes into "1", this module processes the command list that

exists at address (Command List Address) at the command list storage destination one by one. Figure11-13CMDSEQ start image



11.7. Use example



11.7.2.3. Start by Priority4 The procedure of the trigger start by signal (TRIGGER0 ? 14) of Priority4 is as follows.

(1) 0200_000CH beforehand ~ Please write address value (Command List Address) in 0200_0044H at the command list storage destination and write the command list from the address sequentially respectively at the command list storage destination.


(2) Please set the TSET bit of TRIGGER start enable register. Please make Status enable register effective

when you output the interrupt signal from this module. (3) When the signal selected by the TSET bit of TRIGGER start enable register changes into "1", this

module processes the command list that exists at address (Command List Address) at the command list storage destination one by one.

Figure11-15CMDSEQ start image



Note: Please set it after the trigger start completion interrupt signal outputs it when you change the value of

the TSET bit of TRIGGER start enable register while the trigger by TRIGGER0 ? 14 is starting.

11.7. Use example



11.7.3. Register start The procedure of the register start is as follows.

(1) Please store the command list in the memory, and set the memory address that the command list is stored in REGISTER start address register. Please make Status enable register effective when you output the interrupt signal from this module.

Figure11-16Memory image

(2) Please set "1" to Start register. (3) When Start regiser becomes "1", the command list at the address to which this module REGISTER

start address register was set is processed one by one. (4) After the processing of the command list ends, status information is displayed in Status register. When


12.1. Outline


Run-Length Decompression (RLD) FUJITSU SEMICONDUCTOR CONFIDENTIAL 299

12. Run-Length Decompression (RLD) This chapter explains the Run-Length Decompression (RLD) unit of the GDC macro.

12.1. Outline Run-Length Decompression (RLD) defrosts the run length compression data with pure HW in which the processor is not interactive. Run length encoding of easy graphic contents of the pictogram and the corporate image (logo), etc. demonstrates a big effect in the bandwidth reduction when the external bus system in the setup is especially used.

12.2. Feature The run length compressed format is supported. 1/2/4/8/16/24/32bit per pixel form is supported.

12.3. Limitations Please specify VRAM or CMDRAM at the forwarding extension data destination. When an area other

than the above is specified, the operation of RLD is not guaranteed.

12.4. Composition



12.4. Composition

12.4.1. Block diagram Figure12-1The block diagram of RLD is shown.

Figure12-1Block diagram of RLD

RLD

INTMCNT

AHB-slave AHB-Master

GDC AHB

12.5. Register



12.5. Register

12.5.1. Description form of register The register of the endian this module corresponds to the little endian. Please add Base Address(0040_0000H) when seeing from Base addressFR81S(CPU). The bit number of the Bit register is shown. The bit field name of the Name register is shown. Reserved is shown by "-". The attribute of read/write of the R/W each bit field is shown. R0: The read value is always "0. "R1:

The read value is always "1. "W0: The write value is always "0. "One is guaranteed and when the write is done, operation is not guaranteed. W1: The write value is always "1. "0 is guaranteed and when the write is done, operation is not guaranteed. R: ReadW: Write


12.5. Register





01FB_5000H SWReset Software reset register

01FB_5004H RldCfg Set register of module whole

01FB_5008H StrideCfg0 Set register of stride whole

01FB_500CH StrideCfg1 Line/stride length setting register

01FB_5010H BYTECNT Setting of number of targets register of decompression byte

01FB_5014H OFIFO Output FIFO control register

01FB_5018H DestAddress Address setting register at master forwarding destination

01FB_501CH AHBMCtrl Set control register of master forwarding

01FB_5020H RLDCtrl Control of module whole

01FB_5024H IEN Interrupting enable register

01FB_5028H ISTS Interruption status register

01FB_502CH Status Status register

01FB_5030H SAHBData Input data setting register

01FB_5034H TransferCount Master forwarding number count register

01FB_5038H CurAddress Register of confirmation of present address of master forwarding

12.5. Register




12.5.3.1. SWReset This register is a software reset register.

Address 01FB_5000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name - SW

ResetR/W R/WInitial 0B

bit field

No Name Explanation

0 SWReset

When the run length processing is interrupted, this bit is used. Software reset is issued by writing "1". (The run length data is initialized. ) Notes: Please write "0" in the release of software reset again. Please execute the data of the run length processing from the register setting again

after releasing reset because it is not guaranteed when you effectively do this reset.

12.5. Register



12.5.3.2. RldCfg This register is a set register of the module whole.

Address 01FB_5004H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - Align - BPP[3:0] R/W R/W R/W Initial 0B 0H

bit field

No Name Explanation

2-0 BPP[3:0]

Bit per pixel 0H=1 1H=2 2H=4 3H=8 4H=16 5H=24 6H=32 7H=Reserved

8 Align Output data form 0B = bit alignment output 1B = word (32 bits) alignment output

12.5.3.3. StrideCfg0 This register is a set register of stride whole.

Address 01FB_5008H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name - Stride

ENR/W R/WInitial 0B

bit field

No Name Explanation

0 StrideEn The alignment of the output stride is made effective. 0B = invalidity(The StrideCfg1 register is invalidated. ) 1B = effective

12.5. Register



12.5.3.4. StrideCfg1 This register is line/stride length setting register.

Address 01FB_500CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Stride[15:0] R/W R/W Initial 0000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - LineLength[13:0] R/W R/W Initial 0000H

bit field

No Name Explanation

13-0 LineLength

[13:0] Number of bytes -1 for each line

31-16 Stride[15:0] Stride: Number of bytes -1

12.5.3.5. BYTECNT This register is the setting of the number of targets register of the decompression byte.

Address 01FB_5010H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name ByteCnt[31:16] R/W R/W Initial 0000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ByteCnt[15:0] R/W R/W Initial 0000H

bit field

No Name Explanation

31-0 ByteCnt [31:0] Number of targets of decompression bytes

12.5. Register



12.5.3.6. OFIFO This register is output FiFo control register.

Address 01FB_5014H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - WriteThreshold[3:0] R/W R/W Initial 0H

bit field

No Name Explanation

3-0 WriteThreshold

[3:0]

Forwarding begins after it accumulates of set value +4 bytes. Notes: Forwarding begins after it accumulates of eight bytes when WriteThreshold=0H is set.

12.5.3.7. DestAddress This register is an address setting register at the master forwarding destination.

Address 01FB_5018H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name AHBMDA[31:16] R/W R/W Initial 0000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name AHBMDA[15:0] R/W R/W Initial 0000H

bit field

No Name Explanation

31-0 AHBMDA

[31:0] Destination address for master forwarding to begin Notes: Please set the address in the GDC macro to a set value of AHBMDA.

12.5. Register



12.5.3.8. AHBMCtrl This register is a set control register of the master forwarding.

Address 01FB_501CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name - AHBM

Transfer Width[1:0]

- AHBMFixedDest

R/W R/W R/WInitial 0H 0B

bit field

No Name Explanation

0 AHBM Fixed Dest

The increment does 0B = destination address. 1B = destination address is fixed.

9-8 AHBM Transfer

Width[1:0]

0H=1 byte 1H=2 byte 2H=4 byte 3H=Reserved

12.5.3.9. RLDCtrl This register is a control register of the module whole.

Address 01FB_5020H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name - AcceptData

R/W R/WInitial 0B

bit field

No Name Explanation

0 AcceptData The compression data acceptance is made effective. After it completes it, it is reset with hardware.

12.5. Register



12.5.3.10. IEN This register is an interrupt enable register register.

Address 01FB_5024 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name - IEn IF

full

IEn IF

empty -r

IEnComplete

R/W R/W R/W R R/WInitial 0B 0B X 0B

bit field

No Name Explanation

0 IEnComplete Information on the IStsComplete bit of 0B=ISTS is not output as an interrupt signal. Information on the IStsComplete bit of 1B=ISTS is output as an interrupt signal.

2 IEnIFempty Information on the IStsError bit of 0B=ISTS is not output as an interrupt signal. Information on the IStsError bit of 1B=ISTS is output as an interrupt signal.

3 IEnIFfull Information on the IStsError bit of 0B=ISTS is not output as an interrupt signal. Information on the IStsError bit of 1B=ISTS is output as an interrupt signal.

12.5. Register



12.5.3.11. ISTS This register is an interrupt status register register.

Address 01FB_5028H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name - ISts IF

full

ISts IF

empty -

IStsComplete

R/W R/W R/W R R/WInitial 0B 0B X 0B

bit field

No Name Explanation

0 IStsComplete

"1" is displayed for the RLD completion condition (When becoming the number of target bytes). This bit is cleared by writing "1". Interrupt 0B = none There is 1B = interrupt.

2 IStsIFempty

"1" is displayed at input FIFO empty. This bit is cleared by writing "1". Interrupt 0B = none There is 1B = interrupt.

3 IStsIFfull

"1" is displayed at input FIFO full. This bit is cleared by writing "1". Interrupt 0B = none There is 1B = interrupt.

12.5. Register



12.5.3.12. Status This register is a status register.

Address 01FB_502CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W Initial

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name - IFIFO empty

OFIFO full

IFIFOfull Busy

R/W R R R RInitial 1B 0B 0B 0B

bit field

No Name Explanation

0 Busy This bit displays busy of RLD. 0B=RLD is not busy. 1B=RLD is busy.

1 IFIFOfull Input FIFO displays the state of full in this bit. 0B = input FIFO is not full. 1B = input FIFO is full.

2 OFIFOfull Output FIFO displays the state of full in this bit. 0B = output FIFO is not full. 1B = output FIFO is full.

3 IFIFOempty Input FIFO displays the state of empty in this bit. 0B = input FIFO is not empty. 1B = input FIFO is empty.

12.5.3.13. SAHBData This register is an input data setting register.

Address 01FB_5030H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name InData[31:16] R/W R/W Initial 0000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name InData[15:0] R/W R/W Initial 0000H

bit field

No Name Explanation

31-0 InData[31:0] RLD input data. (As for the data written at this address, the latch is done by RLD IFIFO. ) Please access the SAHBData register after setting various registers.

12.5. Register



12.5.3.14. TransferCount This register is a master forwarding number count register.

Address 01FB_5034H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name AHBMTransferCount[31:16] R/W R Initial 0000H

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name AHBMTransferCount[15:0] R/W R Initial 0000H

bit field

No Name Explanation

31-0 AHBMTransferCount

[31:0] Number of forwarding bytes of remainder in transaction (The counter is decreased. )

12.5.3.15. CurAddress This register is a register of the confirmation of a present address of the master forwarding.

Address 01FB_5038H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name AHBMCA[31:16] R/W R Initial X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name AHBMCA[15:0] R/W R Initial X

bit field

No Name Explanation

31-0 AHBMCA

[31:0] Present destination address





12.6.1. Data form

12.6.1.1. Input data form Table12.6-1The data form that supports is shown.

Table12.6-1Supported data form

Form [Bit/Pixel]

Mode Command byte <MSB LSB>

Color byte <MSB LSB>

Compression

<1NNN NNNN> Color bit <C> (bit-aligned)

1bpp Decompression

<0NNN NNNN> (NNN_NNNN +1) bits with color data <C…C> (bit-aligned)

Compression

<1NNN NNNN> Color bit <CC> (bit-aligned)

2bpp Decompression

<0NNN NNNN> (NNN_NNNN+1) x2 bits with color data <CC…CC> (bit-aligned)

4bpp Compression

<1NNN NNNN> Color bits<CCCC> (bit- aligned)

Decompression

<0NNN NNNN> (NNN_NNNN+1) x4 bits with color data <CCCC…CCCC> (bit-aligned)

Compression

<1NNN NNNN> 1 color byte <CCCC CCCC>

8bpp Decompression

<0NNN NNNN> (NNN_NNNN +1) bytes with color data <CCCC CCCC>

Compression

<1NNN NNNN> 2 bytes color data (<CCCC CCCC>,<CCCC CCCC>)

16bpp (*1) Decompression

<0NNN NNNN> (NNN_NNNN +1) x2 bytes with color data (<CCCC CCCC>,<CCCC CCCC>)

Compression

<1NNN NNNN> 3 bytes color data (<CCCC CCCC>,<CCCC CCCC>, <CCCC CCCC>)

24bpp Decompression

<0NNN NNNN> (NNN_NNNN +1) x3 bytes with color data (<CCCC CCCC>,<CCCC CCCC>, <CCCC CCCC>)

Compression

<1NNN NNNN> 4 bytes color data (<CCCC CCCC>,<CCCC CCCC>, <CCCC CCCC>,<CCCC CCCC>)

32bpp Decompression

<0NNN NNNN> (NNN_NNNN +1) x4 bytes with color data (<CCCC CCCC>,<CCCC CCCC>, <CCCC CCCC>,<CCCC CCCC>)

*1) It uses it for RGB555 or RGB565. It applies to all modes as follows: The compression data "<1NNN NNNN><pixel >" is defrosted to the (<NNN NNNN>+ 1) pixel.




Figure12-2Example of inputting decompression data of RGB888

Figure12-3Example of inputting compression data of RGB888




12.6.1.2. Output data form The output data form is different according to the form of selected BPP (Bit Per Pixel). Moreover, bit/word alignment supports the calculation of the memory stride with hardware. Output data is composed of the little endian.

Figure12-4Composition of memory of sprite engine




12.6.1.3. Memory stride About a stride calculation with HWFigure12-5Please refer to.

Figure12-5Memory

stride




12.6.2. Processing flow Figure12-6The processing flow chart of RLD is shown.

Figure12-6Processing flow chart

12.6.3. Control flow

12.6.3.1. Example of control's flowing 1. The decipherment does TGA header information to the micro controller:

BitPerPixel Source size Image size--Number of > decompression bytes

RLD is set: 2. Reset of OFIFO and IFIFO 3. Setting of BPP form 4. Setting of number of targets of bytes 5. Setting of AHB master IF

Example:Destination address of video memory 6. The compression data is sent to the RLD AHB slave: Case A: When the source of the compression data is AHB slave 1. Setting of DMA forwarding

Setting of source(flash etc.) Setting of DMA destination: RLD

2. Beginning of DMA forwarding 3. After it completes it, it interrupts. Case B: When the source of the compression data is AHB master 1. It is writing of active data in the RLD AHB slave. 2. After it completes it, it interrupts.

13.1. Outline


Signature Generator (SIG) FUJITSU SEMICONDUCTOR CONFIDENTIAL 317

13. Signature Generator (SIG) This chapter explains the signature generator of the GDC macro.

13.1. Outline Signature generator unit (SIG) calculates the type of checksum with different input data. The application generates the checksum of the pixel stream data of the evaluation window of the user definition (The entire size and the position can be programmed)(signature). When the display image decides the same as the original picture image data (Or, it is almost the same), the system microcontroller can use the signature. When it is necessary for an important safety display and meets the requirement such as safety standard Automotive Safety Integrity Level (ASIL), this is useful.

13.2. Feature CRC-32 of sum total color value of generation color value of two different image signature of each

color channel Position and size of programmable evaluation window Mask of programmable evaluation window Automatic monitor using reference signature register Generation of interruption Source of ..programmable.. image Self-restoration error counter

13.3. Composition



13.3. Composition

13.3.1. Block diagram Figure13-1The block diagram of SIG is shown.

Figure13-1Position where the entire LSI is blocked

13.4. Register



13.4. Register

13.4.1. Description form of register The register of the endian this module corresponds to the little endian. Please add Base Address(0040_0000H) when seeing from Base addressFR81S(CPU). The bit number of the Bit register is shown. The bit field name of the Name register is shown. The attribute of read/write of the R/W each bit field is shown. R0: The read value is always "0. "R1:



The unused register field is shown by the background of the gray. Especially, the bit vector is an integer of the sign none when there is no description.

13.4. Register



13.4.2. Register list Base address Base address of this module is 01FB_0000H.

Address Register name Explanation

01FB_0000H SigSWreset Reset of software of SIG

01FB_0004H SigCtrl Set register of SIG whole

01FB_0008H MaskHorizontalUpperLeft Mask point (on the left) setting of horizontal direction

01FB_000CH MaskHorizontalLowerRight Mask point (lower right) setting of horizontal direction

01FB_0010H MaskVerticalUpperLeft Mask point (on the left) setting in vertical direction

01FB_0014H MaskVerticalLowerRight Mask point (lower right) setting in vertical direction

01FB_0018H HorizontalUpperLeftW0 Evaluation window (on the left) setting of horizontal direction

01FB_001CH HorizontalLowerRightW0 Evaluation window (lower right) setting of horizontal direction

01FB_0020H VerticalUpperLeftW0 Evaluation window (on the left) setting in vertical direction

01FB_0024H VerticalLowerRightW0 Evaluation window (lower right) setting in vertical direction

01FB_0028H SignAReferenceRW0 Reference value setting of Red of signature A

01FB_002CH SignAReferenceGW0 Reference value setting of Green of signature A

01FB_0030H SignAReferenceBW0 Reference value setting of Blue of signature A

01FB_0034H SignBReferenceRW0 Reference value setting of Red of signature B

01FB_0038H SignBReferenceGW0 Reference value setting of Green of signature B

01FB_003CH SignBReferenceBW0 Reference value setting of Blue of signature B

01FB_0040H ThrBRW0 Red threshold setting of signature B

01FB_0044H ThrBGW0 Green threshold setting of signature B

01FB_0048H ThrBBW0 Blue threshold setting of signature B

01FB_004CH ErrorThreshold Threshold of error counter

01FB_0050H CtrlCfgW0 Control/set register of evaluation window

01FB_0054H TriggerW0 Trigger register

01FB_0058H IENW0 Interrupting enable register

01FB_005CH InterruptStatusW0 Interruption status register

01FB_0060H StatusW0 Status register

01FB_0064H Signature error Number of video frames with signature error

01FB_0068H SignatureARW0 Calculation result of Red of signature A

01FB_006CH SignatureAGW0 Calculation result of Green of signature A

01FB_0070H SignatureABW0 Calculation result of Blue of signature A

01FB_0074H SignatureBRW0 Calculation result of Red of signature B

01FB_0078H SignatureBGW0 Calculation result of Green of signature B

01FB_007CH SignatureBBW0 Calculation result of Blue of signature B

13.4. Register




13.4.3.1. SigSWreset

Register address

01FB_0000H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SWRes

R/W RW

Reset value 0 Reset of software of SIG [bit 0] SWReset

Software reset

13.4.3.2. SigCtrl

Register address

01FB_0004H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name Reserved

Vmask_mode

Hmask_mode

R/W RW RW RW

Reset value 0 0 0 0 0 0

Set register of SIG whole [bit17, bit16] Reserved The limitations: Please do not do writing other than 0 to bit17 and bit16.

[bit9, bit8] Vmask_mode Mask 00= none

Mask in vertical coordinates 01= Mask outside vertical coordinates 10= 11=Reserved

[bit1, bit0] Hmask_mode Mask 00= none

Mask in the horizontal coordinates 01= Mask outside the horizontal coordinates 10= 11=Reserved

13.4. Register



13.4.3.3. MaskHorizontalUpperLeft

Register address

01FB_0008H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name MaskHorizontalUpperLeft

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Horizontal mask point (on the left) setting register [bit11～bit0] MaskHorizontalUpperLeft (on the left) is set.

13.4.3.4. MaskHorizontalLowerRight

Register address 01FB_000CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name MaskHorizontalLowerRight

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Horizontal mask point (lower right) setting register [bit11～bit0] MaskHorizontalLowerRight (lower right) is set.

13.4.3.5. MaskVerticalUpperLeft

Register address 01FB_0010H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name MaskVerticalUpperLeft

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Mask point (on the left) setting register in vertical direction [bit11～bit0] MaskVerticalUpperLeft (on the left) is set.

13.4.3.6. MaskVerticalLowerRight


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name MaskVerticalLowerRight

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Mask point (lower right) setting register in vertical direction [bit11～bit0] MaskVerticalLowerRight (lower right) is set.

13.4. Register



13.4.3.7. HorizontalUpperLeftW0


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name HorizontalUpperLeftW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Horizontal evaluation window (on the left) setting register [bit11～bit0] HorizontalUpperLeftW0 A horizontal evaluation window (on the left) is set.

13.4.3.8. HorizontalLowerRightW0

Register address

01FB_001CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name HorizontalLowerRightW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Horizontal evaluation window (lower right) setting register [bit11～bit0] HorizontalLowerRightW0 A horizontal evaluation window (lower right) is set.

13.4.3.9. VerticalUpperLeftW0

Register address

01FB_0020H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name VerticalUpperLeftW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Evaluation window (on the left) setting register in vertical direction [bit11～bit0] VerticalUpperLeftW0 The evaluation window (on the left) in the vertical direction is set.

13.4.3.10. VerticalLowerRightW0

Register address

01FB_0024H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name VerticalLowerRightW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Evaluation window (lower right) setting register in vertical direction [bit11～bit0] VerticalLowerRightW0 The evaluation window (lower right) in the vertical direction is set.

13.4. Register



13.4.3.11. SignAReferenceRW0


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignAReferenceRW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reference value setting register of Red at signature A mode [bit31～bit0] SignAReferenceRW0 The reference value of Red at signature A mode is set.

13.4.3.12. SignAReferenceGW0

Register address 01FB_002CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignAReferenceGW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reference value setting register of Green at signature A mode [bit31～bit0] SignAReferenceGW0 The reference value of Green at signature A mode is set.

13.4.3.13. SignAReferenceBW0


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignAReferenceBW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reference value setting register of Blue at signature A mode [bit31～bit0] SignAReferenceBW0 The reference value of Blue at signature A mode is set.

13.4.3.14. SignBReferenceRW0


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignBReferenceRW0

R/W RW

Reset value 0H

Setting of reference of Red at signature B mode register

[bit31～bit0] SignBReferenceRW0

The reference value of Red at signature B mode is set.

13.4. Register



13.4.3.15. SignBReferenceGW0

Register address

01FB_0038H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignBReferenceGW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reference value setting register of Green at signature B mode [bit31～bit0] SignBReferenceGW0 The reference value of Green at signature B mode is set.

13.4.3.16. SignBReferenceBW0

Register address

01FB_003CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignBReferenceBW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reference value setting register of Blue at signature B mode [bit31～bit0] SignBReferenceBW0 The reference value of Blue at signature B mode is set.

13.4.3.17. ThrBRW0


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name ThrBRW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red threshold setting register of signature B mode [bit31～bit0] ThrBRW0 The Red threshold at signature B mode is set.

13.4.3.18. ThrBGW0


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name ThrBGW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Threshold setting register of Green at signature B mode [bit31～bit0] ThrBGW0 The threshold of Green at signature B mode is set.

13.4. Register



13.4.3.19. ThrBBW0


Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name ThrBBW0

R/W RW

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Threshold setting register of Blue at signature B mode [bit31～bit0] ThrBBW0 The threshold of Blue at signature B mode is set.

13.4.3.20. ErrorThreshold

Register address

01FB_004CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name ErrThresReset ErrThres

R/W RW RW

Reset value 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1

Threshold of error counter [bit23～bit16] ErrThresReset Number of video frames without consecutive error that becomes factor of reset of error_count

There is no 0x00 = reset. 0x01=1 | 0xFF=255

[bit7～bit0] ErrThres Threshold of error counter

0x00=256 0x01=1 | 0xFF=255 The interruption is generated for error_counter >= "ErrThres".

13.4. Register



13.4.3.21. CtrlCfgW0

Register address

01FB_0050H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name EnCoordW0

EnSignB

EnSignA

R/W RW RW RW

Reset value 0 0 0

Control/set register of evaluation window [bit16] EnCoordW0 Making of coordinates of window 0 effective [bit8] EnSignB Making of signature calculation B effective [bit0] EnSignA Making of signature calculation A effective

13.4.3.22. TriggerW0

Register address

01FB_0054H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name TrigMode Trigger

R/W RW W

Reset value 0 0 0

Trigger register

[bit9, bit8] TrigMode Beginning of 00= one trigger generation and cancellation of cyclic trigger

Beginning of 01= cyclic trigger generation 10=Reserved 11=Reserved

[bit0] Trigger The trigger for the signature generation is generated.

Please refer to TrigMode for the trigger mode.

13.4. Register



13.4.3.23. IENW0

Register address

01FB_0058H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name IEnResVal

IEnCfgCop

IEnDiff

R/W RW RW RW

Reset value 0 0 0

Control/set register of evaluation window [bit2] IEnResVal Making of interruption effective [bit1] IEnCfgCop Making of interruption effective

[bit0] IEnDiff Making of difference detection interruption effective

13.4.3.24. InterruptStatusW0

Register address

01FB_005CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name IStsResVal

IStsCfgCop

IStsDiff

R/W RW RW RW

Reset value 0 0 0

Interruption status register [bit2] IStsResVal Interruption status flag

"1" shows the corresponding interrupting generation. (When the interruption setting is invalid, it is similar. ) The flag is cleared by writing "1". The condition: The Result register must be effective.

[bit1] IStsCfgCop Interruption status flag

"1" shows the corresponding interrupting generation. (When the interruption setting is invalid, it is similar. ) The flag is cleared by writing "1". The condition: When the Configuration register is copied onto the shadow register

[bit0] IStsDiff Interruption status flag

"1" shows the corresponding interrupting generation. (When the interruption setting is invalid, it is similar. ) The flag is cleared by writing "1". The condition: When differing from the reference value that one of the active signature results corresponds

13.4. Register



13.4.3.25. StatusW0

Register address

01FB_0060H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name

Dif

f_B

_B

Dif

f_B

_G

Dif

f_B

_R

Dif

f_A

_B

Dif

f_A

_G

Dif

f_A

_R

Res

erve

d2

Act

ive

Pen

ding

R/W R R R R R R RWS R R

Reset value 0 0 0 0 0 0 0 0 0 0 0

Status register [bit18] Diff_B_B Signature B: The result of effective B and the reference value are compared.

The 0= same It is 1= different.

[bit17] Diff_B_G Signature B: The result of effective G and the reference value are compared.


[bit16] Diff_B_R Signature B: The result of effective R and the reference value are compared.


[bit10] Diff_A_B Signature A: The result of effective B and the reference value are compared.


[bit9] Diff_A_G Signature A: The result of effective G and the reference value are compared.


[bit8] Diff_A_R Signature A: The result of effective R and the reference value are compared.


[bit7～bit5] Reserved2 [bit1] Active The generation task is active. [bit0] Pending The generation task is undecided.

13.4. Register



13.4.3.26. Signature_error

Register address

01FB_0064

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name Sig_error_count

R/W R

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

Number of video frames with signature error [bit11～bit0] Sig_error_count Number of video frames with signature error

All triggers (Refer to TriggerW0) reset Signature_error in "0".

13.4.3.27. SignatureARW0

Register address

01FB_0068H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignatureARW0

R/W R

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Calculation value result register of Red of signature A [bit31～bit0] SignatureARW0 Signature A: Calculation value result of Red

13.4.3.28. SignatureAGW0

Register address

01FB_006CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignatureAGW0

R/W R

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Calculation value result register of Green of signature A [bit31～bit0] SignatureAGW0 Signature A: Calculation value result of Green

13.4. Register



13.4.3.29. SignatureABW0

Register address

01FB_0070H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignatureABW0

R/W R

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Calculation value result register of Blue of signature A [bit31～bit0] SignatureABW0 Signature A: Calculation value result of Blue

13.4.3.30. SignatureBRW0

Register address

01FB_0074H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignatureBRW0

R/W R

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Calculation value result register of Red of signature B [bit31～bit0] SignatureBRW0 Signature B: Calculation value result of Red

13.4.3.31. SignatureBGW0

Register address

01FB_0078H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignatureBGW0

R/W R

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Calculation value result register of Green of signature B [bit31～bit0] SignatureBGW0 Signature B: Calculation value result of Green

13.4. Register



13.4.3.32. SignatureBBW0

Register address

01FB_007CH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field name SignatureBBW0

R/W R

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Calculation value result register of Blue of signature B [bit31～bit0] SignatureBBW0 Signature B: Calculation value result of Blue





13.5.1. Signature A:CRC-32 signature The CRC-32 checksum is generated in each color channel in the evaluation window area. It is the same as the CRC-32 algorithm applied by Ethernet standards (CRC-32-IEEE 802.3) except e of the closing phase. This means the complement of the bit string is not taken as a result at the end.

13.5.2. Signature B: Sum total signature The sum total of the pixel color value of each color channel (R,G,B) in the evaluation window area is calculated.




13.5.3. Programmable evaluation window(position and size)

The position and the size (lower right on the left, coordinates) of the evaluation window can be programmed. The window coordinatesFigure13-2It follows the coordinates system drinking. The reference point of coordinates is decided in Taori edge of display controller's horizontal synchronizing signal and the first active pixel line.

Figure13-2Coordinate system

Active pixels

HBP

VS

Eval window

HDPHS

(0,0)

Blanking

Xupper left

Offset = HTP-HSP

Xlower right

Hsync of Display

HTP

13.5.4. Mask of programmable evaluation window When signature is calculated, the programmable mask window permits the exclusion of the reception pixel. Figure13-2It is applied to the coordinates system drinking.

13.5.5. Automatic monitor and interruption The set of the reference signature register permits the monitor of the calculated signature. The interruption is generated with the difference detection of calculated signature and reference value. In signature B, because the micro controller's interruption loading is limited, the threshold put on the filter is different.




13.5.6. Self-restoration error counter As for the counter, the increment is done when differing from the reference value that one of the active signature corresponds. When it reaches the threshold of the programmable error counter, the interruption can be generated. When the video frame where the number of Programumabl with a correct signature value is consecutive is received, the programmable error counter is reset in "0".

13.5.7. Interruption control flow The interruption can be generated by both beginning and the end of the signature calculation. Beginning interruption (CfgCop) is copied the configuration parameter (window coordinates etc.) from the Shadow register, is active a present signature calculation, and shows that it is. As a result, the following configuration parameter can be loaded into the Shadow register without disturbing a present calculation. End interruption (ResVal) shows that the signature calculation can be completed, and the result data be led from the Result shadow register. These interruptions are useful for the control of the signature calculation of each reception frame with different evaluation window coordinates.

13.5.8. Limitations The maximum resolution of the image source and the window is 4096×4096 It is pixel. Please store the position of the evaluation window in the image source intraframe completely. Please do not do before adjusting the evaluation window, and do not change the source selection while operating. The interlace source is not supported. Because special processing doesn't support the source of the interlace release The reference value : with software in consideration of a correct interlace release algorithm. It is necessary to calculate.




13.5.9. Processing mode

13.5.9.1. Processing flow Figure13-3The processing flow chart of SIG is shown.

Figure13-3Processing flow chart

Checksum_A

Checksum_B

Window & masking Function

Result, shadowed

Result

Config, shadowed

Config

R,G,B, LastRow, LastColumn

Interrupt Generation Int

GDC AHB IF

13.5.9.2. Algorithm processing

エラー! 参照元が見つかりません。Please refer to the feature. The generation of checksum is possible in each reception pixel frame. The checksum generation becomes after each reception pixel frame and if the trigger is done, the result of the signature checksum becomes effective.




13.5.10. Control flow

13.5.10.1. Signature generation of all reception frame Whole setting phase:(Most registers are not shadows. )

Making of mask mode effective Writing of mask window coordinates Making of signature type effective Making of interruption effective

Set phase of calculation 0

Writing of 0 coordinates in window The trigger mode is set to one trigger generation. "1" is written in the trigger field, and one trigger is generated.

The interruption is waited or it is polling as for IstsCfgCop and IstsResVal. IstsCfgCop:

Set phase of calculation n Writing of window n coordinates The trigger mode is set to one trigger generation. "1" is written in the trigger field, and one trigger is generated.

IstsResVal: Reading of signature A (B) of Result register Processing of result

13.5.10.2. Cyclic signature generation of all reception frame

Cyclic monitor of one window: Whole setting phase:(Most registers are not shadows. )



Writing of 0 coordinates in window The trigger mode is set to the cyclic trigger mode. "1" is written in the trigger field, and a cyclic trigger is generated.

The interruption is waited or it is polling as for IstsResVal. IStsResVal:

Reading of signature A (B) of Result register Processing of result




13.5.10.3. Cyclic signature generation and read access limitation of all reception frame

Cyclic trigger of one window in interruption monitor Whole setting phase:(Most registers are not shadows. )



Writing of 0 coordinates in window Writing of reference value of signature A(threshold setting of reference value writing of signature B and B) The trigger mode is set to the cyclic trigger mode. "1" is written in the trigger field, and a cyclic trigger is generated.

The interruption is waited or it is polling as for IStsDiff. IStsDiff:

Reading of signature A (B) of Result register Processing of result

Before displaying the content of the change of the evaluation window:

A cyclic trigger is canceled.

14.1. Outline


DMA Controller (DMAC) FUJITSU SEMICONDUCTOR CONFIDENTIAL 339

14. DMA Controller (DMAC) This chapter explains the function and the movement of DMA controller (DMAC) of the GDC macro.

14.1. Outline DMAC installs DMA of 2ch, and supports the DMA forwarding in the GDC macro. It is not possible to forward it outside the GDC macro.

14.2. Feature Two DMA channels The software demand is supported as DMA forwarding trigger. Two following forwarding is supported as a forwarding mode.

Block transfer Burst transfer

Source/destination address fixed both increment addressing/addressing is supported.

14.3. Composition



14.3. Composition

14.3.1. Block diagram Figure14-1The block diagram of DMAC is shown.

Figure14-1Block diagram of DMAC

14.4. Register



14.4. Register Here, it explains the register of DMAC.

14.4.1. Mark form of register The register of the endian this module corresponds to the little endian. Please add Bass Address(0040_0000H) when Base addressFR81S(CPU) accesses it. The bit number of the Bit register is shown. The bit field name of the Name register is shown. Reserved is shown by "-". The attribute of read/write of the R/W each bit field is shown. R0: The read value is always "0. "R1:

The read value is always "1. "Please do W0 "0" in the write. When "1" is done in the write, the operation guarantee is not done. Please do W1 "1" in the write. When "0" is done in the write, the operation guarantee is not done. The value of each bit field immediately after R: ReadW: WriteInitial value reset is indicated. It becomes 0"0". It becomes one "1". X: It is irregular.

14.4. Register




Module Address Register name Function

DMAC commonness

01FB_4000H DMACR DMAC configuration register

01FB_4010H DMACA0 DMAC0 configuration A register

01FB_4014H DMACB0 DMAC0 configuration B register

01FB_4018H DMACSA0 DMAC0 source address register DMAC ch0

01FB_401CH DMACDA0 DMAC0 destination address register

01FB_4020H DMACA1 DMAC1 configuration A register

01FB_4024H DMACB1 DMAC1 configuration B register

01FB_4028H DMACSA1 DMAC1 source address register DMAC ch1

01FB_402CH DMACDA1 DMAC1 destination address register

14.4. Register




14.4.3.1. DMA configuration register(DMACR)

Address 01FB_4000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name DE DS - PR DH[3:0] -

R/W R/W R/W0 R R/W R/W R/W R/W R/W R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name -

R/W R R R R R R R R R R R R R R R R

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field

Number Name Explanation

31 DE (DMA Enable)

This bit controls forwarding all DMA channel.

0(h) The DMA forwarding is not done until all channels of DMA become invalid, and "1(h)" is set to this bit. The channel under forwarding stops DMA by the forwarding gap when setting it to "0(h)" while forwarding DMA.

1(h) All channels of DMA become effective. The DMA forwarding begins according to the setting of each channel.

Forwarding gap The forwarding gap is different depending on the forwarding mode. The block transfer: The forwarding gap : at "0(h) BC =". (After completing forwarding each BC. ) Burst transfer: The forwarding gap is none. The forwarding gap is that DMAC between about four clocks forwarding DMA Diasarts it the bus demand for Arbitar. This bit is useful to set the Configuration register of all channels again while forwarding DMA.

30 DS (DMA Stop)

This bit shows that the DMA forwarding of all channels has stopped.

0(h) Disabling/Holt setting is cleared. (initial value)

1(h) The DMA forwarding of all channels has stopped by disabling/Holt setting.

When one of the following conditions is satisfied while forwarding DMA, this bit is set to "1(h)". "0(h)" is set to the DE bit of the DMACR register. (All channels are disabled. ) The values other than "0(h)" are set to the DH bit of the DMACR register. (It is Holt as for all channels. ) DMAC stops forwarding by setting disabling of all channels and Holt. This bit is useful to confirm the DMA forwarding of all channels has stopped. Writing "0(h)" and "1(h)" in this bit is disregarded excluding the initialization of the register ("0(h)" setting).

14.4. Register



Bit field


29 (Reserved) Reserved Writing is disregarded. The reading value of this bit is always "0(h). "

28 PR (Priority Rotation)

There is no difference in operation in this DMAC because it supports only DMA of 2ch though this bit controls the priority level of the DMA channel.

0(h) "Fixation" Priority: Ch0 > Ch1

1(h) "Rotation" The priority level is Rortated.

27-24 DH[3:0] (DMA Halt)

The halt condition of all DMA channel is controlled. DMA is not forwarded until all DMA channels stop when the values other than "0(h)" are set to these bits, and "0(h)" is set. The channel under forwarding stops DMA at the forwarding gap when the values other than "0(h)" are set to these bits while forwarding DMA. Please refer to the explanation of the DE bit for the forwarding gap. These bits are useful for wanting the stop of DMA forwarding without setting the Configuration register of all channels again. The DE bit is given to priority when this bit and the DE bit are set at the same time.

0(h) Initial value

Other All channels stop.

14.4. Register



14.4.3.2. DMA configuration A register(DMACAx)

Address ch.0: 01FB_4010H ch.1: 01FB_4020H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name EB0

EB1

PB0

PB1

ST0

ST1-

BT0[3:0]

BT1[3:0]

BC0[3:0]

BC1[3:0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name TC0[15:0]

TC1[15:0]


Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field


31 ch.0: EB0 ch.1: EB1 (Enable Bit)

This bit is used to control forwarding the DMA channel. The channel waits for the trigger for the DMA forwarding to begin when "1(h)" is set to this bit (It is necessary to set the DE bit of the DMACR register to "1(h)" beforehand). After completing the DMA forwarding, DMAC sets this bit to "0(h)". DMA is not forwarded until this channel is disabled when "0(h)" is set

to this bit, and "1(h)" is set to this bit. DMA stops by the

forwarding gap when "0(h)" is set to this bit while forwarding DMA.

This is considered to be a forced ending. Please refer to the explanation of the DE bit of the DMACR register for the forwarding gap. This bit is useful to set the Configuration register of each channel again while forwarding DMA.

0(h) This channel is disabled. (initial value)

1(h) This channel is done enable.

30 ch.0: PB0 ch.1: PB1 (Pause Bit)

This bit is used to control the interruption of forwarding of the DMA channel. When "1(h)" is set to this bit, this channel doesn't forward DMA until forwarding is stopped, and this bit is cleared. DMA stops by the forwarding gap when this bit is set to "1(h)" while forwarding DMA. Please refer to the explanation of the DE bit of the DMACR register for the forwarding gap. The interruption is released when this bit is set to "0(h)" while interrupting the DMA forwarding, and DMAC waits for a new forwarding demand. These bits are useful for wanting the stop of DMA forwarding without setting the Configuration register of each channel again.

0(h) Initial value

1(h) This channel is stopped.

14.4. Register



Bit field


29 ch.0: ST0 ch.1: ST1 (Software Trigger)

This bit is used to generate the software trigger. The DMA forwarding by the software demand begins when this bit is set to "1(h)". After completing this DMA forwarding, DMAC sets this bit to "0(h)". The DMA forwarding stops by the forwarding gap when this bit is set to "0(h)" while forwarding DMA by the software demand.

0(h) Initial value

1(h) Software demand

23-20 ch.0: BT0[3:0] ch.1: BT1[3:0] (Beat Type)

These bits are used to select the beat forwarding on GDC AHB. When these bits are set to NORMAL or SINGLE, the single source access and the single destination access are alternately done. When these bits are set to INCR * or WRAP *, a consecutive source access and a consecutive destination access are alternately done. Please refer to AMBA specification (v2.0) for INCR * and WRAP *. When INCR (undefined length burst) is set, the length of the burst is specified by the BC bit.

BT[3:0] Function

0(h) NORMAL (same as SINGLE)(initial value)

1(h) ? 7(h) Invalidity

8(h) SINGLE (same as NORMAL)

9(h) INCR

A(h) WRAP4

B(h) INCR4

C(h) WRAP8

D(h) INCR8

E(h) WRAP16

F(h) INCR16 19-16 ch.0: BC0[3:0]

ch.1: BC1[3:0] (Block Count)

These bits are used to specify the number of blocks of block/burst transfer. The number of maximum blocks is 16 It is ("F(h)"). These bits are effective for NORMAL, SINGLE or INCR beat type (BT). When other beat types (fixed length burst and lap) are set, these bits are disregarded. These bits can be reading while DMA is forwarded. When the single source access and the single destination access are normally completed, the BC one bit is Dicrimented usually. Notes When beat type bit (BT) is INCR, these bits can be set. However, after the DMA forwarding begins, the reading data of BC is always 0x0 in the INCR DMA forwarding. Therefore, it is not necessary to observe BC forwarding INCR DMA. After normally completing the DMA forwarding, DMAC sets 0(h) to these bits.

BC[3:0] Function

X(h) Number of blocks(initial value: 0(h))

14.4. Register



Bit field


15-0 ch.0: TC0[15:0] ch.1: TC1[15:0] (Transfer Count)

These bits are used to specify the number of forwarding of block/burst transfer. The number of maximum transmissions is 65536 It is (FFFF(h)). Even if which beat type is set to BT, these bits are effective. These bits can be reading while DMA is forwarded. When the DMA forwarding of "0 BC =" is normally completed, the TC one bit is Dicrimented in NORMAL or SINGLE mode (BT=NORMAL or SINGLE) usually. After a consecutive source/destination access is completed once, the TC one bit is Dicrimented in other beat forwarding modes (INCR,INCR*,WRAP*). For instance, when consecutive four source access and four destination accesses are completed, the TC one bit is Dicrimented for INCR4. After normally completing the DMA forwarding, DMAC sets "0000(h)" to these bits.

TC[15:0] Function

X(h) Number of forwarding(initial value: 0000(h))

14.4. Register



14.4.3.3. DMA configuration B register(DMACBx)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name TT0[1:0]

TT1[1:0]

MS0[1:0]

MS1[1:0]

TW0[1:0]

TW1[1:0]

FS0

FS1

FD0

FD1

RC0

RC1

RS0

RS1

RD0

RD1

EI0

EI1

CI0

CI1

SS0[2:0]

SS1[2:0]

R/W R/W R/W R/W0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0 R/W0 R/W0

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name -


Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field


31, 30 ch.0: TT0[1:0] ch.1: TT1[1:0] (Transfer Type)

These bits are used to specify the forwarding type. DMAC supports only two-cycle forwarding mode.

TT[1:0] Function

0(h) Two-cycle forwarding(initial value)

Other Reserved

29, 28 ch.0: MS0[1:0] ch.1: MS1[1:0] (Mode Select)

These bits are used to select the forwarding mode.

MS[1:0] Function

0(h) Block transfer mode(initial value)

1(h) Burst transfer mode

2(h) Reserved

3(h) Reserved

27, 26 ch.0: TW0[1:0] ch.1: TW1[1:0]

(Transfer Width)

These bits are used to specify the width of the forwarding data.

TW[1:0] Function

0(h) 1 Byte (initial value)

1(h) 2 Byte

2(h) 4 Byte

3(h) Reserved

25 ch.0: FS0 ch.1: FS1 (Fixed Source)

This bit is used to decide the source address. Please set "0" to this bit when it is necessary to expand the source address after it forwards it each.

FS Function

0(h) The increment does the source address. (initial value)

1(h) The source address is fixed.

14.4. Register



Bit field


24 ch.0: FD0 ch.1: FD1 (Fixed Destination)

This bit is used to decide the destination address. Please set "0" to this bit when it is necessary to expand the destination address after it forwards it each.

FD Function

0(h) The increment does the destination address. (initial value)

1(h) The destination address is fixed.

23 ch.0: RC0 ch.1: RC1 (Reload Count)

This bit is used to control the reload functions of the number of blocks (BC of the DMACA register) and the number of forwarding (TC of the DMACA register). After the DMA forwarding is completed, BC of the DMACA register and TC of the DMACA register are set to an initial value when this bit is set to "1".

RC Function

0(h) The reload functions of the number of forwarding are disabled. (initial value)

1(h) The reload functions of the number of forwarding are done enable.

22 ch.0: RS0 ch.1: RS1

(Reload Source)

This bit is used to control the reload function of the source address (DMACSA register). After the DMA forwarding is completed, the DMACSA register is set to an initial value when "1" is set to this bit. After completing the DMA forwarding, DMAC sets the following source address to the DMACSA register when "0" is set to this bit.

RS Function

0(h) The reload function of the source address is disabled. (initial value)

1(h) The reload function of the source address is done enable.

21 ch.0: RD0 ch.1: RD1 (Reload Destination)

This bit is used to control the reload function of the destination address (DMACDA register). After the DMA forwarding is completed, the DMACDA register is set to an initial value when "1" is set to this bit. After completing the DMA forwarding, DMAC sets the following destination address to the DMACDA register when "0" is set to this bit.

RD Function

0(h) The reload function of the destination address It disables it. (initial value)

1(h) The reload function of the destination address It does enable.

14.4. Register



Bit field


20 ch0: EI0 ch1: EI1 (Error Interrupt)

This bit controls the error interruption issued to MCNT. Hereafter, when this bit is set to "1(h)", the logical of forwarding error harmony result is issued as an error interruption. ･Address overflow

･Disabling of forwarding by EB and DE bit ･Source access error ･Destination access error

EI Function

0(h) The issue of the error interruption is disabled. (initial value)

1(h) The error interruption is issued enable.

19 ch.0: CI0 ch.1: CI1 (Completion Interrupt)

This bit controls the forwarding completion interruption issued to MCNT. When this bit is set to "1(h)", the forwarding completion interruption is issued.

CI Function

0(h) The issue of the completion interruption is disabled. (initial value)

1(h) The completion interruption is issued enable.

18-16 ch.0: SS0[2:0] ch.1: SS1[2:0] (Stop Status)

These bits are used to show the end code of the DMA forwarding. The end code is shown below. These bits are used also for the rear of error/forwarding completion interruption issued to MCNT. When 000(b) is written in these bits when the interruption is issued by the error or the normal termination, the interruption is cleared.

SS Function ステータスタイプ

0(h) Initial value なし

1(h) Address overflow Error

2(h) Forwarding stop demand Error

3(h) Source access error Error

4(h) Destination access error Error

5(h) Normal termination End

6(h) Reserved -

7(h) DMA interruption None When various errors occur at the same time, the end code is displayed by the following priority levels. Priority amount Reset 000(b) Clearness by writing Address overflow Stop demand Source access error Destination access error Priority Tei

14.4. Register



14.4.3.4. DMAC source address register(DMACSAx)


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name DMACSA0[31:16]

DMACSA1[31:16]


Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name DMACSA0[15:0]

DMACSA1[15:0]


Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field


31-0 ch.0: DMACSA0[31:0] ch.1: DMACSA1[31:0] (DMAC Source Address)

These bits are used to specify the source address that begins the DMA forwarding. These bits can be reading while DMA is forwarded. After the source access is normally done, these bits are Inccrimented according to the width of forwarding (TW bit of the DMACB register) when it is fixed address function's (FS bit of the DMACB register) disabling. When the DMA forwarding is completed, DMAC sets the following source address to these bits. Notes ･Please do not set the address of this module to DMACSA. ･The value set to this register is used for the bus access as it is. Please note that the source access error interruption is generated when the setting

and the adjustment of DMACB register TW bit cannot be taken.

DMACSA Function

X(h) Source address for DMA forwarding to begin (initial value: 00 million(h))

14.4. Register



14.4.3.5. DMAC destination address register(DMACDAx)

Address ch.0: 01FB_401CH ch.1: 01FB_402CH

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name DMACDA0[31:16]

DMACDA1[31:16]


Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name DMACDA0[15:0]

DMACDA1[15:0]


Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field

Number

Name Explanation

31-0 ch.0: DMACDA0[31:0] ch.1: DMACDA1[31:0] (DMAC Destination Address)

These bits are used to specify the destination address where the DMA forwarding begins. These bits can be reading while DMA is forwarded. After the destination access is normally done, these bits are Inccrimented according to the width of forwarding (TW bit of the DMACB register) when it is fixed address function's (FD bit of the DMACB register) disabling. When the DMA forwarding is completed, DMAC sets the following destination address to these bits. Notes ･Please do not set the address of this module to DMACDA. ･The value set to this register is used for the bus access as it is. Please note that the destination access error interruption is generated when the

setting and the adjustment of DMACB register TW bit cannot be taken.

DMACDA Function

X(h) Destination address for DMA forwarding to begin (initial value: 00 million(h))




14.5. Operation explanation Here, it explains the operation of DMAC.

14.5.1. Forwarding mode DMAC has two kinds of forwarding modes. The forwarding mode is decided by the MS bit of the DMACB register.

14.5.1.1. Block transfer

14.5.1.1.1. Operation explanation

In the block transfer mode, the DMA forwarding specified by the number of blocks (BC of the DMACA register) is executed by one forwarding demand. After the DMA forwarding of BC is completed, one TC is Dicrimented when the number of forwarding (TC of the DMACA register) is set to the values other than "0". The DMA forwarding ends after the last forwarding (In BC, 0(h) and TC are 0000(h)) is executed.

14.5.1.1.2. Forwarding gap

After completing forwarding BC, DMAC negates the bus demand to Arbitar once in the block transfer mode. This operation prevents DMAC from occupying the bus. The forwarding gap is useful to reflect the register setting (for instance, setting of disabling/interruption) in DMAC while forwarding DMA.

14.5.1.1.3. Forwarding demand

"1" is set to ST of the DMACA register.




14.5.1.1.4. Timing chart

Figure14-2The timing chart of the block transfer of ..peel.. , is shown.

Figure14-2Block transfer(For BC=1(h) and TC=1(h). )

HCLK

HADDR

HWRITE

Control

DMACA[31:24]

HWDATA

HRDATA

HBUSREQ

HGRANT

HREADY

HRESP

HMASTER other DMAC other DMAC other

OK

SA DA SA DA SA DA SA DA

HTRANS N N N N N N N N I I

Data Data Data

Data Data Data Data

0x00 0xA0

DMACA[19:16] 0x0 0x1 BC

0x00

0x0 0x1 0x0

DMACA[15:0] 0x0 0x1 TC

0x0

DMACSA

DMACDA

SA0 SA1 SA2 SA3 SA4

DA0 DA1 DA2 DA3 DA4

Break of transfer

Data




14.5.1.2. Burst transfer

14.5.1.2.1. Operation explanation

In the burst transfer mode, DMA forwarding of the number of of block × number of forwarding (TC of the BC×DMACA register of the DMACA register) is executed by one forwarding demand. After the DMA forwarding of BC is completed, one TC is Dicrimented when the number of forwarding (TC of the DMACA register) is set to the values other than "0". The DMA forwarding ends after the last forwarding (In BC, 0(h) and TC are 0000(h)) is executed.

14.5.1.2.2. Forwarding gap

After completing the DMA forwarding, DMAC negates the bus demand to Arbitar in the burst transfer mode. Therefore, the forwarding gap doesn't happen in burst transfer. After the DMA forwarding is completed, the change (for instance, setting of disabling/interruption) in the register setting forwarding DMA is reflected.

14.5.1.2.3. Forwarding demand

"1" is set to ST of the DMACA register.




14.5.1.2.4. Timing chart

Figure14-3The timing chart of burst transfer of ..peel.. , is shown.

Figure14-3Burst transfer(For BC=1(h) and TC=1(h). )

HCLK

HADDR

HWRITE

Control

DMACA[31:24]

HWDATA

HRDATA

HBUSREQ

HGRANT

HREADY

HRESP

HMASTER other DMAC other

OK

SA DA SA DA SA DA

HTRANS N N N N N I N

Data Data Data

Data Data Data

0x00 0xA0

DMACA[19:16] 0x0 0x1 BC

0x00

0x0 0x1 0x0

DMACA[15:0] 0x0 0x1

TC 0x0

SA DA

N N

Data

Data




14.5.2. Beat forwarding DMAC supports the beat forwarding. The beat forwarding means Incrementing/ Wrapping Burst of AMBA specification. DMAC has 64 bytes FIFO of all channel sharing, and enables a consecutive source access and the destination access. The type of the beat forwarding is set by the BT bit of the DMACA register. The relation between the BT bit of the DMACA register and HBURST of AHB is following.

Table14-1DMACA/BT and HBURST

DMACA/BT Beat transfer type HBURST DMACA/MS (mode select)

Block Burst

0000(b) NORMAL SINGLE OK OK

1000(b) SINGLE SINGLE OK OK

1001(b) INCR INCR OK OK

1010(b) WRAP4 WRAP4 OK OK

1011(b) INCR4 INCR4 OK OK





14.5.3. Error DMAC supports the error reply from the AHB slave.

14.5.3.1. AHB slave error When the error reply is received from the AHB slave while DMAC is forwarding DMA, DMAC stops forwarding at once while even forwarding DMA. In this case, neither the Block/transfer count register nor the Source/destination address register are updated.

14.6. Use example



14.6. Use example

14.6.1. DMA beginning with single channel Example of block transfer by software request

Specifying source address DMACSA0 ← 0000_0000(h)

Specifying destination address DMACDA0 ← 0100_0000(h)

Specifying transfer data width and completion interrupt, etc.

DMACB0 ← 0808_0000(h)

Specifying transfer control of DMA channel, software trigger, number of block, and number of transfer, etc.

DMACA0 ← A00F_000F(h)

Enable of DMA transfer DMACR ← 8000_0000(h)

DMA transfer start

Please set the DMACA register at the end at the software request. Moreover, please set the DMACR register by writing Byte.

15.1. Outline


Memory Controller (MEMC) FUJITSU SEMICONDUCTOR CONFIDENTIAL 359

15. Memory Controller (MEMC) This chapter explains MemoryControler of the GDC macro (henceforth MEMC).

15.1. Outline The GDC macro provides with the external bus memory interface that can be connected with SRAM or NOR Flash. It explains the feature and the limitations of the MEMC module as follows.

15.1.1. Feature The MEMC module has the following features. Correspondence chip selection 0 (MEM_XCS0) It is = 64M Byte or chip selection 0

(MEM_XCS0) It is = 32M Byte and chip selection 1(MEM_XCS1) It is = 64M Byte or less It is 32 M Byte.

It corresponds to SRAM and NOR Flash of the width of eight bits (Or, 16 bits). Two chip selections (MEM_XCS(0/1)) are installed in the external bus memory interface. The separate setting is possible at each chip selection (MEM_XCS(0/1)). It corresponds to page access of NOR Flash.

15.1.2. Limitations It is necessary to set 64M Byte with MEM_XCS0 by GCONT register ADCS bit (bit0) of the MCNT

module when corresponding. (Please refer to "Chapter 19.4.2.5 GCONT Register" of the MCNT module and "Chapter 19.5.3.1 outside bus memory interface control signal switch" for a detailed content. )

64M Byte is used with MEM_XCS0 and MEM_XCS1 cannot be used when corresponding. It is not possible ..MEM_XCS1.. to correspond to 64M Byte. Please set PULL-UP or PULL-DWN to the terminal MEM_ED by the PPCR01 register and the

PPER01 register of FR81S when you use the MEMC module. (Please refer to "Chapter 5.1.1 GDC access sequence" for the timing of the setting. )

15.2. Composition



15.2. Composition

15.2.1. Block diagram The block diagram of the MEMC module is shown in the following.

Figure15-1Block diagram of MEMC module

15.2.2. External terminal Table15-1External interface terminal

LSI outside terminal name

Terminal name I/O Function

P056 MEM_EA[24]

P055 MEM_EA[23]

P054 MEM_EA[22]

P053 MEM_EA[21]

P052 MEM_EA[20]

P051 MEM_EA[19]

P050 MEM_EA[18]

P047 MEM_EA[17]

P046 MEM_EA[16]

P045 MEM_EA[15]

P044 MEM_EA[14]

P043 MEM_EA[13]

P042 MEM_EA[12]

O Address bus

P041 MEM_EA[11] O Address bus

15.2. Composition



LSI outside terminal name

Terminal name I/O Function

P040 MEM_EA[10]

P047 MEM_EA[9]

P036 MEM_EA[8]

P035 MEM_EA[7]

P034 MEM_EA[6]

P033 MEM_EA[5]

P032 MEM_EA[4]

P031 MEM_EA[3]

P030 MEM_EA[2]

P027 MEM_EA[1]

P026 MEM_EA[0]

P020 MEM_XWR O The write is enable.

P023 MEM_XRD O The read is enable.

P021 MEM_XCS0 O Chip selection 0

P022 MEM_XCS1/MEM_EA[25] OChip selection 1/address bus(*1)

P017 MEM_ED[15]

P016 MEM_ED[14]

P015 MEM_ED[13]

P014 MEM_ED[12]

P013 MEM_ED[11]

P012 MEM_ED[10]

P011 MEM_ED[9]

P010 MEM_ED[8]

P007 MEM_ED[7]

P006 MEM_ED[6]

P005 MEM_ED[5]

P004 MEM_ED[4]

P003 MEM_ED[3]

P002 MEM_ED[2]

P001 MEM_ED[1]

P000 MEM_ED[0]

IO Data bus(*2)

P057 MEM_RDY I Lady input for low-speed device(*3)

(*1) The terminal MEM_XCS1 can be used as MEM_EA 25 terminal. SRAM or NOR Flash of 64M Byte

or less can be connected by using it as MEM_EA 25 terminal. GCONT register (01FB_2500H) of the MCNT module when it uses it as MEM_EA 25 terminal Please set the ADCS bit to one.

(*2) Please set PULL-UP or PULL-DWN to the terminal MEM_ED by the PPCR01 register and the PPER01 register of FR81S. (Please refer to "Chapter 5.1.1 GDC access sequence" for the timing of the setting. )

(*3) Please connect "H" when unused.

15.3. Register



15.3. Register

15.3.1. Description form of register The register of the endian this module corresponds to the little endian. Please add Base Address(0040_0000H) when Base addressFR81S(CPU) accesses it.

The bit number of the Bit register is shown. The bit field name of the Name register is shown. Reserved is shown by "-". The attribute of read/write of the R/W each bit field is shown. R0: The read value is always "0. "R1:



15.3.2. Register list Table15-2Register list


01FB_3000H MCFMODE0 Mode register of SRAM and NOR Flash in MEM_XCS0

01FB_3004H MCFMODE1 Mode register of SRAM and NOR Flash in MEM_XCS1

01FB_3020H MCFTIM0 Timming register of SRAM and NOR Flash in MEM_XCS0

01FB_3024H MCFTIM1 Timming register of SRAM and NOR Flash in MEM_XCS1

01FB_3040H MCFAREA0 Access area register of SRAM and NOR Flash in MEM_XCS0

01FB_3044H MCFAREA1 Access area register of SRAM and NOR Flash in MEM_XCS1

01FB_3200H MCERR Interrupt error in MEMC

15.3. Register



15.3.3. MCFMODE0/1(Memory Controller Flash MODE 0/1)

Address 01FB_3000H (MEM_XCS0) 01FB_3004H (MEM_XCS1)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Name - R/W R/W0 Initial X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - RDY PAGE - WDTH

R/W R/W0 R/W R/W R/W0 R/WInitial X 0 0 X 1

bit field

No name Explanation

0 WDTH

(data WiDTH)

This bit specifies the width of the data bus of the connected device.

WDTH Data width of external BUS memory0 8bit 1 16bit

5 PAGE

(PAGE access mode)

This bit controls page access mode of NOR Flash. In NOR Flash page access mode, the first address cycle is issued according to the setting of the FRADC bit of the MCFTIM0/1 register. Afterwards, the access is executed continuously until it reaches 16 byte boundary according to the setting of the RACC bit of the MCFTIM0/1 register. Please set the RADC bit of the MCFTIM0/1 register to "0" when you select this mode.

PAGE Page access mode of NOR Flash 0 OFF 1 ON

6 RDY

(ReaDY mode)

When a low-speed device and handshaking are done using the MEM_RDY signal, this bit is set to one. Please assert the MEM_RDY signal from Taori of chip select signal (MEM_XCS(0/1)) to one cycle (GSSCGCLK) or less and assert it to "L". Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ

かりません。Please refer to". ) Please set this bit to "0" when you do not use the MEM_RDY signal like SRAM.

RDY Ready mode 0 OFF 1 ON

Attention: Please write "0" in Reserved bit("-"). When "1" is written, the operation of this module is not

guaranteed.

15.3. Register



15.3.4. MCFTIM0/1(Memory Controller Flash TIMming 0/1)

Address 01FB_3020H (MEM_XCS0) 01FB_3024H (MEM_XCS1)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Name WIDLC[3:0] WEC[3:0] WADC[3:0] WACC[3:0] R/W R/W R/W R/W R/W Initial 0H 5H 5H FH

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name RIDLC[3:0] FRADC[3:0] RADC[3:0] RACC[3:0] R/W R/W R/W R/W R/W Initial FH 0H 0H FH

bit field

No name Explanation

3-0 RACC[3:0]

(Read ACcess Cycle)

This bit sets necessary cycle (GSSCGCLK) number for the read access. Data is fetched at the final cycle though the address doesn't change during the cycle specified by this bit. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ

かりません。Please refer to". )

RACC Cycle(GSSCGCLK)0H 1 Cycle | |

FH 16 Cycle

7-4 RADC[3:0]

(Read ADdress setup Cycle)

This bit sets cycle (GSSCGCLK) of the read address setup number. The values specified here should be ranges of read access cycle number. Please set this bit to "0" when NOR Flash page access mode (PAGE bit of the MCFMODE0/1 register) is used. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ


RADC Cycle(GSSCGCLK)0H 0 Cycle | |

FH 15 Cycle

11-8 FRADC[3:0] (First Read

ADdress Cycle)

This bit is exclusively used for the setting of NOR Flash that corresponds to the page mode access. This bit sets initial latency in the address in the read access of NOR Flash. When the values other than "0" are set to this bit, "0" is specified for the RADC bit. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ


FRADC Cycle(GSSCGCLK)0H 0 Cycle | |

FH 15 Cycle

bit field Explanation

15.3. Register



No name

15-12 RIDLC[3:0] (Read IDLe

Cycle)

This bit sets idol cycle number after the read is accessed. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ


RIDLC Cycle(GSSCGCLK)0H 1 Cycle | |

FH 16 Cycle

19-16 WACC[3:0]

(Write ACcess Cycle)

This bit specifies cycle necessary for the write access number. This value should be larger than the total in which the WADC bit is added to the WEC bit. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ


WACC Cycle(GSSCGCLK)0H Reserved 1H Reserved 2H 3 Cycle | |

FH 16 Cycle

23-20 WADC[3:0]

(Write ADdress setup Cycle)

This bit sets cycle of the write access setup number. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ


WADC Cycle(GSSCGCLK)0H 1 Cycle | |

EH 15 Cycle FH Reserved

27-24 WEC[3:0]

(Write Enable Cycle)

This bit sets cycle of an enable write number. The setting of this bit also influences MEM_XWR. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ


WEC Cycle(GSSCGCLK)0H 1 Cycle | |


31-28 WIDLC[3:0] (Write IDLe

Cycle)

This bit sets idol cycle number after the write is accessed. Please specify the value more than "2" when the RDY bit is set to "1". Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ


WIDLC Cycle(GSSCGCLK)0H 1 Cycle | |

FH 16 Cycle

15.3. Register



15.3. Register



15.3.5. MCFAREA0/1(Memory Controller Flash AREA 0/1)

Address 01FB_3040H (MEM_XCS0) Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - MASK[6:0] R/W R/W0 R/W Initial X 1FH

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - ADDR[7:0] R/W R/W0 R/W Initial X 20H

Address 01FB_3044H (MEM_XCS1)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Name - MASK[6:0] R/W R/W0 R/W Initial X 1FH

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - ADDR[7:0] R/W R/W0 R/W Initial X 40H

bit field

No name Explanation

7-0 ADDR[7:0] (ADDRess)

This bit specifies the first address in the corresponding chip selection area. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ

かりません。Please refer to". ) Limitations

Please set 20H to the first address of MEM_XCS0 (01FB_3040H). Because the trigger start of the CMDSEQ module doesn't operate normally when the addresses other than 20H are set, it becomes outside the operation guarantee. When the trigger start of the CMDSEQ module is not used, it is not necessary to fix to 20H.

15.3. Register



bit field

No name Explanation

22-16 MASK[6:0]

(address MASK)

This bit sets the memory size (area) to the address set to the ADDR bit. Details are ("エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ

かりません。" and "エラー! 参照元が見つかりません。Chapter エラー! 参照

元が見つかりません。Please refer to". ) The relation between MASK bit and size of the memory is shown as follows.

MASK Memory size 1FH 32M Byte 0FH 16M Byte 07H 8M Byte 03H 4M Byte 01H 2M Byte 00H 1M Byte

Other Prohibition Limitations

It can normally access the external bus memory when MASK bit = Other (set prohibition) is set and it becomes outside the operation guarantee of the hatchet.


guaranteed. Please set not to come in succession two chip selection (MEM_XCS(0/1)) areas set by the ADDR bit

and the MASK bit. When the chip selection area comes in succession, it becomes an external bus memory outside the operation guarantee because it is normally inaccessible.

15.3. Register



15.3.6. MCERR(Memory Controller ERRor)

Address 01FB_3200H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W R/W0 Initial X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - SFION - SFER

R/W R/W0 R/W R R/WInitial X 0 0 0

bit field

No name Explanation

0 SFER

(Sram nor Flash access ERror)

This bit shows that the access was executed to the area where the mapping of the external bus memory is not done. This module notifies the MCNT module error interruption (Error INT) when the error is detected and sets Error(1) to this bit. The error of this bit can be cleared by writing "1".

SFER Access error 0 No error 1 Error

2

SFION (Sram nor Flash

access error Interrupt ON)

This bit controls interruption information output to INTST register INT26 bit of the MCNT module.

SFION Interrupt output control 0 OFF 1 ON


guaranteed.




15.4. Operation explanation The MEMC module provides with the area of 64M Byte or less and it provides with chip select signal (MEM_XCS(0/1)) of two possession. The corresponding device becomes SRAM and NOR Flash in eight bits (Or, 16 bits). It explains each function as follows.

15.4.1. Endian In the GDC macro, both registers and the external bus memories of the MEMC module become the correspondences only of the little endian. Therefore, please write it in the little endian when writing it in external bus memory (NOR Flash) with the read-only memory writer etc.The operation of the GDC macro becomes outside the guarantee when writing it with Biccendian. The image chart when NOR Flash is read from writing and GDC AHB of 16bit 32M Byte NOR Flash is shown below. In the following image chart, the memory area of MEM_XCS0 is assumed to be 0200_0000H-03FF_FFFFH.

Figure15-2 Endian of NOR Flash




15.4.2. External bus memory mode The external bus memory mode is width of the data bus of the device connected with the external bus memory, accesses NOR Flash the page, and can control a low-speed device. This control can be set with MEM_XCS0=01FB_3000H and MCFMODE0/1 register (MEM_XCS1=(01FB_3004H). Please set this setting before accessing the external bus memory. (Please refer to "Chapter 5.1.1 GDC access sequence" for the timing of the setting. )

15.4.2.1. Width of data bus The width of the data bus of the device connected with each chip selection in the external bus memory interface (8 bits or 16 bits) is specified. This setting is set by the WDTH bit of the MCFMODE0/1 register. Table15-3 Data width of external BUS memory

MCFMODE0/1 Register

WDTH(bit0)

Data width of external BUS memory

0 8bit 1 16bit (Default)

15.4.2.2. Page access mode Page access mode controls page access of NOR Flash. In NOR Flash page access mode, the first address cycle is issued according to the setting of the FRADC bit of the MCFTIM0/1 register. Afterwards, the access is executed continuously until it reaches 16 byte boundary according to the setting of the RACC bit of the MCFTIM0/1 register. Please set the RADC bit of the MCFTIM0/1 register to "0" when you select this mode. This control is set by the PAGE bit of the MCFMODE0/1 register. Table15-4 Page access mode of NOR Flash

MCFMODE0/1 RegisterPAGE(bit1)

Page access mode of NOR Flash

0 OFF (Default) 1 ON

Figure15-3 Page read of 16bit NOR Flash




15.4.2.3. Lady mode The MEMC module has the interface function with a low-speed device and the terminal MEM_RDY. To use this function, the RDY signal of a low-speed device is connected with the terminal MEM_RDY of this LSI. This control is set by the RDY bit of the MCFMODE0/1 register. Please note the following points when you use the lady mode.

This function cannot be applied to the RDY/BUSY signal of NOR Flash. When two low-speed devices are used so that there is only one, it is necessary to process the terminal

MEM_RDY with an external AND circuit. The connection example is ("15.5.4ChapterLow Speed PeripheralPlease refer to". )

The RDY signal of a low-speed device should be Wait(="L") and be Ready(="H"). When the access that exceeds the width of the data bus of a low-speed device (The example: word (32

bits) access to 16 bit device) is executed, it is executed continuously, and a low-speed device is accessed about "Reading → reading and writing → writing" until all the excess bits are covered. In this case, the MEM_XCS(0/1) signal is not negated regardless of the setting in the middle of the access of "Reading → reading and writing → writing".

It is necessary to assert to one cycle (GSSCGCLK) or less from Taori of the MEM_XCS(0/1) signal the setting of the MEM_RDY signal to "L" and to assert it to "L".

Please set "0" to the RDY bit of the corresponding chip selection for the device (for instance, SRAM memory etc.) that doesn't use the RDY function.

Operation when RDY becomes "L" or "H" pulse during the access cycle is not warrantable. When the device that uses negating of the MEM_XCS(0/1) signal is used, it is necessary to access it

by the width or less of the target. When the RDY signal is "H" state of beginning of the access, a usual SRAM access is done to the

access in a similar way. Table15-5 Ready mode

MCFMODE0/1 Register

RDY(bit2) Ready mode

0 OFF (Default)

1 ON The reading shape of waves from a low-speed device is shown below.

Figure15-4 Read access from low speed device




The writing shape of waves to a low-speed device is shown below.

- 000

D00

Within one cycle

GSSCGCLK

MEM_EA[24:1]

MEM_ED[15:0]

MEM_XRD

MEM_XWR

MEM_XCS(0/1)

-

MEM_RDY

Write Address Setup Cycle (WADC)From rising edge of MEM_RDY to rising edge of MEM_XWR (4Cycle)

Figure15-5 Write access to low speed device




15.4.3. External bus memory timing control The external bus memory timing control controls the reading timing and the writing timing of each control signal of the device connected with the external bus memory. This control can be set with MEM_XCS0=01FB_3020H and MCFTIM0/1 register (MEM_XCS1=(01FB_3024H). Please set this setting before accessing the external bus memory. (Please refer to "Chapter 5.1.1 GDC access sequence" for the timing of the setting. )

15.4.3.1. Reading timing control The reading timing control is controlled by the RACC bit of the MCFTIM0/1 register, the RADC bit, the FRADC bit, and the RIDLC bit.

15.4.3.1.1. Read access cycle

Cycle (GSSCGCLK) necessary for the read access number is set at read access cycle (RACC). This control is set by the RACC bit of the MCFTIM0/1 register. Table15-6 Read Access Cycle

MCFTIM0/1 RegisterRACC(bit3-0)

Cycle(GSSCGCLK)

0H 1 Cycle | |

FH 16 Cycle (Default) The shape of waves at read access cycle (RACC) is shown below.

Figure15-6 Read Access Cycle (RACC)




15.4.3.1.2. Read address setup cycle

Cycle (GSSCGCLK) of the setup of the read address of MEM_XRD number is set at read address setup cycle (RADC). After the number the cycle set by the RADC bit based on the standing fall of MEM_XCS(0/1), MEM_XRD is asserted. This control is set by the RADC bit of the MCFTIM0/1 register. Please note the following points when you use RADC. The values specified by the RADC bit should be ranges of read access cycle (RACC) number. Please set this bit to "0" when NOR Flash page access mode (PAGE bit of the SRAM/Flash mode 0/1

register) is used. Table15-7 Read Address Setup Cycle

MCFTIM0/1 RegisterRADC(bit7-4)

Cycle(GSSCGCLK)

0H 0 Cycle (Default) | |

FH 15 Cycle The shape of waves at read address setup cycle (RADC) is shown below.

Figure15-7 Read Address Setup Cycle (RADC)




15.4.3.1.3. The first read address cycle

Initial latency in address (MEM_EA) in page access of NOR Flash is set at first read address cycle (FRADC). Only when the first accessing it, the address is maintained by cycle (GSSCGCLK) specified here number. The access afterwards is executed according to cycle set to the RACC bit number. When the page is accessed, MEM_XCS(0/1) and MEM_XRD are asserted at the same time. When the values other than "0" are set to this bit, "0" is specified for the RADC bit. This control is set by the FRADC bit of the MCFTIM0/1 register. Table15-8 First Read Address Cycle

MCFTIM0/1 RegisterFRADC(bit11-8)

Cycle(GSSCGCLK)


FH 15 Cycle The shape of waves at first read address cycle (FRADC) is shown below.

Figure15-8 First Read Address Cycle (FRADC)




15.4.3.1.4. Read idol cycle

Idol cycle (GSSCGCLK) number after the read is accessed is set at read idol cycle (RIDLC). This bit is used to prevent the data collision that happens because of the write access immediately after the access of the read. This control is set by the RIDLC bit of the MCFTIM0/1 register. Table15-9Read Idle Cycle

MCFTIM0/1 RegisterRIDLC(bit15-12)

Cycle(GSSCGCLK)

0H 1 Cycle | |

FH 16 Cycle (Default) The shape of waves at the read idol cycle is shown below.

Figure15-9 Read Idle Cycle (RIDLC)




15.4.3.2. Writing timing control The writing timing control is controlled by the WACC bit of the MCFTIM0/1 register, the WADC bit, the WEC bit, and the WIDLC bit.

15.4.3.2.1. Write access cycle

Cycle (GSSCGCLK) necessary for the write access number is set at write access cycle (WACC). The address doesn't change during the cycle specified in this bit. This control is set by the WACC bit of the MCFTIM0/1 register. Table15-10Write Access Cycle

MCFTIM0/1 RegisterWACC(bit19-16)

Cycle(GSSCGCLK)

0H Reserved 1H Reserved 2H 3 Cycle | |

FH 16 Cycle (Default) The shape of waves at the write access cycle is shown below.

Figure15-10 Write Access Cycle (WACC)




15.4.3.2.2. Write address setup cycle

Cycle (GSSCGCLK) of WADC number is set at write address setup cycle (WADC). After the number the cycle set by the WADC bit based on the standing fall of the MEMXCS(0/1) signal, the MEM_XWR signal is asserted. This control is set by the WADC bit of the MCFTIM0/1 register. Table15-11 Write Address Setup Cycle

MCFTIM0/1 RegisterWADC(bit23-20)

Cycle(GSSCGCLK)

0H 1 Cycle | |



The shape of waves at the write address setup cycle is shown below.

Figure15-11 Write Address Setup Cycle (WADC)




15.4.3.2.3. Write enable cycle

Enable cycle (GSSCGCLK) of the MEM_XWR signal number is set at write enable cycle (WEC). This control is set by the WEC bit of the MCFTIM0/1 register. Table15-12Write Enable Cycle

MCFTIM0/1 RegisterWEC(bit27-24)

Cycle(GSSCGCLK)

0H 1 Cycle | |



The shape of waves at a write enable cycle is shown below.

Figure15-12 Write Enable Cycle (WEC)




15.4.3.2.4. Write idol cycle

Idol cycle (GSSCGCLK) number after the write is accessed is set at write idol cycle (WIDLC). Please specify the value of three cycles or more when the RDY bit of the MCFMODE0/1 register is set to "1". This control is set by the WIDLC bit of the MCFTIM0/1 register. Table15-13Write Idle Cycle

WCFTIM0/1 RegisterWIDLC(bit31-28)

Cycle(GSSCGCLK)


FH 16 Cycle The shape of waves at the write idol cycle is shown below.

Figure15-13 Write Idle Cycle (WIDLC)




15.4.4. External bus memory area The MEMC module installs two chip selections (MEM_XCS(0/1)) and provides with the address space of 64M Byte in the maximum. (Only chip selection 0(MEM_XCS0) can correspond to 64M Byte by using GCONT register ADCS bit of the MCNT module. However, the area of chip selection 1(MEM_XCS1) cannot be used in this case. ) This control can be set by MCFAREA0/1 register (MEM_XCS0=01FB_3040H, MEM_XCS1=01FB_3044H). The area of each chip selection (MEM_XCS(0/1)) is decided by the ADDR bit and the MASK bit. Details are (Please refer to "Chapter15.4.4.3 Chip selection area setting" ) Please set this setting before accessing the external bus memory. (Please refer to "Chapter 5.1.1 GDC access sequence" for the timing of the setting. )

15.4.4.1. The first address First address (ADDR) of (MEM_XCS(0/1)) is specified at each chip selection. 0200_0000H specification of external bus memory of GDC macro area to 05FF_FFFFH (Please refer to "Chapter 4 memory map" for details of the memory map. ) As for the ADDR bit, a set value is limited by the MASK bit based on 20H. Details are ("Table15-14 Setting top address of MEM_XCS areaPlease refer to". ) The setting of the first address is set by the ADDR bit of the MCFAREA0/1 register. Table15-14 Setting top address of MEM_XCS area

MCFAREA0/1 Register MASK(bit22-16) ADDR(bit7-0)

Setting top address of MEM_XCS area

40H 0400_0000H (MEM_XCS1:Default) 1FH (32M Byte)

20H 0200_0000H (MEM_XCS0:Default) 50H 0500_0000H 40H 0400_0000H 30H 0300_0000H

0FH (16M Byte)

20H 0200_0000H (MEM_XCS0:Default) 58H 0580_0000H 50H 0500_0000H 48H 0480_0000H 40H 0400_0000H (MEM_XCS1:Default) 38H 0380_0000H 30H 0300_0000H 28H 0280_0000H

07H (8M Byte)

20H 0200_0000H (MEM_XCS0:Default) 5CH 05C0_0000H 58H 0580_0000H 54H 0540_0000H 50H 0500_0000H

| | 2CH 02C0_0000H 28H 0280_0000H 24H 0240_0000H

03H (4M Byte)

20H 0200_0000H (MEM_XCS0:Default)




MCFAREA0/1 Register

MASK(bit22-16) ADDR(bit7-0) Setting top address of MEM_XCS area

5EH 05E0_0000H 5CH 05C0_0000H 5AH 05A0_0000H

| | 2EH 02E0_0000H 2CH 02C0_0000H 2AH 02A0_0000H 28H 0280_0000H 26H 0260_0000H 24H 0240_0000H 22H 0220_0000H

01H (2M Byte)

20H 0200_0000H (MEM_XCS0:Default) 5FH 05F0_0000H 5EH 05E0_0000H

| | 2FH 02F0_0000H 2EH 02E0_0000H 2DH 02D0_0000H 2CH 02C0_0000H 2BH 02B0_0000H 2AH 02A0_0000H 29H 0290_0000H 28H 0280_0000H 27H 0270_0000H 26H 0260_0000H 25H 0250_0000H 24H 0240_0000H 23H 0230_0000H 22H 0220_0000H 21H 0210_0000H

00H (1M Byte)

20H 0200_0000H (MEM_XCS0:Default) Notes: ..ADDR bit.. "Table15-14 Setting top address of MEM_XCS areaIt ..".. ..external bus memory..

normally becomes outside access and the operation guarantee when setting it to the value other than. Please set 20H to the first address of MEM_XCS0 (01FB_3040H) when you use the trigger start of

the CMDSEQ module. Because the trigger start of the CMDSEQ module doesn't operate normally when the addresses other than 20H are set, it becomes outside the operation guarantee. When the trigger start of the CMDSEQ module is not used, it is not necessary to fix to 20H. (Please refer to "Chapter 11.5.2.2 trigger start" of the CMDSEQ module for details of the trigger start. )

Please set 20H to the first address when you use MEM_XCS0 in the area of 64M Byte. Because it cannot normally access the external bus memory when the first addresses other than 20H are set, it becomes outside the operation guarantee.

Each MEM_XCS must be set, and the area of two chip selections used must set the ADDR bit and the MASK bit as not coming in succession. When the area of the chip selection comes in succession, it becomes an external bus memory outside the operation guarantee because it is normally inaccessible.




15.4.4.2. Memory size Memory size (MASK) to the ADDR bit of (MEM_XCS(0/1)) is set at each chip selection. In the MEMC module, the access begins to the external bus memory when the access of the chip selection set by the ADDR bit and the MASK bit to the area is judged and it corresponds when it accesses the external bus memory from mastering. Details are (Please refer t "Chapter15.4.4.3 Chip selection area setting" ) The setting of the memory size is set by the MASK bit of the MCFAREA0/1 register. Table15-15 Memory size

MCFAREA0/1 Register

MASK(bit22-16) Memory size

1FH 32M Byte (Default)0FH 16M Byte 07H 8M Byte 03H 4M Byte 01H 2M Byte 00H 1M Byte

Other Prohibition Notes: Because the MASK bit cannot be normally accessed to the external bus memory when Other is set, it

becomes outside the operation guarantee. Please MEM_XCS0 and set 32M Byte(1FH) ..MEM_XCS1.. both with 64M Byte MEM_XCS0 the

MASK bit when it uses it. Because it cannot normally access the external bus memory when setting it excluding 32M Byte, it becomes outside the operation guarantee.

Each MEM_XCS must be set, and the area of two chip selections used must set the ADDR bit and the MASK bit as not coming in succession. When the area of the chip selection comes in succession, it becomes an external bus memory outside the operation guarantee because it is normally inaccessible.




15.4.4.3. Chip selection area setting The chip selection area of the external bus memory is set by bit and ADDR 7:0 MASK 6:0 the bits of MCFAREA0 register (01FB_3040H) and MCFAREA1 register (01FB_3044H). ADDR 7:0 bit specifies the first address for (MEM_XCS0, MEM_XCS1) at each chip selection of the external bus memory. MASK 6:0 bit specifies the area (memory size) to the first address specified in ADDR 7:0 bit. In the MEMC module, the internal bus mask address is generated with bit and ADDR 7:0 MASK 6:0 the bits. Moreover, the external bus mask address is generated with accessed address (Access address) from each mastering and MASK 6:0 bit. The access begins for corresponding MEM_XCS(0/1) when these each bus mask addresses are compared and it agrees. The use example (bus mask address agreement/disagreement) is shown as follows. It is 0200_0000H in the example of the following as for the external bus memory area of MEM_XCS0 - It is assumed 03FF_FFFFH (32M Byte). (example 1)Bus mask address agreement

MCFAREA0 (01FB_3040H setting value ..<.. .... > ADDR 7:0 bit = 0010_0000B (0200_0000H is set. ) MASK 6:0 bit = 001_1111B (32M Byte is set. )

< address that mastering accesses external bus memory > Access address[31:0]= 0200_0004H (access request of 0200_0004H)

With 0010_0000 internal bus mask address = B 0010_0000 external bus mask address = B The access begins to 0200_0004H house number of the external bus memory because it compares and it agrees.




(example 2)Bus mask address disagreement

MCFAREA0/1 ..setting.. value < > ADDR 7:0 bit = 0010_0000B (0200_0000H is set. ) MASK 6:0 bit = 001_1111B (32M Byte is set. )

< address that mastering accesses external bus memory > Access address[31:0]= 0400_0000H (access request of 0400_0000H)

With 0010_0000 internal bus mask address = B 0100_0000 external bus mask address = B It doesn't access the external bus memory because it compares and it becomes a disagreement.




15.4.5. Error interruption In the MEMC module, the error interruption that shows that the access was executed to the area where the mapping is not done in the external bus memory is installed.

15.4.5.1. Access error In the MEMC module, the SRAM/NOR Flash access error notification function to show that the access was executed to the area where the mapping is not done in the external bus memory is installed. This error is notified by the SFER bit of the MCERR register. The error of this bit can be cleared by writing one. Table15-16 Access error

MCERR RegisterSFER (bit0)

Access error

0 No error 1 Error

15.4.5.2. Interruption output control In the MEMC module, the function to notify the MCNT module the above-mentioned access error information is installed. This interruption output control can be set by the SFION bit of the MCERR register. Table15-17 Interrupt output control

MCERR RegisterSFION (bit2)

Interrupt output control

0 OFF 1 ON

Figure15-14Interrupt output to MCNT module




15.4.6. External bus memory access In the external bus memory access, MEM_XCS(0/1) is selected by one access. When the access is demanded by width of the data bus that is wider than the width of the data bus of the target device, the access is converted into a continuous access. In a continuous access, MEM_XCS(0/1) is fixed to L, and the address is changed. For instance, 32 bit read access changes, the address changes with 0->2 when there is a demand from an internal bus for the target device of the width of 16 bits with MEM_XCS(0/1) fixed to "L", and data is fetched continuously from MEM_ED 15:0 according to the transition timing. When there is an access request in width a data bus data bus of the target of the device that is narrower than that of width (for instance, byte access to the target device in 16 bits), it writes and byte access is executed by controlling the MEM_XWR signal when operating. (The MEMC module outputs only necessary data. ) Notes: The above-mentioned explanation becomes reading reading and writing/NOR Flash of SRAM. Please

do the access matched to the width of the data bus of the target device to writing NOR Flash. It is not possible to write it normally when accessing it by width of the data bus different from the target device.

Figure15-15 External BUS memory access




15.4.7. Trigger start of GDC macro The GDC macro can use the trigger start using the CMDSEQ module. The trigger start should write the arrangement address of Command List (first address) at the address where NOR Flash (MEM_XCS0) was decided. Moreover, when the reset start that is one function of the trigger start is used, it is necessary to set the MEMC module in the beginning of Command List. (It is not necessary to set it when there is no problem like the first stage value of MEMC. ) Please note the following points when you use this function. Please set ADDR 7:0 bit of MEM_XCS0 (MCFAREA0 register) to 20H. The trigger start doesn't

operate normally when setting it excluding 20H. (An initial value is 20H. ) Command List for the reset start must settle within MEM_XCS0 when you use the reset start. The

address space with MEM_XCS0 is empty or arrange it, please when extending over MEM_XCS1. Please ..(.. refer to the arrangement of the command list for Chapter 5.1.7 reset start for details. The example of setting 16 bits 64M Byte NOR Flash is shown as follows.

(1) The signal of the control of the external bus memory of the MEMC module switch is set. GCONT register (01FB_2500H) of the MCNT module Please set the ADCS bit to one.

(2) The width of the data bus of the device connected with MEM_XCS0 is specified. MCFMODE0 register (01FB_3000H) of the MEMC module Please set the WDTH bit to one.

(3) A set address in the chip selection area corresponding to MEM_XCS0 is specified. MCFMODE0 register (01FB_3040H) of the MEMC module Please set it to 20 ADDR bit = H and 1 MASK bit = FH.

(4) The width of the data bus of the device connected with MEM_XCS1 is specified. MCFMODE1 register (01FB_3004H) of the MEMC module Please set the WDTH bit to one.

(5) A set address in the chip selection area corresponding to MEM_XCS1 is specified. MCFMODE1 register (01FB_3044H) of the MEMC module Please set it to 40 ADDR bit = H and 1 MASK bit = FH.

Notes: Please set 0200_0000H to a set address in the chip selection area of MEM_XCS0. Please arrange the area of MEM_XCS0 in no excess about CMDLIST of the reset start.

15.5. Connection example




15.5.1. Eight bit 32M Byte SRAM/NOR Flash The example of connecting eight bits 32M Byte SRAM/NOR Flash is shown as follows. Eight bits (Or, 16 bits) Please note the following points when you connect SRAM or NOR Flash of 32M Byte. Please set PULL-UP or PULL-DWN to the terminal MEM_ED by the PPCR01 register and the

PPER01 register of FR81S. (Please refer to "Chapter 5.1.1 GDC access sequence" for the timing of the setting. )

Please connect "H" with the terminal MEM_RDY. The chip selection must use MEM_XCS0 when you use the trigger start of the CMDSEQ module. Please set the ADDR bit of MCFAREA0 register (01FB_3040H) to 20H when you use the trigger start

of the CMDSEQ module. Please set the ADDR bit of MCFAREA1 register (01FB_3044H) to 1FH when you use the trigger start

of the CMDSEQ module. Moreover, please set 0H to the MASK bit. (Please refer to "Chapter 11.5.2.2 trigger start" for the trigger start of the CMDSEQ module. )

Figure15-16Connected chart of eight bits 32M Byte SRAM/NOR Flash




15.5.2. 16 bit 32M Byte SRAM/NOR Flash x2 The example of connecting 16 bits 32M Byte SRAM/NOR Flash is shown as follows. Please note the following points when you connect SRAM or two NOR Flash in 16 bits 32M Byte. Please set PULL-UP or PULL-DWN to the terminal MEM_ED by the PPCR01 register and the


Please set 20H to the ADDR bit of MCFAREA0 register (01FB_3040H). Please set 40H to the ADDR bit of MCFAREA1 register (01FB_3044H). Please set 20H to the ADDR bit by MCFAREA0 register (01FB_3040H) when SRAM or 2 NOR

Flash in eight bits 32M Byte is connected and the trigger start of the CMDSEQ module is used.

Figure15-17Connected chart of 16 bits 32M Byte SRAM/NOR Flash x2




15.5.3. 16 bit 64M Byte SRAM/NOR Flash 16 bits (Or, eight bits) Please note the following points when you connect SRAM or NOR Flash of 64M Byte. Please set PULL-UP or PULL-DWN to the terminal MEM_ED by the PPCR01 register and the


Please connect MEM_XCS0 with the chip selection. MEM_XCS1 is used as MEM_EA 25 and connect it with address bit 25 of an external device, please. Please set the ADCS bit to 1B by the GCONT(01FB_2500H) register of the MCNT module. Please set 20H to the ADDR bit by the MCFAREA0(01FB_3040H) register, and set 1FH to the

MASK bit. Please set 40H to the ADDR bit by the MCFAREA1(01FB_3044H) register, and set 1FH to the

MASK bit. Please set the same value to both MEM_XCS0 and MEM_XCS1 about each register of other MEMC

modules.

Figure15-18Connected chart of 16 bits 64M Byte SRAM/NOR Flash




15.5.4. Low Speed Peripheral Please note the following points when you connect a low-speed device. Please set PULL-UP or PULL-DWN to the terminal MEM_ED by the PPCR01 register and the


Please connect MEM_RDY with a low-speed device. Please connect the AND circuit with the RDY signal as shown in the figure below when you connect

two low-speed devices.

Figure15-19Connected chart of Low Speed Peripheral

16.1. Outline


SPI Controller (SPICNT) FUJITSU SEMICONDUCTOR CONFIDENTIAL 394

16. SPI Controller (SPICNT) This chapter explains SPI Controller (henceforth SPICNT).

16.1. Outline In this module, there is SPI interface used as SerialFlash memory interface. The SerialFlash memory interface can be used by the Parallel FLASH memory interface and exclusion.

16.2. Feature

The read access from slave read mode GDC macro to the SerialFlash memory region is converted into the SerialFlash memory read protocol.

The manual mode command, the address, and data are individually set to the Command/Address register and the Data register of this module, and the SerialFlash memory is controlled directly.

Master forwarding mode Read

The data of the SerialFlash memory is transmitted to GDC macro by this module. Write

The memory on GDC macro is transmitted to the SerialFlash memory by this module. It corresponds to the SerialFlash memory of SPI FLAH size 128Mbit(16MByte) or less.

16.3. Composition



16.3. Composition

16.3.1. Block diagram Figure16-1The block diagram of and SPICNT is shown.

Figure16-1Block diagram of SPICNT

MB91590 Series

GDC macro

GD

C A

HB

P053

SPI_XCS

SPI_SCK

P056

P055

SPI_DI P054

SPI_DO

16.4. Register



16.4. Register





Address Register name Explanation 01FB_3000H Interrupt Status Register Interruption status register 01FB_3004H Interrupt Permission Register Interruption permission/mask setting register 01FB_3008H Internal Status Register Internal status register 01FB_300CH Control Register Control register 01FB_3010H Command/Address Register Command/address register 01FB_3014H Data1 Register Data1 register 01FB_3018H Data2 Register Data2 register 01FB_301CH Manual Transfer Control Register Manual forwarding control register 01FB_3020H AHB Address Register AHB Address register 01FB_3024H SPI FLASH Address Register SerialFlash Address register 01FB_3028H Master Transfer Control Register Master forwarding control register 01FB_302CH Master Transfer Finish Data Number

Register Master forwarding completion data number register

01FB_3030H Master Transfer Guard Release Register Master forwarding guard release register

16.4. Register




16.4.3.1. Interrupt Status Register This register shows the status of the interruption factor.

Address 01FB_3000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - R/W R Initial 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - ISR_MSTGW ISR_SRSTISS ISR_MNLEND ISR_ERRRESP ISR_MSTEND

R/W R R/W R/W R/W R/W R/W Initial 0 0 0 0 0 0

bit field No name

Explanation

0 ISR_MSTEND This bit shows the forwarding completion of the master forwarding mode. When "1" is written in this bit, interruption information is cleared.

0 There is no interruption. 1 There is an interruption.

1 ISR_ERRRESP This bit shows the internal forwarding error forwarding it in the master forwarding mode. When "1" is written in this bit, interruption information is cleared. When the error reply is received, forwarding is stopped. When the error reply is generated, necessary processing is not done.


2 ISR_MNLEND This bit shows the forwarding completion of the manual mode. When "1" is written in this bit, interruption information is cleared.


3 ISR_SRSTISS This bit shows the soft reset issue. When "1" is written in this bit, interruption information is cleared.


4 ISR_MSTGW It is shown that the master forwarding mode (write) was executed without setting the guard release code.


16.4. Register



16.4.3.2. Interrupt Permission Register

This register sets interruption permission/mask of Interrupt Status Register. When the interruption that sets the interruption mask according to this register is started, the mask stops logical add interruption output to the MCNT module. However, the interruption factor shown in Interrupt Status Register remains.

Address 01FB_3004H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - R/W R Initial 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - IPR_MSTGW IPR_SRSTISS IPR_MNLEND IPR_ERRRESP IPR_MSTEND

R/W R R/W R/W R/W R/W R/W Initial 0 0 0 0 0 0

bit field No name

Explanation

0 IPR_MSTEND This bit controls Interrupt Status Register bit0(ISR_MSTEN), and the logical add to the MCNT module interrupts and to output it, controls.

0 Mask 1 Permission

1 IPR_ERRRESP This bit controls Interrupt Status Register bit1(ISR_ERRRESP), and the logical add to the MCNT module interrupts and to output it, controls.

0 Mask 1 Permission

2 IPR_MNLEND This bit controls Interrupt Status Register bit2(ISR_MNLEND), and the logical add to the MCNT module interrupts and to output it, controls.

0 Mask 1 Permission

3 IPR_SRSTISS This bit controls Interrupt Status Register bit3(ISR_SRSTISS), and the logical add to the MCNT module interrupts and to output it, controls.

0 Mask 1 Permission

4 IPR_MSTGW This bit controls Interrupt Status Register bit4(ISR_MSTGW), and the logical add to the MCNT module interrupts and to output it, controls.

0 Mask 1 Permission

16.4. Register



16.4.3.3. Internal Status Register This register shows forwarding SPICNT.

Address 01FB_3008H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - R/W R Initial 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - MNLBUSY - MSTBUSY

R/W R R R R Initial 0 0 0 0

bit field No name

Explanation

0 MSTBUSY This bit shows forwarding the master forwarding mode. 0 It is not forwarding it by the master forwarding mode. 1 It is forwarding it by the master forwarding mode.

4 MNLBUSY This bit shows forwarding the manual mode to the SerialFlash memory. 0 It is not forwarding it by the manual mode. 1 It is forwarding it by the manual mode.

16.4. Register



16.4.3.4. Control Register

This register controls the issue and byte swap of SerialFlash I/F and soft reset. Address 01FB_300CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - BYTESWAP - SRST - CSHT[4:0] R/W R R/W R R0/W R R/W R/W R/W R/W R/WInitial 0 0 0 0 0 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CLK_PR[3:0] SF_CDIV[3:0] - TEST[1:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W0 R/W0Initial 1 1 1 1 0 0 0 0 0 0 0

bit field No name

Explanation

1-0 TEST[1:0] It is a bit for TEST. Please set this bit field to "00".

11-8 SF_CDIV[3:0] The ratio of dividing frequency of the input clock to the SerialFlash memory is set. SPI_SCK[MHz] = GDCSSCGCLK[MHz]/(SF_CDIV+2) * If the ratio of dividing frequency of the frequency is set to the odd number, the High period of SPI_SCK becomes long.

15-12 CLK_PR[3:0] The period (unit of GDCSSCGCLK) from asserting of the SPI_XCS signal output to the SerialFlash memory to the SPI_SCK operation beginning is set. The period is CLK_PR+1.

20-16 CSHT[4:0] High sets the maintained period (unit of GDCSSCGCLK) when entering from ..asserting.. state the SPI_XCS signal in ..negating.. state. The period is CSHT+1.

24 SRST Soft reset is issued. The data transfer by the manual mode and the master forwarding mode stops when soft reset is issued. Please use it while forwarding it by the manual mode and the master forwarding mode when you want to interrupt the forwarding. This bit is automatically cleared, and "0" is always led.

0 Invalidity 1 Soft reset issue

28 BYTESWAP The replacement of data (byte swap) is set. 0 Setting that risks subordinate position byte to MSB side and

replaces data 1 Setting that risks subordinate position byte to LSB side and

replaces data

16.4. Register



16.4.3.5. Command/Address Register

This register decides the address the command forwarded to the SerialFlash memory. Please set the command and the address when you forward it in the manual mode.

Address 01FB_3010H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CMD[7:0] ADDR[23:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ADDR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bit field No name

Explanation

23-0 ADDR[23:0] The address forwarded to the SerialFlash memory is set. 31-24 CMD[7:0] The command forwarded to the SerialFlash memory is set.

16.4.3.6. Data1 Register

This register sets the writing data to the SerialFlash memory at the manual mode. Moreover, the data that the SerialFlash memory output at the manual mode is stored.

Address 01FB_3014H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name DATA1[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DATA1[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bit field No name

Explanation

31-0 DATA1 [31:0] Data that does the write to the SerialFlash memory is set.

The data that the SerialFlash memory output is stored.

16.4. Register



16.4.3.7. Data2 Register

This register stores the data that the SerialFlash memory outputs at the manual mode. Address 01FB_3018H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name DATA2[31:16] R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DATA2[15:0] R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bit field No name

Explanation

31-0 DATA2 [31:0] The data that the SerialFlash memory output is stored.

16.4.3.8. Manual Transfer Control Register

When the manual command is issued, this register sets the data transmitted to the forwarding size and the SerialFlash memory of the address. Moreover, beginning of forwarding by the manual mode is set.

Address 01FB_301CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - MNL_START

R/W R R0/W Initial 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - ADDR_SIZE[1:0] - DATA_SIZE[2:0] R/W R R/W R/W R R/W R/W R/W Initial 0 0 0 0 0 0 0

bit field No name

Explanation

2-0 DATA_SIZE[2:0] When the manual command is issued, the size of the data transmitted to the SerialFlash memory (unit of Byte) is set. When data is led from the SerialFlash memory by the manual mode, the forwarding size of data (unit of Byte) is set. An effective, maximum value is 101(b) It is (5 byte).

5-4 ADDR_SIZE[1:0] When the manual command is issued, the forwarding size of the address forwarded to the SerialFlash memory (unit of Byte) is set.

16 MNL_START Forwarding begins in the manual mode. This bit is automatically cleared, and "0" is always led.

0 Invalidity 1 Forwarding beginning by manual mode

16.4. Register



16.4.3.9. AHB Address Register

This register specifies the address in GDC macro accessed in the master forwarding mode. The access by the master forwarding mode begins from the address specified here.

Address 01FB_3020H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name AHB_ADDR[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name AHB_ADDR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bit field No name

Explanation

31-0 AHB_ADDR[31:0] The address forwarded in GDC macro is set. The address value is sure to reach a set value in every four bytes (It is not possible to write it in AHB_ADDR 1:0).

16.4.3.10. SPI FLASH Address Register

This register specifies the address of the SerialFlash memory accessed in the master forwarding mode. The access by the master forwarding mode begins from the address specified here.

Address 01FB_3024H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - SPI FLASH_ADDR[23:16] R/W R R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name SPI FLASH_ADDR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bit field No name

Explanation

23-0 SPI FLASH ADDR[23:0]

The address forwarded to the SerialFlash memory side is set.

16.4. Register



16.4.3.11. Master Transfer Control Register

This register decides the forwarding size of the master forwarding mode. Moreover, the direction of forwarding (GDC macro→SerialFlash memory or SerialFlash memory →GDC macro) in the master forwarding mode is set. Forwarding begins in the master forwarding mode.

Address 01FB_3028H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - MST_START - WXR - SIZE[24:16] R/W R R0/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name SIZE[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bit field No name

Explanation

24-0 SIZE[24:0] The forwarding territory (unit of Byte) by the master forwarding mode is set. The amount of forwarding is sure to become set of every four bytes (It is not possible to write it in SIZE 1:0).

28 WXR The direction of forwarding is set. 0 Direction of Read(SerialFlash memory → GDC macro) 1 Direction of Write(GDC macro → SerialFlash memory)

30 MST_START Forwarding begins in the master forwarding mode. Forwarding when the guard release code is not set to Master Transfer Guard Release Register becomes direction of Write, and the forwarding beginning by this bit is not executed. Please execute it after setting an error-free guard release code to Master Transfer Guard Release Register at the time of forwarding in the direction of Write. Even when the guard release code is not set, it is possible to forward it in the direction of Read. Moreover, when forwarding the direction of Write begins without setting the guard release code, the interruption is generated. This bit is automatically cleared, and "0" is always led.

0 Invalidity 1 Forwarding beginning

16.4. Register



16.4.3.12. Master Transfer Finish Data Number Register

In this register, the number of forwarding completion data in the master forwarding mode is shown. Address 01FB_302CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name - FINDATA[24:16] R/W R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name FINDATA[15:0] R/W R R R R R R R R R R R R R R R R Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bit field No name

Explanation

24-0 FINDATA[24:0] The number of forwarding completion ending data in the master forwarding mode is shown. (unit of Byte) When beginning to forward it by the master forwarding, this bit is cleared.

16.4.3.13. Master Transfer Guard Release Register

This register sets the guard release of the master forwarding mode. If a specific guard release code is not input to this register, writing in the master forwarding mode cannot be executed.

Address 01FB_3030H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name MSTGR[31:16] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name MSTGR[15:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bit field No name

Explanation

31-0 MSTGR[31:0] The guard release code is set. - The guard release code is 5752_454EH. This bit is cleared at the following.

When forwarding by master forwarding (Write) is completed When soft reset is issued by master forwarding (Write) while forwarding

it When you receive the internal forwarding error while forwarding it by

master forwarding (Write)





16.5.1. Slave read mode

*1 After the data transfer of the master forwarding mode is completed, the data transfer of the slave read mode is executed when the data transfer by the slave read mode is done for the period of the data transfer by the master forwarding mode.

*2 After the data transfer of the manual mode, the data transfer of the slave read mode is executed when the data transfer by the slave read mode is done for the period of the data transfer by the manual mode.

The flow of the slave read mode is shown below.

Figure16-2Flow of slave read mode

MASTER SPICNT Serial Flash

Read(Addr)

Addr (3Byte)

FAST_READ (0x0B)

Dummy Byte (1Byte)

Data (1Byte)

Data (1Byte)

Data (1Byte)

Data (1Byte)

Data (4Byte)

Wait until four bytes' worth of data is read

The control flow of the slave read mode is shown below.

1. MASTER executes the read access for SPICNT. 2. To read data from the SerialFlash memory, SPICNT issues the FAST_READ command, the address,

and the dummy byte. 3. SPICNT weighting does GDCAHB from the SerialFlash memory to the read of the data of 4 bytes.




16.5.2. Manual mode

The manual mode is a mode that sets the command, the address, and data respectively of Command/Address Register (01FB_300CH ) of this module and Data1 Register (01FB_3014H ), and controls the SerialFlash memory directly.

* Please do not change the settings of all registers other than the SRST bit of Control Register (01FB_300CH ) between these forwarding.




16.5.2.1. Write

Flow when writing it in the SerialFlash memory with the manual is shown as follows.

Figure16-3Flow of manual write




The control flow of the manual write is shown below.

1. It is confirmed that the manual or the master forwarding mode is not executed by Internal Status Register (01FB_3008H ).

2. The size of transmitted address and data is set to Manual Transfer Control register (01FB_301CH ).

* Because the transmission of the address and data is unnecessary in the WREN command, each forwarding size is set as 0 bytes.

3. The WREN command is set to Command/Address Register (01FB_3010H ). 4. The manual forwarding begins by Manual Transfer Control register (01FB_301CH ). When

forwarding a prescribed size is completed, the manual forwarding completion interruption is issued.

5. The factor and the clearness of the interruption are confirmed by Interrupt Status register (01FB_3000H ). Bit2 of Interrupt Status register becomes the object of the confirmation.

6. The size of transmitted address and data is set to Manual Transfer Control register (01FB_301CH ).

* Forwarding the address is unnecessary in the RDSR command and one byte data is read from the SerialFlash memory. Therefore, the forwarding size of the address is set as 0 bytes, and the forwarding size of data is set as one byte.

7. ..RDSR command (.. is set to Command/Address Register (01FB_3010H ). 8. The manual forwarding begins by Manual Transfer Control register (01FB_301CH ). When


9. The factor and the clearness of the interruption are confirmed by Interrupt Status register (01FB_3000H). Bit2 of Interrupt Status register becomes the object of the confirmation.

10. In the data reading by the RDSR command, data is stored in Data1 register (01FB_3014H). Whether the WEL bit is "1" is confirmed. The procedure from 5 to 8 ..no "1" the WEL bit.. is repeated.

11. The size of transmitted address and data is set to Manual Transfer Control register (01FB_301CH).

12. The PP command and the address are set to Command/Address Register (01FB_3010H ). 13. The data written in the SerialFlash memory is set to Data1 register (01FB_3014H). 14. The manual forwarding begins by Manual Transfer Control register (01FB_301CH ). When



16. The status of the SerialFlash memory is read by issuing the RDSR command. Whether the WIP bit is "0" is confirmed. If the WIP bit is not "0", this processing is repeated.




16.5.2.2. Read

It is only processing of each every word. The master mode is used for processing more than two words.

* The FAST_READ command is not issuable in the read of the manual. It executes it by the READ command.

* To accept the READ command, the ratio of dividing frequency of the frequency setting of the cereal clock is changed.

Flow when the SerialFlash memory is read with the manual is shown as follows.

Figure16-4Flow of manual read




The control flow of the manual read is shown below.

1. It is confirmed that the manual or the master mode is not executed by Internal Status Register(01FB_3008H ).

2. The ratio of dividing frequency of the frequency of the cereal clock to which the READ command is accepted is set to Control register (01FB_300CH ).

3. The size of transmitted address and data is set to Manual Transfer Control register(01FB_301CH ). * The forwarding size of the address is set as three bytes to read the data of four bytes from the

SerialFlash memory in the READ command, and the forwarding size of data is set as four bytes. 4. The READ command and the address are set to Command/Address Register(01FB_3010H ). 5. The manual forwarding begins by Manual Transfer Control register(01FB_301CH ).

When forwarding a prescribed size is completed, the manual forwarding completion interruption is issued.


7. In reading data by the READ command, data is preserved in Data register (01FB_3014H ). The content is confirmed.




16.5.2.3. Deletion of sector

The flow of the sector deletion of the SerialFlash memory by the manual is shown as follows.

Figure16-1Sector deletion flow of manual


3. Setting of command(WREN: 0x06)

2. Setting of address and amount of data

Write Enable

1. Confirmation of transfer condition

4. Manual transfer start

Write Enable (WREN: 0x06)

Manual Transfer completion interrupt

5. Check interrupt factor and clear

Read Status Register

7. Setting of command(RDSR: 0x05)



Read Status Register (RDSR: 0x05)

Value of Status Register(1Byte)



10. Data Register read

12. Setting of command(SE: 0xD8) and address



Sector Erase (SE: 0xD8)



Address (3Byte)

Sector Erase

Sector Erase execute


Check interrupt factor and clear

Data Register read

Not WIP=1'b0

Not WEL=1'b1




The control flow of the sector deletion of the manual is shown below.


2. The size of transmitted address and data is set to Manual Transfer Control register(01FB_301CH ). * Because the transmission of the address and data is unnecessary in the WREN command, each

forwarding size is set as 0 bytes. 3. The WREN command is set to Command/Address Register(01FB_3010H ). 4. The manual forwarding begins by Manual Transfer Control register(01FB_301CH ). When

forwarding a prescribed size is completed, the manual forwarding completion interruption is issued. 5. The factor and the clearness of the interruption are confirmed by Interrupt Status

register(01FB_3000H ). Bit2 of Interrupt Status register becomes the object of the confirmation. 6. The size of transmitted address and data is set to Manual Transfer Control register(01FB_301CH ).


7. The RDSR command is set to Command/Address Register(01FB_3010H ). 8. The manual forwarding begins by Manual Transfer Control register(01FB_301CH ). When


register(01FB_3000H ). Bit2 of Interrupt Status register becomes the object of the confirmation. 10. In reading data by the RDSR command, data is preserved in Data register(01FB_3014H ). Whether

the WEL bit is "1" is confirmed. If the WEL bit is not "1", the procedure of 5-8 is repeated. 11. The size of transmitted address and data is set to Manual Transfer Control register(01FB_301CH ).

* The forwarding size of the address is set as three bytes because the transmission of data is unnecessary in the SE command, and the forwarding size of data is set as 0 bytes.

12. The SE command and the address are set to Command/Address Register(01FB_3010H ). 13. The manual forwarding begins by Manual Transfer Control register(01FB_301CH ). When

forwarding a prescribed size is completed, the manual forwarding completion interruption is issued. The deletion of the sector is executed.

14. The factor and the clearness of the interruption are confirmed by Interrupt Status register(01FB_3000H ). Bit2 of Interrupt Status register becomes the object of the confirmation.

15. The status of the SerialFlash memory is read by issuing the RDSR command. Whether the WIP bit is "0" is confirmed. If the WIP bit is not 0, this processing is repeated.




16.5.2.4. Deletion of bulk

The flow of the bulk sector deletion of the SerialFlash memory by the manual is shown as follows.

Figure16-5Bulk deletion flow of manual


3. Setting of command(WREN: 0x06)


Write Enable



Write Enable (WREN: 0x06)




7. Setting of command (RDSR: 0x05)



Read Status Register (RDSR: 0x05)

Value of Status Register(1Byte)



10. Data Register read

12. Setting of command(BE: 0xC7)



Bulk Erase (BE: C7)



Bulk Erase

Bulk Erase execute


Check interrupt factor and clear

Data Register read

Not WIP=1'b0

Not WEL=1'b1




The control flow of the bulk deletion of the manual is shown below.


2. The size of transmitted address and data is set to Manual Transfer Control register(01FB_301CH ). * Because the transmission of the address and data is unnecessary in the WREN command, each

forwarding size is set as 0 bytes. 3. The WREN command is set to Command/Address Register(01FB_3010H ). 4. The manual forwarding begins by Manual Transfer Control register(01FB_301CH ). When


register(01FB_3000H ). Bit2 of Interrupt Status register becomes the object of the confirmation. 6. The size of transmitted address and data is set to Manual Transfer Control register(01FB_3001CH ).


7. The RDSR command is set to Command/Address Register(01FB_3010H ). 8. The manual forwarding begins by Manual Transfer Control register(01FB_301CH ). When


register(01FB_3000H ). Bit2 of Interrupt Status register becomes the object of the confirmation. 10. In reading data by the RDSR command, data is preserved in Data register(01FB_3014H ). Whether

the WEL bit is "1" is confirmed. The procedure of 5.-8 ..no "1" the WEL bit.. is repeated. 11. The size of transmitted address and data is set to Manual Transfer Control register(01FB_301CH ).

* Because the transmission of the address and data is unnecessary in the BE command, the forwarding size of the address and data is set as 0 bytes.

12. The BE command is set to Command/Address Register(01FB_3010H ). 13. The manual forwarding begins by Manual Transfer Control register(01FB_301CH ). When

forwarding a prescribed size is completed, the manual forwarding completion interruption is issued. The deletion of the bulk is executed.

14. The factor and the clearness of the interruption are confirmed by Interrupt Status register(01FB_3000H ). Bit2 of Interrupt Status register becomes the object of the confirmation.

15. The status of the SerialFlash memory is read by issuing the RDSR command. Whether the WIP bit is "0" is confirmed. If the WIP bit is not "0", this processing is repeated.




16.5.3. Master forwarding mode

16.5.3.1. Write

Forwarding begins by the start bit after setting the source address (GDC macro side), the destination address (SerialFlash memory side), the direction of forwarding, and the size of forwarding. After forwarding is completed, the master forwarding completion interruption is issued.

*1 Please do not change the settings of all registers other than the SRST bit of Control Register(01FB_300CH ) between these forwarding.

*2 When soft reset is issued during forwarding the master forwarding mode (write), the SerialFlash memory might be processing the PP command. In this case, after the status of the SerialFlash memory is checked, and it is confirmed that it is not a state of BUSY, the following accesses are executed.




The flow of the master right is shown below.

Figure16-6Flow of master right




The control flow of the master right is shown below.

1. It is confirmed that the manual or the master mode is not executed by Internal Status Register (01FB_3008H ).

2. The guard release code is set to Master Transfer Guard Release register (01FB_3030H ). 3. The source address is set to AHB Address register (01FB_3020H ). 4. The destination address is set to SPI FLASH memory Address register (01FB_3024H ). 5. Master's direction of the data transfer (The write: GDD macro→SerialFlash memory) and the

forwarding size are set to Master Transfer Control register (01FB_3028H ). 6. The master right forwarding begins by Master Transfer Control register (01FB_3028H ).

(1) The WREN command is forwarded to the SerialFlash memory. (2) The RDSR command is forwarded to the SerialFlash memory, and the content of the read

data (WEL bit =1) is confirmed. If WEL is not "1", this processing is repeated. (3) The destination address set according to PP command and procedure 4 is forwarded. The

data of 16 words (=64 bytes) is transmitted from the source address set according to procedure 3 to internal buffer (Buff0) simultaneously with this.

(4) When the data transfer to Buff0 ends, the data stored in Buff0 is transmitted to the SerialFlash memory. At this time, data is transmitted from the AHB side to Buff1 at the same time.

(5) When the data transfer to Buff1 ends, the data stored in Buff1 is transmitted to the SerialFlash memory. At this time, data is transmitted from the AHB side to Buff0 at the same time.

(6) Procedure 1.-5 is repeated until the data transfer of the amount in 256 bytes ends in the SerialFlash memory because of the GDCmacro side.

(7) The RDSR command is forwarded to the SerialFlash memory, and the content of the read data (WIP bit =0) is confirmed. If WIP is not "0", this processing is repeated.

(8) Procedure 1-7 is repeated until forwarding set in procedure 5 is completed. (9) When forwarding a prescribed size is completed, the master forwarding completion

interruption is issued. 7. The factor and the clearness of the interruption are confirmed by Interrupt Status register

(01FB_3000H ). Bit0 of Interrupt Status register becomes the object of the confirmation.




16.5.3.2. Read

Forwarding begins by the start bit after setting the source address (SerialFlash memory side), the destination address (GDC macro side), the direction of forwarding, and the size of forwarding. After forwarding is completed, the master forwarding completion interruption is issued.

*1 Please do not change the settings of all registers other than the SRST bit of Control Register(01FB_300CH ) between these forwarding.




The flow of the master read is shown below.

Figure16-7Flow of master read

Memory SPICNTMASTER

Addr (3Byte)

FAST_READ (0x0B)

Data (1Byte)

Data (1Byte)

Serial Flash

Dummy Byte (1Byte)

Buff0

Buff1

16word(64Byte) transfer

Data (1Byte)

16word(64Byte) transfer

Data (1Byte)

Data (1Byte)

Data (1Byte)

Buff0 16word(64Byte) transfer

Until transfer set amount of transfer finished, repeat



2. Setting of source address(SPI FLASH side address)

3. Setting of destination address(AHB side address)

6. Master transfer start

4. Setting of transfer direction(SPI FLASH → AHB)

5. Setting of amount of transfer


Buff0

Buff1

Data transfer

Data(16word)

Data transfer

Data(16word)




The control flow of the master read is shown below.

1. It is confirmed that the manual or the master mode is not executed by Internal Status Register (01FB_3008H ).

2. The source address is set to SPI FLASH memory Address register (01FB_3024H ). 3. The destination address is set to AHB Address register (01FB_3020H ). 4. Master's direction of the data transfer (The read: SerialFlash memory →GDC macro) and the

forwarding size are set to Master Transfer Control register (01FB_3028H ). 5. The master read forwarding begins by Master Transfer Control register (01FB_3028H ).

(1) The source address and the dummy byte set by FAST_READ command and procedure 2 are forwarded to the SerialFlash memory.

(2) The data led from the SerialFlash memory is stored in Buff0. (3) When the data transfer to Buff0 ends, the data led from the SerialFlash memory is stored in

Buff1. At this time, the data stored in Buff0 is transmitted to the GDC macro side at the same time.

(4) When the data transfer to Buff1 ends, the data led from the SerialFlash memory is stored in Buff0. At this time, the data stored in Buff1 is transmitted to the GDC macro side at the same time.

(5) Procedure 1.-4 is repeated until forwarding set in procedure 4 is completed. (6) When forwarding a prescribed size is completed, the master forwarding completion

interruption is issued. 6. The factor and the clearness of the interruption are confirmed by Interrupt Status

register(01FB_3000H ). Bit0 of Interrupt Status register becomes the object of the confirmation.

16.6. Notes



16.6. Notes

16.6.1. Limitations

SPI mode SPICNT corresponds to SPI mode only 0. SPICNT supports the SerialFlash memory that corresponds to SPI mode 0.

17.1. Outline


NTSC Decoder FUJITSU SEMICONDUCTOR CONFIDENTIAL 423

17. NTSC Decoder This chapter explains NTSC Decoder of the GDC macro (Hereafter, it is assumed NTSC).

17.1. Outline NTSC/ It is Y as for the analogue video signal of PAL method/ Cb/ Form is recovered to the digital data of Cr. The data recovered one's is sent to capture.

17.2. Feature There is the following features.

With built-in exclusive use ADC NTSC, PAL, PAL-M, and PAL-N support No signal automatic operation judgment

17.3. Composition



17.3. Composition Figure17-1NTSC and a peripheral block diagram are shown.

Figure17-1NTSC and peripheral block diagram


MB91590 Series

GDC Macro

ADCNTSC

decoder

CaptureController

Video dataprocessor


SpriteEngine


DRiDGiDBi

GD

C L

ocal

Bus

DrawEngine



GD

C A

HB

Bus

Analog NTSC

Digital RGBor

ITU-R BT656


17.4. Register



17.4. Register


The read value is always "1. "W0: The write value is always "0. "One is guaranteed and when the write is done, operation is not guaranteed. W1: The write value is always "1. "0 is guaranteed and when the write is done, operation is not guaranteed. R: ReadW: Write


17.4. Register




Address Register name Explanation

01FB_1000H NTSC_CFG Set register of module whole

01FB_1004H NTSC_KILL Color killer level adjustment

01FB_1008H NTSC_PIC High region correction-edge enhancement

01FB_100CH NTSC_TINT Tint adjustment for NTSC

01FB_1010H NTSC_TINT_P Tint adjustment for PAL

01FB_1014H NTSC_COL_CR Gain adjustment of Cr

01FB_1018H NTSC_COL_CB Gain adjustment of Cb

01FB_101CH NTSC_CONT Contrast adjustment(gain adjustment of Y)

01FB_1020H NTSC_BRT Brightness adjustment(adjustment of offset of Y)

01FB_1024H NTSC_RELATE Correlation coefficient of comb filter

01FB_1028H NTSC_HDEL Delay adjustment of internal timing signal

01FB_102CH NTSC_HSDLY Output image positioning

01FB_1030H NTSC_THRES Threshold setting of synchronous separation

01FB_1034H NTSC_NO_SIG No signal detection

01FB_1038H - -

01FB_103CH NTSC_PWRDWN Down of AD converter power control

17.4. Register




17.4.3.1. NTSC_CFG

Address 01FB_1000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - MUTE MV AGC FORMAT[1:0]

R/W R0 R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0

Set register of module whole

bit field

No name Explanation

1-0 FORMAT[1:0]

NTSC/PAL/PAL-M/PAL-N switch 00: NTSC signal input 01: PAL signal input 10: PAL-M signal input 11: PAL-N signal input

2 AGC AGC On/Off switch 0: Off 1: On

3 MV

Only macro vision mode NTSC is effective. 0: Non-macro vision signal input 1: Macro vision signal input To evade the color strike lamp of the macro vision signal (color burst signal reversing), it moves it from the value in which the position where the color burst is detected is set with HDEL 7:0 behind about 600ns.

4 MUTE

Mute On/Off 0 : Off 1 : On Black level Y=16 and Cb=Cr=128 are output at mute On o'clock.

17.4. Register



17.4.3.2. NTSC_KILL

Address 01FB_1004H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - KILL[5:0]

R/W R0 R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 1 0 0

Color killer level

bit field

No name Explanation

5-0 KILL[5:0] KILL 5:0=00H: Color killer Off Color..killer..work..become. (The color killer doesn't necessarily become On even if it sets it to KILL 5:0=3FH. )

17.4. Register



17.4.3.3. NTSC_PIC

Address 01FB_1008H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PIC[5:0]


High region correction and edge enhancement

bit field

No name Explanation

5-0 PIC[5:0]

PIC 5:0<32(20H ): Attenuation PIC 5:0=32(20H ): Flat PIC 5:0>32(20H ): Emphasis The frequency response in the value of arbitrary PIC is shown as follows.

Figure17-2Frequency response of high region correction-edge enhancement

-40

-30

-20

-10

0

10

20

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

f (MHz)

dB

241680

6348403632

17.4. Register



17.4.3.4. NTSC_TINT

Address 01FB_100CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - TINT[7:0]

R/W R0 R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 1 0 0 0 0 0 0 0

Tint adjustment for NTSC

bit field

No name Explanation

7-0 TINT[7:0] TINT 7:0=80H: Flat The calculation type of the Tint adjustment is shown as follows. Degree=(TINT[7:0]-128)×0.35°

17.4.3.5. NTSC_TINT_P

Address 01FB_1010H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - TINT_P[7:0]


Tint adjustment for PAL

bit field

No name Explanation

7-0 TINT_P[7:0] TINT_P 7:0=80H: Flat The calculation type of the Tint adjustment is shown as follows. Degree=(TINT_P[7:0]-128)×0.35°

17.4. Register



17.4.3.6. NTSC_COL_CR

Address 01FB_1014H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - COL_CR[7:0]

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 1 0 0 0 0 0 0 0

Color adjustment of Cr(about 0 times-twice)

bit field

No name Explanation

7-0 COL_CR[7:0]

COL_CR 7:0=80H:1 time The calculation type of the color adjustment is shown as follows. Cr=(R-Y)×COL_CR[7:0]÷128 1(01 H ) It does in 254 when Cr becomes it 254(FE H ) above and the clip is done to one as follows when becoming it.

17.4.3.7. NTSC_COL_CB

Address 01FB_1018H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - COL_CB[7:0]


Color adjustment of Cb(about 0 times-twice)

bit field

No name Explanation

7-0 COL_CB[7:0]

COL_CB 7:0=80 H :1 time The calculation type of the color adjustment is shown as follows. Cb=(B-Y)×COL_CB[7:0]÷128 1(01 H ) It does in 254 when Cb becomes it 254(FE H ) above and the clip is done to one as follows when becoming it.

17.4. Register



17.4.3.8. NTSC_CONT

Address 01FB_101CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - CONT[7:0]

R/W R0 R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Contrast adjustment(0 times-four times)

bit field

No name Explanation

7-0 CONT[7:0]

CONT 7:0=40 H :1 time The calculation type of the contrast adjustment is shown as follows. Y'=Y×CONT[7:0]÷64

16(10 H ) It does in 254 when Y becomes it 254(FE H ) above and the clip is done to 16 as follows when becoming it.

17.4.3.9. NTSC_BRT

Address 01FB_1020H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - BRT[7:0]


Brightness adjustment(-128～+128)

bit field

No name Explanation

7-0 BRT[7:0]

The calculation type of the brightness adjustment is shown as follows. Y''=Y'+(BRT[7:0]-128) 16(10 H ) It does in 254 when Y becomes it 254(FE H ) above and the clip is done to 16 as follows when becoming it.

17.4. Register



17.4.3.10. NTSC_RELATE

Address 01FB_1024H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - RELATE[7:0]


Correlation coefficient of comb filter

bit field

No name Explanation

7-0 RELATE[7:0] It becomes only RELATE=00 H:BPF. (The comb filter becomes Off. ) RELATE=FF H: The comb filter works almost.

17.4.3.11. NTSC_HDEL

Address 01FB_1028H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - HDEL[7:0]


Detection positioning of color burst

bit field

No name Explanation

7-0 HDEL[7:0] It is a timing adjustment register from internal H.SYNC to the color burst.

17.4. Register



17.4.3.12. NTSC_HSDLY

Address 01FB_102CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - HSDLY[5:0]


Positioning of direction of H of output image

bit field

No name Explanation

5-0 HSDLY[5:0] HSDLY=00H: The image moves to the right. HSDLY=3FH: The image moves to the left.

17.4.3.13. NTSC_THRES

Address 01FB_1030H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - THRES[7:0]

R/W R R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 1 0 0 1 0

Threshold of synchronous separation

bit field

No name Explanation

7-0 THRES[7:0]

THRES=00H: Synchronization cannot be separated. THRES=FFH: Synchronization cannot be separated. A synchronous separation considers minimum value + THRES or less of the image to be SYNC.

17.4. Register



17.4.3.14. NTSC_NO_SIG

Address 01FB_1034H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - NO_SIG

R/W R0 R

Initial 0 0 No signal detection signal

bit field

No name Explanation

0 NO_SIG NO_SIG=0: Image having NO_SIG=1: No signal The image output is made black picture (Y=10H,Cb=Cr=80H) at a no signal.

17.4.3.15. NTSC_PWRDWN

Address 01FB_103CH Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name -

R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - PWRDWN

R/W R0 R/W

Initial 0 0 Down of power

bit field

No name Explanation

0 PWRDWN

PWRDWN=0:AD converter power down Disnabl The PWRDWN=1:AD converter power is down enable. Notes: The down of power of the AD converter ..state of default.. is used and the invalid ..state.. hatchet and the NTSC decoder function cannot be used. Please do one to the NTSC_PWRDWN register in the write before using the NTSC decoder function.





17.5.1. Analog clamping internal ADC circuit

The ADC input signal should clamp the Sync level at the Low Reference level of ADC. The example of the circuit is as shown in the figure below.

Figure17-3Example of analog clamping circuit

Having inserted VR in the input signal : peak magnitude (100% White - Sync) of the input signal. In the meaning matched to about 70% of dynamic range (High Reference - Low Reference) of ADC, It is not a translation to which VR is needed. In general, 70% is used by the fineness of not an especially significant numerical value but the input signal within the range like 50%-75%. If you may saturate what the signal that exceeds 100% White or nor exceeds it You may use by 75%, that improves, and S/N of ADC improves. Do not exceed 75% because the color element of 100% Yellow and Cyan collapses when making it to 75% or more. The input signal though 75Ω and terminal figure In general, if it is figure when the signal has been sent by 75Ω is received and a signal of very low impedance ､There is no problem. Because Tr1(NPN) and Tr2(PNP) hold the temperature compensating concurrently One one ..Comprimentari.. if possible is preferable.




17.5.2. Y / C separation

It is com/adaptive two-dimension filter and Y / C is separate.

17.5.3. ACC

The color level is automatically adjusted seeing the burst level. (1-8 times) Compulsion color/killer works when becoming below the value that the burst level set by the register. ( Off cannot do the ACC function. )

17.5.4. AGC

The brightness level is automatically adjusted seeing the Sync level. (1-4 times)Off can do AGC by the register. (If it is a signal with correct level at the image period that goes out of a recent image equipment, Off can evade the influence of the sink collapsing of the macro vision insertion signal and the sink collapsing by the trouble of an analog circuit, and AGC calls the great result. )

17.5.5. For macro vision

PseudoSync added to the macro vision signal is always removed. After about 600nsec, the position where the burst signal is detected is moved when setting it to the macro vision mode by the register.

17.5.6. Automatic judgment function(no signal judgment)

A black image is output as an image signal with H. Sync and V. Sync of self-propelled when there is no input signal. The no signal detection signal is output at the same time.

17.5.7. Other adjustments Various adjustments are possible by the register. Please refer to the register list for them.




17.5.8. Flow figure of register and data

Figure17-4Flow of data




17.5.9. BPF characteristic for Y/C separation

Figure17-5Frequency response of BPF for Y/C separation

-60

-50

-40

-30

-20

-10

0

10

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

f (MHz)

dB

-60

-50

-40

-30

-20

-10

0

10

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

f (MHz)

dB

18.1. Outline


Command RAM (CMDRAM) FUJITSU SEMICONDUCTOR CONFIDENTIAL 440

18. Command RAM (CMDRAM)

18.1. Outline Command RAM (following CMDRAM) has the memory area of 8K Byte as a user data storage area. Moreover, the data check and the error correction function by Error Correcting Code (henceforth ECC) are possessed every one user data byte. ECC function can set effective/invalidity according to the register.

18.2. Feature RAM area of 8K Byte is installed. Effective/invalidity of ECC mode setting ECC mode can be set. ECC generation and inspection function- one bit error correction- of every one byte Two bit error

detection in every one byte(The error in three bits or more is outside the operation guarantees. )

18.3. Composition Effective/invalidity of ECC mode can be selected by setting GDCCR register (0000_0F65H) bit2 of FR81S. (In ECC mode setting, please refer to "The MB91590 Series hardware manual Chapter 44 GDC external control GDCCR register". )

Figure18-1CMDRAM module block chart

18.4. Register



18.4. Register




18.4.2. Register list Only when ECC mode is assumed to be effective, the register described as follows can be accessed. It becomes Reserved, writing is disregarded when ECC mode is assumed to be invalid, and reading responds ALL "0".

Table18-1Register list


01F9_F000H EEAR Error address register of ECC

01F9_F004H EECSR Error control register of ECC

18.4. Register




18.4.3.1. EEAR EEAR(Ecc Error Address Register) is used when ECC mode is effective, and maintains one bit error correction when ECC is inspected and the mistake by two bits generation address of the verification.

Address 01F9_F000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DEEAR[7:0] DEEAR[10:8] Name ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

- ADR10 ADR9 ADR8

R/W R R R R R R R R R0 R R RInitial 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEEAR[7:0] SEEAR[10:8] Name

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0-

ADR10 ADR9 ADR8

R/W R R R R R R R R R0 R R RInitial 0 0 0 0 0 0 0 0 0 0 0 0

bit field

No name Explanation

2-0, 15-8

SEEAR[10:0] (Single bit Ecc Error AddRess)

When the error correction is executed the bit one ECC inspection ("1 SEI bit =" of EECSR register), the generation address is set in this bitAs for this bit, the SEI bit is maintained until one bit error correction is executed again after "0" write is cleared. The address stored in this register becomes the unit of the word in bit12-bit2 in CMDRAM Memory area (0080_0000H-0080_1FFFH). Ex. Single bit error address (0080_0010H)

SEEAR[10:0](ADR10-ADR0)=004H

18-16, 31-24

DEEAR[10:0] (Double bit Ecc Error AddRess)

When the mistake is detected the bit two ECC inspection ("1 DEI bit =" of EECSR register), the generation address is set in this bitAs for this bit, the DEI bit is maintained until the mistake by two bits is detected again after "0" write is cleared. The address stored in this register becomes the unit of the word in bit12-bit2 in CMDRAM Memory area (0080_0000H-0080_1FFFH). Ex. Double bit error address (0080_0140H) DEEAR[10:0](ADR10-ADR0)=050H

Attention: This register responds "Writing is invalid" and "Reading is ALL "0"" when ECC mode is

invalid ..Reserved and...

18.4. Register



18.4.3.2. EECSR (Ecc Error Control and Status Register) ECC..mode..effective..use..ECC..inspect..error correction..mistake..verification..interruption..information..interruption..logic..harmony..output..control.

Address 01F9_F004H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name - R/W R0 Initial 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - DEIE DEI SEIE SEIR/W R1 R0 R/W R/W R/W R/WInitial 1 0 0 0 0 0

bit field

No name Explanation

0 SEI

(Single bit ecc Error Interrupt)

When ECC is inspected, this bit shows the generation existence of one bit error correction. When "0" is written in this bit, interruption information is cleared. When one bit error correction is executed and this bit becomes "1", the address generated at that time is set in the SEEAR bit of the EEAR register.

SEI One bit error correction 0 None 1 It is.

1

SEIE (Single bit ecc Error Interrupt

Enable)

This bit is INTST register (01FB_2100H) of the MCNT module as for the interrupt of the SEI bit It is controlled to do the logical harmony output to bit31.

SEIE SEI logic harmony output control 0 Disable (logical harmony output prohibition) 1 Enable (logical harmony output permission)

2 DEI

(Double bit ecc Error Interrupt)

This bit mistakes by two bits when ECC is inspected and shows the generation existence of detection. When "0" is written in this bit, interruption information is cleared. When the mistake by two bits is detected and this bit becomes "1", the address generated at that time is set in the DEEAR bit of the EEAR register.

DEI It mistakes by two bits and it detects it. 0 None 1 It is.

3

DEIE (Double bit ecc Error Interrupt

Enable)

This bit is INTST register (01FB_2100H) of the MCNT module as for the interrupt of the DEI bit It is controlled to do the logical harmony output to bit31.

DEIE DEI logic harmony output control 0 Disable (logical harmony output prohibition) 1 Enable (logical harmony output permission)

Attention: This register responds "Writing is invalid" and "Reading is ALL "0"" when ECC mode is

invalid ..Reserved and...





18.5.1. ECC mode switch GDCCR register (0000_0F65H) of FR81S Effective/invalidity of the following ECC modes can be switched by the bit2 setting. Details of the switch are "Table18-2Please refer to". The function operation of this module is different according to ECC mode switch. About the function operation of each mode, "エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つかりません。" and "エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ

かりません。Please refer to". (Please refer to "Chapter 5.1.1 GDC access sequence" for the switch timing of ECC mode. ) (Please refer to "The MB91590 Series hardware manual Chapter 44 GDC external control GDCCR register" for details of the GDCCR register. )

Table18-2ECC mode switch

Register setting value ECC mode GDCCR register bit2=0 Invalidity GDCCR register bit2=1 Effective

18.5.1.1. Limitations Please execute GDCCR register bit2 switch while the GDC macro is resetting it. Reset of the GDC macro can be controlled by bit0 of the GDCCR register.




18.5.2. ECC mode(effective) It is done one bit error correction and to detect it by each byte mistaking it by two bits when ECC mode is assumed to be effective. (When the error in three bits or more occurs, become outside the operation guarantee. ) It explains each function when ECC mode is assumed to be effective as follows.

18.5.2.1. Interruption ECC mode executes the output to the interruption detection and the external (INTST register of the MCNT module) to this module when it is effective.

18.5.2.1.1. Interruption factor

The interruption factor of this module is as follows. ECC single bit error interruption (EECSR register(01F9_F004H, bit0(SEI)) ECC double bit error interruption (EECSR register(01F9_F004H, bit2(DEI)) Above-mentioned interruption information can be done by clearing by writing "0" in a pertinent bit (EECSR register bit0/bit2). Details of the EECSR register are "18.4.3.2ChapterEECSR (Ecc Error Control and Status Register)Please refer to".

18.5.2.1.2. Interruption output

When the interruption is generated, this module is INTST register (01FB_2100H) of the MCNT module as for interruption information The logical harmony output is done to bit31. The logical harmony output can be controlled with bit1(SEIE) and bit3(DEIE) of the EECSR register. Details of the logical harmony output control are "18.4.3.2ChapterEECSR (Ecc Error Control and Status Register)Please refer to".

18.5.2.2. Reserved area Writing is disregarded as for Reserved (01F9_F08H-01F9_FFFFH) in the register area and reading responds ALL "1".




18.5.2.3. Memory access The single with an effective ECC mode and the latency of the burst access become as follows.

18.5.2.3.1. Single access

18.5.2.3.1.1. Single write access

Write latency = four cycles(GSSCGCLK)

18.5.2.3.1.2. Single read access

Redoratenshi = three cycles(GSSCGCLK)




18.5.2.3.2. Burst access

18.5.2.3.2.1. Burst write access

Write latency = four cycles(GSSCGCLK) Write through putto = four cycles(GSSCGCLK)

18.5.2.3.2.2. Burst read access

Redoratenshi = three cycles(GSSCGCLK) Read throughput = three cycles(GSSCGCLK)




18.5.3. ECC mode(invalidity) Neither the inspection nor the correction by ECC mode are executed. Moreover, "エラー! 参照元が見つかりません。エラー! 参照元が見つかりません。All registers described in ..".. become Reserved.

18.5.3.1. Interruption There is no generated interruption when ECC mode is invalid.

18.5.3.2. Reserved area Writing is disregarded as for Reserved (01F9_F000H-01F9_FFFFH) in the register area and reading responds ALL "0".




18.5.3.3. Memory access The single to which ECC mode is invalid and the latency of the burst access become as follows.

18.5.3.3.1. Single access

18.5.3.3.1.1. Single write latency

Write latency = one cycle(GSSCGCLK)

18.5.3.3.1.2. Shinglredoratenshi

Redoratenshi 4= cycle(GSSCGCLK)




18.5.3.3.2. Burst access

18.5.3.3.2.1. Burst write latency

Write latency = one cycle(GSSCGCLK) Write through putto = one cycle(GSSCGCLK)

18.5.3.3.2.2. Burst read latency

Redoratenshi = four cycles(GSSCGCLK) Read throughput = one cycle(GSSCGCLK)

19.1. Outline


Module Controller (MCNT) FUJITSU SEMICONDUCTOR CONFIDENTIAL 451

19. Module Controller (MCNT)

19.1. Outline As for Module Controller (following MCNT), Graphic Display Controller (following GDC) reading information and the control signal in external bus memory interface switch can be done.

19.2. Feature ID can be confirmed in the version of GDC information GDC macro and year of production. Each interruption signal in interruption control GDC macro is detected and the logical harmony output

is done to the interruption controller of FR81S (IRPR6H register). CS1 when external bus memory interface control signal switch external bus memory interface (NOR

Flash/SRAM) is used can be changed to address high-ranking bit (Address bit25). It is possible to correspond from 32M Byte to 64M Byte by changing to Address bit25 external bus memory maximum capacity of one (CS0).

19.3. Composition



19.3. Composition

Figure19-1 MCNT Block

19.4. Register



19.4. Register





Table19-1Register list


01FB_2000H GINFO GDC information

01FB_2100H INTST Status of interrupt

01FB_2110H INTDET Interrupt detection control

01FB_2120H INTEN Output control of external interrupt

01FB_2500H GCONT GDC control

19.4. Register




19.4.3.1. GINFO Register GINFO (GDC information) Register can confirm the version of the GDC macro, ID, and production year information.

Address 01FB_2000H Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name YEAR[15:0] R/W R R R R R R R R R R R R R R R RInitial 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ID[7:0] VER[7:0] R/W R R R R R R R R R R R R R R R RInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

bit field

No name Explanation

7-0 VER[7:0] (VERsion)

This bit is version information on the GDC macro. Versions are the third editions (VER 7:0=02H).

15-8 ID[7:0]

(ID) This bit is ID information on the GDC macro. ID is 0 It is (ID 7:0=00H. )

31-16 YEAR[15:0]

(YEAR) This bit is production year of GDC macro information. The production year is 2011(YEAD 15:0=2011H).

19.4. Register



19.4.3.2. INTST Register INTST (Interrupt status) Register displays interruption information from each module in the GDC macro. Moreover, interrupt informationINTEN RegisterIRPR6H register (0000_0424H) The logical harmony output of FR81S ..interruption controller (.. is done to bit7(GDC) by the control. Interrupt information can be cleared by writing "1" in this register.

Address 01FB_2100H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name INT 31

INT 30

INT29

INT 28

INT 27

INT26

INT25

INT24

INT23

INT22

INT21

INT20

INT 19

INT 18

INT17

INT16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name INT 15

INT 14

INT13

INT 12

INT 11

INT10

INT9

INT8

INT7

INT6

INT5

INT4

INT 3

INT 2

INT1

INT0


bit field

No name Explanation

0 INT0

(INTerrupt0)

This bit displays the state of Interrupt of CMDSEQ. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT0 CMDSEQ(Interrupt) interruption 0 None 1 It is.

1 INT1

(INTerrupt1) Reserved

2 INT2

(INTerrupt2)

This bit displays the state of VSYNC of DISPLAY. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT2 DISPLAY(VSYNC) interruption 0 None 1 It is.

3 INT3

(INTerrupt3)

This bit displays the state of FSYNC of DISPLAY. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT3 DISPLAY(FSYNC) interruption 0 None 1 It is.

19.4. Register



bit field

No name Explanation

4 INT4

(INTerrupt4)

This bit displays the state of SYNCERR of DISPLAY. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT4 DISPLAY(SYNCERR) interruption 0 None 1 It is.

5 INT5

(INTerrupt5)

This bit displays the state of RUPDATE of DISPLAY. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT5 DISPLAY(RUPDATE) interruption 0 None 1 It is.

6 INT6

(INTerrupt6)

This bit displays the state of BUS access error of DISPLAY. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT6 DISPLAY(BUS access error) interruption 0 None 1 It is.

7 INT7

(INTerrupt7)

This bit displays the state of Interrupt of CAPTURE. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT7 CAPTURE(Interrupt) interruption 0 None 1 It is.

10-8 INT10-8

(INTerrupt10-8) Reserved

11 INT11

(INTerrupt11)

This bit displays the state of Command error of DRAW. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT11 CAPTURE(Command error) interruption 0 None 1 It is.

12 INT12

(INTerrupt12)

This bit displays the state of INT command execution of DRAW. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT12 DRAW(INT command execution) interruption 0 None 1 It is.

19.4. Register



bit field

No name Explanation

13 INT13

(INTerrupt13)

This bit displays the state of DMA command execution of DRAW. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT13 DRAW(DMA command execution) interruption 0 None 1 It is.

14 INT14

(INTerrupt14)

This bit displays the state of BUS access error of DRAW. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT14 DRAW(BUS access error) interruption 0 None 1 It is.

15 INT15

(INTerrupt15)

This bit displays the state of Enable bits change of SPE. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT15 SPE(Enable bits change) interruption 0 None 1 It is.

16 INT16

(INTerrupt16)

This bit displays the state of BUS error of SPE. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT16 SPE(BUS error) interruption 0 None 1 It is.

17 INT17

(INTerrupt17)

This bit displays the state of Processing error of SPE. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT17 SPE(Processing error) interruption 0 None 1 It is.

18 INT18

(INTerrupt18)

This bit displays the state of Line blank of SPE. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT18 SPE(Line blank) interruption 0 None 1 It is.

19.4. Register



bit field

No name Explanation

19 INT19

(INTerrupt19)

This bit displays the state of Specified line processing over of SPE. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT19 SPE(Specified line processing) interruption 0 None 1 It is.

20 INT20

(INTerrupt20)

This bit displays the state of No signal detection of NTSC. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT20 NTSC(No signal detection) interruption 0 None 1 It is.

21 INT21

(INTerrupt21)

This bit displays the state of Interrupt of SIG. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT21 SIG(Interrupt) interruption 0 None 1 It is.

22 INT22

(INTerrupt22)

This bit displays the state of Ch0 interrupt of DMAC. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT22 DMAC(Ch0 interrupt) interruption 0 None 1 It is.

23 INT23

(INTerrupt23)

This bit displays the state of Ch1 interrupt of DMAC. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT23 DMAC(Ch1 interrupt) interruption 0 None 1 It is.

24 INT24

(INTerrupt24)

This bit displays the state of Interrupt of RLD. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT24 RLD(Interrupt) interruption 0 None 1 It is.

25 INT25


19.4. Register



bit field

No name Explanation

26 INT26

(INTerrupt26)

This bit displays the state of Interrupt of MEMC. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared. - MEMC is SPICNT and exclusive control. Therefore, when MEMC is unused, this interruption is not generated. Please refer to "5.1.4. the chapter outside bus memory interface exclusive operation" for a detailed content of exclusive control.

INT26 MEMC(Interrupt) interruption 0 None 1 It is.

27 INT27

(INTerrupt27)

This bit displays the state of Interrupt of SPICNT. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared. - SPICNT is MEMC and exclusive control. Therefore, when SPICNT is unused, this interruption is not generated. Please refer to "5.1.4. the chapter outside bus memory interface exclusive operation" for a detailed content of exclusive control.

INT27 SPICNT(Interrupt) interruption 0 None 1 It is.

28 INT28


29 INT29

(INTerrupt29)

This bit displays the state of BUS protocol error of GDC Local BUS Bridge. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT29 GDC Local BUS Bridge(BUS protocol error) interruption

0 None 1 It is.

30 INT30

(INTerrupt30)

This bit displays the state of Protocol error of GDC AHB-Local BUS Bridge. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT30 GDC AHB-Local BUS Bridge(Protocol error) interruption

0 None 1 It is.

31 INT31

(INTerrupt31)

This bit displays the state of Error of CMDRAM. A detailed content is "19.5.2.6ChapterInput interrupt signalPlease refer to". When "1" is written in this bit, interruption information is cleared.

INT31 CMDRAM(Error) interruption 0 None 1 It is.

19.4. Register



19.4.3.3. INTDET Register INTDET (Interrupt detection) Register :. EECSR (Ecc Error Control and Status RegisterIt drinks and the detection method including Wa (edge and level detection) can be selected. As for the edge detection, the Ta edge and the level detection become the High levels.

Address 01FB_2110H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name IDET

31 IDET

30 IDET

29 IDET

28 IDET

27 IDET

26 IDET

25 IDET

24 IDET

23 IDET

22 IDET

21 IDET

20 IDET

19 IDET

18 IDET

17 IDET

16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name IDET

15 IDET

14 IDET

13 IDET

12 IDET

11 IDET

10 IDET

9 IDET

8 IDET

7 IDET

6 IDET

5 IDET

4 IDET

3 IDET

2 IDET

1 IDET

0


bit field

No name Explanation

0 IDET0

(Interrupt DETection 0)

This bit sets the method of detecting the interruption of INTST register bit0 (Interrupt of CMDSEQ).

IDET0 Method of detecting INT0 0 Edge detection 1 Level detection

1 IDET1


Reserved

2 IDET2


This bit sets the method of detecting the interruption of INTST register bit2 (VSYNC of DISPLAY).


3 IDET3


This bit sets the method of detecting the interruption of INTST register bit3 (FSYNC of DISPLAY).


4 IDET4


This bit sets the interruption detection of INTST register bit4 (SYNCERR of DISPLAY).


19.4. Register



bit field

No name Explanation

5 IDET5


This bit sets the interruption detection of INTST register bit5 (RUPDATE of DISPLAY).


6 IDET6


This bit sets the interruption detection of INTST register bit6 (BUS access error of DISPLAY).


7 IDET7


This bit sets the method of detecting the interruption of INTST register bit7 (Interrupt of CAPTURE).


10-8 IDET10-8 (Interrupt

DETection 10-8) Reserved

11 IDET11


This bit sets the method of detecting the interruption of INTST register bit11 (Command error of DRAW).


12 IDET12


This bit sets the method of detecting the interruption of INTST register bit12 (INT command execution of DRAW).


13 IDET13


This bit sets the interruption detection of INTST register bit13 (DMA command execution of DRAW).


14 IDET14


This bit sets the interruption detection of INTST register bit14 (BUS access error of DRAW).


19.4. Register



bit field

No name Explanation

15 IDET15


This bit sets the interruption detection of INTST register bit15 (Enable bits change of SPE).


16 IDET16


This bit sets the interruption detection of INTST register bit16 (BUS error of SPE). IDET16 Method of detecting INT16

0 Edge detection 1 Level detection

17 IDET17


This bit sets the interruption detection of INTST register bit17 (Processing error of SPE).


18 IDET18


This bit sets the method of detecting the interruption of INTST register bit18 (Line blank of SPE). IDET18 Method of detecting INT18


19 IDET19


This bit sets the method of detecting the interruption of INTST register bit19 (Specified line processing over of SPE).


20 IDET20


This bit sets the method of detecting the interruption of INTST register bit20 (No signal detection of NTSC).


21 IDET21


This bit sets the interruption detection of INTST register bit21 (Interrupt of SIG). IDET21 Method of detecting INT21


19.4. Register



bit field

No name Explanation

22 IDET22


This bit sets the interruption detection of INTST register bit22 (Ch0 interrupt of DMAC).


23 IDET23


This bit sets the interruption detection of INTST register bit23 (Ch1 interrupt of DMAC).


24 IDET24


This bit sets the interruption detection of INTST register bit24 (Interrupt of RLD). IDET24 Method of detecting INT24


25 IDET25


Reserved

26 IDET26


This bit sets the interruption detection of INTST register bit26 (Interrupt of MEMC). - MEMC is SPICNT and exclusive control. Therefore, even if this detection is set when MEMC is unused, it becomes invalid. Please refer to "5.1.4. the chapter outside bus memory interface exclusive operation" for a detailed content of exclusive control.


27 IDET27


This bit sets the interruption detection of INTST register bit27 (Interrupt of SPICNT). - SPICNT is MEMC and exclusive control. Therefore, even if this detection is set when SPICNT is unused, it becomes invalid. Please refer to "5.1.4. the chapter outside bus memory interface exclusive operation" for a detailed content of exclusive control.


28 IDET28


Reserved

19.4. Register



bit field

No name Explanation

29 IDET29


This bit sets the method of detecting the interruption of INTST register bit29 (BUS protocol error of GDC Local BUS Bridge).


30 IDET30


This bit sets the method of detecting the interruption of INTST register bit30 (Protocol error of GDC AHB-Local BUS Bridge).


31 IDET31


This bit sets the interruption detection of INTST register bit31 (Error of CMDRAM). IDET31 Method of detecting INT31


19.4. Register



19.4.3.4. INTEN Register INTEN (Interrupt enable) Register :. EECSR (Ecc Error Control and Status RegisterInformation on doing the logical harmony output to interruption controller (bit7(GDC) of FR81S of IRPR6H register (0000_0424H) is drinking controlled.

Address 01FB_2120H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name IEN 31

IEN 30

IEN29

IEN 28

IEN 27

IEN26

IEN25

IEN24

IEN23

IEN22

IEN21

IEN20

IEN 19

IEN 18

IEN17

IEN16


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name IEN 15

IEN 14

IEN13

IEN 12

IEN 11

IEN10

IEN9

IEN8

IEN7

IEN6

IEN5

IEN4

IEN 3

IEN 2

IEN1

IEN0


bit field

No name Explanation

0 IEN0

(Interrupt ENable 0)

This bit controls INTST register bit0 (Interrupt of CMDSEQ) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).

IEN0 INT0 logic harmony output control

0 Disable (IRPR6H レジスタへ論理和出力しません)

1 Enable (The logical harmony output is done to the IRPR6H register. )

1 IEN1


Reserved

2 IEN2


This bit controls INTST register bit2 (VSYNC of DISPLAY) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




3 IEN3


This bit controls INTST register bit3 (FSYNC of DISPLAY) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




4 IEN4


This bit controls INTST register bit4 (SYNCERR of DISPLAY) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




19.4. Register



bit field

No name Explanation

5 IEN5


This bit controls INTST register bit5 (RUPDATE of DISPLAY) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




6 IEN6


This bit controls INTST register bit6 (BUS access error of DISPLAY) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




7 IEN7


This bit controls INTST register bit7 (Interrupt of CAPTURE) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




10-8 IEN10-8 (Interrupt

ENable 10-8) Reserved

11 IEN11


This bit controls INTST register bit11 (Command error of DRAW) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




12 IEN12


This bit controls INTST register bit12 (INT command execution of DRAW) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




13 IEN13


This bit controls INTST register bit13 (DMA command execution of DRAW) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




19.4. Register



bit field

No name Explanation

14 IEN14


This bit controls INTST register bit14 (BUS access error of DRAW) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




15 IEN15


This bit controls INTST register bit15 (Enable bits change of SPE) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




16 IEN16


This bit controls INTST register bit16 (BUS error of SPE) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




17 IEN17


This bit controls INTST register bit17 (Processing error of SPE) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




18 IEN18


This bit controls INTST register bit18 (Line blank of SPE) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




19 IEN19


This bit controls INTST register bit19 (Specified line processing over of SPE) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




19.4. Register



bit field

No name Explanation

20 IEN20


This bit controls INTST register bit20 (No signal detection of NTSC) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




21 IEN21


This bit controls INTST register bit21 (Interrupt of SIG) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




22 IEN22


This bit controls INTST register bit22 (Ch0 interrupt of DMAC) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




23 IEN23


This bit controls INTST register bit23 (Ch1 interrupt of DMAC) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




24 IEN24


This bit controls INTST register bi24 (Interrupt of RLD) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




25 IEN25


Reserved

26 IEN26


This bit controls INTST register bit26 (Interrupt of MEMC) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register). - MEMC is SPICNT and exclusive control. Therefore, even if this output control is set to Enable when MEMC is unused, it becomes invalid. Please refer to "5.1.4. the chapter outside bus memory interface exclusive operation" for a detailed content of exclusive control.




19.4. Register



19.4. Register



bit field

No name Explanation

27 IEN27


This bit controls INTST register bit27 (Interrupt of SPICNT) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register). - SPICNT is MEMC and exclusive control. Therefore, even if this output control is set to Enable when SPICNT is unused, it becomes invalid. Please refer to "5.1.4. the chapter outside bus memory interface exclusive operation" for a detailed content of exclusive control.




28 IEN28


Reserved

29 IEN29


This bit controls INTST register bit29 (BUS protocol error of GDC Local BUS Bridge) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




30 IEN30


This bit controls INTST register bit30 (Protocol error of GDC AHB-Local BUS Bridge) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




31 IEN31


This bit controls INTST register bit31 (Error of CMDRAM) of doing the logical harmony output to the interruption controller of FR81S (IRPR6H register).




19.4. Register



19.4.3.5. GCONT Register GCONT (GDC Control) Register is a register that controls the MEMC module.

Address 01FB_2500H

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Name -


Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - ADSC


bit field

No name Explanation

0 ADCS

(ADdress/Cs Select)

This bit can switch the external bus memory interface control signal of MEMC. Details are "エラー! 参照元が見つかりません。Chapter エラー! 参照元が見つ

かりません。Please refer to".

ADCS External bus memory interface control signal switch

0 CS1 制御信号を CS1 に切り替えます 1 Addr25 The control signal is switched to Address bit25.





19.5.1. GDC information (GINFO) GDC information can confirm version information on the GDC macro, ID, and the production year.

19.5.1.1. Version information It is version information on the GDC macro. Details are ("18.4.3.1ChapterEEARPlease refer to". )

19.5.1.2. ID It is ID information on the GDC macro. Details are ("18.4.3.1ChapterEEARPlease refer to". )

19.5.1.3. Production year It is production year of GDC macro information. Details are ("18.4.3.1ChapterEEARPlease refer to". )




19.5.2. Interrupt control Interrupt control : the interruption signal from each module in the GDC macro. EECSR (Ecc Error Control and Status RegisterCacnou is done the decrease. Moreover, interrupt informationINTEN RegisterThe logical harmony output is done to the interruption controller of FR81S (bit7(GDC) of IRPR6H register (0000_0424H)) by the control.

19.5.2.1. Interruption detection The interruption detectionINTDET RegisterThe interruption signal from each module is detected by the content (edge detection or level detection) that sets. EECSR (Ecc Error Control and Status RegisterCacnou is done the decrease.

19.5.2.2. Edge detection The interruption signal is detected by the Ta edge.

19.5.2.3. Level detection The interruption signal is detected at the High level.

19.5.2.4. Interruption clearness Interruption informationEECSR (Ecc Error Control and Status RegisterIt clears by drinking and writing "1" in the bit for.

19.5.2.5. External interruption output An external interruption is output to the interruption controller of FR81S (IRPR6H register (0000_0424H) bit7(GDC)). This external interruptionINTEN Register..drinking.. by SeiEECSR (Ecc Error Control and Status RegisterIt drinks and the logical ..information.. harmony output is done. ..putting.. ,INTEN RegisterAs for interrupt to which Disable is set, the logical harmony output is not done as external interrupt. A detailed setting is ("19.4.3.4ChapterINTEN RegisterPlease refer to". )




19.5.2.6. Input interrupt signal The relation of interruption information from status and each module is as follows. Please refer to the chapter of each module for a detailed content of the interrupt condition.

Table19-2Interruption list

Status No Output module Interruption condition Reference register

INT0 CMDSEQ

1.

2.

3.

4.

5.

6.7.8.9.

10.11.12.13.

14.

15.

16.

17.

18.

19.

End of reset start(End of commandlist prosessing) End of priority1 trigger start (End of commandlist prosessing) End of priority3 trigger start (End of commandlist prosessing) End of variout trigger start (End of commandlist prosessing) End of regester start (End of commandlist prosessing) Forced ending of commandlist prosessing Error of AHB slave acess Error of comparison Non boot mode setted by GDCCR register The data of External Flash are all "f" Error of WAIT trigger command Error of END command Interrupt start by priority (Reset start is starting) Interrupt start by priority (Priority3 start is starting) Interrupt start by priority (Various trigger start is starting) Interrupt start by priority (Register start is starting) Error of CMDSEQ (The internal state error) Individual Reset completion (The internal state error) Byte lane of CMPREG2 command is all "0"

01FB_7000H

INT1 Reserved - - INT2 Display 1. Vertical SYNC - INT3 Display 1. Frame SYNC - INT4 Display 1. SYNC error - INT5 Display 1. Register update - INT6 Display 1. BUS access error (Master) detection -

1.2.

Frame SYNC Single shot end

01FD_8178H INT7 Capture

1. 656 stream error 01FD_8180H INT8-10 Reserved - - INT11 Draw 1. Command error - INT12 Draw 1. INT command execution - INT13 Draw 1. DMA command execution - INT14 Draw 1. BUS access error (Master) detection - INT15 SPE 1. Enable bits change - INT16 SPE 1. BUS error - INT17 SPE 1. Processing error - INT18 SPE 1. Line blank - INT19 SPE 1. Specified line processing over - INT20 NTSC 1. No signal detection 01FB_1034H




Status No Output module Interruption condition Reference register

INT21 SIG 1.2.3.

Unequal sum Unequal CRC Shadow took over register

01FB_005CH

INT22 DMAC (ch1)

1.2.3.4.

Address overflow (Error) Transfer stop request (Error) Source access error (Error) Normal end

01FB_4014H

INT23 DMAC (ch2)

1.2.3.4.

Address overflow (Error) Transfer stop request (Error) Source access error (Error) Normal end

01FB_4024H

INT24 RLD

1.2.3.4.

Byte count achieved AHB Slave error Input FiFo empty Input FiFo full

01FB_5028H

INT25 Reserved - - INT26(*1) MEMC 1. Access error outside area 01FB_3200H

INT27(*1) SPICNT

1.2.3.4.5.

Transfer complete in Master Transfer Mode Error response of AHB during Manual Mode transfer complete Soft reset Without setting the guard release code when Master Transfer Mode (Write) is executed.

01FB_3000H

INT28 Reserved - - INT29 GDC Local BUS Bridge 1. Local BUS protocol error - INT30 GDC AHB-Local BUS Bridge 1. Protocol Error -

INT31(*2) CMDRAM 1.2.

Single-bit error Double-bit error

01F9_F000H

*1: Interruption (MEMC/SPICNT) that corresponds to INT26 and INT27 is excluded. An exclusive switch

selects MEMC/SPICNT by GDCCR register (0000_0F65H) of FR81S. (Please refer to "5.1.4. the chapter outside bus memory interface exclusive operation" for an exclusive switch. )

*2: When CMDRAM is only ECC mode, the interruption of INT31 becomes effective. (Please refer to "The MB91590 Series hardware manual Chapter 44 GDC external control GDCCR register" for the switch control of ECC mode. )




19.5.3. GDC control The GDC control is "19.4.3.5ChapterGCONT RegisterThe MEMC module is controlled by".

19.5.3.1. External bus memory interface control signal

switch When MEMC is used by this control (ADCS bit), external bus memory interface (NOR Flash/SRAM) control signal of (*1) (address high-ranking bit/CS) can be switched. *1: MEMC (NOR Flash/SRAM control) and SPICNT (cereal Flash control) can be exclusively switched by

GDCCR register (0000_0F65H) of FR81S. (Please refer to "The MB91590 Series hardware manual Chapter 44 GDC external control GDCCR register" for details of the GDCCR register. )

Correspondence and the limitations of the external bus memory control signal by the ADCS control are described as follows.

Limitations ADCS (bit0)

External bus memory interface control signal External bus memory

maximum capacity Number of external bus memory maximum controls

0 CS1 32M Byte 2 pieces 1 Address bit25 64M Byte 1 piece

19.5.4. Limitations (ADCS=1) and the external bus memory that can be controlled become one (CS0) when switching to Address bit25 by switching the external bus memory interface control signal. Moreover, external bus memory maximum capacity of (ADCS=0) when doing and one becomes CS1 with 32M Byte.




20.1. Outline


Local bus bridge FUJITSU SEMICONDUCTOR CONFIDENTIAL 478

20. Local bus bridge This chapter explains the local bus bridge in the GDC macro.

20.1. Outline There are two kinds of local bus bridges between GDC Local BUS and GDC AHB BUS in the GDC macro. In each bus bridge, GDC Local BUS. - GDC Local BUS Among GDC Local BUS. - The bus access conversion between GDC AHB BUS is done, the transaction generated on the bus is processed normally or it observes it.

GDC Local BUS - It is a bus bridge between GDC Local BUS. (GDC Local Bus Bridge) GDC Local BUS - It is a bus bridge between GDC AHB BUS. (GDC AHB-Local Bus Bridge)

Note:GDC Bus Bridge is not an object of this chapter. Details of GDC Bus Brdige are '21ChapterGDC Bus bridgePlease refer to'.

20.2. Feature When the access error occurs, the interruption is issued.

20.3. Composition



20.3. Composition

20.3.1. Block diagram Figure20-1Local bridge and a peripheral block diagram are shown.

Figure20-1Local bridge and peripheral block diagram





20.4.1. GDC Local Bus Bridge When the display list is transmitted from the memory that exists in the GDC macro by using display list DMA function provided in the GDC Bus Bridge module to Draw Engine, it accesses the memory through this Bridge. In the above-mentioned access, when the access error response is generated on GDC Local BUS, this module issues the interruption. Please initialize the GDC macro when the interruption of this module is issued. Interruption information that this bridge issued can be confirmed by the MCNT module 'INTST register (01FB_2100H) bit29'.

20.4.2. GDC AHB-Local Bus Bridge Access on GDC AHB BUS to slave module from master module on GDC Local BUS The bus access conversion is done from the master module on GDC AHB BUS for the access on GDC Local BUS to the slave module. When the access error response is generated from the slave module on GDC AHB BUS for the access on GDC AHB BUS to the slave module, this bridge issues the interruption from the master module on GDC Local BUS. Please retry the corresponding access when the interruption of this module is issued. Interruption information that this bridge issued can be confirmed by the MCNT module 'INTST register (01FB_2100H) bit30'.

21.1. Outline


GDC Bus bridge FUJITSU SEMICONDUCTOR CONFIDENTIAL 481

21. GDC Bus bridge

21.1. Outline This module has the register that maintains the DMA transfer function of the display list and the interrupt factor of Draw Engine.

21.2. Feature The GDC macro has DMA controller only for the display list. This module becomes a master, and the

display list arranged in the memory can be transmitted to display list FIFO of Draw Engine. The register and the mask register that maintains the interrupt factor of the display controller and Draw

Engine are built into.

21.3. Composition

GDC Local Bus

DFIFO

DrawEngine

GDC Local Bus

GDC AHB Bus

GDCBus Bridge

VRAM

LineEngine

BitBltEngine

GDCLocal

Bus Bridge

21.4. Register



21.4. Register

21.4.1. List of register related to display list DMA

Address 31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9 8 7 6 5 4 3 2 1 0

LTS 01FC_0008H

LTS

LSTA 01FC_0010H

LS

TA

LSA 01FC_0040H LSA

LCO 01FC_0044H LCO

LREQ 01FC_0048H

LR

EQ

21.4. Register



21.4.1.1. LTS (displayList Transfer Stop) Register address 01FC_0009H

Bit number 7 6 5 4 3 2 1 0

Bit field name - LTS

R/W R0 RW

Initial value 0 0

The display list forwarding is discontinued. When "1" is written in this register, the display list forwarding executing it now is discontinued.

21.4.1.2. LSTA (displayList transfer STAtus) Register address 01FC_0010H

Bit number 7 6 5 4 3 2 1 0

Bit field name - LSTA

R/W R0 R

Initial value 0 0

The display list forwarding status from VRAM is shown. It becomes "1" while forwarding it. When forwarding ends, it is cleared to "0".

21.4.1.3. LSA (displayList Source Address) Register address 01FC_0040H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name - LSA

R/W R0 RW R0

Initial value 0 X 0

The source address of the display list forwarding is set. Forwarding beginning address of the display list stored on VRAM when the display list is transmitted is set. Two subordinate position bits of this register are always treated as 0, and arrange the display list by four Baitoarain, please. The value of this register doesn't change while forwarding it after forwarding ends.

21.4. Register



21.4.1.4. LCO(displayList Count) Register address 01FC_0044H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name - LCO

R/W R0 RW

Initial value 0 X

The display list forwarding count setting is done. The frequency forwarded when the display list is transmitted is set in each long word. When "0(h)" is set though the forwarding frequency is forwarding once when "1(h)" is set, it becomes the maximum value and 16M(16777216) times are forwarded. The value of this register doesn't change while forwarding it after forwarding ends.

21.4.1.5. LREQ(displayList transfer REQuest) Register address 01FC_0048H

Bit number 7 6 5 4 3 2 1 0 Bit field name - LREQ R/W R0 RW1 Initial value 0 0

The display list forwarding is started. The display list on VRAM is transmitted to display list FIFO by writing "1" in this register.

21.4. Register



21.4.2. Register related to GDC interruption

21.4.2.1. List of register related to GDC interruption

Address 31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9 8 7 6 5 4 3 2 1 0

IST

01FC_0020H

SY

NC

ER

R0

FS

YN

C0

VS

YN

C0

CE

ND

CE

RR

IMASK

01FC_0024H

SY

NC

ER

R0M

FS

YN

C0M

VS

YN

C0M

CE

ND

M

CE

RR

M

21.4. Register



21.4.2.1.1. IST(Interrupt STatus)

Register address 01FC_0020H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name - - -

SY

NC

ER

R0

FS

YN

C0

VS

YN

C0

CE

ND

CE

RR

R/W R0 R0W0 R0 RW0


It is an interruption status register. It is shown that the interruption demand is generated when one is set. Status can be cleared by doing 0 in the write.

[bit4] SYNCERR0 (Sync. Error 0)

An external synchronous error of display controller 0 is shown.

[bit3] FSYNC0 (Frame Sync. 0)

The state of a synchronous frame interruption of display controller 0 is shown.

[bit2] VSYNC0 (Vertical Sync. 0)

The state of a vertical, synchronous interruption of display controller 0 is shown.

[bit1] CEND (Command END)

The state of the display list command end interruption is shown.

[bit0] CERR (Command Error Flag)

The state of the display list command execution error interruption is shown.

21.4. Register



21.4.2.1.2. IMASK (Interrupt MASK)

Register address 01FC_0024H

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit field name - - -

SY

NC

ER

R0M

FS

YN

C0M

VS

YN

C0M

CE

ND

M

CE

RR

M

R/W R0 R0W0 R0 RW


It is a signal that masking does the interruption demand. Even if the interruption demand has been generated for the bit in which 0 is written, the interruption signal is not asserted to CPU. (It is default and a mask. )

[bit4] SYNCERR0M (Sync Error 0 Mask)

The mask does the external synchronous error interruption of display controller 0.

[bit3] FSYNC0M (Frame Sync. Interrupt 0 Mask)

The mask does a synchronous frame interruption of display controller 0.

[bit2] VSYNC0M (Vertical Sync. Interrupt 0 Mask)

The mask does a vertical, synchronous interruption of display controller 0.

[bit1] CENDM (Command Interrupt Mask)

The mask does the display list command end interruption.

[bit0] CERRM (Command Error Interrupt Mask)

The mask does the display list command execution error interruption.

Documents

MB91590 series GDC macro specifications - Fujitsu...Sapphire GDC macro specifications FUJITSU SEMICONDUCTOR CONFIDENTIAL ･The content of the description of this material might change